From e636c8d336489bf3eed5878299e6cc045bbad077 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 20 Feb 2024 01:17:29 +0000
Subject: [PATCH] debug lk
---
kernel/drivers/spi/spi-s3c24xx.c | 43 ++++++++-----------------------------------
1 files changed, 8 insertions(+), 35 deletions(-)
diff --git a/kernel/drivers/spi/spi-s3c24xx.c b/kernel/drivers/spi/spi-s3c24xx.c
index 4e7d1bf..d6f5169 100644
--- a/kernel/drivers/spi/spi-s3c24xx.c
+++ b/kernel/drivers/spi/spi-s3c24xx.c
@@ -1,12 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2006 Ben Dooks
* Copyright 2006-2009 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#include <linux/spinlock.h>
@@ -23,16 +19,15 @@
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/s3c24xx.h>
+#include <linux/spi/s3c24xx-fiq.h>
#include <linux/module.h>
-
-#include <plat/regs-spi.h>
#include <asm/fiq.h>
-#include "spi-s3c24xx-fiq.h"
+#include "spi-s3c24xx-regs.h"
/**
- * s3c24xx_spi_devstate - per device data
+ * struct s3c24xx_spi_devstate - per device data
* @hz: Last frequency calculated for @sppre field.
* @mode: Last mode setting for the @spcon field.
* @spcon: Value to write to the SPCON register.
@@ -231,23 +226,8 @@
struct spi_fiq_code {
u32 length;
u32 ack_offset;
- u8 data[0];
+ u8 data[];
};
-
-extern struct spi_fiq_code s3c24xx_spi_fiq_txrx;
-extern struct spi_fiq_code s3c24xx_spi_fiq_tx;
-extern struct spi_fiq_code s3c24xx_spi_fiq_rx;
-
-/**
- * ack_bit - turn IRQ into IRQ acknowledgement bit
- * @irq: The interrupt number
- *
- * Returns the bit to write to the interrupt acknowledge register.
- */
-static inline u32 ack_bit(unsigned int irq)
-{
- return 1 << (irq - IRQ_EINT0);
-}
/**
* s3c24xx_spi_tryfiq - attempt to claim and setup FIQ for transfer
@@ -265,6 +245,7 @@
struct pt_regs regs;
enum spi_fiq_mode mode;
struct spi_fiq_code *code;
+ u32 *ack_ptr = NULL;
int ret;
if (!hw->fiq_claimed) {
@@ -287,13 +268,10 @@
regs.uregs[fiq_rrx] = (long)hw->rx;
regs.uregs[fiq_rtx] = (long)hw->tx + 1;
regs.uregs[fiq_rcount] = hw->len - 1;
- regs.uregs[fiq_rirq] = (long)S3C24XX_VA_IRQ;
set_fiq_regs(®s);
if (hw->fiq_mode != mode) {
- u32 *ack_ptr;
-
hw->fiq_mode = mode;
switch (mode) {
@@ -313,12 +291,10 @@
BUG_ON(!code);
ack_ptr = (u32 *)&code->data[code->ack_offset];
- *ack_ptr = ack_bit(hw->irq);
-
set_fiq_handler(&code->data, code->length);
}
- s3c24xx_set_fiq(hw->irq, true);
+ s3c24xx_set_fiq(hw->irq, ack_ptr, true);
hw->fiq_mode = mode;
hw->fiq_inuse = 1;
@@ -491,7 +467,6 @@
struct s3c2410_spi_info *pdata;
struct s3c24xx_spi *hw;
struct spi_master *master;
- struct resource *res;
int err = 0;
master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
@@ -540,8 +515,7 @@
dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
/* find and map our resources */
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- hw->regs = devm_ioremap_resource(&pdev->dev, res);
+ hw->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(hw->regs)) {
err = PTR_ERR(hw->regs);
goto err_no_pdata;
@@ -549,7 +523,6 @@
hw->irq = platform_get_irq(pdev, 0);
if (hw->irq < 0) {
- dev_err(&pdev->dev, "No IRQ specified\n");
err = -ENOENT;
goto err_no_pdata;
}
--
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