From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
u-boot/drivers/net/gmac_rockchip.c | 494 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 494 insertions(+), 0 deletions(-)
diff --git a/u-boot/drivers/net/gmac_rockchip.c b/u-boot/drivers/net/gmac_rockchip.c
index bc8dcc9..dfb8342 100644
--- a/u-boot/drivers/net/gmac_rockchip.c
+++ b/u-boot/drivers/net/gmac_rockchip.c
@@ -18,6 +18,9 @@
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_DWC_ETH_QOS
+#include <asm/arch/grf_rk3528.h>
+#include <asm/arch/grf_rk3562.h>
+#include <asm/arch/ioc_rk3562.h>
#include <asm/arch/grf_rk3568.h>
#include <asm/arch/grf_rk3588.h>
#include <asm/arch/grf_rv1106.h>
@@ -516,6 +519,147 @@
return 0;
}
#else
+static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct rockchip_eth_dev *dev)
+{
+ struct eqos_priv *priv = &dev->eqos;
+ struct rk3528_grf *grf;
+ unsigned int div;
+
+ enum {
+ RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3,
+ RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3),
+ RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3),
+ RK3528_GMAC0_CLK_RMII_DIV20 = 0,
+ };
+
+ enum {
+ RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10,
+ RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10),
+ RK3528_GMAC1_CLK_RGMII_DIV1 = 0,
+ RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10),
+ RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11),
+ RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11),
+ RK3528_GMAC1_CLK_RMII_DIV20 = 0,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ switch (priv->phy->speed) {
+ case 10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ else
+ div = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case 100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ else
+ div = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case 1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ div = RK3528_GMAC1_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
+ return -EINVAL;
+ }
+
+ if (pdata->bus_id)
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div);
+ else
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div);
+
+ return 0;
+}
+
+static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata,
+ struct rockchip_eth_dev *dev)
+{
+ struct eqos_priv *priv = &dev->eqos;
+ struct rk3562_grf *grf;
+ unsigned int div;
+
+ enum {
+ RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7,
+ RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7),
+ RK3562_GMAC0_CLK_RGMII_DIV1 = 0,
+ RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7),
+ RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8),
+ RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7),
+ RK3562_GMAC0_CLK_RMII_DIV20 = 0,
+ };
+
+ enum {
+ RK3562_GMAC1_SPEED_SHIFT = 0x0,
+ RK3562_GMAC1_SPEED_MASK = BIT(0),
+ RK3562_GMAC1_SPEED_10M = 0,
+ RK3562_GMAC1_SPEED_100M = BIT(0),
+ };
+
+ enum {
+ RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13,
+ RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13),
+ RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13),
+ RK3562_GMAC1_CLK_RMII_DIV20 = 0,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ switch (priv->phy->speed) {
+ case 10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ if (pdata->bus_id > 0) {
+ div = RK3562_GMAC1_CLK_RMII_DIV20;
+ rk_clrsetreg(&grf->soc_con[0],
+ RK3562_GMAC1_SPEED_MASK,
+ RK3562_GMAC1_SPEED_10M);
+ } else {
+ div = RK3562_GMAC0_CLK_RMII_DIV20;
+ }
+ } else {
+ div = RK3562_GMAC0_CLK_RGMII_DIV50;
+ }
+ break;
+ case 100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ if (pdata->bus_id > 0) {
+ div = RK3562_GMAC1_CLK_RMII_DIV2;
+ rk_clrsetreg(&grf->soc_con[0],
+ RK3562_GMAC1_SPEED_MASK,
+ RK3562_GMAC1_SPEED_100M);
+ } else {
+ div = RK3562_GMAC0_CLK_RMII_DIV2;
+ }
+ } else {
+ div = RK3562_GMAC0_CLK_RGMII_DIV5;
+ }
+ break;
+ case 1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ div = RK3562_GMAC0_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
+ return -EINVAL;
+ }
+
+ if (pdata->bus_id)
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div);
+ else
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div);
+
+ return 0;
+}
+
static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct rockchip_eth_dev *dev)
{
@@ -1064,6 +1208,251 @@
}
#else
+static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3528_grf *grf;
+ unsigned char bgs[1] = {0};
+
+ enum {
+ RK3528_MACPHY_ENABLE_MASK = BIT(1),
+ RK3528_MACPHY_DISENABLE = BIT(1),
+ RK3528_MACPHY_ENABLE = 0,
+ RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
+ RK3528_MACPHY_XMII_SEL = BIT(6),
+ RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
+ RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)),
+ RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
+ RK3528_MACPHY_PHY_ID = BIT(11),
+ };
+
+ enum {
+ RK3528_MACPHY_BGS_MASK = GENMASK(3, 0),
+ };
+
+#if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ u32 regs[2] = {0};
+ ofnode node;
+ int ret = 0;
+
+ /* retrieve the device */
+ if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(rockchip_efuse),
+ &dev);
+ else
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(rockchip_otp),
+ &dev);
+ if (!ret) {
+ node = dev_read_subnode(dev, "macphy-bgs");
+ if (ofnode_valid(node)) {
+ if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
+ /* read the bgs from the efuses */
+ ret = misc_read(dev, regs[0], &bgs, 1);
+ if (ret) {
+ printf("read bgs from efuse/otp failed, ret=%d\n",
+ ret);
+ bgs[0] = 0;
+ }
+ }
+ }
+ }
+#endif
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ reset_assert(&pdata->phy_reset);
+ udelay(20);
+ rk_clrsetreg(&grf->macphy_con0,
+ RK3528_MACPHY_ENABLE_MASK |
+ RK3528_MACPHY_XMII_SEL_MASK |
+ RK3528_MACPHY_24M_CLK_SEL_MASK |
+ RK3528_MACPHY_PHY_ID_MASK,
+ RK3528_MACPHY_ENABLE |
+ RK3528_MACPHY_XMII_SEL |
+ RK3528_MACPHY_24M_CLK_SEL_24M |
+ RK3528_MACPHY_PHY_ID);
+
+ rk_clrsetreg(&grf->macphy_con1,
+ RK3528_MACPHY_BGS_MASK,
+ bgs[0]);
+ udelay(20);
+ reset_deassert(&pdata->phy_reset);
+ udelay(30 * 1000);
+}
+
+static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ unsigned int clk_mode;
+ struct rk3528_grf *grf;
+
+ enum {
+ RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1,
+ RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1),
+ RK3528_GMAC0_CLK_RMII_MODE = 0x1,
+ };
+
+ enum {
+ RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8,
+ RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8),
+ RK3528_GMAC1_CLK_RMII_MODE = 0x1,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (pdata->bus_id == 1) {
+ clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode);
+ } else {
+ clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode);
+ }
+}
+
+static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ unsigned int rx_enable;
+ unsigned int rx_delay;
+ struct rk3528_grf *grf;
+
+ enum {
+ RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8,
+ RK3528_GMAC1_RGMII_MODE_MASK = BIT(8),
+ RK3528_GMAC1_RGMII_MODE = 0x0,
+
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14),
+ RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0,
+ RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14),
+
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15),
+ RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0,
+ RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15),
+ };
+
+ enum {
+ RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8,
+ RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8),
+
+ RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0,
+ RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0),
+ };
+
+ if (!pdata->bus_id)
+ return;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (pdata->rx_delay < 0) {
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE;
+ rx_delay = 0;
+ } else {
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE;
+ rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT;
+ }
+
+ rk_clrsetreg(&grf->gmac1_con0,
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK |
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK |
+ RK3528_GMAC1_RGMII_MODE_MASK,
+ rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE |
+ (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT));
+
+ rk_clrsetreg(&grf->gmac1_con1,
+ RK3528_GMAC1_RX_DL_CFG_MASK |
+ RK3528_GMAC1_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) |
+ rx_delay);
+}
+
+static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ unsigned int mode;
+
+ enum {
+ RK3562_GMAC0_RMII_MODE_SHIFT = 0x5,
+ RK3562_GMAC0_RMII_MODE_MASK = BIT(5),
+ RK3562_GMAC0_RMII_MODE = 0x1,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (!pdata->bus_id) {
+ mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode);
+ }
+}
+
+static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ struct rk3562_ioc *ioc;
+ unsigned int rx_enable;
+ unsigned int rx_delay;
+
+ enum {
+ RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5,
+ RK3562_GMAC0_RGMII_MODE_MASK = BIT(5),
+ RK3562_GMAC0_RGMII_MODE = 0x0,
+
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0),
+ RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0,
+ RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0),
+
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1),
+ RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0,
+ RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1),
+ };
+
+ enum {
+ RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8,
+ RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8),
+
+ RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0,
+ RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0),
+ };
+
+ if (pdata->bus_id)
+ return;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
+
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK,
+ RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT);
+
+ if (pdata->rx_delay < 0) {
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE;
+ rx_delay = 0;
+ } else {
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE;
+ rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT;
+ }
+
+ rk_clrsetreg(&ioc->mac0_io_con1,
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
+
+ rk_clrsetreg(&ioc->mac0_io_con0,
+ RK3562_GMAC0_RX_DL_CFG_MASK |
+ RK3562_GMAC0_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
+ rx_delay);
+
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
+
+ rk_clrsetreg(&ioc->mac1_io_con0,
+ RK3562_GMAC0_RX_DL_CFG_MASK |
+ RK3562_GMAC0_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
+ rx_delay);
+}
+
static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3568_grf *grf;
@@ -1438,6 +1827,86 @@
#endif
#ifdef CONFIG_DWC_ETH_QOS
+static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3528_grf *grf;
+ unsigned int val;
+
+ enum {
+ RK3528_GMAC1_CLK_SELET_SHIFT = 0x12,
+ RK3528_GMAC1_CLK_SELET_MASK = BIT(12),
+ RK3528_GMAC1_CLK_SELET_CRU = 0,
+ RK3528_GMAC1_CLK_SELET_IO = BIT(12),
+ };
+
+ if (!pdata->bus_id)
+ return;
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO :
+ RK3528_GMAC1_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val);
+}
+
+static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ struct rk3562_ioc *ioc;
+ unsigned int val;
+
+ enum {
+ RK3562_GMAC0_CLK_SELET_SHIFT = 0x9,
+ RK3562_GMAC0_CLK_SELET_MASK = BIT(9),
+ RK3562_GMAC0_CLK_SELET_CRU = 0,
+ RK3562_GMAC0_CLK_SELET_IO = BIT(9),
+ };
+
+ enum {
+ RK3562_GMAC1_CLK_SELET_SHIFT = 15,
+ RK3562_GMAC1_CLK_SELET_MASK = BIT(15),
+ RK3562_GMAC1_CLK_SELET_CRU = 0,
+ RK3562_GMAC1_CLK_SELET_IO = BIT(15),
+ };
+
+ enum {
+ RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2),
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0,
+ RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2),
+ };
+
+ enum {
+ RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3,
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3),
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0,
+ RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
+
+ if (!pdata->bus_id) {
+ val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO :
+ RK3562_GMAC0_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val);
+ val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
+ rk_clrsetreg(&ioc->mac0_io_con1,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
+
+ } else {
+ val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO :
+ RK3562_GMAC1_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val);
+ val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val);
+ }
+}
+
static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata)
{
struct rk3588_php_grf *php_grf;
@@ -1701,6 +2170,21 @@
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
#else
+const struct rk_gmac_ops rk3528_gmac_ops = {
+ .fix_mac_speed = rk3528_set_rgmii_speed,
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup,
+};
+
+const struct rk_gmac_ops rk3562_gmac_ops = {
+ .fix_mac_speed = rk3562_set_gmac_speed,
+ .set_to_rgmii = rk3562_set_to_rgmii,
+ .set_to_rmii = rk3562_set_to_rmii,
+ .set_clock_selection = rk3562_set_clock_selection,
+};
+
const struct rk_gmac_ops rk3568_gmac_ops = {
.fix_mac_speed = rv1126_set_rgmii_speed,
.set_to_rgmii = rk3568_set_to_rgmii,
@@ -1774,6 +2258,16 @@
.data = (ulong)&rv1108_gmac_ops },
#endif
#else
+#ifdef CONFIG_ROCKCHIP_RK3528
+ { .compatible = "rockchip,rk3528-gmac",
+ .data = (ulong)&rk3528_gmac_ops },
+#endif
+
+#ifdef CONFIG_ROCKCHIP_RK3562
+ { .compatible = "rockchip,rk3562-gmac",
+ .data = (ulong)&rk3562_gmac_ops },
+#endif
+
#ifdef CONFIG_ROCKCHIP_RK3568
{ .compatible = "rockchip,rk3568-gmac",
.data = (ulong)&rk3568_gmac_ops },
--
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