From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/staging/mt7621-pci/pci-mt7621.c | 905 +++++++++++++++++++++++++++++---------------------------
1 files changed, 472 insertions(+), 433 deletions(-)
diff --git a/kernel/drivers/staging/mt7621-pci/pci-mt7621.c b/kernel/drivers/staging/mt7621-pci/pci-mt7621.c
index a49e279..8831db3 100644
--- a/kernel/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/kernel/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -1,33 +1,10 @@
// SPDX-License-Identifier: GPL-2.0+
-/**************************************************************************
- *
- * BRIEF MODULE DESCRIPTION
+/*
+ * BRIEF MODULE DESCRIPTION
* PCI init for Ralink RT2880 solution
*
- * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
+ * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
*
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
- * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
- * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- *
- **************************************************************************
* May 2007 Bruce Chang
* Initial Release
*
@@ -36,13 +13,12 @@
*
* May 2011 Bruce Chang
* support RT6855/MT7620 PCIe
- *
- **************************************************************************
*/
#include <linux/bitops.h>
-#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
@@ -50,36 +26,46 @@
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/pci.h>
+#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include <linux/sys_soc.h>
#include <mt7621.h>
#include <ralink_regs.h>
#include "../../pci/pci.h"
-/*
- * These functions and structures provide the BIOS scan and mapping of the PCI
- * devices.
- */
+/* sysctl */
+#define MT7621_GPIO_MODE 0x60
-#define RALINK_PCIE0_CLK_EN BIT(24)
-#define RALINK_PCIE1_CLK_EN BIT(25)
-#define RALINK_PCIE2_CLK_EN BIT(26)
+/* MediaTek specific configuration registers */
+#define PCIE_FTS_NUM 0x70c
+#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
+#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
-#define RALINK_PCI_CONFIG_ADDR 0x20
-#define RALINK_PCI_CONFIG_DATA 0x24
-#define RALINK_PCI_MEMBASE 0x28
-#define RALINK_PCI_IOBASE 0x2C
-#define RALINK_PCIE0_RST BIT(24)
-#define RALINK_PCIE1_RST BIT(25)
-#define RALINK_PCIE2_RST BIT(26)
+/* rt_sysc_membase relative registers */
+#define RALINK_CLKCFG1 0x30
+/* Host-PCI bridge registers */
#define RALINK_PCI_PCICFG_ADDR 0x0000
#define RALINK_PCI_PCIMSK_ADDR 0x000C
+#define RALINK_PCI_CONFIG_ADDR 0x0020
+#define RALINK_PCI_CONFIG_DATA 0x0024
+#define RALINK_PCI_MEMBASE 0x0028
+#define RALINK_PCI_IOBASE 0x002C
-#define RT6855_PCIE0_OFFSET 0x2000
-#define RT6855_PCIE1_OFFSET 0x3000
-#define RT6855_PCIE2_OFFSET 0x4000
+/* PCICFG virtual bridges */
+#define PCIE_P2P_CNT 3
+#define PCIE_P2P_BR_DEVNUM_SHIFT(p) (16 + (p) * 4)
+#define PCIE_P2P_BR_DEVNUM0_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(0)
+#define PCIE_P2P_BR_DEVNUM1_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(1)
+#define PCIE_P2P_BR_DEVNUM2_SHIFT PCIE_P2P_BR_DEVNUM_SHIFT(2)
+#define PCIE_P2P_BR_DEVNUM_MASK 0xf
+#define PCIE_P2P_BR_DEVNUM_MASK_FULL (0xfff << PCIE_P2P_BR_DEVNUM0_SHIFT)
+
+/* PCIe RC control registers */
+#define MT7621_PCIE_OFFSET 0x2000
+#define MT7621_NEXT_PORT 0x1000
#define RALINK_PCI_BAR0SETUP_ADDR 0x0010
#define RALINK_PCI_IMBASEBAR0_ADDR 0x0018
@@ -88,54 +74,42 @@
#define RALINK_PCI_SUBID 0x0038
#define RALINK_PCI_STATUS 0x0050
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
-#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
+/* Some definition values */
+#define PCIE_REVISION_ID BIT(0)
+#define PCIE_CLASS_CODE (0x60400 << 8)
+#define PCIE_BAR_MAP_MAX GENMASK(30, 16)
+#define PCIE_BAR_ENABLE BIT(0)
+#define PCIE_PORT_INT_EN(x) BIT(20 + (x))
+#define PCIE_PORT_CLK_EN(x) BIT(24 + (x))
+#define PCIE_PORT_LINKUP BIT(0)
-#define RALINK_PCI_MM_MAP_BASE 0x60000000
-#define RALINK_PCI_IO_MAP_BASE 0x1e160000
-
-#define ASSERT_SYSRST_PCIE(val) \
- do { \
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(0, val, RALINK_RSTCTRL); \
- else \
- rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
- } while (0)
-#define DEASSERT_SYSRST_PCIE(val) \
- do { \
- if (rt_sysc_r32(SYSC_REG_CHIP_REV) == 0x00030101) \
- rt_sysc_m32(val, 0, RALINK_RSTCTRL); \
- else \
- rt_sysc_m32(0, val, RALINK_RSTCTRL); \
- } while (0)
-
-#define RALINK_CLKCFG1 0x30
-#define RALINK_RSTCTRL 0x34
-#define RALINK_GPIOMODE 0x60
-#define RALINK_PCIE_CLK_GEN 0x7c
-#define RALINK_PCIE_CLK_GEN1 0x80
-//RALINK_RSTCTRL bit
-#define RALINK_PCIE_RST BIT(23)
-#define RALINK_PCI_RST BIT(24)
-//RALINK_CLKCFG1 bit
-#define RALINK_PCI_CLK_EN BIT(19)
-#define RALINK_PCIE_CLK_EN BIT(21)
-
-#define MEMORY_BASE 0x0
-static int pcie_link_status = 0;
+#define MEMORY_BASE 0x0
+#define PERST_MODE_MASK GENMASK(11, 10)
+#define PERST_MODE_GPIO BIT(10)
+#define PERST_DELAY_MS 100
/**
* struct mt7621_pcie_port - PCIe port information
- * @base: IO mapped register base
+ * @base: I/O mapped register base
* @list: port list
* @pcie: pointer to PCIe host info
- * @reset: pointer to port reset control
+ * @phy: pointer to PHY control block
+ * @pcie_rst: pointer to port reset control
+ * @gpio_rst: gpio reset
+ * @slot: port slot
+ * @irq: GIC irq
+ * @enabled: indicates if port is enabled
*/
struct mt7621_pcie_port {
void __iomem *base;
struct list_head list;
struct mt7621_pcie *pcie;
- struct reset_control *reset;
+ struct phy *phy;
+ struct reset_control *pcie_rst;
+ struct gpio_desc *gpio_rst;
+ u32 slot;
+ int irq;
+ bool enabled;
};
/**
@@ -146,7 +120,11 @@
* @busn: bus range
* @offset: IO / Memory offset
* @dev: Pointer to PCIe device
+ * @io_map_base: virtual memory base address for io
* @ports: pointer to PCIe port information
+ * @irq_map: irq mapping info according pcie link status
+ * @resets_inverted: depends on chip revision
+ * reset lines are inverted.
*/
struct mt7621_pcie {
void __iomem *base;
@@ -158,7 +136,10 @@
resource_size_t mem;
resource_size_t io;
} offset;
+ unsigned long io_map_base;
struct list_head ports;
+ int irq_map[PCIE_P2P_CNT];
+ bool resets_inverted;
};
static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
@@ -169,6 +150,26 @@
static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
{
writel(val, pcie->base + reg);
+}
+
+static inline void pcie_rmw(struct mt7621_pcie *pcie, u32 reg, u32 clr, u32 set)
+{
+ u32 val = readl(pcie->base + reg);
+
+ val &= ~clr;
+ val |= set;
+ writel(val, pcie->base + reg);
+}
+
+static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
+{
+ return readl(port->base + reg);
+}
+
+static inline void pcie_port_write(struct mt7621_pcie_port *port,
+ u32 val, u32 reg)
+{
+ writel(val, port->base + reg);
}
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
@@ -196,8 +197,7 @@
.write = pci_generic_config_write,
};
-static u32
-read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
+static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
{
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
@@ -205,8 +205,8 @@
return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
}
-static void
-write_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg, u32 val)
+static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
+ u32 reg, u32 val)
{
u32 address = mt7621_pci_get_cfgaddr(0, dev, 0, reg);
@@ -214,128 +214,83 @@
pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
}
-void
-set_pcie_phy(struct mt7621_pcie *pcie, u32 offset,
- int start_b, int bits, int val)
+static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
{
- u32 reg = pcie_read(pcie, offset);
-
- reg &= ~(((1 << bits) - 1) << start_b);
- reg |= val << start_b;
- pcie_write(pcie, reg, offset);
+ if (port->gpio_rst)
+ gpiod_set_value(port->gpio_rst, 1);
}
-void
-bypass_pipe_rst(struct mt7621_pcie *pcie)
+static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
{
- /* PCIe Port 0 */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
- /* PCIe Port 1 */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
- /* PCIe Port 2 */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01); // rg_pe1_pipe_cmd_frc[4]
+ if (port->gpio_rst)
+ gpiod_set_value(port->gpio_rst, 0);
}
-void
-set_phy_for_ssc(struct mt7621_pcie *pcie)
+static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
{
- unsigned long reg = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG0);
-
- reg = (reg >> 6) & 0x7;
- /* Set PCIe Port0 & Port1 PHY to disable SSC */
- /* Debug Xtal Type */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00); // rg_pe1_phy_en //Port 1 disable
- if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- printk("***** Xtal 40MHz *****\n");
- } else { // 25MHz | 20MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- if (reg >= 6) {
- printk("***** Xtal 25MHz *****\n");
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
- } else {
- printk("***** Xtal 20MHz *****\n");
- }
- }
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
- }
- /* Enable PHY and disable force mode */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01); // rg_pe1_phy_en //Port 1 enable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
-
- /* Set PCIe Port2 PHY to disable SSC */
- /* Debug Xtal Type */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00); // rg_pe1_h_xtal_type
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00); // rg_pe1_phy_en //Port 0 disable
- if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- } else { // 25MHz | 20MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
- if (reg >= 6) { // 25MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for host mode)
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude control
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude control for initial
- }
- }
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02); // RG_PE1_PLL_DIVEN
- if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force mode enable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
- }
- /* Enable PHY and disable force mode */
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01); // rg_pe1_phy_en //Port 0 enable
- set_pcie_phy(pcie, (RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
+ return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
}
-static void setup_cm_memory_region(struct resource *mem_resource)
+static inline void mt7621_pcie_port_clk_enable(struct mt7621_pcie_port *port)
{
+ rt_sysc_m32(0, PCIE_PORT_CLK_EN(port->slot), RALINK_CLKCFG1);
+}
+
+static inline void mt7621_pcie_port_clk_disable(struct mt7621_pcie_port *port)
+{
+ rt_sysc_m32(PCIE_PORT_CLK_EN(port->slot), 0, RALINK_CLKCFG1);
+}
+
+static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
+{
+ struct mt7621_pcie *pcie = port->pcie;
+
+ if (pcie->resets_inverted)
+ reset_control_assert(port->pcie_rst);
+ else
+ reset_control_deassert(port->pcie_rst);
+}
+
+static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
+{
+ struct mt7621_pcie *pcie = port->pcie;
+
+ if (pcie->resets_inverted)
+ reset_control_deassert(port->pcie_rst);
+ else
+ reset_control_assert(port->pcie_rst);
+}
+
+static void setup_cm_memory_region(struct mt7621_pcie *pcie)
+{
+ struct resource *mem_resource = &pcie->mem;
+ struct device *dev = pcie->dev;
resource_size_t mask;
if (mips_cps_numiocu(0)) {
- /* FIXME: hardware doesn't accept mask values with 1s after
+ /*
+ * FIXME: hardware doesn't accept mask values with 1s after
* 0s (e.g. 0xffef), so it would be great to warn if that's
- * about to happen */
+ * about to happen
+ */
mask = ~(mem_resource->end - mem_resource->start);
write_gcr_reg1_base(mem_resource->start);
write_gcr_reg1_mask(mask | CM_GCR_REGn_MASK_CMTGT_IOCU0);
- printk("PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
+ dev_info(dev, "PCI coherence region base: 0x%08llx, mask/settings: 0x%08llx\n",
(unsigned long long)read_gcr_reg1_base(),
(unsigned long long)read_gcr_reg1_mask());
}
+}
+
+static int mt7621_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
+{
+ struct mt7621_pcie *pcie = pdev->bus->sysdata;
+ struct device *dev = pcie->dev;
+ int irq = pcie->irq_map[slot];
+
+ dev_info(dev, "bus=%d slot=%d irq=%d\n", pdev->bus->number, slot, irq);
+ return irq;
}
static int mt7621_pci_parse_request_of_pci_ranges(struct mt7621_pcie *pcie)
@@ -352,22 +307,21 @@
}
for_each_of_pci_range(&parser, &range) {
- struct resource *res = NULL;
-
switch (range.flags & IORESOURCE_TYPE_BITS) {
case IORESOURCE_IO:
- ioremap(range.cpu_addr, range.size);
- res = &pcie->io;
+ pcie->io_map_base =
+ (unsigned long)ioremap(range.cpu_addr,
+ range.size);
+ of_pci_range_to_resource(&range, node, &pcie->io);
+ pcie->io.start = range.cpu_addr;
+ pcie->io.end = range.cpu_addr + range.size - 1;
pcie->offset.io = 0x00000000UL;
break;
case IORESOURCE_MEM:
- res = &pcie->mem;
+ of_pci_range_to_resource(&range, node, &pcie->mem);
pcie->offset.mem = 0x00000000UL;
break;
}
-
- if (res != NULL)
- of_pci_range_to_resource(&range, node, res);
}
err = of_pci_parse_bus_range(node, &pcie->busn);
@@ -379,22 +333,77 @@
pcie->busn.flags = IORESOURCE_BUS;
}
+ set_io_port_base(pcie->io_map_base);
+
+ return 0;
+}
+
+static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
+ struct device_node *node,
+ int slot)
+{
+ struct mt7621_pcie_port *port;
+ struct device *dev = pcie->dev;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct device_node *pnode = dev->of_node;
+ struct resource regs;
+ char name[10];
+ int err;
+
+ port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return -ENOMEM;
+
+ err = of_address_to_resource(pnode, slot + 1, ®s);
+ if (err) {
+ dev_err(dev, "missing \"reg\" property\n");
+ return err;
+ }
+
+ port->base = devm_ioremap_resource(dev, ®s);
+ if (IS_ERR(port->base))
+ return PTR_ERR(port->base);
+
+ snprintf(name, sizeof(name), "pcie%d", slot);
+ port->pcie_rst = devm_reset_control_get_exclusive(dev, name);
+ if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
+ dev_err(dev, "failed to get pcie%d reset control\n", slot);
+ return PTR_ERR(port->pcie_rst);
+ }
+
+ snprintf(name, sizeof(name), "pcie-phy%d", slot);
+ port->phy = devm_phy_get(dev, name);
+ if (IS_ERR(port->phy) && slot != 1)
+ return PTR_ERR(port->phy);
+
+ port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
+ GPIOD_OUT_LOW);
+ if (IS_ERR(port->gpio_rst)) {
+ dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
+ return PTR_ERR(port->gpio_rst);
+ }
+
+ port->slot = slot;
+ port->pcie = pcie;
+
+ port->irq = platform_get_irq(pdev, slot);
+ if (port->irq < 0) {
+ dev_err(dev, "Failed to get IRQ for PCIe%d\n", slot);
+ return -ENXIO;
+ }
+
+ INIT_LIST_HEAD(&port->list);
+ list_add_tail(&port->list, &pcie->ports);
+
return 0;
}
static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
{
struct device *dev = pcie->dev;
- struct device_node *node = dev->of_node;
+ struct device_node *node = dev->of_node, *child;
struct resource regs;
- const char *type;
int err;
-
- type = of_get_property(node, "device_type", NULL);
- if (!type || strcmp(type, "pci") != 0) {
- dev_err(dev, "invalid \"device_type\" %s\n", type);
- return -EINVAL;
- }
err = of_address_to_resource(node, 0, ®s);
if (err) {
@@ -406,24 +415,249 @@
if (IS_ERR(pcie->base))
return PTR_ERR(pcie->base);
+ for_each_available_child_of_node(node, child) {
+ int slot;
+
+ err = of_pci_get_devfn(child);
+ if (err < 0) {
+ of_node_put(child);
+ dev_err(dev, "failed to parse devfn: %d\n", err);
+ return err;
+ }
+
+ slot = PCI_SLOT(err);
+
+ err = mt7621_pcie_parse_port(pcie, child, slot);
+ if (err) {
+ of_node_put(child);
+ return err;
+ }
+ }
+
return 0;
}
-static int mt7621_pcie_request_resources(struct mt7621_pcie *pcie,
- struct list_head *res)
+static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
{
+ struct mt7621_pcie *pcie = port->pcie;
struct device *dev = pcie->dev;
+ u32 slot = port->slot;
int err;
- pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
- pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
- pci_add_resource(res, &pcie->busn);
-
- err = devm_request_pci_bus_resources(dev, res);
- if (err < 0)
+ err = phy_init(port->phy);
+ if (err) {
+ dev_err(dev, "failed to initialize port%d phy\n", slot);
return err;
+ }
+
+ err = phy_power_on(port->phy);
+ if (err) {
+ dev_err(dev, "failed to power on port%d phy\n", slot);
+ phy_exit(port->phy);
+ return err;
+ }
+
+ port->enabled = true;
return 0;
+}
+
+static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
+{
+ struct mt7621_pcie_port *port;
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ /* PCIe RC reset assert */
+ mt7621_control_assert(port);
+
+ /* PCIe EP reset assert */
+ mt7621_rst_gpio_pcie_assert(port);
+ }
+
+ mdelay(PERST_DELAY_MS);
+}
+
+static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
+{
+ struct mt7621_pcie_port *port;
+
+ list_for_each_entry(port, &pcie->ports, list)
+ mt7621_control_deassert(port);
+}
+
+static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
+{
+ struct mt7621_pcie_port *port;
+
+ list_for_each_entry(port, &pcie->ports, list)
+ mt7621_rst_gpio_pcie_deassert(port);
+
+ mdelay(PERST_DELAY_MS);
+}
+
+static void mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ struct mt7621_pcie_port *port, *tmp;
+ int err;
+
+ rt_sysc_m32(PERST_MODE_MASK, PERST_MODE_GPIO, MT7621_GPIO_MODE);
+
+ mt7621_pcie_reset_assert(pcie);
+ mt7621_pcie_reset_rc_deassert(pcie);
+
+ list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
+ u32 slot = port->slot;
+
+ if (slot == 1) {
+ port->enabled = true;
+ continue;
+ }
+
+ err = mt7621_pcie_init_port(port);
+ if (err) {
+ dev_err(dev, "Initiating port %d failed\n", slot);
+ list_del(&port->list);
+ }
+ }
+
+ mt7621_pcie_reset_ep_deassert(pcie);
+
+ tmp = NULL;
+ list_for_each_entry(port, &pcie->ports, list) {
+ u32 slot = port->slot;
+
+ if (!mt7621_pcie_port_is_linkup(port)) {
+ dev_err(dev, "pcie%d no card, disable it (RST & CLK)\n",
+ slot);
+ mt7621_control_assert(port);
+ mt7621_pcie_port_clk_disable(port);
+ port->enabled = false;
+
+ if (slot == 0) {
+ tmp = port;
+ continue;
+ }
+
+ if (slot == 1 && tmp && !tmp->enabled)
+ phy_power_off(tmp->phy);
+
+ }
+ }
+}
+
+static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
+{
+ struct mt7621_pcie *pcie = port->pcie;
+ u32 slot = port->slot;
+ u32 offset = MT7621_PCIE_OFFSET + (slot * MT7621_NEXT_PORT);
+ u32 val;
+
+ /* enable pcie interrupt */
+ val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
+ val |= PCIE_PORT_INT_EN(slot);
+ pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
+
+ /* map 2G DDR region */
+ pcie_write(pcie, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
+ offset + RALINK_PCI_BAR0SETUP_ADDR);
+ pcie_write(pcie, MEMORY_BASE,
+ offset + RALINK_PCI_IMBASEBAR0_ADDR);
+
+ /* configure class code and revision ID */
+ pcie_write(pcie, PCIE_CLASS_CODE | PCIE_REVISION_ID,
+ offset + RALINK_PCI_CLASS);
+}
+
+static void mt7621_pcie_enable_ports(struct mt7621_pcie *pcie)
+{
+ struct device *dev = pcie->dev;
+ struct mt7621_pcie_port *port;
+ u8 num_slots_enabled = 0;
+ u32 slot;
+ u32 val;
+
+ /* Setup MEMWIN and IOWIN */
+ pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
+ pcie_write(pcie, pcie->io.start, RALINK_PCI_IOBASE);
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ if (port->enabled) {
+ mt7621_pcie_port_clk_enable(port);
+ mt7621_pcie_enable_port(port);
+ dev_info(dev, "PCIE%d enabled\n", port->slot);
+ num_slots_enabled++;
+ }
+ }
+
+ for (slot = 0; slot < num_slots_enabled; slot++) {
+ val = read_config(pcie, slot, PCI_COMMAND);
+ val |= PCI_COMMAND_MASTER;
+ write_config(pcie, slot, PCI_COMMAND, val);
+ /* configure RC FTS number to 250 when it leaves L0s */
+ val = read_config(pcie, slot, PCIE_FTS_NUM);
+ val &= ~PCIE_FTS_NUM_MASK;
+ val |= PCIE_FTS_NUM_L0(0x50);
+ write_config(pcie, slot, PCIE_FTS_NUM, val);
+ }
+}
+
+static int mt7621_pcie_init_virtual_bridges(struct mt7621_pcie *pcie)
+{
+ u32 pcie_link_status = 0;
+ u32 n = 0;
+ int i = 0;
+ u32 p2p_br_devnum[PCIE_P2P_CNT];
+ int irqs[PCIE_P2P_CNT];
+ struct mt7621_pcie_port *port;
+
+ list_for_each_entry(port, &pcie->ports, list) {
+ u32 slot = port->slot;
+
+ irqs[i++] = port->irq;
+ if (port->enabled)
+ pcie_link_status |= BIT(slot);
+ }
+
+ if (pcie_link_status == 0)
+ return -1;
+
+ /*
+ * Assign device numbers from zero to the enabled ports,
+ * then assigning remaining device numbers to any disabled
+ * ports.
+ */
+ for (i = 0; i < PCIE_P2P_CNT; i++)
+ if (pcie_link_status & BIT(i))
+ p2p_br_devnum[i] = n++;
+
+ for (i = 0; i < PCIE_P2P_CNT; i++)
+ if ((pcie_link_status & BIT(i)) == 0)
+ p2p_br_devnum[i] = n++;
+
+ pcie_rmw(pcie, RALINK_PCI_PCICFG_ADDR,
+ PCIE_P2P_BR_DEVNUM_MASK_FULL,
+ (p2p_br_devnum[0] << PCIE_P2P_BR_DEVNUM0_SHIFT) |
+ (p2p_br_devnum[1] << PCIE_P2P_BR_DEVNUM1_SHIFT) |
+ (p2p_br_devnum[2] << PCIE_P2P_BR_DEVNUM2_SHIFT));
+
+ /* Assign IRQs */
+ n = 0;
+ for (i = 0; i < PCIE_P2P_CNT; i++)
+ if (pcie_link_status & BIT(i))
+ pcie->irq_map[n++] = irqs[i];
+
+ for (i = n; i < PCIE_P2P_CNT; i++)
+ pcie->irq_map[i] = -1;
+
+ return 0;
+}
+
+static void mt7621_pcie_add_resources(struct mt7621_pcie *pcie,
+ struct list_head *res)
+{
+ pci_add_resource_offset(res, &pcie->io, pcie->offset.io);
+ pci_add_resource_offset(res, &pcie->mem, pcie->offset.mem);
}
static int mt7621_pcie_register_host(struct pci_host_bridge *host,
@@ -435,20 +669,24 @@
host->busnr = pcie->busn.start;
host->dev.parent = pcie->dev;
host->ops = &mt7621_pci_ops;
- host->map_irq = of_irq_parse_and_map_pci;
+ host->map_irq = mt7621_map_irq;
host->swizzle_irq = pci_common_swizzle;
host->sysdata = pcie;
return pci_host_probe(host);
}
+static const struct soc_device_attribute mt7621_pci_quirks_match[] = {
+ { .soc_id = "mt7621", .revision = "E2" }
+};
+
static int mt7621_pci_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
+ const struct soc_device_attribute *attr;
struct mt7621_pcie *pcie;
struct pci_host_bridge *bridge;
int err;
- u32 val = 0;
LIST_HEAD(res);
if (!dev->of_node)
@@ -456,225 +694,21 @@
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
if (!bridge)
- return -ENODEV;
+ return -ENOMEM;
pcie = pci_host_bridge_priv(bridge);
pcie->dev = dev;
platform_set_drvdata(pdev, pcie);
INIT_LIST_HEAD(&pcie->ports);
+ attr = soc_device_match(mt7621_pci_quirks_match);
+ if (attr)
+ pcie->resets_inverted = true;
+
err = mt7621_pcie_parse_dt(pcie);
if (err) {
dev_err(dev, "Parsing DT failed\n");
return err;
- }
-
- /* set resources limits */
- iomem_resource.start = 0;
- iomem_resource.end = ~0UL; /* no limit */
- ioport_resource.start = 0;
- ioport_resource.end = ~0UL; /* no limit */
-
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
-
- *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
- *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
- mdelay(100);
- *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
- mdelay(100);
- *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7); // clear DATA
-
- mdelay(100);
-
- val = RALINK_PCIE0_RST;
- val |= RALINK_PCIE1_RST;
- val |= RALINK_PCIE2_RST;
-
- DEASSERT_SYSRST_PCIE(val);
-
- if ((*(unsigned int *)(0xbe00000c)&0xFFFF) == 0x0101) // MT7621 E2
- bypass_pipe_rst(pcie);
- set_phy_for_ssc(pcie);
-
- val = read_config(pcie, 0, 0x70c);
- printk("Port 0 N_FTS = %x\n", (unsigned int)val);
-
- val = read_config(pcie, 1, 0x70c);
- printk("Port 1 N_FTS = %x\n", (unsigned int)val);
-
- val = read_config(pcie, 2, 0x70c);
- printk("Port 2 N_FTS = %x\n", (unsigned int)val);
-
- rt_sysc_m32(0, RALINK_PCIE_RST, RALINK_RSTCTRL);
- rt_sysc_m32(0x30, 2 << 4, SYSC_REG_SYSTEM_CONFIG1);
-
- rt_sysc_m32(0x80000000, 0, RALINK_PCIE_CLK_GEN);
- rt_sysc_m32(0x7f000000, 0xa << 24, RALINK_PCIE_CLK_GEN1);
- rt_sysc_m32(0, 0x80000000, RALINK_PCIE_CLK_GEN);
-
- mdelay(50);
- rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
-
- /* Use GPIO control instead of PERST_N */
- *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // set DATA
- mdelay(1000);
-
- if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
- printk("PCIE0 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
- rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(1<<0);
- } else {
- pcie_link_status |= 1<<0;
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= (1<<20); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE1_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
- printk("PCIE1 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
- rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(1<<1);
- } else {
- pcie_link_status |= 1<<1;
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= (1<<21); // enable pcie1 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if ((pcie_read(pcie, RT6855_PCIE2_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
- printk("PCIE2 no card, disable it(RST&CLK)\n");
- ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
- rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
- pcie_link_status &= ~(1<<2);
- } else {
- pcie_link_status |= 1<<2;
- val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
- val |= (1<<22); // enable pcie2 interrupt
- pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
- }
-
- if (pcie_link_status == 0)
- return 0;
-
-/*
-pcie(2/1/0) link status pcie2_num pcie1_num pcie0_num
-3'b000 x x x
-3'b001 x x 0
-3'b010 x 0 x
-3'b011 x 1 0
-3'b100 0 x x
-3'b101 1 x 0
-3'b110 1 0 x
-3'b111 2 1 0
-*/
- switch (pcie_link_status) {
- case 2:
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val &= ~0x00ff0000;
- val |= 0x1 << 16; // port 0
- val |= 0x0 << 20; // port 1
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
- break;
- case 4:
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val &= ~0x0fff0000;
- val |= 0x1 << 16; //port0
- val |= 0x2 << 20; //port1
- val |= 0x0 << 24; //port2
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
- break;
- case 5:
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val &= ~0x0fff0000;
- val |= 0x0 << 16; //port0
- val |= 0x2 << 20; //port1
- val |= 0x1 << 24; //port2
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
- break;
- case 6:
- val = pcie_read(pcie, RALINK_PCI_PCICFG_ADDR);
- val &= ~0x0fff0000;
- val |= 0x2 << 16; //port0
- val |= 0x0 << 20; //port1
- val |= 0x1 << 24; //port2
- pcie_write(pcie, val, RALINK_PCI_PCICFG_ADDR);
- break;
- }
-
-/*
- ioport_resource.start = mt7621_res_pci_io1.start;
- ioport_resource.end = mt7621_res_pci_io1.end;
-*/
-
- pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
- pcie_write(pcie, RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
-
- //PCIe0
- if ((pcie_link_status & 0x1) != 0) {
- /* open 7FFF:2G; ENABLE */
- pcie_write(pcie, 0x7FFF0001,
- RT6855_PCIE0_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
- pcie_write(pcie, MEMORY_BASE,
- RT6855_PCIE0_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
- pcie_write(pcie, 0x06040001,
- RT6855_PCIE0_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE0 enabled\n");
- }
-
- //PCIe1
- if ((pcie_link_status & 0x2) != 0) {
- /* open 7FFF:2G; ENABLE */
- pcie_write(pcie, 0x7FFF0001,
- RT6855_PCIE1_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
- pcie_write(pcie, MEMORY_BASE,
- RT6855_PCIE1_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
- pcie_write(pcie, 0x06040001,
- RT6855_PCIE1_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE1 enabled\n");
- }
-
- //PCIe2
- if ((pcie_link_status & 0x4) != 0) {
- /* open 7FFF:2G; ENABLE */
- pcie_write(pcie, 0x7FFF0001,
- RT6855_PCIE2_OFFSET + RALINK_PCI_BAR0SETUP_ADDR);
- pcie_write(pcie, MEMORY_BASE,
- RT6855_PCIE2_OFFSET + RALINK_PCI_IMBASEBAR0_ADDR);
- pcie_write(pcie, 0x06040001,
- RT6855_PCIE2_OFFSET + RALINK_PCI_CLASS);
- printk("PCIE2 enabled\n");
- }
-
- switch (pcie_link_status) {
- case 7:
- val = read_config(pcie, 2, 0x4);
- write_config(pcie, 2, 0x4, val|0x4);
- val = read_config(pcie, 2, 0x70c);
- val &= ~(0xff)<<8;
- val |= 0x50<<8;
- write_config(pcie, 2, 0x70c, val);
- case 3:
- case 5:
- case 6:
- val = read_config(pcie, 1, 0x4);
- write_config(pcie, 1, 0x4, val|0x4);
- val = read_config(pcie, 1, 0x70c);
- val &= ~(0xff)<<8;
- val |= 0x50<<8;
- write_config(pcie, 1, 0x70c, val);
- default:
- val = read_config(pcie, 0, 0x4);
- write_config(pcie, 0, 0x4, val|0x4); //bus master enable
- val = read_config(pcie, 0, 0x70c);
- val &= ~(0xff)<<8;
- val |= 0x50<<8;
- write_config(pcie, 0, 0x70c, val);
}
err = mt7621_pci_parse_request_of_pci_ranges(pcie);
@@ -683,13 +717,23 @@
return err;
}
- setup_cm_memory_region(&pcie->mem);
+ /* set resources limits */
+ ioport_resource.start = pcie->io.start;
+ ioport_resource.end = pcie->io.end;
- err = mt7621_pcie_request_resources(pcie, &res);
+ mt7621_pcie_init_ports(pcie);
+
+ err = mt7621_pcie_init_virtual_bridges(pcie);
if (err) {
- dev_err(dev, "Error requesting resources\n");
- return err;
+ dev_err(dev, "Nothing is connected in virtual bridges. Exiting...");
+ return 0;
}
+
+ mt7621_pcie_enable_ports(pcie);
+
+ setup_cm_memory_region(pcie);
+
+ mt7621_pcie_add_resources(pcie, &res);
err = mt7621_pcie_register_host(bridge, &res);
if (err) {
@@ -714,9 +758,4 @@
},
};
-static int __init mt7621_pci_init(void)
-{
- return platform_driver_register(&mt7621_pci_driver);
-}
-
-arch_initcall(mt7621_pci_init);
+builtin_platform_driver(mt7621_pci_driver);
--
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