From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c | 79 +++++++--------------------------------
1 files changed, 15 insertions(+), 64 deletions(-)
diff --git a/kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c b/kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c
index 3ace4ab..e051b1a 100644
--- a/kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c
+++ b/kernel/drivers/phy/rockchip/phy-rockchip-naneng-usb2.c
@@ -109,7 +109,6 @@
* @ls_det_en: linestate detection enable register.
* @ls_det_st: linestate detection state register.
* @ls_det_clr: linestate detection clear register.
- * @phy_chg_mode: set phy in charge detection mode.
* @phy_sus: phy suspend register.
* @utmi_bvalid: utmi vbus bvalid status register.
* @utmi_iddig: otg port id pin status register.
@@ -141,7 +140,6 @@
struct usb2phy_reg ls_det_en;
struct usb2phy_reg ls_det_st;
struct usb2phy_reg ls_det_clr;
- struct usb2phy_reg phy_chg_mode;
struct usb2phy_reg phy_sus;
struct usb2phy_reg utmi_bvalid;
struct usb2phy_reg utmi_iddig;
@@ -221,7 +219,6 @@
* @dev: pointer to our struct device.
* @grf: General Register Files regmap.
* @base: the base address of APB interface.
- * @apb_reset: apb reset signal for phy.
* @reset: power reset signal for phy.
* @clks: array of input clocks.
* @num_clks: number of input clocks.
@@ -240,7 +237,6 @@
struct device *dev;
struct regmap *grf;
void __iomem *base;
- struct reset_control *apb_reset;
struct reset_control *reset;
struct clk_bulk_data *clks;
int num_clks;
@@ -358,7 +354,7 @@
/* optional override of the clockname */
of_property_read_string(node, "clock-output-names", &init.name);
- if (refclk) {
+ if (!IS_ERR(refclk)) {
clk_name = __clk_get_name(refclk);
init.parent_names = &clk_name;
init.num_parents = 1;
@@ -663,7 +659,8 @@
return ret;
}
-static int rockchip_usb2phy_set_mode(struct phy *phy, enum phy_mode mode)
+static int rockchip_usb2phy_set_mode(struct phy *phy,
+ enum phy_mode mode, int submode)
{
struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
@@ -800,45 +797,12 @@
struct rockchip_usb2phy_port *rport)
{
bool chg_valid, phy_connect;
- const struct usb2phy_reg *phy_sus_reg;
- unsigned int phy_sus_cfg, mask;
- int result, cnt, ret;
+ int result;
+ int cnt;
mutex_lock(&rport->mutex);
- /*
- * We are violating what the phy specification says about
- * the charge detection process. Ideally we need to hold
- * the phy in the reset state during the charge detection
- * process, but that's causing trouble synchronizing between
- * the phy and usb controller because CLK60_30 is disabled
- * while phy in reset.
- *
- * We have discussed this with the phy IP Provider, and
- * it was suggested to keep the CLK60_30 while do charging
- * detection.
- *
- * Set the phy in charge mode (keep the CLK60_30):
- * Enable the DP/DM pulldown resistor;
- * Set the opmode to non-driving mode;
- * Set the phy controlled by GRF utmi interface, and set
- * the utmi in normal mode to keep the CLK60_30.
- */
- phy_sus_reg = &rport->port_cfg->phy_sus;
- ret = regmap_read(rphy->grf, phy_sus_reg->offset, &phy_sus_cfg);
- if (ret) {
- dev_err(&rport->phy->dev,
- "Fail to read phy_sus reg offset 0x%x, ret %d\n",
- phy_sus_reg->offset, ret);
- goto unlock;
- }
-
- ret = property_enable(rphy->grf, &rport->port_cfg->phy_chg_mode, true);
- if (ret) {
- dev_err(&rport->phy->dev,
- "Fail to set phy_chg_mode reg, ret %d\n", ret);
- goto unlock;
- }
+ reset_control_assert(rphy->reset);
/* CHG_RST is set to 1'b0 to start charge detection */
property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, true);
@@ -878,21 +842,15 @@
dev_info(&rport->phy->dev, "charger = %s\n",
chg_to_string(rphy->chg_type));
+ usleep_range(1000, 1100);
+ reset_control_deassert(rphy->reset);
+ /* waiting for the utmi_clk to become stable */
+ usleep_range(2500, 3000);
+
/* disable the chg detection module */
property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_rst, true);
property_enable(rphy->grf, &rphy->phy_cfg->chg_det.chg_en, false);
- mask = GENMASK(phy_sus_reg->bitend, phy_sus_reg->bitstart);
- /* Restore the phy suspend configuration */
- ret = regmap_write(rphy->grf, phy_sus_reg->offset,
- ((phy_sus_cfg << phy_sus_reg->bitstart) |
- (mask << BIT_WRITEABLE_SHIFT)));
- if (ret)
- dev_err(&rport->phy->dev,
- "Fail to set phy_sus reg offset 0x%x, ret %d\n",
- phy_sus_reg->offset, ret);
-
-unlock:
mutex_unlock(&rport->mutex);
}
@@ -1120,7 +1078,7 @@
extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
extcon_sync(rphy->edev, EXTCON_USB);
extcon_sync(rphy->edev, EXTCON_USB_HOST);
- rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST);
+ rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
property_enable(rphy->grf, &rport->port_cfg->idpullup,
false);
property_enable(rphy->grf, &rport->port_cfg->iddig_output,
@@ -1129,7 +1087,7 @@
true);
break;
case USB_DR_MODE_PERIPHERAL:
- rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE);
+ rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_DEVICE, 0);
property_enable(rphy->grf, &rport->port_cfg->idpullup,
true);
property_enable(rphy->grf, &rport->port_cfg->iddig_output,
@@ -1138,7 +1096,7 @@
true);
break;
case USB_DR_MODE_OTG:
- rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG);
+ rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_OTG, 0);
property_enable(rphy->grf, &rport->port_cfg->iddig_output,
false);
property_enable(rphy->grf, &rport->port_cfg->iddig_en,
@@ -1309,7 +1267,7 @@
extcon_set_state(rphy->edev, EXTCON_USB, false);
extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
}
- rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST);
+ rockchip_usb2phy_set_mode(rport->phy, PHY_MODE_USB_HOST, 0);
/*
* Here set iddig to 0 by disable idpullup, the otg_suspendm
* will be set to 1 to enable the disconnect detection module,
@@ -1509,10 +1467,6 @@
if (IS_ERR(rphy->reset))
return PTR_ERR(rphy->reset);
- rphy->apb_reset = devm_reset_control_get(dev, "u2phy-apb");
- if (IS_ERR(rphy->apb_reset))
- return PTR_ERR(rphy->apb_reset);
-
rphy->vup_gpio = devm_gpiod_get_optional(dev, "vup", GPIOD_OUT_LOW);
if (IS_ERR(rphy->vup_gpio)) {
ret = PTR_ERR(rphy->vup_gpio);
@@ -1520,11 +1474,9 @@
return ret;
}
- reset_control_assert(rphy->apb_reset);
reset_control_assert(rphy->reset);
udelay(1);
reset_control_deassert(rphy->reset);
- reset_control_deassert(rphy->apb_reset);
match = of_match_device(dev->driver->of_match_table, dev);
if (!match || !match->data) {
@@ -1914,7 +1866,6 @@
.ls_det_en = { 0x10300, 0, 0, 0, 1 },
.ls_det_st = { 0x10304, 0, 0, 0, 1 },
.ls_det_clr = { 0x10308, 0, 0, 0, 1 },
- .phy_chg_mode = { 0x10230, 8, 0, 0x052, 0x1d7 },
.phy_sus = { 0x10230, 8, 0, 0x052, 0x1d5 },
.utmi_bvalid = { 0x10248, 9, 9, 0, 1 },
.utmi_iddig = { 0x10248, 6, 6, 0, 1 },
--
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