From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c | 444 +++++++++++--------------------------------------------
1 files changed, 92 insertions(+), 352 deletions(-)
diff --git a/kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c b/kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c
index d1304a8..4166d4b 100644
--- a/kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c
+++ b/kernel/drivers/phy/rockchip/phy-rockchip-inno-video-combo-phy.c
@@ -14,12 +14,10 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
-#include <linux/regmap.h>
#include <linux/reset.h>
#include <linux/phy/phy.h>
#include <linux/pm_runtime.h>
#include <linux/mfd/syscon.h>
-#include <linux/rockchip/cpu.h>
#define PSEC_PER_SEC 1000000000000LL
@@ -84,27 +82,12 @@
#define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
#define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
/* Analog Register Part: reg08 */
-#define PRE_EMPHASIS_ENABLE_MASK BIT(7)
-#define PRE_EMPHASIS_ENABLE BIT(7)
-#define PRE_EMPHASIS_DISABLE 0
-#define PLL_POST_DIV_ENABLE_MASK BIT(5)
-#define PLL_POST_DIV_ENABLE BIT(5)
-#define PLL_POST_DIV_DISABLE 0
-#define DATA_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
-#define DATA_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
#define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
#define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
#define SAMPLE_CLOCK_DIRECTION_FORWARD 0
#define LOWFRE_EN_MASK BIT(5)
#define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
#define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
-/* Analog Register Part: reg0b */
-#define CLOCK_LANE_VOD_RANGE_SET_MASK GENMASK(3, 0)
-#define CLOCK_LANE_VOD_RANGE_SET(x) UPDATE(x, 3, 0)
-#define VOD_MIN_RANGE 0x1
-#define VOD_MID_RANGE 0x3
-#define VOD_BIG_RANGE 0x7
-#define VOD_MAX_RANGE 0xf
/* Analog Register Part: reg1e */
#define PLL_MODE_SEL_MASK GENMASK(6, 5)
#define PLL_MODE_SEL_LVDS_MODE 0
@@ -124,22 +107,20 @@
#define T_LPX_CNT_MASK GENMASK(5, 0)
#define T_LPX_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
-#define T_HS_ZERO_CNT_HI_MASK BIT(7)
-#define T_HS_ZERO_CNT_HI(x) UPDATE(x, 7, 7)
#define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
#define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
-#define T_HS_ZERO_CNT_LO_MASK GENMASK(5, 0)
-#define T_HS_ZERO_CNT_LO(x) UPDATE(x, 5, 0)
+#define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
+#define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
#define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
#define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
-#define T_HS_EXIT_CNT_LO_MASK GENMASK(4, 0)
-#define T_HS_EXIT_CNT_LO(x) UPDATE(x, 4, 0)
+#define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
+#define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
-#define T_CLK_POST_CNT_LO_MASK GENMASK(3, 0)
-#define T_CLK_POST_CNT_LO(x) UPDATE(x, 3, 0)
+#define T_CLK_POST_CNT_MASK GENMASK(3, 0)
+#define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
#define LPDT_TX_PPI_SYNC_MASK BIT(2)
#define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
@@ -153,13 +134,9 @@
#define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
#define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
-#define T_CLK_POST_HI_MASK GENMASK(7, 6)
-#define T_CLK_POST_HI(x) UPDATE(x, 7, 6)
#define T_TA_GO_CNT_MASK GENMASK(5, 0)
#define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
-#define T_HS_EXIT_CNT_HI_MASK BIT(6)
-#define T_HS_EXIT_CNT_HI(x) UPDATE(x, 6, 6)
#define T_TA_SURE_CNT_MASK GENMASK(5, 0)
#define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
/* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
@@ -197,19 +174,6 @@
#define DSI_PHY_STATUS 0xb0
#define PHY_LOCK BIT(0)
-enum soc_type {
- PX30,
- PX30S,
- RK3128,
- RK3368,
- RK3568,
-};
-
-enum phy_max_rate {
- MAX_1GHZ,
- MAX_2_5GHZ,
-};
-
struct mipi_dphy_timing {
unsigned int clkmiss;
unsigned int clkpost;
@@ -235,26 +199,14 @@
unsigned int wakeup;
};
-struct inno_mipi_dphy_timing {
- unsigned int max_lane_mbps;
- u8 lpx;
- u8 hs_prepare;
- u8 clk_lane_hs_zero;
- u8 data_lane_hs_zero;
- u8 hs_trail;
-};
-
struct inno_video_phy {
struct device *dev;
struct clk *ref_clk;
struct clk *pclk_phy;
struct clk *pclk_host;
- struct regmap *regmap;
+ void __iomem *phy_base;
void __iomem *host_base;
struct reset_control *rst;
- enum phy_mode mode;
- unsigned int lanes;
- const struct inno_video_phy_plat_data *pdata;
struct {
struct clk_hw hw;
@@ -262,13 +214,6 @@
u16 fbdiv;
unsigned long rate;
} pll;
-};
-
-struct inno_video_phy_plat_data {
- enum soc_type soc_type;
- const struct inno_mipi_dphy_timing *inno_mipi_dphy_timing_table;
- const unsigned int num_timings;
- enum phy_max_rate max_rate;
};
enum {
@@ -282,44 +227,6 @@
REGISTER_PART_LVDS,
};
-static const
-struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_1GHz[] = {
- { 110, 0x0, 0x20, 0x16, 0x02, 0x22},
- { 150, 0x0, 0x06, 0x16, 0x03, 0x45},
- { 200, 0x0, 0x18, 0x17, 0x04, 0x0b},
- { 250, 0x0, 0x05, 0x17, 0x05, 0x16},
- { 300, 0x0, 0x51, 0x18, 0x06, 0x2c},
- { 400, 0x0, 0x64, 0x19, 0x07, 0x33},
- { 500, 0x0, 0x20, 0x1b, 0x07, 0x4e},
- { 600, 0x0, 0x6a, 0x1d, 0x08, 0x3a},
- { 700, 0x0, 0x3e, 0x1e, 0x08, 0x6a},
- { 800, 0x0, 0x21, 0x1f, 0x09, 0x29},
- {1000, 0x0, 0x09, 0x20, 0x09, 0x27},
-};
-
-static const
-struct inno_mipi_dphy_timing inno_mipi_dphy_timing_table_max_2_5GHz[] = {
- { 110, 0x02, 0x7f, 0x16, 0x02, 0x02},
- { 150, 0x02, 0x7f, 0x16, 0x03, 0x02},
- { 200, 0x02, 0x7f, 0x17, 0x04, 0x02},
- { 250, 0x02, 0x7f, 0x17, 0x05, 0x04},
- { 300, 0x02, 0x7f, 0x18, 0x06, 0x04},
- { 400, 0x03, 0x7e, 0x19, 0x07, 0x04},
- { 500, 0x03, 0x7c, 0x1b, 0x07, 0x08},
- { 600, 0x03, 0x70, 0x1d, 0x08, 0x10},
- { 700, 0x05, 0x40, 0x1e, 0x08, 0x30},
- { 800, 0x05, 0x02, 0x1f, 0x09, 0x30},
- {1000, 0x05, 0x08, 0x20, 0x09, 0x30},
- {1200, 0x06, 0x03, 0x32, 0x14, 0x0f},
- {1400, 0x09, 0x03, 0x32, 0x14, 0x0f},
- {1600, 0x0d, 0x42, 0x36, 0x0e, 0x0f},
- {1800, 0x0e, 0x47, 0x7a, 0x0e, 0x0f},
- {2000, 0x11, 0x64, 0x7a, 0x0e, 0x0b},
- {2200, 0x13, 0x64, 0x7e, 0x15, 0x0b},
- {2400, 0x13, 0x33, 0x7f, 0x15, 0x6a},
- {2500, 0x15, 0x54, 0x7f, 0x15, 0x6a},
-};
-
static inline struct inno_video_phy *hw_to_inno(struct clk_hw *hw)
{
return container_of(hw, struct inno_video_phy, pll.hw);
@@ -329,8 +236,12 @@
u8 first, u8 second, u8 mask, u8 val)
{
u32 reg = PHY_REG(first, second) << 2;
+ unsigned int tmp, orig;
- regmap_update_bits(inno->regmap, reg, mask, val);
+ orig = readl(inno->phy_base + reg);
+ tmp = orig & ~mask;
+ tmp |= val & mask;
+ writel(tmp, inno->phy_base + reg);
}
static void host_update_bits(struct inno_video_phy *inno,
@@ -372,49 +283,37 @@
timing->wakeup = 1000000000;
}
-static const struct inno_mipi_dphy_timing *
-inno_mipi_dphy_get_timing(struct inno_video_phy *inno)
+static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
{
- const struct inno_mipi_dphy_timing *timings;
- unsigned int num_timings;
- unsigned int lane_mbps = inno->pll.rate / USEC_PER_SEC;
+ struct mipi_dphy_timing gotp;
+ const struct {
+ unsigned long rate;
+ u8 hs_prepare;
+ u8 clk_lane_hs_zero;
+ u8 data_lane_hs_zero;
+ u8 hs_trail;
+ } timings[] = {
+ { 110000000, 0x20, 0x16, 0x02, 0x22},
+ { 150000000, 0x06, 0x16, 0x03, 0x45},
+ { 200000000, 0x18, 0x17, 0x04, 0x0b},
+ { 250000000, 0x05, 0x17, 0x05, 0x16},
+ { 300000000, 0x51, 0x18, 0x06, 0x2c},
+ { 400000000, 0x64, 0x19, 0x07, 0x33},
+ { 500000000, 0x20, 0x1b, 0x07, 0x4e},
+ { 600000000, 0x6a, 0x1d, 0x08, 0x3a},
+ { 700000000, 0x3e, 0x1e, 0x08, 0x6a},
+ { 800000000, 0x21, 0x1f, 0x09, 0x29},
+ {1000000000, 0x09, 0x20, 0x09, 0x27},
+ };
+ u32 t_txbyteclkhs, t_txclkesc, ui;
+ u32 txbyteclkhs, txclkesc, esc_clk_div;
+ u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
+ u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
unsigned int i;
- timings = inno->pdata->inno_mipi_dphy_timing_table;
- num_timings = inno->pdata->num_timings;
-
- for (i = 0; i < num_timings; i++)
- if (lane_mbps <= timings[i].max_lane_mbps)
- break;
-
- if (i == num_timings)
- --i;
-
- return &timings[i];
-
-}
-
-static void inno_mipi_dphy_max_2_5GHz_pll_enable(struct inno_video_phy *inno)
-{
-
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
- REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
- REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
- REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
- PLL_POST_DIV_ENABLE_MASK, PLL_POST_DIV_ENABLE);
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x0b,
- CLOCK_LANE_VOD_RANGE_SET_MASK,
- CLOCK_LANE_VOD_RANGE_SET(VOD_MAX_RANGE));
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
- REG_LDOPD_MASK | REG_PLLPD_MASK,
- REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
-}
-
-static void inno_mipi_dphy_max_1GHz_pll_enable(struct inno_video_phy *inno)
-{
+ /* Select MIPI mode */
+ phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
+ MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
/* Configure PLL */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
@@ -426,10 +325,6 @@
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
REG_LDOPD_MASK | REG_PLLPD_MASK,
REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
-}
-
-static void inno_mipi_dphy_reset(struct inno_video_phy *inno)
-{
/* Reset analog */
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
REG_SYNCRST_MASK, REG_SYNCRST_RESET);
@@ -442,21 +337,10 @@
udelay(1);
phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
-}
-
-static void inno_mipi_dphy_timing_init(struct inno_video_phy *inno)
-{
- struct mipi_dphy_timing gotp;
- u32 t_txbyteclkhs, t_txclkesc, ui, sys_clk;
- u32 txbyteclkhs, txclkesc, esc_clk_div;
- u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
- u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
- const struct inno_mipi_dphy_timing *timing;
- unsigned int i;
txbyteclkhs = inno->pll.rate / 8;
t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
- sys_clk = clk_get_rate(inno->pclk_phy);
+
esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
txclkesc = txbyteclkhs / esc_clk_div;
t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
@@ -482,9 +366,14 @@
*/
clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
- wakeup = DIV_ROUND_CLOSEST_ULL(gotp.wakeup * sys_clk, PSEC_PER_SEC);
- if (wakeup > 0x3ff)
- wakeup = 0x3ff;
+ /*
+ * The value of counter for HS Tlpx Time
+ * Tlpx = Tpin_txbyteclkhs * (2 + value)
+ */
+ lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
+ if (lpx >= 2)
+ lpx -= 2;
+
/*
* The value of counter for HS Tta-go
* Tta-go for turnaround
@@ -504,23 +393,18 @@
*/
ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
- timing = inno_mipi_dphy_get_timing(inno);
+ for (i = 0; i < ARRAY_SIZE(timings); i++)
+ if (inno->pll.rate <= timings[i].rate)
+ break;
- /*
- * The value of counter for HS Tlpx Time
- * Tlpx = Tpin_txbyteclkhs * (2 + value)
- */
- if (inno->pdata->max_rate == MAX_1GHZ) {
- lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
- if (lpx >= 2)
- lpx -= 2;
- } else
- lpx = timing->lpx;
+ if (i == ARRAY_SIZE(timings))
+ --i;
- hs_prepare = timing->hs_prepare;
- hs_trail = timing->hs_trail;
- clk_lane_hs_zero = timing->clk_lane_hs_zero;
- data_lane_hs_zero = timing->data_lane_hs_zero;
+ hs_prepare = timings[i].hs_prepare;
+ hs_trail = timings[i].hs_trail;
+ clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
+ data_lane_hs_zero = timings[i].data_lane_hs_zero;
+ wakeup = 0x3ff;
for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
if (i == REGISTER_PART_CLOCK_LANE)
@@ -532,29 +416,14 @@
T_LPX_CNT(lpx));
phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
T_HS_PREPARE_CNT(hs_prepare));
-
- if (inno->pdata->max_rate == MAX_2_5GHZ)
- phy_update_bits(inno, i, 0x06, T_HS_ZERO_CNT_HI_MASK,
- T_HS_ZERO_CNT_HI(hs_zero >> 6));
-
- phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_LO_MASK,
- T_HS_ZERO_CNT_LO(hs_zero));
+ phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
+ T_HS_ZERO_CNT(hs_zero));
phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
T_HS_TRAIL_CNT(hs_trail));
-
- if (inno->pdata->max_rate == MAX_2_5GHZ)
- phy_update_bits(inno, i, 0x11, T_HS_EXIT_CNT_HI_MASK,
- T_HS_EXIT_CNT_HI(hs_exit >> 5));
-
- phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_LO_MASK,
- T_HS_EXIT_CNT_LO(hs_exit));
-
- if (inno->pdata->max_rate == MAX_2_5GHZ)
- phy_update_bits(inno, i, 0x10, T_CLK_POST_HI_MASK,
- T_CLK_POST_HI(clk_post >> 4));
-
- phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_LO_MASK,
- T_CLK_POST_CNT_LO(clk_post));
+ phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
+ T_HS_EXIT_CNT(hs_exit));
+ phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
+ T_CLK_POST_CNT(clk_post));
phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
T_CLK_PRE_CNT(clk_pre));
phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
@@ -569,53 +438,10 @@
T_TA_WAIT_CNT(ta_wait));
}
-}
-
-static void inno_mipi_dphy_lane_enable(struct inno_video_phy *inno)
-{
- u8 val = LANE_EN_CK;
-
- switch (inno->lanes) {
- case 1:
- val |= LANE_EN_0;
- break;
- case 2:
- val |= LANE_EN_1 | LANE_EN_0;
- break;
- case 3:
- val |= LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
- break;
- case 4:
- default:
- val |= LANE_EN_3 | LANE_EN_2 | LANE_EN_1 | LANE_EN_0;
- break;
- }
-
- phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, val);
-}
-
-
-static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
-{
- /* Select MIPI mode */
- phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
- MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
-
- /* set pin_txclkesc_0 pin_txbyteclk invert disable */
- if (inno->pdata->soc_type == PX30S)
- phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x01,
- INVERT_TXCLKESC_MASK, INVERT_TXCLKESC_DISABLE);
-
- if (inno->pdata->max_rate == MAX_2_5GHZ)
- inno_mipi_dphy_max_2_5GHz_pll_enable(inno);
- else
- inno_mipi_dphy_max_1GHz_pll_enable(inno);
-
- inno_mipi_dphy_reset(inno);
-
- inno_mipi_dphy_timing_init(inno);
-
- inno_mipi_dphy_lane_enable(inno);
+ /* Enable all lanes on analog part */
+ phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
+ LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
+ LANE_EN_1 | LANE_EN_0);
}
static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
@@ -630,16 +456,6 @@
SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
SAMPLE_CLOCK_DIRECTION_REVERSE |
PLL_OUTPUT_FREQUENCY_DIV_BY_1);
-
- /* Reset LVDS digital logic */
- phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
- LVDS_DIGITAL_INTERNAL_RESET_MASK,
- LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
- udelay(1);
- phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
- LVDS_DIGITAL_INTERNAL_RESET_MASK,
- LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
-
/* Select LVDS mode */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
@@ -664,6 +480,14 @@
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
+ /* Reset LVDS digital logic */
+ phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
+ LVDS_DIGITAL_INTERNAL_RESET_MASK,
+ LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
+ udelay(1);
+ phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
+ LVDS_DIGITAL_INTERNAL_RESET_MASK,
+ LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
/* Enable LVDS digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
@@ -677,6 +501,9 @@
static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
{
+ /* Select TTL mode */
+ phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
+ MODE_ENABLE_MASK, TTL_MODE_ENABLE);
/* Reset digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
@@ -685,10 +512,6 @@
phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
LVDS_DIGITAL_INTERNAL_RESET_MASK,
LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
-
- /* Select TTL mode */
- phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
- MODE_ENABLE_MASK, TTL_MODE_ENABLE);
/* Enable digital logic */
phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
@@ -705,6 +528,7 @@
static int inno_video_phy_power_on(struct phy *phy)
{
struct inno_video_phy *inno = phy_get_drvdata(phy);
+ enum phy_mode mode = phy_get_mode(phy);
clk_prepare_enable(inno->pclk_host);
clk_prepare_enable(inno->pclk_phy);
@@ -717,18 +541,16 @@
phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
POWER_WORK_MASK, POWER_WORK_ENABLE);
- switch (inno->mode) {
- case PHY_MODE_VIDEO_MIPI:
+ switch (mode) {
+ case PHY_MODE_MIPI_DPHY:
inno_video_phy_mipi_mode_enable(inno);
break;
- case PHY_MODE_VIDEO_LVDS:
+ case PHY_MODE_LVDS:
inno_video_phy_lvds_mode_enable(inno);
break;
- case PHY_MODE_VIDEO_TTL:
+ default:
inno_video_phy_ttl_mode_enable(inno);
break;
- default:
- return -EINVAL;
}
return 0;
@@ -764,18 +586,6 @@
static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
{
- struct inno_video_phy *inno = phy_get_drvdata(phy);
-
- switch (mode) {
- case PHY_MODE_VIDEO_MIPI:
- case PHY_MODE_VIDEO_LVDS:
- case PHY_MODE_VIDEO_TTL:
- inno->mode = mode;
- break;
- default:
- return -EINVAL;
- }
-
return 0;
}
@@ -941,48 +751,6 @@
of_clk_del_provider(dev->of_node);
}
-static const struct regmap_config inno_video_phy_regmap_config = {
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .max_register = 0x3ac,
-};
-
-static const struct inno_video_phy_plat_data px30_video_phy_plat_data = {
- .soc_type = PX30,
- .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
- .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
- .max_rate = MAX_1GHZ,
-};
-
-static const struct inno_video_phy_plat_data px30s_video_phy_plat_data = {
- .soc_type = PX30S,
- .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
- .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
- .max_rate = MAX_2_5GHZ,
-};
-
-static const struct inno_video_phy_plat_data rk3128_video_phy_plat_data = {
- .soc_type = RK3128,
- .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
- .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
- .max_rate = MAX_1GHZ,
-};
-
-static const struct inno_video_phy_plat_data rk3368_video_phy_plat_data = {
- .soc_type = RK3368,
- .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_1GHz,
- .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_1GHz),
- .max_rate = MAX_1GHZ,
-};
-
-static const struct inno_video_phy_plat_data rk3568_video_phy_plat_data = {
- .soc_type = RK3568,
- .inno_mipi_dphy_timing_table = inno_mipi_dphy_timing_table_max_2_5GHz,
- .num_timings = ARRAY_SIZE(inno_mipi_dphy_timing_table_max_2_5GHz),
- .max_rate = MAX_2_5GHZ,
-};
-
static int inno_video_phy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -990,7 +758,6 @@
struct phy_provider *phy_provider;
struct phy *phy;
struct resource *res;
- void __iomem *regs;
int ret;
inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
@@ -998,10 +765,6 @@
return -ENOMEM;
inno->dev = dev;
- inno->pdata = of_device_get_match_data(inno->dev);
- if (soc_is_px30s())
- inno->pdata = &px30s_video_phy_plat_data;
-
platform_set_drvdata(pdev, inno);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1010,17 +773,9 @@
return -EINVAL;
}
- regs = devm_ioremap_resource(dev, res);
- if (IS_ERR(regs))
- return PTR_ERR(regs);
-
- inno->regmap = devm_regmap_init_mmio(dev, regs,
- &inno_video_phy_regmap_config);
- if (IS_ERR(inno->regmap)) {
- ret = PTR_ERR(inno->regmap);
- dev_err(dev, "failed to init regmap: %d\n", ret);
- return ret;
- }
+ inno->phy_base = devm_ioremap(dev, res->start, resource_size(res));
+ if (!inno->phy_base)
+ return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
if (!res) {
@@ -1067,9 +822,6 @@
return ret;
}
- if (of_property_read_u32(dev->of_node, "inno,lanes", &inno->lanes))
- inno->lanes = 4;
-
phy_set_drvdata(phy, inno);
phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
@@ -1099,22 +851,10 @@
}
static const struct of_device_id inno_video_phy_of_match[] = {
- {
- .compatible = "rockchip,px30-video-phy",
- .data = &px30_video_phy_plat_data,
- }, {
- .compatible = "rockchip,px30s-video-phy",
- .data = &px30s_video_phy_plat_data,
- }, {
- .compatible = "rockchip,rk3128-video-phy",
- .data = &rk3128_video_phy_plat_data,
- }, {
- .compatible = "rockchip,rk3368-video-phy",
- .data = &rk3368_video_phy_plat_data,
- }, {
- .compatible = "rockchip,rk3568-video-phy",
- .data = &rk3568_video_phy_plat_data,
- },
+ { .compatible = "rockchip,px30-video-phy", },
+ { .compatible = "rockchip,rk3128-video-phy", },
+ { .compatible = "rockchip,rk3368-video-phy", },
+ { .compatible = "rockchip,rk3568-video-phy", },
{}
};
MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);
--
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