From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/phy/rockchip/phy-rockchip-dp.c | 116 ++++++++++++++++++++-------------------------------------
1 files changed, 41 insertions(+), 75 deletions(-)
diff --git a/kernel/drivers/phy/rockchip/phy-rockchip-dp.c b/kernel/drivers/phy/rockchip/phy-rockchip-dp.c
index 3f77ecb..592aa95 100644
--- a/kernel/drivers/phy/rockchip/phy-rockchip-dp.c
+++ b/kernel/drivers/phy/rockchip/phy-rockchip-dp.c
@@ -1,72 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Rockchip DP PHY driver
*
* Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
* Author: Yakir Yang <ykk@@rock-chips.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License.
*/
#include <linux/clk.h>
-#include <linux/clk-provider.h>
#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of.h>
-#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
-#include <linux/reset.h>
-struct rockchip_dp_phy_data {
- u32 grf_reg_offset;
- u8 ref_clk_sel_shift;
- u8 iddq_shift;
-};
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON 0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
struct rockchip_dp_phy {
struct device *dev;
struct regmap *grf;
struct clk *phy_24m;
- struct reset_control *rst;
- const struct rockchip_dp_phy_data *data;
};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
static int rockchip_dp_phy_power_on(struct phy *phy)
{
- struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
- const struct rockchip_dp_phy_data *data = dp->data;
-
- if (!__clk_is_enabled(dp->phy_24m))
- clk_prepare_enable(dp->phy_24m);
-
- if (dp->rst) {
- /* EDP 24m clock domain software reset */
- reset_control_assert(dp->rst);
- usleep_range(20, 40);
- reset_control_deassert(dp->rst);
- }
-
- regmap_write(dp->grf, data->grf_reg_offset,
- 0 | BIT(16 + data->iddq_shift));
-
- return 0;
+ return rockchip_set_phy_state(phy, true);
}
static int rockchip_dp_phy_power_off(struct phy *phy)
{
- struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
- const struct rockchip_dp_phy_data *data = dp->data;
-
- regmap_write(dp->grf, data->grf_reg_offset,
- BIT(data->iddq_shift) | BIT(16 + data->iddq_shift));
-
- if (__clk_is_enabled(dp->phy_24m))
- clk_disable_unprepare(dp->phy_24m);
-
- return 0;
+ return rockchip_set_phy_state(phy, false);
}
static const struct phy_ops rockchip_dp_phy_ops = {
@@ -81,7 +77,6 @@
struct device_node *np = dev->of_node;
struct phy_provider *phy_provider;
struct rockchip_dp_phy *dp;
- const struct rockchip_dp_phy_data *data = of_device_get_match_data(dev);
struct phy *phy;
int ret;
@@ -96,7 +91,6 @@
return -ENOMEM;
dp->dev = dev;
- dp->data = data;
dp->phy_24m = devm_clk_get(dev, "24m");
if (IS_ERR(dp->phy_24m)) {
@@ -110,30 +104,15 @@
return ret;
}
- ret = clk_prepare_enable(dp->phy_24m);
- if (ret) {
- dev_err(dev, "failed to enable phy 24m clock: %d\n", ret);
- return ret;
- }
-
- dp->rst = devm_reset_control_get_optional(dev, "edp_24m");
- if (IS_ERR(dp->rst)) {
- ret = PTR_ERR(dp->rst);
- dev_err(dev, "failed to get reset control: %d\n", ret);
- return ret;
- }
-
dp->grf = syscon_node_to_regmap(dev->parent->of_node);
if (IS_ERR(dp->grf)) {
dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
return PTR_ERR(dp->grf);
}
- /* eDP PHY reference clock source from internal clock */
- ret = regmap_write(dp->grf, data->grf_reg_offset,
- BIT(data->ref_clk_sel_shift) |
- BIT(16 + data->ref_clk_sel_shift));
- if (ret) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+ GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+ if (ret != 0) {
dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
return ret;
}
@@ -150,21 +129,8 @@
return PTR_ERR_OR_ZERO(phy_provider);
}
-static const struct rockchip_dp_phy_data rk3288_dp_phy_data = {
- .grf_reg_offset = 0x274,
- .ref_clk_sel_shift = 4,
- .iddq_shift = 5,
-};
-
-static const struct rockchip_dp_phy_data rk3368_dp_phy_data = {
- .grf_reg_offset = 0x410,
- .ref_clk_sel_shift = 0,
- .iddq_shift = 1,
-};
-
static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
- { .compatible = "rockchip,rk3288-dp-phy", .data = &rk3288_dp_phy_data },
- { .compatible = "rockchip,rk3368-dp-phy", .data = &rk3368_dp_phy_data },
+ { .compatible = "rockchip,rk3288-dp-phy" },
{}
};
--
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