From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h | 166 +++++++++++++++++++++++++++++++++++++++++++++++++++----
1 files changed, 154 insertions(+), 12 deletions(-)
diff --git a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h
index ca5bcf7..1bf647a 100644
--- a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h
+++ b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/pcicfg.h
@@ -1,15 +1,16 @@
-/* SPDX-License-Identifier: GPL-2.0 */
/*
* pcicfg.h: PCI configuration constants and structures.
*
- * Copyright (C) 1999-2019, Broadcom Corporation
- *
+ * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation
+ *
+ * Copyright (C) 1999-2017, Broadcom Corporation
+ *
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
- *
+ *
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
@@ -17,7 +18,7 @@
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
- *
+ *
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
@@ -25,12 +26,11 @@
*
* <<Broadcom-WL-IPTag/Open:>>
*
- * $Id: pcicfg.h 514727 2014-11-12 03:02:48Z $
+ * $Id: pcicfg.h 690133 2017-03-14 21:02:02Z $
*/
#ifndef _h_pcicfg_
#define _h_pcicfg_
-
/* pci config status reg has a bit to indicate that capability ptr is present */
@@ -53,6 +53,11 @@
#define PCI_CFG_HDR 0xe
#define PCI_CFG_BIST 0xf
#define PCI_CFG_BAR0 0x10
+/*
+* TODO: PCI_CFG_BAR1 is wrongly defined to be 0x14 whereas it should be
+* 0x18 as per the PCIe full dongle spec. Need to modify the values below
+* correctly at a later point of time
+*/
#define PCI_CFG_BAR1 0x14
#define PCI_CFG_BAR2 0x18
#define PCI_CFG_BAR3 0x1c
@@ -68,13 +73,14 @@
#define PCI_CFG_MINGNT 0x3e
#define PCI_CFG_MAXLAT 0x3f
#define PCI_CFG_DEVCTRL 0xd8
-
+#define PCI_CFG_TLCNTRL_5 0x814
/* PCI CAPABILITY DEFINES */
#define PCI_CAP_POWERMGMTCAP_ID 0x01
#define PCI_CAP_MSICAP_ID 0x05
#define PCI_CAP_VENDSPEC_ID 0x09
#define PCI_CAP_PCIECAP_ID 0x10
+#define PCI_CAP_MSIXCAP_ID 0x11
/* Data structure to define the Message Signalled Interrupt facility
* Valid for PCI and PCIE configurations
@@ -132,11 +138,13 @@
/* PCIE Extended configuration */
#define PCIE_ADV_CORR_ERR_MASK 0x114
+#define PCIE_ADV_CORR_ERR_MASK_OFFSET 0x14
#define CORR_ERR_RE (1 << 0) /* Receiver */
-#define CORR_ERR_BT (1 << 6) /* Bad TLP */
+#define CORR_ERR_BT (1 << 6) /* Bad TLP */
#define CORR_ERR_BD (1 << 7) /* Bad DLLP */
#define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
#define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
+#define CORR_ERR_AE (1 << 13) /* Adviosry Non-Fital Error Mask */
#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
CORR_ERR_RR | CORR_ERR_RT)
@@ -150,6 +158,9 @@
/* PCIE Root Capability Register bits (Host mode only) */
#define PCIE_RC_CRS_VISIBILITY 0x0001
+/* PCIe PMCSR Register bits */
+#define PCIE_PMCSR_PMESTAT 0x8000
+
/* Header to define the PCIE specific capabilities in the extended config space */
typedef struct _pcie_enhanced_caphdr {
uint16 capID;
@@ -157,10 +168,11 @@
uint16 next_ptr : 12;
} pcie_enhanced_caphdr;
-
+#define PCIE_CFG_PMCSR 0x4C
#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
+#define PCIE_CFG_SUBSYSTEM_CONTROL 0x88 /* used as subsystem control in PCIE devices */
#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
@@ -170,9 +182,19 @@
#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
#define PCI_BAR0_WIN2 0xac /* backplane addres space accessed by second 4KB of BAR0 */
#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
+#define PCIE_CFG_DEVICE_CAPABILITY 0xb0 /* used as device capability in PCIE devices */
#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
+#define PCIE_CFG_DEVICE_CONTROL 0xb4 /* 0xb4 is used as device control in PCIE devices */
+#define PCIE_DC_AER_CORR_EN (1u << 0u)
+#define PCIE_DC_AER_NON_FATAL_EN (1u << 1u)
+#define PCIE_DC_AER_FATAL_EN (1u << 2u)
+#define PCIE_DC_AER_UNSUP_EN (1u << 3u)
+
+#define PCI_BAR0_WIN2_OFFSET 0x1000u
+#define PCIE2_BAR0_CORE2_WIN2_OFFSET 0x5000u
+
#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
-#define PCI_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */
+#define PCI_PM_L1SS_CTRL2 0x24c /* The L1 PM Substates Control register */
/* Private Registers */
#define PCI_STAT_CTRL 0xa80
@@ -187,11 +209,90 @@
#define PCI_L2_EVENTCNT 0xaa4
#define PCI_L2_STATETMR 0xaa8
+#define PCI_LINK_STATUS 0x4dc
+#define PCI_LINK_SPEED_MASK (15u << 0u)
+#define PCI_LINK_SPEED_SHIFT (0)
+#define PCIE_LNK_SPEED_GEN1 0x1
+#define PCIE_LNK_SPEED_GEN2 0x2
+#define PCIE_LNK_SPEED_GEN3 0x3
+
+#define PCI_PL_SPARE 0x1808 /* Config to Increase external clkreq deasserted minimum time */
+#define PCI_CONFIG_EXT_CLK_MIN_TIME_MASK (1u << 31u)
+#define PCI_CONFIG_EXT_CLK_MIN_TIME_SHIFT (31)
+
+#define PCI_ADV_ERR_CAP 0x100
+#define PCI_UC_ERR_STATUS 0x104
+#define PCI_UNCORR_ERR_MASK 0x108
+#define PCI_UCORR_ERR_SEVR 0x10c
+#define PCI_CORR_ERR_STATUS 0x110
+#define PCI_CORR_ERR_MASK 0x114
+#define PCI_ERR_CAP_CTRL 0x118
+#define PCI_TLP_HDR_LOG1 0x11c
+#define PCI_TLP_HDR_LOG2 0x120
+#define PCI_TLP_HDR_LOG3 0x124
+#define PCI_TLP_HDR_LOG4 0x128
+#define PCI_TL_CTRL_5 0x814
+#define PCI_TL_HDR_FC_ST 0x980
+#define PCI_TL_TGT_CRDT_ST 0x990
+#define PCI_TL_SMLOGIC_ST 0x998
+#define PCI_DL_ATTN_VEC 0x1040
+#define PCI_DL_STATUS 0x1048
+
+#define PCI_PHY_CTL_0 0x1800
+#define PCI_SLOW_PMCLK_EXT_RLOCK (1 << 7)
+
+#define PCI_LINK_STATE_DEBUG 0x1c24
+#define PCI_RECOVERY_HIST 0x1ce4
+#define PCI_PHY_LTSSM_HIST_0 0x1cec
+#define PCI_PHY_LTSSM_HIST_1 0x1cf0
+#define PCI_PHY_LTSSM_HIST_2 0x1cf4
+#define PCI_PHY_LTSSM_HIST_3 0x1cf8
+#define PCI_PHY_DBG_CLKREG_0 0x1e10
+#define PCI_PHY_DBG_CLKREG_1 0x1e14
+#define PCI_PHY_DBG_CLKREG_2 0x1e18
+#define PCI_PHY_DBG_CLKREG_3 0x1e1c
+
+/* Bit settings for PCIE_CFG_SUBSYSTEM_CONTROL register */
+#define PCIE_BAR1COHERENTACCEN_BIT 8
+#define PCIE_BAR2COHERENTACCEN_BIT 9
+#define PCIE_SSRESET_STATUS_BIT 13
+#define PCIE_SSRESET_DISABLE_BIT 14
+#define PCIE_SSRESET_DIS_ENUM_RST_BIT 15
+
+#define PCIE_BARCOHERENTACCEN_MASK 0x300
+
+/* Bit settings for PCI_UC_ERR_STATUS register */
+#define PCI_UC_ERR_URES (1 << 20) /* Unsupported Request Error Status */
+#define PCI_UC_ERR_ECRCS (1 << 19) /* ECRC Error Status */
+#define PCI_UC_ERR_MTLPS (1 << 18) /* Malformed TLP Status */
+#define PCI_UC_ERR_ROS (1 << 17) /* Receiver Overflow Status */
+#define PCI_UC_ERR_UCS (1 << 16) /* Unexpected Completion Status */
+#define PCI_UC_ERR_CAS (1 << 15) /* Completer Abort Status */
+#define PCI_UC_ERR_CTS (1 << 14) /* Completer Timeout Status */
+#define PCI_UC_ERR_FCPES (1 << 13) /* Flow Control Protocol Error Status */
+#define PCI_UC_ERR_PTLPS (1 << 12) /* Poisoned TLP Status */
+#define PCI_UC_ERR_DLPES (1 << 4) /* Data Link Protocol Error Status */
+
+#define PCI_DL_STATUS_PHY_LINKUP (1 << 13) /* Status of LINK */
+
#define PCI_PMCR_REFUP 0x1814 /* Trefup time */
+#define PCI_PMCR_TREFUP_LO_MASK 0x3f
+#define PCI_PMCR_TREFUP_LO_SHIFT 24
+#define PCI_PMCR_TREFUP_LO_BITS 6
+#define PCI_PMCR_TREFUP_HI_MASK 0xf
+#define PCI_PMCR_TREFUP_HI_SHIFT 5
+#define PCI_PMCR_TREFUP_HI_BITS 4
+#define PCI_PMCR_TREFUP_MAX 0x400
+#define PCI_PMCR_TREFUP_MAX_SCALE 0x2000
+
#define PCI_PMCR_REFUP_EXT 0x1818 /* Trefup extend Max */
+#define PCI_PMCR_TREFUP_EXT_SHIFT 22
+#define PCI_PMCR_TREFUP_EXT_SCALE 3
+#define PCI_PMCR_TREFUP_EXT_ON 1
+#define PCI_PMCR_TREFUP_EXT_OFF 0
+
#define PCI_TPOWER_SCALE_MASK 0x3
#define PCI_TPOWER_SCALE_SHIFT 3 /* 0:1 is scale and 2 is rsvd */
-
#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
@@ -208,6 +309,16 @@
#define PCIE2_BAR0_WIN2 0x70 /* backplane addres space accessed by second 4KB of BAR0 */
#define PCIE2_BAR0_CORE2_WIN 0x74 /* backplane addres space accessed by second 4KB of BAR0 */
#define PCIE2_BAR0_CORE2_WIN2 0x78 /* backplane addres space accessed by second 4KB of BAR0 */
+#define PCIE2_BAR0_WINSZ 0x8000
+
+#define PCI_BAR0_WIN2_OFFSET 0x1000u
+#define PCI_CORE_ENUM_OFFSET 0x2000u
+#define PCI_CC_CORE_ENUM_OFFSET 0x3000u
+#define PCI_SEC_BAR0_WIN_OFFSET 0x4000u
+#define PCI_SEC_BAR0_WRAP_OFFSET 0x5000u
+#define PCI_CORE_ENUM2_OFFSET 0x6000u
+#define PCI_CC_CORE_ENUM2_OFFSET 0x7000u
+#define PCI_LAST_OFFSET 0x8000u
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
@@ -216,6 +327,37 @@
#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
#define PCI_SECOND_BAR0_OFFSET (16 * 1024) /* secondary bar 0 window */
+/* On AI chips we have a second window to map DMP regs are mapped: */
+#define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
+
+/* PCI_INT_STATUS */
+#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
+
+/* PCI_INT_MASK */
+#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
+#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
+#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
+#define PCI_CTO_INT_SHIFT 16 /* backplane SBErr interrupt mask */
+#define PCI_CTO_INT_MASK (1 << PCI_CTO_INT_SHIFT) /* backplane SBErr interrupt mask */
+
+/* PCI_SPROM_CONTROL */
+#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
+#define SPROM_LOCKED 0x08 /* SPROM Locked */
+#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
+#define SPROM_WRITEEN 0x10 /* SPROM write enable */
+#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
+#define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
+#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
+#define SPROM_CFG_TO_SB_RST 0x400 /* backplane reset */
+
+/* Bits in PCI command and status regs */
+#define PCI_CMD_IO 0x00000001 /* I/O enable */
+#define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
+#define PCI_CMD_MASTER 0x00000004 /* Master enable */
+#define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
+#define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
+#define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
+#define PCI_STAT_TA 0x08000000 /* target abort status */
/* Header types */
#define PCI_HEADER_MULTI 0x80
--
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