From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Mon, 11 Dec 2023 02:45:28 +0000 Subject: [PATCH] add boot partition size --- kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h | 82 ++++++++++++++++++++++++++++++---------- 1 files changed, 61 insertions(+), 21 deletions(-) diff --git a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h index 822d7fa..6662d50 100644 --- a/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h +++ b/kernel/drivers/net/wireless/rockchip_wlan/cywdhd/bcmdhd/include/hndsoc.h @@ -1,15 +1,16 @@ -/* SPDX-License-Identifier: GPL-2.0 */ /* * Broadcom HND chip & on-chip-interconnect-related definitions. * - * Copyright (C) 1999-2019, Broadcom Corporation - * + * Portions of this code are copyright (c) 2022 Cypress Semiconductor Corporation + * + * Copyright (C) 1999-2017, Broadcom Corporation + * * Unless you and Broadcom execute a separate written software license * agreement governing use of this software, this software is licensed to you * under the terms of the GNU General Public License version 2 (the "GPL"), * available at http://www.broadcom.com/licenses/GPLv2.php, with the * following added to such license: - * + * * As a special exception, the copyright holders of this software give you * permission to link this software with independent modules, and to copy and * distribute the resulting executable under terms of your choice, provided that @@ -17,7 +18,7 @@ * the license of that module. An independent module is a module which is not * derived from this software. The special exception does not apply to any * modifications of the software. - * + * * Notwithstanding the above, under no circumstances may you combine this * software in any way with any other Broadcom software provided under a license * other than the GPL, without Broadcom's express prior written consent. @@ -25,7 +26,7 @@ * * <<Broadcom-WL-IPTag/Open:>> * - * $Id: hndsoc.h 517544 2014-11-26 00:40:42Z $ + * $Id: hndsoc.h 672520 2016-11-28 23:30:55Z $ */ #ifndef _HNDSOC_H @@ -46,10 +47,35 @@ #define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */ #define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */ -#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */ +#ifdef STB_SOC_WIFI +#define SI_REG_BASE_SIZE 0xB000 /* size from 0xf1800000 to 0xf180AFFF (44KB) */ +#define SI_ENUM_BASE_DEFAULT 0xF1800000 /* Enumeration space base */ +#define SI_WRAP_BASE_DEFAULT 0xF1900000 /* Wrapper space base */ +#endif /* STB_SOC_WIFI */ -#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */ -#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ +#ifndef SI_ENUM_BASE_DEFAULT +#define SI_ENUM_BASE_DEFAULT 0x18000000 /* Enumeration space base */ +#endif // endif + +#ifndef SI_WRAP_BASE_DEFAULT +#define SI_WRAP_BASE_DEFAULT 0x18100000 /* Wrapper space base */ +#endif // endif + +#ifndef SI_ENUM_PCIE2_BASE +#define SI_ENUM_PCIE2_BASE 0x18003000 /* PCIE Enumeration space base */ +#endif // endif + +/** new(er) chips started locating their chipc core at a different BP address than 0x1800_0000 */ +// NIC and DHD driver binaries should support both old(er) and new(er) chips at the same time +#define SI_ENUM_BASE(sih) ((sih)->enum_base) +#define SI_WRAP_BASE(sih) (SI_ENUM_BASE(sih) + 0x00100000) + +#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */ + +#define SI_NIC400_GPV_BASE 0x18200000 /* NIC-400 Global Programmers View (GPV) */ +#define SI_GPV_WR_CAP_ADDR 0x4008 /* WR-CAP offset */ +#define SI_GPV_RD_CAP_EN 0x1 /* issue read */ +#define SI_GPV_WR_CAP_EN 0x2 /* issue write */ #ifndef SI_MAXCORES #define SI_MAXCORES 32 /* NorthStar has more cores */ @@ -80,7 +106,9 @@ #define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */ #define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */ #define SI_ARMCA7_ROM 0x00000000 /* ARM Cortex-A7 ROM */ +#ifndef SI_ARMCA7_RAM #define SI_ARMCA7_RAM 0x00200000 /* ARM Cortex-A7 RAM */ +#endif // endif #define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */ #define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */ @@ -97,6 +125,7 @@ #define SI_BCM53573_NANDFLASH 0x30000000 /* 53573 NAND flash base */ #define SI_BCM53573_NORFLASH 0x1c000000 /* 53573 NOR flash base */ +#define SI_BCM53573_FLASH2_SZ 0x04000000 /* 53573 NOR flash2 size */ #define SI_BCM53573_NORFLASH_WINDOW 0x01000000 /* only support 16M direct access for * 3-byte address modes in spi flash @@ -104,8 +133,18 @@ #define SI_BCM53573_BOOTDEV_MASK 0x3 #define SI_BCM53573_BOOTDEV_NOR 0x0 +#define SI_BCM53573_NAND_PRE_MASK 0x100 /* 53573 NAND present mask */ + #define SI_BCM53573_DDRTYPE_MASK 0x10 #define SI_BCM53573_DDRTYPE_DDR3 0x10 + +#define SI_BCM47189_RGMII_VDD_MASK 0x3 +#define SI_BCM47189_RGMII_VDD_SHIFT 21 +#define SI_BCM47189_RGMII_VDD_3_3V 0 +#define SI_BCM47189_RGMII_VDD_2_5V 1 +#define SI_BCM47189_RGMII_VDD_1_5V 1 + +#define SI_BCM53573_LOCKED_CPUPLL 0x1 /* APB bridge code */ #define APB_BRIDGE_ID 0x135 /* APB Bridge 0, 1, etc. */ @@ -173,10 +212,13 @@ #define USB30D_CORE_ID 0x83d /* usb 3.0 device core */ #define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */ #define GCI_CORE_ID 0x840 /* GCI Core */ +#define SR_CORE_ID 0x841 /* SR_CORE ID */ #define M2MDMA_CORE_ID 0x844 /* memory to memory dma */ #define CMEM_CORE_ID 0x846 /* CNDS DDR2/3 memory controller */ #define ARMCA7_CORE_ID 0x847 /* ARM CA7 CPU */ #define SYSMEM_CORE_ID 0x849 /* System memory core */ +#define HUB_CORE_ID 0x84b /* Hub core ID */ +#define HND_OOBR_CORE_ID 0x85c /* Hnd oob router core ID */ #define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */ #define AXI_CORE_ID 0x301 /* AXI/GPV core ID */ #define EROM_CORE_ID 0x366 /* EROM core ID */ @@ -185,7 +227,6 @@ * unused address ranges */ -#define CC_4706_CORE_ID 0x500 /* chipcommon core */ #define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */ #define NS_DMA_CORE_ID 0x502 /* DMA core */ #define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */ @@ -197,12 +238,9 @@ #define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */ #define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */ #define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */ -#define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */ -#define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID +#define NS_SOCRAM_CORE_ID 0x50e /* internal memory core */ #define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */ #define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */ -#define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */ -#define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */ #define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */ #define ALTA_CORE_ID 0x534 /* I2S core */ #define DDR23_PHY_CORE_ID 0x5dd @@ -212,12 +250,9 @@ #define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2 * (2 ZettaBytes), high 32 bits */ -#define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */ -#define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */ -#define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */ #define NS_PCIEG2_CORE_REV_B0 0x7 /* NS-B0 PCIE Gen 2 core rev */ -/* There are TWO constants on all HND chips: SI_ENUM_BASE above, +/* There are TWO constants on all HND chips: SI_ENUM_BASE_DEFAULT above, * and chipcommon being the first core: */ #define SI_CC_IDX 0 @@ -226,6 +261,7 @@ #define SOCI_AI 1 #define SOCI_UBUS 2 #define SOCI_NAI 3 +#define SOCI_DVTBUS 4 /* BCM7XXX Digital Video Tech bus */ /* Common core control flags */ #define SICF_BIST_EN 0x8000 @@ -249,6 +285,10 @@ #define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */ #define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */ +/* dot11 core-specific status flags */ +#define SISF_MINORREV_D11_SHIFT 16 +#define SISF_MINORREV_D11_MASK 0xF /**< minor corerev (corerev == 61) */ + /* A register that is common to all cores to * communicate w/PMU regarding clock control. */ @@ -266,6 +306,7 @@ #define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */ #define CCS_SECICLKREQ 0x00000100 /* SECI Clock Req */ #define CCS_ARMFASTCLOCKREQ 0x00000100 /* ARM CR4/CA7 fast clock request */ +#define CCS_SFLASH_CLKREQ 0x00000200 /* Sflash clk request */ #define CCS_AVBCLKREQ 0x00000400 /* AVB Clock enable request */ #define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */ #define CCS_ERSRC_REQ_SHIFT 8 @@ -276,9 +317,7 @@ #define CCS_ARMFASTCLOCKSTATUS 0x01000000 /* Fast CPU clock is running */ #define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */ #define CCS_ERSRC_STS_SHIFT 24 - -#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */ -#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */ +#define CCS_SECI_AVAIL 0x01000000 /* RO: SECI is available */ /* Not really related to SOC Interconnect, but a couple of software * conventions for the use the flash space: @@ -313,4 +352,5 @@ int soc_knl_dev(void *sih); #endif /* !defined(_LANGUAGE_ASSEMBLY) && !defined(__ASSEMBLY__) */ +#define PMU_BASE_OFFSET 0x00012000 /* PMU offset is changed for ccrev >= 56 */ #endif /* _HNDSOC_H */ -- Gitblit v1.6.2