From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h | 88 ++++++++++++++++++++++++++++++++++++++-----
1 files changed, 77 insertions(+), 11 deletions(-)
diff --git a/kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
index 47c19f8..e73cee2 100644
--- a/kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
+++ b/kernel/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h
@@ -37,11 +37,14 @@
dm_444_64 = 2,
dm_420_8 = 3,
dm_420_10 = 4,
- dm_422_8 = 5,
- dm_422_10 = 6,
- dm_444_8 = 7,
- dm_mono_8,
- dm_mono_16
+ dm_420_12 = 5,
+ dm_422_8 = 6,
+ dm_422_10 = 7,
+ dm_444_8 = 8,
+ dm_mono_8 = dm_444_8,
+ dm_mono_16 = dm_444_16,
+ dm_rgbe = 9,
+ dm_rgbe_alpha = 10,
};
enum output_bpc_class {
dm_out_6 = 0, dm_out_8 = 1, dm_out_10 = 2, dm_out_12 = 3, dm_out_16 = 4
@@ -77,16 +80,17 @@
dm_sw_SPARE_13 = 24,
dm_sw_64kb_s_x = 25,
dm_sw_64kb_d_x = 26,
- dm_sw_SPARE_14 = 27,
+ dm_sw_64kb_r_x = 27,
dm_sw_SPARE_15 = 28,
dm_sw_var_s_x = 29,
dm_sw_var_d_x = 30,
- dm_sw_64kb_r_x,
- dm_sw_gfx7_2d_thin_lvp,
- dm_sw_gfx7_2d_thin_gl
+ dm_sw_var_r_x = 31,
+ dm_sw_gfx7_2d_thin_l_vp,
+ dm_sw_gfx7_2d_thin_gl,
};
enum lb_depth {
- dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16
+ dm_lb_10 = 0, dm_lb_8 = 1, dm_lb_6 = 2, dm_lb_12 = 3, dm_lb_16 = 4,
+ dm_lb_19 = 5
};
enum voltage_state {
dm_vmin = 0, dm_vmid = 1, dm_vnom = 2, dm_vmax = 3
@@ -111,7 +115,12 @@
enum mpc_combine_affinity {
dm_mpc_always_when_possible,
dm_mpc_reduce_voltage,
- dm_mpc_reduce_voltage_and_clocks
+ dm_mpc_reduce_voltage_and_clocks,
+ dm_mpc_never
+};
+
+enum RequestType {
+ REQ_256Bytes, REQ_128BytesNonContiguous, REQ_128BytesContiguous, REQ_NA
};
enum self_refresh_affinity {
@@ -121,4 +130,61 @@
dm_neither_self_refresh_nor_mclk_switch
};
+enum dm_validation_status {
+ DML_VALIDATION_OK,
+ DML_FAIL_SCALE_RATIO_TAP,
+ DML_FAIL_SOURCE_PIXEL_FORMAT,
+ DML_FAIL_VIEWPORT_SIZE,
+ DML_FAIL_TOTAL_V_ACTIVE_BW,
+ DML_FAIL_DIO_SUPPORT,
+ DML_FAIL_NOT_ENOUGH_DSC,
+ DML_FAIL_DSC_CLK_REQUIRED,
+ DML_FAIL_DSC_VALIDATION_FAILURE,
+ DML_FAIL_URGENT_LATENCY,
+ DML_FAIL_REORDERING_BUFFER,
+ DML_FAIL_DISPCLK_DPPCLK,
+ DML_FAIL_TOTAL_AVAILABLE_PIPES,
+ DML_FAIL_NUM_OTG,
+ DML_FAIL_WRITEBACK_MODE,
+ DML_FAIL_WRITEBACK_LATENCY,
+ DML_FAIL_WRITEBACK_SCALE_RATIO_TAP,
+ DML_FAIL_CURSOR_SUPPORT,
+ DML_FAIL_PITCH_SUPPORT,
+ DML_FAIL_PTE_BUFFER_SIZE,
+ DML_FAIL_HOST_VM_IMMEDIATE_FLIP,
+ DML_FAIL_DSC_INPUT_BPC,
+ DML_FAIL_PREFETCH_SUPPORT,
+ DML_FAIL_V_RATIO_PREFETCH,
+};
+
+enum writeback_config {
+ dm_normal,
+ dm_whole_buffer_for_single_stream_no_interleave,
+ dm_whole_buffer_for_single_stream_interleave,
+};
+
+enum odm_combine_mode {
+ dm_odm_combine_mode_disabled,
+ dm_odm_combine_mode_2to1,
+ dm_odm_combine_mode_4to1,
+};
+
+enum odm_combine_policy {
+ dm_odm_combine_policy_dal,
+ dm_odm_combine_policy_none,
+ dm_odm_combine_policy_2to1,
+ dm_odm_combine_policy_4to1,
+};
+
+enum immediate_flip_requirement {
+ dm_immediate_flip_not_required,
+ dm_immediate_flip_required,
+};
+
+enum unbounded_requesting_policy {
+ dm_unbounded_requesting,
+ dm_unbounded_requesting_edp_only,
+ dm_unbounded_requesting_disable
+};
+
#endif
--
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