From d2ccde1c8e90d38cee87a1b0309ad2827f3fd30d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 02:45:28 +0000
Subject: [PATCH] add boot partition size
---
kernel/drivers/clk/rockchip/clk-rk1808.c | 156 +++++++++++++++++++++++++++------------------------
1 files changed, 82 insertions(+), 74 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-rk1808.c b/kernel/drivers/clk/rockchip/clk-rk1808.c
index 63ba8c2..e177a3d 100644
--- a/kernel/drivers/clk/rockchip/clk-rk1808.c
+++ b/kernel/drivers/clk/rockchip/clk-rk1808.c
@@ -4,8 +4,10 @@
* Author: Elaine Zhang <zhangqing@rock-chips.com>
*/
#include <linux/clk-provider.h>
+#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_device.h>
#include <linux/syscore_ops.h>
#include <dt-bindings/clock/rk1808-cru.h>
#include "clk.h"
@@ -128,7 +130,6 @@
PNAME(mux_pll_p) = { "xin24m", "xin32k"};
PNAME(mux_usb480m_p) = { "xin24m", "usb480m_phy", "xin32k" };
-PNAME(mux_armclk_p) = { "apll_core", "cpll_core", "gpll_core" };
PNAME(mux_gpll_cpll_p) = { "gpll", "cpll" };
PNAME(mux_gpll_cpll_apll_p) = { "gpll", "cpll", "apll" };
PNAME(mux_npu_p) = { "clk_npu_div", "clk_npu_np5" };
@@ -297,7 +298,7 @@
GATE(SCLK_PVTM_CORE, "clk_pvtm_core", "xin24m", 0,
RK1808_CLKGATE_CON(0), 5, GFLAGS),
- COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", 0,
+ COMPOSITE_NOMUX(MSCLK_CORE_NIU, "msclk_core_niu", "gpll", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(18), 0, 5, DFLAGS,
RK1808_CLKGATE_CON(0), 1, GFLAGS),
@@ -305,12 +306,12 @@
* Clock-Architecture Diagram 3
*/
- COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, 0,
+ COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(15), 11, 1, MFLAGS, 12, 4, DFLAGS,
RK1808_CLKGATE_CON(1), 0, GFLAGS),
- GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_gic_niu", "aclk_gic_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(1), 1, GFLAGS),
- GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", 0,
+ GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(1), 2, GFLAGS),
GATE(0, "aclk_core2gic", "aclk_gic_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(1), 3, GFLAGS),
@@ -337,9 +338,9 @@
/*
* Clock-Architecture Diagram 4
*/
- COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
+ COMPOSITE_NOGATE(0, "clk_npu_div", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
RK1808_CLKSEL_CON(1), 8, 2, MFLAGS, 0, 4, DFLAGS),
- COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_KEEP_REQ_RATE | CLK_OPS_PARENT_ENABLE,
+ COMPOSITE_NOGATE_HALFDIV(0, "clk_npu_np5", mux_gpll_cpll_p, CLK_OPS_PARENT_ENABLE,
RK1808_CLKSEL_CON(1), 10, 2, MFLAGS, 4, 4, DFLAGS),
MUX(0, "clk_npu_pre", mux_npu_p, CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(1), 15, 1, MFLAGS),
@@ -355,40 +356,40 @@
RK1808_CLKGATE_CON(1), 9, GFLAGS),
GATE(ACLK_NPU, "aclk_npu", "aclk_npu_pre", 0,
RK1808_CLKGATE_CON(1), 11, GFLAGS),
- GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_npu_niu", "aclk_npu_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(1), 13, GFLAGS),
COMPOSITE_NOMUX(0, "aclk_npu2mem", "aclk_npu_pre", CLK_IGNORE_UNUSED,
RK1808_CLKSEL_CON(2), 4, 4, DFLAGS,
RK1808_CLKGATE_CON(1), 15, GFLAGS),
GATE(HCLK_NPU, "hclk_npu", "hclk_npu_pre", 0,
RK1808_CLKGATE_CON(1), 12, GFLAGS),
- GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "hclk_npu_niu", "hclk_npu_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(1), 14, GFLAGS),
GATE(SCLK_PVTM_NPU, "clk_pvtm_npu", "xin24m", 0,
RK1808_CLKGATE_CON(0), 15, GFLAGS),
- COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IGNORE_UNUSED,
+ COMPOSITE(ACLK_IMEM_PRE, "aclk_imem_pre", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(17), 7, 1, MFLAGS, 0, 5, DFLAGS,
RK1808_CLKGATE_CON(7), 0, GFLAGS),
GATE(ACLK_IMEM0, "aclk_imem0", "aclk_imem_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(7), 6, GFLAGS),
- GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_imem0_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(7), 10, GFLAGS),
GATE(ACLK_IMEM1, "aclk_imem1", "aclk_imem_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(7), 7, GFLAGS),
- GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_imem1_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(7), 11, GFLAGS),
GATE(ACLK_IMEM2, "aclk_imem2", "aclk_imem_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(7), 8, GFLAGS),
- GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_imem2_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(7), 12, GFLAGS),
GATE(ACLK_IMEM3, "aclk_imem3", "aclk_imem_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(7), 9, GFLAGS),
- GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "aclk_imem3_niu", "aclk_imem_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(7), 13, GFLAGS),
- COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, 0,
+ COMPOSITE(HSCLK_IMEM, "hsclk_imem", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(17), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK1808_CLKGATE_CON(7), 5, GFLAGS),
@@ -417,12 +418,12 @@
RK1808_CLKGATE_CON(8), 5, GFLAGS),
GATE(0, "gpll_ddr", "gpll", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(8), 6, GFLAGS),
- COMPOSITE_DDRCLK(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
- RK1808_CLKSEL_CON(3), 7, 1, 0, 5,
- ROCKCHIP_DDRCLK_SIP_V2),
+
+ COMPOSITE_NOGATE(SCLK_DDRCLK, "sclk_ddrc", mux_ddr_p, CLK_IGNORE_UNUSED,
+ RK1808_CLKSEL_CON(3), 7, 1, MFLAGS, 0, 5, DFLAGS),
FACTOR(0, "clk_ddrphy1x_out", "sclk_ddrc", CLK_IGNORE_UNUSED, 1, 1),
- COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", 0,
+ COMPOSITE_NOMUX(PCLK_DDR, "pclk_ddr", "gpll", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(3), 8, 5, DFLAGS,
RK1808_CLKGATE_CON(2), 1, GFLAGS),
GATE(PCLK_DDRMON, "pclk_ddrmon", "pclk_ddr", CLK_IGNORE_UNUSED,
@@ -433,7 +434,7 @@
RK1808_CLKGATE_CON(2), 9, GFLAGS),
GATE(PCLK_STDBY, "pclk_stdby", "pclk_ddr", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(2), 12, GFLAGS),
- GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IGNORE_UNUSED,
+ GATE(0, "pclk_ddr_grf", "pclk_ddr", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(2), 14, GFLAGS),
GATE(0, "pclk_ddrdfi_ctl", "pclk_ddr", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(2), 2, GFLAGS),
@@ -485,7 +486,7 @@
COMPOSITE_FRACMUX(0, "dclk_vopraw_frac", "dclk_vopraw_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(6), 0,
RK1808_CLKGATE_CON(3), 2, GFLAGS,
- &rk1808_dclk_vopraw_fracmux, RK1808_VOP_RAW_FRAC_MAX_PRATE),
+ &rk1808_dclk_vopraw_fracmux),
GATE(DCLK_VOPRAW, "dclk_vopraw", "dclk_vopraw_mux", 0,
RK1808_CLKGATE_CON(3), 3, GFLAGS),
@@ -495,7 +496,7 @@
COMPOSITE_FRACMUX(0, "dclk_voplite_frac", "dclk_voplite_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(8), 0,
RK1808_CLKGATE_CON(3), 5, GFLAGS,
- &rk1808_dclk_voplite_fracmux, RK1808_VOP_LITE_FRAC_MAX_PRATE),
+ &rk1808_dclk_voplite_fracmux),
GATE(DCLK_VOPLITE, "dclk_voplite", "dclk_voplite_mux", 0,
RK1808_CLKGATE_CON(3), 6, GFLAGS),
@@ -582,18 +583,18 @@
/* PD_PHP */
- COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, 0,
+ COMPOSITE_NODIV(0, "clk_peri_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(19), 15, 1, MFLAGS,
RK1808_CLKGATE_CON(8), 0, GFLAGS),
- COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", 0,
+ COMPOSITE_NOMUX(MSCLK_PERI, "msclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(19), 0, 5, DFLAGS,
RK1808_CLKGATE_CON(8), 1, GFLAGS),
- COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", 0,
+ COMPOSITE_NOMUX(LSCLK_PERI, "lsclk_peri", "clk_peri_src", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(19), 8, 5, DFLAGS,
RK1808_CLKGATE_CON(8), 2, GFLAGS),
- GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IGNORE_UNUSED,
+ GATE(0, "msclk_peri_niu", "msclk_peri", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(8), 3, GFLAGS),
- GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IGNORE_UNUSED,
+ GATE(0, "lsclk_peri_niu", "lsclk_peri", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(8), 4, GFLAGS),
/* PD_MMC */
@@ -711,21 +712,21 @@
/* PD_BUS */
- COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, 0,
+ COMPOSITE_NODIV(0, "clk_bus_src", mux_gpll_cpll_p, CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(27), 15, 1, MFLAGS,
RK1808_CLKGATE_CON(11), 0, GFLAGS),
- COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", 0,
+ COMPOSITE_NOMUX(HSCLK_BUS_PRE, "hsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(27), 8, 5, DFLAGS,
RK1808_CLKGATE_CON(11), 1, GFLAGS),
- COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", 0,
+ COMPOSITE_NOMUX(MSCLK_BUS_PRE, "msclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(28), 0, 5, DFLAGS,
RK1808_CLKGATE_CON(11), 2, GFLAGS),
- COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", 0,
+ COMPOSITE_NOMUX(LSCLK_BUS_PRE, "lsclk_bus_pre", "clk_bus_src", CLK_IS_CRITICAL,
RK1808_CLKSEL_CON(28), 8, 5, DFLAGS,
RK1808_CLKGATE_CON(11), 3, GFLAGS),
- GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "hsclk_bus_niu", "hsclk_bus_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(15), 0, GFLAGS),
- GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "msclk_bus_niu", "msclk_bus_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(15), 1, GFLAGS),
GATE(0, "msclk_sub", "msclk_bus_pre", CLK_IGNORE_UNUSED,
RK1808_CLKGATE_CON(15), 2, GFLAGS),
@@ -739,7 +740,7 @@
RK1808_CLKGATE_CON(15), 6, GFLAGS),
GATE(ACLK_DCF, "aclk_dcf", "msclk_bus_pre", 0,
RK1808_CLKGATE_CON(15), 7, GFLAGS),
- GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IGNORE_UNUSED,
+ GATE(0, "lsclk_bus_niu", "lsclk_bus_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(15), 3, GFLAGS),
GATE(PCLK_DCF, "pclk_dcf", "lsclk_bus_pre", 0,
RK1808_CLKGATE_CON(15), 8, GFLAGS),
@@ -803,7 +804,7 @@
RK1808_CLKGATE_CON(17), 3, GFLAGS),
GATE(0, "hclk_audio_pre", "msclk_bus_pre", 0,
RK1808_CLKGATE_CON(17), 8, GFLAGS),
- GATE(0, "pclk_top_pre", "lsclk_bus_pre", 0,
+ GATE(0, "pclk_top_pre", "lsclk_bus_pre", CLK_IS_CRITICAL,
RK1808_CLKGATE_CON(11), 4, GFLAGS),
COMPOSITE(SCLK_CRYPTO, "clk_crypto", mux_gpll_cpll_p, 0,
@@ -822,7 +823,7 @@
COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(40), 0,
RK1808_CLKGATE_CON(11), 10, GFLAGS,
- &rk1808_uart1_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart1_fracmux),
GATE(SCLK_UART1, "clk_uart1", "clk_uart1_mux", 0,
RK1808_CLKGATE_CON(11), 11, GFLAGS),
@@ -835,7 +836,7 @@
COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(43), 0,
RK1808_CLKGATE_CON(11), 14, GFLAGS,
- &rk1808_uart2_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart2_fracmux),
GATE(SCLK_UART2, "clk_uart2", "clk_uart2_mux", 0,
RK1808_CLKGATE_CON(11), 15, GFLAGS),
@@ -848,7 +849,7 @@
COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(46), 0,
RK1808_CLKGATE_CON(12), 2, GFLAGS,
- &rk1808_uart3_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart3_fracmux),
GATE(SCLK_UART3, "clk_uart3", "clk_uart3_mux", 0,
RK1808_CLKGATE_CON(12), 3, GFLAGS),
@@ -861,7 +862,7 @@
COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(49), 0,
RK1808_CLKGATE_CON(12), 6, GFLAGS,
- &rk1808_uart4_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart4_fracmux),
GATE(SCLK_UART4, "clk_uart4", "clk_uart4_mux", 0,
RK1808_CLKGATE_CON(12), 7, GFLAGS),
@@ -874,7 +875,7 @@
COMPOSITE_FRACMUX(0, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(52), 0,
RK1808_CLKGATE_CON(12), 10, GFLAGS,
- &rk1808_uart5_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart5_fracmux),
GATE(SCLK_UART5, "clk_uart5", "clk_uart5_mux", 0,
RK1808_CLKGATE_CON(12), 11, GFLAGS),
@@ -887,7 +888,7 @@
COMPOSITE_FRACMUX(0, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(55), 0,
RK1808_CLKGATE_CON(12), 14, GFLAGS,
- &rk1808_uart6_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart6_fracmux),
GATE(SCLK_UART6, "clk_uart6", "clk_uart6_mux", 0,
RK1808_CLKGATE_CON(12), 15, GFLAGS),
@@ -900,7 +901,7 @@
COMPOSITE_FRACMUX(0, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(58), 0,
RK1808_CLKGATE_CON(13), 2, GFLAGS,
- &rk1808_uart7_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart7_fracmux),
GATE(SCLK_UART7, "clk_uart7", "clk_uart7_mux", 0,
RK1808_CLKGATE_CON(13), 3, GFLAGS),
@@ -1003,7 +1004,7 @@
COMPOSITE_FRACMUX(0, "clk_pdm_frac", "clk_pdm_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(31), 0,
RK1808_CLKGATE_CON(17), 10, GFLAGS,
- &rk1808_pdm_fracmux, RK1808_PDM_FRAC_MAX_PRATE),
+ &rk1808_pdm_fracmux),
GATE(SCLK_PDM, "clk_pdm", "clk_pdm_mux", 0,
RK1808_CLKGATE_CON(17), 11, GFLAGS),
@@ -1013,7 +1014,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(33), 0,
RK1808_CLKGATE_CON(17), 13, GFLAGS,
- &rk1808_i2s0_8ch_tx_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
+ &rk1808_i2s0_8ch_tx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", mux_i2s0_8ch_tx_rx_p, CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(32), 12, 1, MFLAGS,
RK1808_CLKGATE_CON(17), 14, GFLAGS),
@@ -1027,7 +1028,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(35), 0,
RK1808_CLKGATE_CON(18), 1, GFLAGS,
- &rk1808_i2s0_8ch_rx_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
+ &rk1808_i2s0_8ch_rx_fracmux),
COMPOSITE_NODIV(SCLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", mux_i2s0_8ch_rx_tx_p, CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(34), 12, 1, MFLAGS,
RK1808_CLKGATE_CON(18), 2, GFLAGS),
@@ -1041,7 +1042,7 @@
COMPOSITE_FRACMUX(0, "clk_i2s1_2ch_frac", "clk_i2s1_2ch_src", CLK_SET_RATE_PARENT,
RK1808_CLKSEL_CON(37), 0,
RK1808_CLKGATE_CON(18), 5, GFLAGS,
- &rk1808_i2s1_2ch_fracmux, RK1808_I2S_FRAC_MAX_PRATE),
+ &rk1808_i2s1_2ch_fracmux),
GATE(SCLK_I2S1_2CH, "clk_i2s1_2ch", "clk_i2s1_2ch_mux", 0,
RK1808_CLKGATE_CON(18), 6, GFLAGS),
COMPOSITE_NODIV(SCLK_I2S1_2CH_OUT, "clk_i2s1_2ch_out", mux_i2s1_2ch_out_p, CLK_SET_RATE_PARENT,
@@ -1073,7 +1074,7 @@
COMPOSITE_FRACMUX(SCLK_RTC32K_FRAC, "clk_rtc32k_frac", "xin24m", CLK_IGNORE_UNUSED,
RK1808_PMU_CLKSEL_CON(1), 0,
RK1808_PMU_CLKGATE_CON(0), 13, GFLAGS,
- &rk1808_rtc32k_pmu_fracmux, 0),
+ &rk1808_rtc32k_pmu_fracmux),
COMPOSITE_NOMUX(XIN24M_DIV, "xin24m_div", "xin24m", CLK_IGNORE_UNUSED,
RK1808_PMU_CLKSEL_CON(0), 8, 5, DFLAGS,
@@ -1095,7 +1096,7 @@
COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_pmu_src", CLK_SET_RATE_PARENT,
RK1808_PMU_CLKSEL_CON(5), 0,
RK1808_PMU_CLKGATE_CON(1), 2, GFLAGS,
- &rk1808_uart0_pmu_fracmux, RK1808_UART_FRAC_MAX_PRATE),
+ &rk1808_uart0_pmu_fracmux),
GATE(SCLK_UART0_PMU, "clk_uart0_pmu", "clk_uart0_pmu_mux", CLK_SET_RATE_PARENT,
RK1808_PMU_CLKGATE_CON(1), 3, GFLAGS),
@@ -1128,11 +1129,11 @@
RK1808_PMU_CLKSEL_CON(7), 4, 1, MFLAGS,
RK1808_PMU_CLKGATE_CON(1), 12, GFLAGS),
- COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", 0,
+ COMPOSITE_NOMUX(PCLK_PMU_PRE, "pclk_pmu_pre", "ppll", CLK_IS_CRITICAL,
RK1808_PMU_CLKSEL_CON(0), 0, 5, DFLAGS,
RK1808_PMU_CLKGATE_CON(0), 0, GFLAGS),
- GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
+ GATE(0, "pclk_pmu_niu", "pclk_pmu_pre", CLK_IS_CRITICAL, RK1808_PMU_CLKGATE_CON(0), 1, GFLAGS),
GATE(0, "pclk_pmu_sgrf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 2, GFLAGS),
GATE(0, "pclk_pmu_grf", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 3, GFLAGS),
GATE(0, "pclk_pmu", "pclk_pmu_pre", CLK_IGNORE_UNUSED, RK1808_PMU_CLKGATE_CON(0), 4, GFLAGS),
@@ -1144,27 +1145,6 @@
MUXPMUGRF(SCLK_32K_IOE, "clk_32k_ioe", mux_clk_32k_ioe_p, 0,
RK1808_PMUGRF_SOC_CON0, 0, 1, MFLAGS)
-};
-
-static const char *const rk1808_critical_clocks[] __initconst = {
- "msclk_core_niu",
- "aclk_gic_niu",
- "aclk_npu_niu",
- "hclk_npu_niu",
- "aclk_imem0_niu",
- "aclk_imem1_niu",
- "aclk_imem2_niu",
- "aclk_imem3_niu",
- "msclk_peri_niu",
- "lsclk_peri_niu",
- "hsclk_bus_niu",
- "msclk_bus_niu",
- "lsclk_bus_niu",
- "pclk_pmu_niu",
- "pclk_top_pre",
- "pclk_ddr_grf",
- "aclk_gic",
- "hsclk_imem",
};
static void __iomem *rk1808_cru_base;
@@ -1198,6 +1178,7 @@
{
struct rockchip_clk_provider *ctx;
void __iomem *reg_base;
+ struct clk **clks;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -1213,17 +1194,16 @@
iounmap(reg_base);
return;
}
+ clks = ctx->clk_data.clks;
rockchip_clk_register_plls(ctx, rk1808_pll_clks,
ARRAY_SIZE(rk1808_pll_clks),
RK1808_GRF_SOC_STATUS0);
rockchip_clk_register_branches(ctx, rk1808_clk_branches,
ARRAY_SIZE(rk1808_clk_branches));
- rockchip_clk_protect_critical(rk1808_critical_clocks,
- ARRAY_SIZE(rk1808_critical_clocks));
rockchip_clk_register_armclk(ctx, ARMCLK, "armclk",
- mux_armclk_p, ARRAY_SIZE(mux_armclk_p),
+ 3, clks[PLL_APLL], clks[PLL_GPLL],
&rk1808_cpuclk_data, rk1808_cpuclk_rates,
ARRAY_SIZE(rk1808_cpuclk_rates));
@@ -1239,3 +1219,31 @@
}
CLK_OF_DECLARE(rk1808_cru, "rockchip,rk1808-cru", rk1808_clk_init);
+
+static int __init clk_rk1808_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+
+ rk1808_clk_init(np);
+
+ return 0;
+}
+
+static const struct of_device_id clk_rk1808_match_table[] = {
+ {
+ .compatible = "rockchip,rk1808-cru",
+ },
+ { }
+};
+MODULE_DEVICE_TABLE(of, clk_rk1808_match_table);
+
+static struct platform_driver clk_rk1808_driver = {
+ .driver = {
+ .name = "clk-rk1808",
+ .of_match_table = clk_rk1808_match_table,
+ },
+};
+builtin_platform_driver_probe(clk_rk1808_driver, clk_rk1808_probe);
+
+MODULE_DESCRIPTION("Rockchip RK1808 Clock Driver");
+MODULE_LICENSE("GPL");
--
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