From cf4ce59b3b70238352c7f1729f0f7223214828ad Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 20 Sep 2024 01:46:19 +0000
Subject: [PATCH] rtl88x2CE_WiFi_linux add concurrent mode

---
 kernel/sound/soc/rockchip/rockchip_i2s_tdm.h |   49 +++++++++++++++++++++++++++++++++++++++++--------
 1 files changed, 41 insertions(+), 8 deletions(-)

diff --git a/kernel/sound/soc/rockchip/rockchip_i2s_tdm.h b/kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
index fa41f81..904afe0 100644
--- a/kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
+++ b/kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
@@ -24,8 +24,9 @@
 #define I2S_TXCR_RCNT_SHIFT	17
 #define I2S_TXCR_RCNT_MASK	(0x3f << I2S_TXCR_RCNT_SHIFT)
 #define I2S_TXCR_CSR_SHIFT	15
-#define I2S_TXCR_CSR(x)		((x) << I2S_TXCR_CSR_SHIFT)
 #define I2S_TXCR_CSR_MASK	(3 << I2S_TXCR_CSR_SHIFT)
+#define I2S_TXCR_CSR(x)		((x) << I2S_TXCR_CSR_SHIFT)
+#define I2S_TXCR_CSR_V(v)	((((v) & I2S_TXCR_CSR_MASK) >> 15) + 1)
 #define I2S_TXCR_HWT		BIT(14)
 #define I2S_TXCR_SJM_SHIFT	12
 #define I2S_TXCR_SJM_R		(0 << I2S_TXCR_SJM_SHIFT)
@@ -59,8 +60,9 @@
 #define I2S_RXCR_PATH_MASK(x)	(0x3 << I2S_RXCR_PATH_SHIFT(x))
 #define I2S_RXCR_PATH(x, v)	((v) << I2S_RXCR_PATH_SHIFT(x))
 #define I2S_RXCR_CSR_SHIFT	15
-#define I2S_RXCR_CSR(x)		((x) << I2S_RXCR_CSR_SHIFT)
 #define I2S_RXCR_CSR_MASK	(3 << I2S_RXCR_CSR_SHIFT)
+#define I2S_RXCR_CSR(x)		((x) << I2S_RXCR_CSR_SHIFT)
+#define I2S_RXCR_CSR_V(v)	((((v) & I2S_RXCR_CSR_MASK) >> 15) + 1)
 #define I2S_RXCR_HWT		BIT(14)
 #define I2S_RXCR_SJM_SHIFT	12
 #define I2S_RXCR_SJM_R		(0 << I2S_RXCR_SJM_SHIFT)
@@ -144,15 +146,21 @@
 #define I2S_DMACR_RDE_SHIFT	24
 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
+#define I2S_DMACR_RDE_MASK	(1 << I2S_DMACR_RDE_SHIFT)
+#define I2S_DMACR_RDE(x)	((x) << I2S_DMACR_RDE_SHIFT)
 #define I2S_DMACR_RDL_SHIFT	16
-#define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
+#define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
+#define I2S_DMACR_RDL_V(v)	((((v) & I2S_DMACR_RDL_MASK) >> 16) + 1)
 #define I2S_DMACR_TDE_SHIFT	8
 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
+#define I2S_DMACR_TDE_MASK	(1 << I2S_DMACR_TDE_SHIFT)
+#define I2S_DMACR_TDE(x)	((x) << I2S_DMACR_TDE_SHIFT)
 #define I2S_DMACR_TDL_SHIFT	0
-#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
+#define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
+#define I2S_DMACR_TDL_V(v)	(((v) & I2S_DMACR_TDL_MASK) >> 0)
 
 /*
  * INTCR
@@ -162,8 +170,8 @@
 #define I2S_INTCR_RFT(x)	(((x) - 1) << I2S_INTCR_RFT_SHIFT)
 #define I2S_INTCR_RXOIC		BIT(18)
 #define I2S_INTCR_RXOIE_SHIFT	17
-#define I2S_INTCR_RXOIE_DISABLE	(0 << I2S_INTCR_RXOIE_SHIFT)
-#define I2S_INTCR_RXOIE_ENABLE	(1 << I2S_INTCR_RXOIE_SHIFT)
+#define I2S_INTCR_RXOIE_MASK	(1 << I2S_INTCR_RXOIE_SHIFT)
+#define I2S_INTCR_RXOIE(x)	((x) << I2S_INTCR_RXOIE_SHIFT)
 #define I2S_INTCR_RXFIE_SHIFT	16
 #define I2S_INTCR_RXFIE_DISABLE	(0 << I2S_INTCR_RXFIE_SHIFT)
 #define I2S_INTCR_RXFIE_ENABLE	(1 << I2S_INTCR_RXFIE_SHIFT)
@@ -172,8 +180,8 @@
 #define I2S_INTCR_TFT_MASK	(0x1f << I2S_INTCR_TFT_SHIFT)
 #define I2S_INTCR_TXUIC		BIT(2)
 #define I2S_INTCR_TXUIE_SHIFT	1
-#define I2S_INTCR_TXUIE_DISABLE	(0 << I2S_INTCR_TXUIE_SHIFT)
-#define I2S_INTCR_TXUIE_ENABLE	(1 << I2S_INTCR_TXUIE_SHIFT)
+#define I2S_INTCR_TXUIE_MASK	(1 << I2S_INTCR_TXUIE_SHIFT)
+#define I2S_INTCR_TXUIE(x)	((x) << I2S_INTCR_TXUIE_SHIFT)
 
 /*
  * INTSR
@@ -199,12 +207,37 @@
  * XFER
  * Transfer start register
  */
+/*
+ * lp mode2 swap:
+ * i2s sdi0_l <- i2s sdo0_l
+ * i2s sdi0_r <- codec sdo_r
+ *
+ * lp mode2:
+ * i2s sdi0_l <- codec sdo_l
+ * i2s sdi0_r <- i2s sdo0_r
+ *
+ * lp mode1:
+ * i2s sdi0_l <- codec sdo_l
+ * i2s sdi0_r <- codec sdo_r
+ * i2s sdi1_l <- i2s sdo0_l
+ * i2s sdi1_r <- i2s sdo0_r
+ *
+ */
+#define I2S_XFER_LP_MODE_MASK	GENMASK(4, 2)
+#define I2S_XFER_LP_MODE_2_SWAP	(BIT(4) | BIT(3))
+#define I2S_XFER_LP_MODE_2	BIT(3)
+#define I2S_XFER_LP_MODE_1	BIT(2)
+#define I2S_XFER_LP_MODE_DIS	0
 #define I2S_XFER_RXS_SHIFT	1
 #define I2S_XFER_RXS_STOP	(0 << I2S_XFER_RXS_SHIFT)
 #define I2S_XFER_RXS_START	(1 << I2S_XFER_RXS_SHIFT)
+#define I2S_XFER_RXS_MASK	(1 << I2S_XFER_RXS_SHIFT)
+#define I2S_XFER_RXS(x)		((x) << I2S_XFER_RXS_SHIFT)
 #define I2S_XFER_TXS_SHIFT	0
 #define I2S_XFER_TXS_STOP	(0 << I2S_XFER_TXS_SHIFT)
 #define I2S_XFER_TXS_START	(1 << I2S_XFER_TXS_SHIFT)
+#define I2S_XFER_TXS_MASK	(1 << I2S_XFER_TXS_SHIFT)
+#define I2S_XFER_TXS(x)		((x) << I2S_XFER_TXS_SHIFT)
 
 /*
  * CLR

--
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