From bedbef8ad3e75a304af6361af235302bcc61d06b Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 14 May 2024 06:39:01 +0000
Subject: [PATCH] 修改内核路径
---
kernel/drivers/net/phy/rk630phy.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++----
1 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/kernel/drivers/net/phy/rk630phy.c b/kernel/drivers/net/phy/rk630phy.c
index 327301d..de76196 100644
--- a/kernel/drivers/net/phy/rk630phy.c
+++ b/kernel/drivers/net/phy/rk630phy.c
@@ -160,14 +160,33 @@
phy_write(phydev, REG_PAGE_SEL, 0x0000);
}
-static void rk630_phy_set_uaps(struct phy_device *phydev)
+static void rk630_phy_set_aps(struct phy_device *phydev, bool enable)
+{
+ u32 value;
+
+ /* Switch to page 1 */
+ phy_write(phydev, REG_PAGE_SEL, 0x0100);
+ value = phy_read(phydev, REG_PAGE1_APS_CTRL);
+ if (enable)
+ value |= BIT(15);
+ else
+ value &= ~BIT(15);
+ phy_write(phydev, REG_PAGE1_APS_CTRL, value);
+ /* Switch to page 0 */
+ phy_write(phydev, REG_PAGE_SEL, 0x0000);
+}
+
+static void rk630_phy_set_uaps(struct phy_device *phydev, bool enable)
{
u32 value;
/* Switch to page 1 */
phy_write(phydev, REG_PAGE_SEL, 0x0100);
value = phy_read(phydev, REG_PAGE1_UAPS_CONFIGURE);
- value |= BIT(15);
+ if (enable)
+ value |= BIT(15);
+ else
+ value &= ~BIT(15);
phy_write(phydev, REG_PAGE1_UAPS_CONFIGURE, value);
/* Switch to page 0 */
phy_write(phydev, REG_PAGE_SEL, 0x0000);
@@ -208,6 +227,8 @@
/* Switch to page 1 */
phy_write(phydev, REG_PAGE_SEL, 0x0100);
+ /* Enable offset clock */
+ phy_write(phydev, 0x10, 0xfbfe);
/* Disable APS */
phy_write(phydev, REG_PAGE1_APS_CTRL, 0x4824);
/* Switch to page 2 */
@@ -244,6 +265,8 @@
phy_write(phydev, REG_PAGE_SEL, 0x0800);
/* Disable auto-cal */
phy_write(phydev, REG_PAGE8_AUTO_CAL, 0x0844);
+ /* Reatart offset calibration */
+ phy_write(phydev, 0x13, 0xc096);
/* Switch to page 0 */
phy_write(phydev, REG_PAGE_SEL, 0x0000);
@@ -264,10 +287,12 @@
* Ultra Auto-Power Saving Mode (UAPS) is designed to
* save power when cable is not plugged into PHY.
*/
- rk630_phy_set_uaps(phydev);
+ rk630_phy_set_uaps(phydev, true);
break;
case PHY_ADDR_T22:
rk630_phy_t22_config_init(phydev);
+ rk630_phy_set_aps(phydev, false);
+ rk630_phy_set_uaps(phydev, false);
break;
default:
phydev_err(phydev, "Unsupported address for current phy: %d\n",
@@ -278,6 +303,23 @@
rk630_phy_ieee_set(phydev, true);
return 0;
+}
+
+static void rk630_link_change_notify(struct phy_device *phydev)
+{
+ unsigned int val;
+
+ if (phydev->state == PHY_RUNNING || phydev->state == PHY_NOLINK) {
+ /* Switch to page 6 */
+ phy_write(phydev, REG_PAGE_SEL, 0x0600);
+ val = phy_read(phydev, REG_PAGE6_AFE_TX_CTRL);
+ val &= ~GENMASK(14, 13);
+ if (phydev->speed == SPEED_10 && phydev->link)
+ val |= BIT(13);
+ phy_write(phydev, REG_PAGE6_AFE_TX_CTRL, val);
+ /* Switch to page 0 */
+ phy_write(phydev, REG_PAGE_SEL, 0x0000);
+ }
}
static irqreturn_t rk630_wol_irq_thread(int irq, void *dev_id)
@@ -365,6 +407,7 @@
.name = "RK630 PHY",
.features = PHY_BASIC_FEATURES,
.flags = 0,
+ .link_change_notify = rk630_link_change_notify,
.probe = rk630_phy_probe,
.remove = rk630_phy_remove,
.soft_reset = genphy_soft_reset,
@@ -381,7 +424,7 @@
{ }
};
-MODULE_DEVICE_TABLE(mdio, rockchip_phy_tbl);
+MODULE_DEVICE_TABLE(mdio, rk630_phy_tbl);
module_phy_driver(rk630_phy_driver);
--
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