From b625cdcd68479b3d540a915785b6d9809b52a2f8 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 14 Feb 2023 06:37:54 +0000
Subject: [PATCH] stmmac read mac form eeprom
---
kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c | 380 +++++++++++++++++++++++------------------------------
1 files changed, 166 insertions(+), 214 deletions(-)
diff --git a/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
index 870e60a..c6b6cae 100644
--- a/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
+++ b/kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
@@ -47,10 +47,7 @@
void (*set_to_qsgmii)(struct rk_priv_data *bsp_priv);
void (*set_rgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
void (*set_rmii_speed)(struct rk_priv_data *bsp_priv, int speed);
- void (*set_sgmii_speed)(struct rk_priv_data *bsp_priv, int speed);
- void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input,
- bool enable);
- void (*integrated_phy_power)(struct rk_priv_data *bsp_priv, bool up);
+ void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv);
};
struct rk_priv_data {
@@ -64,7 +61,6 @@
bool clk_enabled;
bool clock_input;
bool integrated_phy;
- struct phy *comphy;
struct clk *clk_mac;
struct clk *gmac_clkin;
@@ -169,10 +165,10 @@
int ret, i, id = bsp_priv->bus_id;
u32 val;
- if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
+ if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
return 0;
- ret = xpcs_soft_reset(bsp_priv, 0);
+ ret = xpcs_soft_reset(bsp_priv, id);
if (ret) {
dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
return ret;
@@ -199,10 +195,10 @@
SR_MII_CTRL_AN_ENABLE);
}
} else {
- val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
- xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
+ val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
+ xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
val | MII_MAC_AUTO_SW);
- xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
+ xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
SR_MII_CTRL_AN_ENABLE);
}
@@ -216,55 +212,8 @@
#define GRF_CLR_BIT(nr) (BIT(nr+16))
#define DELAY_ENABLE(soc, tx, rx) \
- ((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
- (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
-
-#define DELAY_VALUE(soc, tx, rx) \
- ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) | \
- (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
-
-/* Integrated EPHY */
-
-#define RK_GRF_MACPHY_CON0 0xb00
-#define RK_GRF_MACPHY_CON1 0xb04
-#define RK_GRF_MACPHY_CON2 0xb08
-#define RK_GRF_MACPHY_CON3 0xb0c
-
-#define RK_MACPHY_ENABLE GRF_BIT(0)
-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
-
-static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
-{
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
-
- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
-
- if (priv->phy_reset) {
- /* PHY needs to be disabled before trying to reset it */
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
- if (priv->phy_reset)
- reset_control_assert(priv->phy_reset);
- usleep_range(10, 20);
- if (priv->phy_reset)
- reset_control_deassert(priv->phy_reset);
- usleep_range(10, 20);
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
- msleep(30);
- }
-}
-
-static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
-{
- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
- if (priv->phy_reset)
- reset_control_assert(priv->phy_reset);
-}
+ (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \
+ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
#define PX30_GRF_GMAC_CON1 0x0904
@@ -357,10 +306,12 @@
regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
RK1808_GMAC_PHY_INTF_SEL_RGMII |
- DELAY_ENABLE(RK1808, tx_delay, rx_delay));
+ RK1808_GMAC_RXCLK_DLY_ENABLE |
+ RK1808_GMAC_TXCLK_DLY_ENABLE);
regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
- DELAY_VALUE(RK1808, tx_delay, rx_delay));
+ RK1808_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK1808_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -488,7 +439,8 @@
RK3128_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
DELAY_ENABLE(RK3128, tx_delay, rx_delay) |
- DELAY_VALUE(RK3128, tx_delay, rx_delay));
+ RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -604,7 +556,8 @@
DELAY_ENABLE(RK3228, tx_delay, rx_delay));
regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
- DELAY_VALUE(RK3128, tx_delay, rx_delay));
+ RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -667,16 +620,10 @@
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
-static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
+static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
{
- if (up) {
- regmap_write(priv->grf, RK3228_GRF_CON_MUX,
- RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
-
- rk_gmac_integrated_ephy_powerup(priv);
- } else {
- rk_gmac_integrated_ephy_powerdown(priv);
- }
+ regmap_write(priv->grf, RK3228_GRF_CON_MUX,
+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
}
static const struct rk_gmac_ops rk3228_ops = {
@@ -684,7 +631,7 @@
.set_to_rmii = rk3228_set_to_rmii,
.set_rgmii_speed = rk3228_set_rgmii_speed,
.set_rmii_speed = rk3228_set_rmii_speed,
- .integrated_phy_power = rk3228_integrated_phy_power,
+ .integrated_phy_powerup = rk3228_integrated_phy_powerup,
};
#define RK3288_GRF_SOC_CON1 0x0248
@@ -730,7 +677,8 @@
RK3288_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
DELAY_ENABLE(RK3288, tx_delay, rx_delay) |
- DELAY_VALUE(RK3288, tx_delay, rx_delay));
+ RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -901,10 +849,12 @@
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
RK3328_GMAC_PHY_INTF_SEL_RGMII |
RK3328_GMAC_RMII_MODE_CLR |
- DELAY_ENABLE(RK3328, tx_delay, rx_delay));
+ RK3328_GMAC_RXCLK_DLY_ENABLE |
+ RK3328_GMAC_TXCLK_DLY_ENABLE);
regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
- DELAY_VALUE(RK3328, tx_delay, rx_delay));
+ RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -972,16 +922,10 @@
dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
}
-static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
+static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
{
- if (up) {
- regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
- RK3328_MACPHY_RMII_MODE);
-
- rk_gmac_integrated_ephy_powerup(priv);
- } else {
- rk_gmac_integrated_ephy_powerdown(priv);
- }
+ regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
+ RK3328_MACPHY_RMII_MODE);
}
static const struct rk_gmac_ops rk3328_ops = {
@@ -989,7 +933,7 @@
.set_to_rmii = rk3328_set_to_rmii,
.set_rgmii_speed = rk3328_set_rgmii_speed,
.set_rmii_speed = rk3328_set_rmii_speed,
- .integrated_phy_power = rk3328_integrated_phy_power,
+ .integrated_phy_powerup = rk3328_integrated_phy_powerup,
};
#define RK3366_GRF_SOC_CON6 0x0418
@@ -1035,7 +979,8 @@
RK3366_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
DELAY_ENABLE(RK3366, tx_delay, rx_delay) |
- DELAY_VALUE(RK3366, tx_delay, rx_delay));
+ RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -1145,7 +1090,8 @@
RK3368_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
DELAY_ENABLE(RK3368, tx_delay, rx_delay) |
- DELAY_VALUE(RK3368, tx_delay, rx_delay));
+ RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -1255,7 +1201,8 @@
RK3399_GMAC_RMII_MODE_CLR);
regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
DELAY_ENABLE(RK3399, tx_delay, rx_delay) |
- DELAY_VALUE(RK3399, tx_delay, rx_delay));
+ RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -1402,10 +1349,12 @@
regmap_write(bsp_priv->grf, offset_con1,
RK3568_GMAC_PHY_INTF_SEL_RGMII |
- DELAY_ENABLE(RK3568, tx_delay, rx_delay));
+ RK3568_GMAC_RXCLK_DLY_ENABLE |
+ RK3568_GMAC_TXCLK_DLY_ENABLE);
regmap_write(bsp_priv->grf, offset_con0,
- DELAY_VALUE(RK3568, tx_delay, rx_delay));
+ RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) |
+ RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
}
static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -1451,34 +1400,6 @@
__func__, rate, ret);
}
-static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
-{
- struct device *dev = &bsp_priv->pdev->dev;
- unsigned int ctrl;
-
- /* Only gmac1 set the speed for port1 */
- if (!bsp_priv->bus_id)
- return;
-
- switch (speed) {
- case 10:
- ctrl = BMCR_SPEED10;
- break;
- case 100:
- ctrl = BMCR_SPEED100;
- break;
- case 1000:
- ctrl = BMCR_SPEED1000;
- break;
- default:
- dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
- return;
- }
-
- xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
- ctrl | BMCR_FULLDPLX);
-}
-
static const struct rk_gmac_ops rk3568_ops = {
.set_to_rgmii = rk3568_set_to_rgmii,
.set_to_rmii = rk3568_set_to_rmii,
@@ -1486,7 +1407,6 @@
.set_to_qsgmii = rk3568_set_to_qsgmii,
.set_rgmii_speed = rk3568_set_gmac_speed,
.set_rmii_speed = rk3568_set_gmac_speed,
- .set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
};
#define RV1108_GRF_GMAC_CON0 0X0900
@@ -1552,18 +1472,21 @@
(GRF_CLR_BIT(4) | GRF_CLR_BIT(5) | GRF_BIT(6))
#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
-#define RV1126_M0_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
-#define RV1126_M0_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
-#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
-#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
-#define RV1126_M1_GMAC_RXCLK_DLY_ENABLE GRF_BIT(3)
-#define RV1126_M1_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
-#define RV1126_M1_GMAC_TXCLK_DLY_ENABLE GRF_BIT(2)
-#define RV1126_M1_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
+#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
+#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
+#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
+#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
+#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
+#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
+#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
+#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
-/* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
-#define RV1126_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
-#define RV1126_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+/* RV1126_GRF_GMAC_CON1 */
+#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
+/* RV1126_GRF_GMAC_CON2 */
+#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
+#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
int tx_delay, int rx_delay)
@@ -1577,14 +1500,18 @@
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
RV1126_GMAC_PHY_INTF_SEL_RGMII |
- DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) |
- DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
+ RV1126_GMAC_M0_RXCLK_DLY_ENABLE |
+ RV1126_GMAC_M0_TXCLK_DLY_ENABLE |
+ RV1126_GMAC_M1_RXCLK_DLY_ENABLE |
+ RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
- DELAY_VALUE(RV1126, tx_delay, rx_delay));
+ RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) |
+ RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
- DELAY_VALUE(RV1126, tx_delay, rx_delay));
+ RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) |
+ RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
}
static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
@@ -1657,6 +1584,50 @@
.set_rgmii_speed = rv1126_set_rgmii_speed,
.set_rmii_speed = rv1126_set_rmii_speed,
};
+
+#define RK_GRF_MACPHY_CON0 0xb00
+#define RK_GRF_MACPHY_CON1 0xb04
+#define RK_GRF_MACPHY_CON2 0xb08
+#define RK_GRF_MACPHY_CON3 0xb0c
+
+#define RK_MACPHY_ENABLE GRF_BIT(0)
+#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
+#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
+#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7))
+#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
+#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
+
+static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
+{
+ if (priv->ops->integrated_phy_powerup)
+ priv->ops->integrated_phy_powerup(priv);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
+
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
+
+ if (priv->phy_reset) {
+ /* PHY needs to be disabled before trying to reset it */
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+ usleep_range(10, 20);
+ if (priv->phy_reset)
+ reset_control_deassert(priv->phy_reset);
+ usleep_range(10, 20);
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
+ msleep(30);
+ }
+}
+
+static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
+{
+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
+ if (priv->phy_reset)
+ reset_control_assert(priv->phy_reset);
+}
static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
{
@@ -1777,23 +1748,15 @@
if (!IS_ERR(bsp_priv->pclk_xpcs))
clk_prepare_enable(bsp_priv->pclk_xpcs);
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
- bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
- true);
-
/**
* if (!IS_ERR(bsp_priv->clk_mac))
* clk_prepare_enable(bsp_priv->clk_mac);
*/
- usleep_range(100, 200);
+ mdelay(5);
bsp_priv->clk_enabled = true;
}
} else {
if (bsp_priv->clk_enabled) {
- if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
- bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
- false);
-
if (phy_iface == PHY_INTERFACE_MODE_RMII) {
clk_disable_unprepare(bsp_priv->mac_clk_rx);
@@ -1890,7 +1853,7 @@
ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
if (ret) {
- bsp_priv->tx_delay = -1;
+ bsp_priv->tx_delay = 0x30;
dev_err(dev, "Can not read property: tx_delay.");
dev_err(dev, "set tx_delay to 0x%x\n",
bsp_priv->tx_delay);
@@ -1901,7 +1864,7 @@
ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
if (ret) {
- bsp_priv->rx_delay = -1;
+ bsp_priv->rx_delay = 0x10;
dev_err(dev, "Can not read property: rx_delay.");
dev_err(dev, "set rx_delay to 0x%x\n",
bsp_priv->rx_delay);
@@ -1915,11 +1878,14 @@
bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
"rockchip,xpcs");
if (!IS_ERR(bsp_priv->xpcs)) {
- bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
- if (IS_ERR(bsp_priv->comphy)) {
- bsp_priv->comphy = NULL;
+ struct phy *comphy;
+
+ comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
+ if (IS_ERR(comphy))
dev_err(dev, "devm_of_phy_get error\n");
- }
+ ret = phy_init(comphy);
+ if (ret)
+ dev_err(dev, "phy_init error\n");
}
if (plat->phy_node) {
@@ -1961,17 +1927,17 @@
case PHY_INTERFACE_MODE_RGMII_ID:
dev_info(dev, "init for RGMII_ID\n");
if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
- bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
+ bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
break;
case PHY_INTERFACE_MODE_RGMII_RXID:
dev_info(dev, "init for RGMII_RXID\n");
if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
+ bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
break;
case PHY_INTERFACE_MODE_RGMII_TXID:
dev_info(dev, "init for RGMII_TXID\n");
if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
- bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
+ bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
break;
case PHY_INTERFACE_MODE_RMII:
dev_info(dev, "init for RMII\n");
@@ -1980,23 +1946,11 @@
break;
case PHY_INTERFACE_MODE_SGMII:
dev_info(dev, "init for SGMII\n");
- ret = phy_init(bsp_priv->comphy);
- if (ret) {
- dev_err(dev, "phy_init error: %d\n", ret);
- return ret;
- }
-
if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
bsp_priv->ops->set_to_sgmii(bsp_priv);
break;
case PHY_INTERFACE_MODE_QSGMII:
dev_info(dev, "init for QSGMII\n");
- ret = phy_init(bsp_priv->comphy);
- if (ret) {
- dev_err(dev, "phy_init error: %d\n", ret);
- return ret;
- }
-
if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
bsp_priv->ops->set_to_qsgmii(bsp_priv);
break;
@@ -2013,6 +1967,9 @@
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
+ if (bsp_priv->integrated_phy)
+ rk_gmac_integrated_phy_powerup(bsp_priv);
+
return 0;
}
@@ -2020,9 +1977,8 @@
{
struct device *dev = &gmac->pdev->dev;
- if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII ||
- gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
- phy_exit(gmac->comphy);
+ if (gmac->integrated_phy)
+ rk_gmac_integrated_phy_powerdown(gmac);
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
@@ -2049,26 +2005,11 @@
bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
break;
case PHY_INTERFACE_MODE_SGMII:
- if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
- bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
case PHY_INTERFACE_MODE_QSGMII:
break;
default:
dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
}
-}
-
-static int rk_integrated_phy_power(void *priv, bool up)
-{
- struct rk_priv_data *bsp_priv = priv;
-
- if (!bsp_priv->integrated_phy || !bsp_priv->ops ||
- !bsp_priv->ops->integrated_phy_power)
- return 0;
-
- bsp_priv->ops->integrated_phy_power(bsp_priv, up);
-
- return 0;
}
void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
@@ -2109,17 +2050,24 @@
{
}
+static unsigned char macaddr[6];
+extern ssize_t at24_mac_read(unsigned char* addr);
void rk_get_eth_addr(void *priv, unsigned char *addr)
{
struct rk_priv_data *bsp_priv = priv;
struct device *dev = &bsp_priv->pdev->dev;
- unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
- int ret, id = bsp_priv->bus_id;
+ int i;
+ //unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
+ //int ret, id = bsp_priv->bus_id;
+ //ben
+ printk("nk-debug:enter rk_get_eth_addr.. \n");
+
+ #if 0
rk_devinfo_get_eth_mac(addr);
if (is_valid_ether_addr(addr))
goto out;
-
+
if (id < 0 || id >= MAX_ETH) {
dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
return;
@@ -2146,7 +2094,35 @@
} else {
memcpy(addr, ðaddr[id * ETH_ALEN], ETH_ALEN);
}
+ #endif
+
+ #if 0
+ macaddr[0] = 0xee;
+ macaddr[1] = 0x31;
+ macaddr[2] = 0x32;
+ macaddr[3] = 0x33;
+ macaddr[4] = 0x34;
+ macaddr[5] = 0x35;
+
+ memcpy(addr, macaddr, 6);
+ #endif
+
+ #if 1
+ if (at24_mac_read(macaddr) > 0) {
+ printk("ben %s: at24_mac_read Success!! \n", __func__);
+ memcpy(addr, macaddr, 6);
+ printk("Read the Ethernet MAC address from :");
+ for (i = 0; i < 5; i++)
+ printk("%2.2x:", addr[i]);
+
+ printk("%2.2x\n", addr[i]);
+ } else {
+ printk("ben %s: at24_mac_read Failed!! \n", __func__);
+ goto out;
+ }
+ #endif
+
out:
dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
}
@@ -2158,6 +2134,7 @@
const struct rk_gmac_ops *data;
int ret;
+ printk("nk-debug:enter rk_gmac_probe 1.. \n");
data = of_device_get_match_data(&pdev->dev);
if (!data) {
dev_err(&pdev->dev, "no of match data provided\n");
@@ -2177,7 +2154,6 @@
plat_dat->fix_mac_speed = rk_fix_speed;
plat_dat->get_eth_addr = rk_get_eth_addr;
- plat_dat->integrated_phy_power = rk_integrated_phy_power;
plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
if (IS_ERR(plat_dat->bsp_priv)) {
@@ -2185,6 +2161,7 @@
goto err_remove_config_dt;
}
+ printk("nk-debug:enter rk_gmac_probe 2.. \n");
ret = rk_gmac_clk_init(plat_dat);
if (ret)
goto err_remove_config_dt;
@@ -2254,45 +2231,19 @@
static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
static const struct of_device_id rk_gmac_dwmac_match[] = {
-#ifdef CONFIG_CPU_PX30
{ .compatible = "rockchip,px30-gmac", .data = &px30_ops },
-#endif
-#ifdef CONFIG_CPU_RK1808
{ .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
-#endif
-#ifdef CONFIG_CPU_RK312X
{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
-#endif
-#ifdef CONFIG_CPU_RK322X
{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
-#endif
-#ifdef CONFIG_CPU_RK3288
{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
-#endif
-#ifdef CONFIG_CPU_RK3308
{ .compatible = "rockchip,rk3308-mac", .data = &rk3308_ops },
-#endif
-#ifdef CONFIG_CPU_RK3328
{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
-#endif
-#ifdef CONFIG_CPU_RK3366
{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
-#endif
-#ifdef CONFIG_CPU_RK3368
{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
-#endif
-#ifdef CONFIG_CPU_RK3399
{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
-#endif
-#ifdef CONFIG_CPU_RK3568
{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
-#endif
-#ifdef CONFIG_CPU_RV110X
{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
-#endif
-#ifdef CONFIG_CPU_RV1126
{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
-#endif
{ }
};
MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
@@ -2306,7 +2257,8 @@
.of_match_table = rk_gmac_dwmac_match,
},
};
-module_platform_driver(rk_gmac_dwmac_driver);
+//module_platform_driver(rk_gmac_dwmac_driver);
+ module_platform_driver1(rk_gmac_dwmac_driver);
MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");
--
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