From b22da3d8526a935aa31e086e63f60ff3246cb61c Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 09 Dec 2023 07:24:11 +0000
Subject: [PATCH] add stmac read mac form eeprom
---
kernel/drivers/char/tlclk.c | 87 ++++++++++++++++++++++---------------------
1 files changed, 44 insertions(+), 43 deletions(-)
diff --git a/kernel/drivers/char/tlclk.c b/kernel/drivers/char/tlclk.c
index dce22b7..896a355 100644
--- a/kernel/drivers/char/tlclk.c
+++ b/kernel/drivers/char/tlclk.c
@@ -506,28 +506,28 @@
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
- if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
- SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
- SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
- } else if (val >= CLK_8_592MHz) {
- SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
- switch (val) {
- case CLK_8_592MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
- break;
- case CLK_11_184MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
- break;
- case CLK_34_368MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
- break;
- case CLK_44_736MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
- break;
- }
- } else
- SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
-
+ if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
+ SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
+ SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
+ } else if (val >= CLK_8_592MHz) {
+ SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
+ switch (val) {
+ case CLK_8_592MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
+ break;
+ case CLK_11_184MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
+ break;
+ case CLK_34_368MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
+ break;
+ case CLK_44_736MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
+ break;
+ }
+ } else {
+ SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
+ }
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
@@ -548,27 +548,28 @@
val = (unsigned char)tmp;
spin_lock_irqsave(&event_lock, flags);
- if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
- SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
- SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
- } else if (val >= CLK_8_592MHz) {
- SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
- switch (val) {
- case CLK_8_592MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
- break;
- case CLK_11_184MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
- break;
- case CLK_34_368MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
- break;
- case CLK_44_736MHz:
- SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
- break;
- }
- } else
- SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
+ if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
+ SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
+ SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
+ } else if (val >= CLK_8_592MHz) {
+ SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
+ switch (val) {
+ case CLK_8_592MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
+ break;
+ case CLK_11_184MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
+ break;
+ case CLK_34_368MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
+ break;
+ case CLK_44_736MHz:
+ SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
+ break;
+ }
+ } else {
+ SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
+ }
spin_unlock_irqrestore(&event_lock, flags);
return strnlen(buf, count);
--
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