From a5969cabbb4660eab42b6ef0412cbbd1200cf14d Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 12 Oct 2024 07:10:09 +0000
Subject: [PATCH] 修改led为gpio
---
kernel/arch/x86/include/asm/invpcid.h | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
diff --git a/kernel/arch/x86/include/asm/invpcid.h b/kernel/arch/x86/include/asm/invpcid.h
index 989cfa8..734482a 100644
--- a/kernel/arch/x86/include/asm/invpcid.h
+++ b/kernel/arch/x86/include/asm/invpcid.h
@@ -12,12 +12,9 @@
* stale TLB entries and, especially if we're flushing global
* mappings, we don't want the compiler to reorder any subsequent
* memory accesses before the TLB flush.
- *
- * The hex opcode is invpcid (%ecx), %eax in 32-bit mode and
- * invpcid (%rcx), %rax in long mode.
*/
- asm volatile (".byte 0x66, 0x0f, 0x38, 0x82, 0x01"
- : : "m" (desc), "a" (type), "c" (&desc) : "memory");
+ asm volatile("invpcid %[desc], %[type]"
+ :: [desc] "m" (desc), [type] "r" (type) : "memory");
}
#define INVPCID_TYPE_INDIV_ADDR 0
--
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