From a36159eec6ca17402b0e146b86efaf76568dc353 Mon Sep 17 00:00:00 2001 From: hc <hc@nodka.com> Date: Fri, 20 Sep 2024 01:41:23 +0000 Subject: [PATCH] 重命名 AX88772C_eeprom/asix.c 为 asix_mac.c --- kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c b/kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c index 3d91baf..9d36228 100644 --- a/kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c +++ b/kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.c @@ -2009,6 +2009,11 @@ goto cleanup_clk; } + /* Reset core now that clocks are enabled, prior to accessing MDIO */ + ret = __axienet_device_reset(lp); + if (ret) + goto cleanup_clk; + /* Autodetect the need for 64-bit DMA pointers. * When the IP is configured for a bus width bigger than 32 bits, * writing the MSB registers is mandatory, even if they are all 0. @@ -2054,11 +2059,6 @@ lp->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD; lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD; - - /* Reset core now that clocks are enabled, prior to accessing MDIO */ - ret = __axienet_device_reset(lp); - if (ret) - goto cleanup_clk; ret = axienet_mdio_setup(lp); if (ret) -- Gitblit v1.6.2