From 9df731a176aab8e03b984b681b1bea01ccff6644 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 07:23:06 +0000
Subject: [PATCH] rk3568 rt uboot init
---
u-boot/drivers/ram/rockchip/sdram_rv1126.c | 38 ++++++++++++++++++++++++++++++--------
1 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/u-boot/drivers/ram/rockchip/sdram_rv1126.c b/u-boot/drivers/ram/rockchip/sdram_rv1126.c
index bb2ce37..65f08a2 100644
--- a/u-boot/drivers/ram/rockchip/sdram_rv1126.c
+++ b/u-boot/drivers/ram/rockchip/sdram_rv1126.c
@@ -374,6 +374,8 @@
break;
delay--;
}
+ if (delay <= 0)
+ printascii("ERROR: DPLL lock timeout!\n");
writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
}
@@ -557,11 +559,18 @@
{
void __iomem *phy_base = dram->phy;
u32 fbdiv, prediv, postdiv, postdiv_en;
+ int delay = 1000;
if (wait) {
clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB);
- while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK))
- continue;
+ while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: phy pll lock timeout!\n");
+ while (1)
+ ;
+ }
+ }
} else {
freq /= MHz;
prediv = 1;
@@ -2484,13 +2493,13 @@
return 0;
}
-static int sdram_init_(struct dram_info *dram,
- struct rv1126_sdram_params *sdram_params, u32 post_init)
+int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init)
{
void __iomem *pctl_base = dram->pctl;
void __iomem *phy_base = dram->phy;
u32 ddr4_vref;
u32 mr_tmp, tmp;
+ int delay = 1000;
rkclk_configure_ddr(dram, sdram_params);
@@ -2538,8 +2547,14 @@
rkclk_ddr_reset(dram, 0, 0, 0, 0);
- while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
- continue;
+ while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: Cannot wait dfi_init_done!\n");
+ while (1)
+ ;
+ }
+ }
if (sdram_params->base.dramtype == LPDDR3) {
pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3);
@@ -3300,6 +3315,7 @@
struct rv1126_sdram_params *sdram_params_new;
void __iomem *pctl_base = dram->pctl;
void __iomem *phy_base = dram->phy;
+ int delay = 1000;
lp_stat = low_power_update(dram, 0);
sdram_params_new = get_default_sdram_config(freq);
@@ -3388,8 +3404,14 @@
(0x0 << ACLK_DDR_UPCTL_EN_SHIFT),
BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12);
while ((readl(pctl_base + DDR_PCTL2_DFISTAT) &
- PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE)
- continue;
+ PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: Cannot wait DFI_INIT_COMPLETE\n");
+ while (1)
+ ;
+ }
+ }
sw_set_req(dram);
setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);
--
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