From 9df731a176aab8e03b984b681b1bea01ccff6644 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 07:23:06 +0000
Subject: [PATCH] rk3568 rt uboot init
---
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c | 313
u-boot/arch/arm/dts/rk3588.dtsi | 4
u-boot/cmd/ddr_tool/memtester/types.h | 0
u-boot/arch/arm/dts/rk3308-u-boot.dtsi | 12
u-boot/arch/arm/mach-rockchip/rk3562/Makefile | 11
u-boot/lib/sha1.c | 33
u-boot/drivers/phy/phy-rockchip-inno-usb2.c | 364
u-boot/configs/rk3568-spl-spi-nand_defconfig | 11
u-boot/drivers/ufs/Makefile | 8
u-boot/drivers/scsi/scsi.c | 4
u-boot/arch/arm/include/asm/arch-rockchip/uimage.h | 3
u-boot/drivers/video/drm/rockchip_vop2.c | 2254 +
u-boot/drivers/video/drm/dw-dp.c | 54
u-boot/configs/rk3568-rt.config | 2
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h | 416
u-boot/board/rockchip/evb_rk3528/Kconfig | 15
u-boot/arch/arm/cpu/armv7/start.S | 2
u-boot/drivers/video/drm/Makefile | 15
u-boot/common/fb_mmc.c | 18
u-boot/drivers/net/phy/rk630phy.c | 3
u-boot/drivers/ram/rockchip/sdram_rk3562.c | 31
u-boot/drivers/phy/phy-rockchip-naneng-combphy.c | 231
u-boot/scripts/setlocalversion | 7
u-boot/drivers/nvme/nvme.c | 27
u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c | 41
u-boot/drivers/core/read.c | 11
u-boot/arch/arm/cpu/armv8/sha256_ce_core.S | 134
u-boot/drivers/video/drm/Kconfig | 28
u-boot/configs/rv1106-usb.config | 17
u-boot/drivers/pinctrl/Makefile | 1
u-boot/drivers/video/drm/rockchip_rgb.c | 362
u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c | 89
u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c | 661
u-boot/common/image-fdt.c | 80
u-boot/arch/arm/dts/px30-u-boot.dtsi | 7
u-boot/arch/arm/lib/bootm-fdt.c | 3
u-boot/drivers/power/charge_animation.c | 6
u-boot/drivers/usb/dwc3/io.h | 5
u-boot/cmd/pci.c | 285
u-boot/arch/arm/dts/rk3528-u-boot.dtsi | 206
u-boot/arch/arm/mach-rockchip/rockchip_smccc.c | 17
u-boot/disk/part_efi.c | 5
u-boot/drivers/core/root.c | 13
u-boot/drivers/power/pmic/rk8xx.c | 73
u-boot/disk/part_env.c | 9
u-boot/configs/rv1126-bat-spi-nor-tb.config | 2
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c | 4
u-boot/drivers/core/device.c | 2
u-boot/drivers/video/drm/rockchip_tve.h | 253
u-boot/include/dm/fdtaddr.h | 12
u-boot/cmd/script_update.c | 38
u-boot/arch/arm/include/asm/system.h | 1
u-boot/drivers/video/drm/rockchip_tve.c | 848
u-boot/include/linux/mtd/mtd.h | 24
u-boot/configs/rk3036_defconfig | 2
u-boot/drivers/ram/rockchip/sdram_rv1126.c | 38
u-boot/drivers/power/regulator/fixed.c | 10
u-boot/disk/part.c | 25
u-boot/arch/arm/include/asm/arch-rockchip/vendor.h | 3
u-boot/scripts/android2fit.sh | 4
u-boot/drivers/mtd/mtd_blk.c | 16
u-boot/drivers/clk/clk-uclass.c | 3
u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S | 4
u-boot/drivers/mtd/nand/spi/skyhigh.c | 51
u-boot/drivers/ufs/Kconfig | 24
u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c | 426
u-boot/include/configs/woodburn_common.h | 4
u-boot/drivers/video/drm/rohm-bu18tl82.c | 17
u-boot/include/configs/rk3528_common.h | 109
u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c | 3
u-boot/arch/arm/mach-rockchip/fit.c | 68
u-boot/drivers/i2c/muxes/max96745.c | 44
u-boot/drivers/clk/rockchip/clk_rk3562.c | 2046 +
u-boot/arch/arm/cpu/armv8/Kconfig | 15
u-boot/fs/ubifs/super.c | 21
u-boot/drivers/mtd/nand/spi/xincun.c | 108
u-boot/drivers/mmc/sdhci.c | 53
u-boot/drivers/clk/rockchip/Makefile | 2
u-boot/include/configs/rk3588_common.h | 8
u-boot/common/Makefile | 10
u-boot/configs/rv1106-optee.config | 5
u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c | 26
u-boot/drivers/misc/rk3562-secure-otp.S | 15906 ++++++++++
u-boot/drivers/ram/rockchip/Makefile | 2
u-boot/drivers/gpio/Makefile | 1
u-boot/include/configs/evb_rk3528.h | 26
u-boot/include/key.h | 7
u-boot/include/spl_ab.h | 10
u-boot/drivers/input/rk_key.c | 8
u-boot/board/rockchip/evb_rk3528/Makefile | 7
u-boot/drivers/ufs/ufs-uclass.c | 18
u-boot/drivers/video/drm/rockchip_display.h | 50
u-boot/drivers/mtd/nand/spi/fmsh.c | 40
u-boot/drivers/video/drm/rockchip_display.c | 661
u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile | 7
u-boot/configs/rk3399_defconfig | 3
u-boot/drivers/phy/phy-rockchip-usbdp.c | 26
u-boot/drivers/input/key-uclass.c | 83
u-boot/drivers/video/drm/rockchip_spl_display.c | 265
u-boot/drivers/usb/dwc3/gadget.c | 2
u-boot/arch/arm/dts/rk3528-evb.dts | 31
u-boot/cmd/ddr_tool/memtester/Makefile | 8
u-boot/include/dt-bindings/power/rk3562-power.h | 33
u-boot/drivers/video/drm/rockchip_display_helper.c | 279
u-boot/drivers/input/spl_adc_key.c | 141
u-boot/lib/avb/libavb_user/avb_ops_user.c | 147
u-boot/drivers/misc/Makefile | 8
u-boot/include/configs/rk3562_common.h | 84
u-boot/common/mp_boot_rk3528.S | 9682 ++++++
u-boot/examples/standalone/rkspi.h | 138
u-boot/drivers/cpu/rockchip_amp.c | 52
u-boot/common/spl/Kconfig | 24
u-boot/configs/rv1106-spi-nor_defconfig | 10
u-boot/board/rockchip/evb_rk3562/Kconfig | 15
u-boot/common/image-android.c | 306
u-boot/include/dt-bindings/display/rockchip-tve.h | 15
u-boot/include/u-boot/sha1.h | 2
u-boot/include/mp_boot.h | 25
u-boot/drivers/mtd/nand/spi/core.c | 14
u-boot/drivers/rkflash/sfc_nand.c | 30
u-boot/tools/Makefile | 6
u-boot/configs/rk3562_defconfig | 211
u-boot/arch/arm/cpu/armv8/Makefile | 2
u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h | 396
u-boot/drivers/video/drm/panel-rohm-bu18rl82.c | 349
u-boot/common/spl/spl.c | 14
u-boot/cmd/ddr_tool/Makefile | 25
u-boot/drivers/video/drm/rockchip_post_csc.c | 1587 +
u-boot/lib/rsa/rsa-verify.c | 16
u-boot/configs/px30-tb_defconfig | 2
u-boot/arch/arm/dts/rk3528-pinctrl.dtsi | 1241
u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c | 17
u-boot/drivers/video/drm/rockchip_post_csc.h | 35
u-boot/drivers/net/gmac_rockchip.c | 494
u-boot/arch/arm/dts/rk3568-u-boot.dtsi | 33
u-boot/arch/arm/mach-rockchip/vendor.c | 32
u-boot/arch/arm/dts/rk3588-u-boot.dtsi | 3
u-boot/drivers/i2c/muxes/Makefile | 1
u-boot/arch/arm/dts/rk3588s.dtsi | 21
u-boot/include/android_ab.h | 2
u-boot/arch/arm/mach-rockchip/chip_info.c | 4
u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi | 28
u-boot/arch/arm/dts/rv1106-u-boot.dtsi | 42
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h | 89
u-boot/drivers/mtd/spi/sf_internal.h | 1
u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h | 81
u-boot/drivers/video/drm/rockchip_panel.c | 120
u-boot/cmd/Makefile | 4
u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c | 24
u-boot/drivers/video/drm/rockchip_vop_reg.c | 22
u-boot/drivers/spi/soft_spi.c | 34
u-boot/include/android_avb/avb_ops_user.h | 16
u-boot/drivers/mtd/nand/spi/Makefile | 2
u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c | 69
u-boot/cmd/ddr_tool/memtester/memtester.h | 6
u-boot/drivers/video/drm/rockchip_connector.h | 124
u-boot/cmd/mmc.c | 4
u-boot/lib/optee_clientApi/OpteeClientInterface.c | 16
u-boot/cmd/ddr_tool/stressapptest/Makefile | 7
u-boot/drivers/video/Makefile | 6
u-boot/lib/avb/libavb_user/Kconfig | 1
u-boot/drivers/video/drm/rockchip_connector.c | 45
u-boot/arch/arm/mach-rockchip/fit_nodes.sh | 73
u-boot/drivers/video/drm/dw_hdmi.h | 4
u-boot/cmd/ddr_tool/memtester/memtester.c | 4
u-boot/drivers/mtd/nand/spi/hyf.c | 22
u-boot/configs/rk322x_defconfig | 2
u-boot/drivers/clk/rockchip/clk_rk3528.c | 2145 +
u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c | 13
u-boot/configs/rk3588_defconfig | 9
u-boot/drivers/video/drm/rockchip_crtc.h | 6
u-boot/configs/px30_defconfig | 1
u-boot/configs/rk3328_defconfig | 2
u-boot/drivers/video/drm/dw_hdmi.c | 186
u-boot/common/android_bootloader.c | 415
u-boot/drivers/phy/Makefile | 2
u-boot/cmd/ddr_tool/Kconfig | 32
u-boot/arch/arm/mach-rockchip/rk_meta.c | 25
u-boot/drivers/video/drm/rockchip_crtc.c | 40
u-boot/tools/rkcommon.c | 2
u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S | 4
u-boot/arch/arm/dts/Makefile | 2
u-boot/arch/arm/mach-rockchip/rk3528/Kconfig | 17
u-boot/drivers/ufs/unipro.h | 270
u-boot/include/spl_display.h | 28
u-boot/common/spl/spl_fit.c | 20
u-boot/include/configs/rk3288_common.h | 2
u-boot/drivers/gpio/gpio-uclass.c | 2
u-boot/arch/arm/dts/rk3308.dtsi | 7
u-boot/common/android_ab.c | 56
u-boot/include/configs/evb_rk3562.h | 26
u-boot/env/envf.c | 51
u-boot/drivers/ufs/ti-j721e-ufs.c | 74
u-boot/cmd/ddr_tool/stressapptest/stressapptest.c | 1207
u-boot/include/edid.h | 41
u-boot/common/board_f.c | 4
u-boot/lib/avb/libavb/avb_slot_verify.c | 15
u-boot/arch/arm/mach-rockchip/boot_mode.c | 4
u-boot/arch/arm/mach-rockchip/hotkey.c | 4
u-boot/arch/arm/mach-rockchip/Kconfig | 95
u-boot/cmd/ddr_tool/stressapptest/stressapptest.h | 70
u-boot/arch/arm/cpu/armv8/start.S | 74
u-boot/make.sh | 8
u-boot/examples/standalone/Makefile | 1
u-boot/arch/arm/include/asm/arch-rockchip/fit.h | 2
u-boot/examples/standalone/rkspi.c | 454
u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c | 81
u-boot/include/dt-bindings/clock/rk3528-cru.h | 754
u-boot/configs/rk3588-qnx_defconfig | 212
u-boot/include/dt-bindings/suspend/rockchip-rk3528.h | 54
u-boot/drivers/mmc/dw_mmc.c | 78
u-boot/drivers/video/drm/dw_mipi_dsi.c | 19
u-boot/drivers/video/drm/dw_mipi_dsi2.c | 248
u-boot/include/linux/dw_hdmi.h | 3
u-boot/cmd/Kconfig | 17
u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c | 38
u-boot/configs/rv1126-spi-nor-tiny_defconfig | 1
u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S | 4
u-boot/configs/rv1106-display.config | 2
u-boot/include/image.h | 14
u-boot/cmd/bootfit.c | 1
u-boot/common/Kconfig | 12
u-boot/drivers/mmc/rockchip_dw_mmc.c | 2
u-boot/include/android_image.h | 6
u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c | 41
u-boot/examples/standalone/README_rkspi.md | 126
u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h | 2
u-boot/drivers/mtd/ubi/debug.h | 9
u-boot/arch/arm/dts/rk3562.dtsi | 2325 +
u-boot/fs/ubifs/debug.h | 24
u-boot/arch/arm/mach-rockchip/uimage.c | 67
u-boot/include/scsi.h | 4
u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c | 494
u-boot/drivers/watchdog/rockchip_wdt.c | 11
u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h | 76
u-boot/drivers/misc/rk3528-secure-otp.S | 15901 ++++++++++
u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h | 11
u-boot/include/configs/rv1106_common.h | 1
u-boot/common/image-fit.c | 1
u-boot/drivers/Kconfig | 2
u-boot/drivers/core/fdtaddr.c | 10
u-boot/drivers/rkflash/sfc_nor.c | 23
u-boot/configs/rk3326_defconfig | 4
u-boot/drivers/ufs/cdns-platform.c | 125
u-boot/configs/rk3126_defconfig | 1
u-boot/drivers/pinctrl/Kconfig | 8
u-boot/include/asm-generic/u-boot.h | 2
u-boot/scripts/fit-core.sh | 39
u-boot/arch/arm/mach-rockchip/board.c | 202
u-boot/board/rockchip/evb_rk3528/evb_rk3528.c | 33
u-boot/cmd/cache.c | 28
u-boot/drivers/video/drm/analogix_dp.c | 52
u-boot/configs/rv1126-ipc.config | 2
u-boot/arch/arm/mach-rockchip/pstore.c | 2
u-boot/include/configs/rv1126_common.h | 2
u-boot/drivers/mtd/nand/spi/gigadevice.c | 202
u-boot/lib/rsa/rsa-sign.c | 21
u-boot/drivers/video/drm/rockchip_vop.c | 31
u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c | 12
u-boot/include/drm_modes.h | 94
u-boot/drivers/power/regulator/regulator-uclass.c | 92
u-boot/drivers/video/drm/rockchip_vop.h | 5
u-boot/cmd/ddr_tool/io_map.c | 0
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h | 211
u-boot/cmd/ddr_tool/io_map.h | 6
u-boot/cmd/ddr_tool/memtester/tests.h | 5
u-boot/drivers/mtd/spi/spi-nor-ids.c | 186
u-boot/drivers/mtd/nand/spi/unim.c | 9
u-boot/drivers/crypto/rockchip/crypto_v2.c | 226
u-boot/drivers/input/adc_key.c | 62
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h | 12
u-boot/fs/ubifs/io.c | 8
u-boot/cmd/ddr_tool/memtester/tests.c | 2
u-boot/cmd/ddr_tool/memtester/sizes.h | 6
u-boot/drivers/clk/rockchip/clk_pll.c | 23
u-boot/lib/sha256.c | 31
u-boot/include/irq-platform.h | 40
u-boot/drivers/video/drm/rohm-bu18rl82.c | 1
u-boot/drivers/mtd/nand/spi/dosilicon.c | 22
u-boot/board/rockchip/evb_rk3562/Makefile | 7
u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c | 25
u-boot/common/spl/spl_boot_image.c | 305
u-boot/arch/arm/dts/rk3562-pinctrl.dtsi | 1872 +
u-boot/arch/arm/mach-rockchip/Makefile | 5
u-boot/drivers/adc/rockchip-saradc-v2.c | 33
u-boot/drivers/gpio/Kconfig | 15
u-boot/drivers/mmc/rockchip_sdhci.c | 212
u-boot/drivers/cpu/amp.its | 24
u-boot/common/spl/spl_ab.c | 35
u-boot/drivers/mmc/mmc-uclass.c | 14
u-boot/arch/arm/dts/px30.dtsi | 7
u-boot/arch/arm/dts/rk3128.dtsi | 14
u-boot/drivers/clk/rockchip/clk_rk3399.c | 4
u-boot/common/board_r.c | 18
u-boot/include/dt-bindings/power/rk3528-power.h | 18
u-boot/drivers/mtd/nand/spi/foresee.c | 20
u-boot/arch/arm/dts/rk3562-evb.dts | 31
u-boot/scripts/check-rkconfig.sh | 23
u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c | 21
u-boot/arch/arm/lib/crt0_64.S | 36
u-boot/drivers/video/drm/rockchip_lvds.c | 26
u-boot/common/spl/Makefile | 3
u-boot/drivers/video/drm/panel-maxim-max96752f.c | 303
u-boot/arch/arm/dts/rk3036-sdk.dts | 14
u-boot/drivers/ufs/ufs.c | 1970 +
u-boot/configs/rv1106-spi-nor-tb_defconfig | 11
u-boot/include/charset.h | 3
u-boot/drivers/spi/rockchip_sfc.c | 2
u-boot/drivers/ufs/ufs.h | 917
u-boot/include/mmc.h | 10
u-boot/drivers/Makefile | 3
u-boot/drivers/video/drm/max96755f.c | 47
u-boot/arch/arm/dts/rv1106.dtsi | 2
u-boot/configs/rv1106-emmc-tb_defconfig | 11
u-boot/include/boot_rkimg.h | 1
u-boot/arch/arm/mach-rockchip/boot_rkimg.c | 27
u-boot/configs/rk3588-ab.config | 3
u-boot/include/linux/mtd/spinand.h | 2
u-boot/drivers/clk/rockchip/clk_rk3568.c | 14
u-boot/arch/arm/dts/rv1106-evb2.dts | 22
u-boot/drivers/ram/rockchip/sdram_rk3528.c | 21
u-boot/drivers/ufs/ufshci-dwc.h | 33
u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h | 23
u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c | 23
u-boot/include/dm/read.h | 17
u-boot/include/sdhci.h | 13
u-boot/drivers/pci/pcie_dw_rockchip.c | 63
u-boot/include/max96755f.h | 1
u-boot/cmd/ddr_tool/ddr_test/Makefile | 20
u-boot/arch/arm/mach-rockchip/fit_args.sh | 4
u-boot/arch/arm/mach-rockchip/spl.c | 12
u-boot/arch/arm/cpu/armv8/sha1_ce_core.S | 132
u-boot/configs/rk3528-aarch32.config | 24
u-boot/arch/arm/dts/rk3568.dtsi | 8
u-boot/arch/arm/include/asm/arch-rockchip/clock.h | 8
u-boot/include/max96745.h | 15
u-boot/drivers/misc/rockchip-otp.c | 10
u-boot/include/dm/uclass-id.h | 1
u-boot/fs/ubifs/ubifs.h | 8
u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c | 21
u-boot/arch/arm/lib/bootm.c | 9
u-boot/configs/rk-amp.config | 3
u-boot/drivers/i2c/muxes/Kconfig | 7
u-boot/include/asm-generic/atomic-long.h | 2
u-boot/arch/arm/dts/rv1126-u-boot.dtsi | 9
u-boot/configs/rk3308-amp.config | 3
u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h | 196
u-boot/configs/rv1106_defconfig | 3
u-boot/arch/arm/mach-rockchip/kernel_dtb.c | 517
u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c | 324
u-boot/include/rk_timer_irq.h | 6
u-boot/arch/arm/dts/rk3562-u-boot.dtsi | 203
u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c | 689
u-boot/common/spl_mp_boot_rk3528.S | 9214 +++++
u-boot/fs/ubifs/ubifs.c | 18
u-boot/drivers/mtd/nand/spi/gsto.c | 92
u-boot/cmd/mtd.c | 24
u-boot/configs/rk312x-rkflash.config | 6
u-boot/drivers/mmc/mmc.c | 77
u-boot/arch/arm/mach-rockchip/rk3528/Makefile | 11
u-boot/usb_update.txt | 4
u-boot/drivers/video/drm/max96745.c | 105
u-boot/drivers/video/drm/rockchip_dw_hdmi.c | 127
u-boot/cmd/ddr_tool/ddr_tool_mp.S | 171
u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h | 15
u-boot/cmd/boot_android.c | 4
u-boot/include/configs/rockchip-common.h | 2
u-boot/arch/arm/dts/rk3036.dtsi | 29
u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h | 12
u-boot/arch/arm/dts/rk3128-u-boot.dtsi | 5
u-boot/lib/avb/libavb/avb_sha512.c | 59
u-boot/drivers/video/drm/dw_hdmi_qp.c | 66
u-boot/configs/rk3528_defconfig | 201
u-boot/arch/arm/Kconfig | 4
u-boot/drivers/mtd/nand/spi/Kconfig | 12
u-boot/configs/rk3128x_defconfig | 2
u-boot/arch/arm/mach-rockchip/fit_misc.c | 34
u-boot/configs/rk3128_defconfig | 5
u-boot/common/board_info.c | 1
u-boot/drivers/thermal/rockchip_thermal.c | 283
u-boot/arch/arm/mach-rockchip/resource_img.c | 705
u-boot/board/rockchip/evb_rk3562/evb_rk3562.c | 33
u-boot/configs/rk3568_defconfig | 2
u-boot/drivers/pinctrl/rockchip/Makefile | 2
u-boot/disk/Kconfig | 8
u-boot/include/dt-bindings/soc/rockchip,boot-mode.h | 2
u-boot/common/image-sparse.c | 17
u-boot/arch/arm/mach-rockchip/resource_hwid.c | 9
u-boot/common/bootm.c | 2
u-boot/include/power/rk8xx_pmic.h | 2
u-boot/arch/arm/mach-rockchip/rk3562/Kconfig | 17
u-boot/cmd/ddr_tool/ddr_tool_common.c | 9
u-boot/drivers/ufs/ufshcd-dwc.h | 23
u-boot/fs/ubifs/tnc.c | 25
u-boot/scripts/README.rockchip | 2
u-boot/cmd/ddr_tool/ddr_tool_common.h | 6
u-boot/drivers/clk/rockchip/clk_rk3588.c | 34
u-boot/drivers/rng/rockchip_rng.c | 143
u-boot/arch/arm/dts/rk3528.dtsi | 2184 +
u-boot/include/dt-bindings/clock/rk3562-cru.h | 733
u-boot/drivers/video/Kconfig | 21
u-boot/include/rockchip/crypto_v2.h | 2
u-boot/cmd/ddr_tool/ddr_dq_eye/ddr_dq_eye.c | 0
u-boot/cmd/ufs.c | 37
u-boot/drivers/ufs/ufshcd-dwc.c | 149
u-boot/drivers/mtd/nand/spi/jsc.c | 9
u-boot/drivers/gpio/rk_gpio.c | 11
/dev/null | 66
u-boot/Kconfig | 15
u-boot/drivers/video/drm/drm_modes.c | 52
410 files changed, 91,241 insertions(+), 3,840 deletions(-)
diff --git a/u-boot/Kconfig b/u-boot/Kconfig
index b92331e..5489509 100644
--- a/u-boot/Kconfig
+++ b/u-boot/Kconfig
@@ -203,6 +203,18 @@
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
+config FIT_ENABLE_RSA4096_SUPPORT
+ bool "Support RSA4096 verification of FIT image contents"
+ select RSA_SOFTWARE_EXP if !DM_CRYPTO
+ default n
+ help
+ Enable this to support RSA4096 checksum of FIT image contents. A
+ RSA4096 is a 4096-bit (512-byte) key used to check that
+ check if the content comes from an encryption party. RSA4096 is one
+ of algorithms recommended for use in secure applications since (as at 2016)
+ there is no known feasible attack that could produce a 'collision' with differing
+ input data. Use this for the higher security than RSA2048 in default.
+
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
@@ -278,6 +290,9 @@
Say y here if you want to enable fit image structure and data
print.
+config FIT_OMIT_UBOOT
+ bool "Omit u-boot-nodtb.bin and u-boot.dtb when output uboot.itb"
+
if SPL
config SPL_FIT
diff --git a/u-boot/arch/arm/Kconfig b/u-boot/arch/arm/Kconfig
index 5152615..374817b 100644
--- a/u-boot/arch/arm/Kconfig
+++ b/u-boot/arch/arm/Kconfig
@@ -343,6 +343,10 @@
help
This ARM64 system supports AArch32 execution state.
+config ARM_SMP
+ bool "Enable ARM Symmetric Multiprocessing"
+ default n
+
choice
prompt "Target select"
default TARGET_HIKEY
diff --git a/u-boot/arch/arm/cpu/armv7/start.S b/u-boot/arch/arm/cpu/armv7/start.S
index ed631e9..218625e 100644
--- a/u-boot/arch/arm/cpu/armv7/start.S
+++ b/u-boot/arch/arm/cpu/armv7/start.S
@@ -164,7 +164,9 @@
mrc p15, 0, r0, c1, c0, 0
bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
+#if 0 /* There is unalign access when decompress firmware. */
orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
+#endif
orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
#ifdef CONFIG_SYS_ICACHE_OFF
bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
diff --git a/u-boot/arch/arm/cpu/armv8/Kconfig b/u-boot/arch/arm/cpu/armv8/Kconfig
index 8e4c3dd..38efe90 100644
--- a/u-boot/arch/arm/cpu/armv8/Kconfig
+++ b/u-boot/arch/arm/cpu/armv8/Kconfig
@@ -143,4 +143,19 @@
endif
+menuconfig ARMV8_CRYPTO
+ bool "ARM64 Accelerated Cryptographic Algorithms"
+
+if ARMV8_CRYPTO
+
+config ARMV8_CE_SHA1
+ bool "SHA-1 digest algorithm (ARMv8 Crypto Extensions)"
+ default y if SHA1
+
+config ARMV8_CE_SHA256
+ bool "SHA-256 digest algorithm (ARMv8 Crypto Extensions)"
+ default y if SHA256
+
+endif
+
endif
diff --git a/u-boot/arch/arm/cpu/armv8/Makefile b/u-boot/arch/arm/cpu/armv8/Makefile
index c200dc2..0140f22 100644
--- a/u-boot/arch/arm/cpu/armv8/Makefile
+++ b/u-boot/arch/arm/cpu/armv8/Makefile
@@ -36,3 +36,5 @@
obj-$(CONFIG_TARGET_HIKEY) += hisilicon/
obj-$(CONFIG_ARMV8_PSCI) += psci.o
obj-$(CONFIG_ARCH_SUNXI) += lowlevel_init.o
+obj-$(CONFIG_ARMV8_CE_SHA1) += sha1_ce_glue.o sha1_ce_core.o
+obj-$(CONFIG_ARMV8_CE_SHA256) += sha256_ce_glue.o sha256_ce_core.o
diff --git a/u-boot/arch/arm/cpu/armv8/sha1_ce_core.S b/u-boot/arch/arm/cpu/armv8/sha1_ce_core.S
new file mode 100644
index 0000000..fbf2714
--- /dev/null
+++ b/u-boot/arch/arm/cpu/armv8/sha1_ce_core.S
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * sha1_ce_core.S - SHA-1 secure hash using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
+ */
+
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/macro.h>
+
+ .text
+ .arch armv8-a+crypto
+
+ k0 .req v0
+ k1 .req v1
+ k2 .req v2
+ k3 .req v3
+
+ t0 .req v4
+ t1 .req v5
+
+ dga .req q6
+ dgav .req v6
+ dgb .req s7
+ dgbv .req v7
+
+ dg0q .req q12
+ dg0s .req s12
+ dg0v .req v12
+ dg1s .req s13
+ dg1v .req v13
+ dg2s .req s14
+
+ .macro add_only, op, ev, rc, s0, dg1
+ .ifc \ev, ev
+ add t1.4s, v\s0\().4s, \rc\().4s
+ sha1h dg2s, dg0s
+ .ifnb \dg1
+ sha1\op dg0q, \dg1, t0.4s
+ .else
+ sha1\op dg0q, dg1s, t0.4s
+ .endif
+ .else
+ .ifnb \s0
+ add t0.4s, v\s0\().4s, \rc\().4s
+ .endif
+ sha1h dg1s, dg0s
+ sha1\op dg0q, dg2s, t1.4s
+ .endif
+ .endm
+
+ .macro add_update, op, ev, rc, s0, s1, s2, s3, dg1
+ sha1su0 v\s0\().4s, v\s1\().4s, v\s2\().4s
+ add_only \op, \ev, \rc, \s1, \dg1
+ sha1su1 v\s0\().4s, v\s3\().4s
+ .endm
+
+ .macro loadrc, k, val, tmp
+ movz \tmp, :abs_g0_nc:\val
+ movk \tmp, :abs_g1:\val
+ dup \k, \tmp
+ .endm
+
+ /*
+ * void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
+ * uint32_t blocks)
+ */
+ENTRY(sha1_armv8_ce_process)
+ /* load round constants */
+ loadrc k0.4s, 0x5a827999, w6
+ loadrc k1.4s, 0x6ed9eba1, w6
+ loadrc k2.4s, 0x8f1bbcdc, w6
+ loadrc k3.4s, 0xca62c1d6, w6
+
+ /* load state (4+1 digest states) */
+ ld1 {dgav.4s}, [x0]
+ ldr dgb, [x0, #16]
+
+ /* load input (64 bytes into v8->v11 16B vectors) */
+0: ld1 {v8.4s-v11.4s}, [x1], #64
+ sub w2, w2, #1
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+ rev32 v8.16b, v8.16b
+ rev32 v9.16b, v9.16b
+ rev32 v10.16b, v10.16b
+ rev32 v11.16b, v11.16b
+#endif
+
+1: add t0.4s, v8.4s, k0.4s
+ mov dg0v.16b, dgav.16b
+
+ add_update c, ev, k0, 8, 9, 10, 11, dgb
+ add_update c, od, k0, 9, 10, 11, 8
+ add_update c, ev, k0, 10, 11, 8, 9
+ add_update c, od, k0, 11, 8, 9, 10
+ add_update c, ev, k1, 8, 9, 10, 11
+
+ add_update p, od, k1, 9, 10, 11, 8
+ add_update p, ev, k1, 10, 11, 8, 9
+ add_update p, od, k1, 11, 8, 9, 10
+ add_update p, ev, k1, 8, 9, 10, 11
+ add_update p, od, k2, 9, 10, 11, 8
+
+ add_update m, ev, k2, 10, 11, 8, 9
+ add_update m, od, k2, 11, 8, 9, 10
+ add_update m, ev, k2, 8, 9, 10, 11
+ add_update m, od, k2, 9, 10, 11, 8
+ add_update m, ev, k3, 10, 11, 8, 9
+
+ add_update p, od, k3, 11, 8, 9, 10
+ add_only p, ev, k3, 9
+ add_only p, od, k3, 10
+ add_only p, ev, k3, 11
+ add_only p, od
+
+ /* update state */
+ add dgbv.2s, dgbv.2s, dg1v.2s
+ add dgav.4s, dgav.4s, dg0v.4s
+
+ /* loop on next block? */
+ cbz w2, 2f
+ b 0b
+
+ /* store new state */
+2: st1 {dgav.4s}, [x0]
+ str dgb, [x0, #16]
+ mov w0, w2
+ ret
+ENDPROC(sha1_armv8_ce_process)
diff --git a/u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c b/u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c
new file mode 100644
index 0000000..780b119
--- /dev/null
+++ b/u-boot/arch/arm/cpu/armv8/sha1_ce_glue.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * sha1_ce_glue.c - SHA-1 secure hash using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
+ */
+
+#include <common.h>
+#include <u-boot/sha1.h>
+
+extern void sha1_armv8_ce_process(uint32_t state[5], uint8_t const *src,
+ uint32_t blocks);
+
+void sha1_process(sha1_context *ctx, const unsigned char *data,
+ unsigned int blocks)
+{
+ if (!blocks)
+ return;
+
+ sha1_armv8_ce_process(ctx->state, data, blocks);
+}
diff --git a/u-boot/arch/arm/cpu/armv8/sha256_ce_core.S b/u-boot/arch/arm/cpu/armv8/sha256_ce_core.S
new file mode 100644
index 0000000..fbae3ca
--- /dev/null
+++ b/u-boot/arch/arm/cpu/armv8/sha256_ce_core.S
@@ -0,0 +1,134 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * sha256-ce-core.S - core SHA-256 transform using v8 Crypto Extensions
+ *
+ * Copyright (C) 2014 Linaro Ltd <ard.biesheuvel@linaro.org>
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
+ */
+
+ #include <config.h>
+ #include <linux/linkage.h>
+ #include <asm/system.h>
+ #include <asm/macro.h>
+
+ .text
+ .arch armv8-a+crypto
+
+ dga .req q20
+ dgav .req v20
+ dgb .req q21
+ dgbv .req v21
+
+ t0 .req v22
+ t1 .req v23
+
+ dg0q .req q24
+ dg0v .req v24
+ dg1q .req q25
+ dg1v .req v25
+ dg2q .req q26
+ dg2v .req v26
+
+ .macro add_only, ev, rc, s0
+ mov dg2v.16b, dg0v.16b
+ .ifeq \ev
+ add t1.4s, v\s0\().4s, \rc\().4s
+ sha256h dg0q, dg1q, t0.4s
+ sha256h2 dg1q, dg2q, t0.4s
+ .else
+ .ifnb \s0
+ add t0.4s, v\s0\().4s, \rc\().4s
+ .endif
+ sha256h dg0q, dg1q, t1.4s
+ sha256h2 dg1q, dg2q, t1.4s
+ .endif
+ .endm
+
+ .macro add_update, ev, rc, s0, s1, s2, s3
+ sha256su0 v\s0\().4s, v\s1\().4s
+ add_only \ev, \rc, \s1
+ sha256su1 v\s0\().4s, v\s2\().4s, v\s3\().4s
+ .endm
+
+ /*
+ * The SHA-256 round constants
+ */
+ .align 4
+.Lsha2_rcon:
+ .word 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5
+ .word 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5
+ .word 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3
+ .word 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174
+ .word 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc
+ .word 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da
+ .word 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7
+ .word 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967
+ .word 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13
+ .word 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85
+ .word 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3
+ .word 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070
+ .word 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5
+ .word 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3
+ .word 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208
+ .word 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
+
+ /*
+ * void sha256_armv8_ce_process(struct sha256_ce_state *sst,
+ * uint8_t const *src, uint32_t blocks)
+ */
+ENTRY(sha256_armv8_ce_process)
+ /* load round constants */
+ adr x8, .Lsha2_rcon
+ ld1 { v0.4s- v3.4s}, [x8], #64
+ ld1 { v4.4s- v7.4s}, [x8], #64
+ ld1 { v8.4s-v11.4s}, [x8], #64
+ ld1 {v12.4s-v15.4s}, [x8]
+
+ /* load state */
+ ldp dga, dgb, [x0]
+
+ /* load input */
+0: ld1 {v16.4s-v19.4s}, [x1], #64
+ sub w2, w2, #1
+#if __BYTE_ORDER == __LITTLE_ENDIAN
+ rev32 v16.16b, v16.16b
+ rev32 v17.16b, v17.16b
+ rev32 v18.16b, v18.16b
+ rev32 v19.16b, v19.16b
+#endif
+
+1: add t0.4s, v16.4s, v0.4s
+ mov dg0v.16b, dgav.16b
+ mov dg1v.16b, dgbv.16b
+
+ add_update 0, v1, 16, 17, 18, 19
+ add_update 1, v2, 17, 18, 19, 16
+ add_update 0, v3, 18, 19, 16, 17
+ add_update 1, v4, 19, 16, 17, 18
+
+ add_update 0, v5, 16, 17, 18, 19
+ add_update 1, v6, 17, 18, 19, 16
+ add_update 0, v7, 18, 19, 16, 17
+ add_update 1, v8, 19, 16, 17, 18
+
+ add_update 0, v9, 16, 17, 18, 19
+ add_update 1, v10, 17, 18, 19, 16
+ add_update 0, v11, 18, 19, 16, 17
+ add_update 1, v12, 19, 16, 17, 18
+
+ add_only 0, v13, 17
+ add_only 1, v14, 18
+ add_only 0, v15, 19
+ add_only 1
+
+ /* update state */
+ add dgav.4s, dgav.4s, dg0v.4s
+ add dgbv.4s, dgbv.4s, dg1v.4s
+
+ /* handled all input blocks? */
+ cbnz w2, 0b
+
+ /* store new state */
+3: stp dga, dgb, [x0]
+ ret
+ENDPROC(sha256_armv8_ce_process)
diff --git a/u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c b/u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c
new file mode 100644
index 0000000..67dd796
--- /dev/null
+++ b/u-boot/arch/arm/cpu/armv8/sha256_ce_glue.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * sha256_ce_glue.c - SHA-256 secure hash using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2022 Linaro Ltd <loic.poulain@linaro.org>
+ */
+
+#include <common.h>
+#include <u-boot/sha256.h>
+
+extern void sha256_armv8_ce_process(uint32_t state[8], uint8_t const *src,
+ uint32_t blocks);
+
+void sha256_process(sha256_context *ctx, const unsigned char *data,
+ unsigned int blocks)
+{
+ if (!blocks)
+ return;
+
+ sha256_armv8_ce_process(ctx->state, data, blocks);
+}
diff --git a/u-boot/arch/arm/cpu/armv8/start.S b/u-boot/arch/arm/cpu/armv8/start.S
index 8447fc6..f84932d 100644
--- a/u-boot/arch/arm/cpu/armv8/start.S
+++ b/u-boot/arch/arm/cpu/armv8/start.S
@@ -117,6 +117,43 @@
0:
/*
+ * Enable instruction cache (if required), stack pointer,
+ * data access alignment checks and SError.
+ */
+#ifndef CONFIG_SYS_ICACHE_OFF
+ mov x1, #CR_I
+#else
+ mov x1, #0
+#endif
+ switch_el x2, 3f, 2f, 1f
+3: mrs x0, sctlr_el3
+ orr x0, x0, x1
+ msr sctlr_el3, x0
+#ifndef CONFIG_SUPPORT_USBPLUG
+ msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
+#endif
+ b 0f
+2: mrs x0, sctlr_el2
+ orr x0, x0, x1
+ msr sctlr_el2, x0
+
+ mrs x0, hcr_el2
+ orr x0, x0, #HCR_EL2_TGE
+ orr x0, x0, #HCR_EL2_AMO
+#if CONFIG_IS_ENABLED(IRQ)
+ orr x0, x0, #HCR_EL2_IMO
+#endif
+ msr hcr_el2, x0
+ msr daifclr, #4
+ b 0f
+1: mrs x0, sctlr_el1
+ orr x0, x0, x1
+ msr sctlr_el1, x0
+ msr daifclr, #4
+0:
+ isb
+
+ /*
* Enable SMPEN bit for coherency.
* This register is not architectural but at the moment
* this bit should be set for A53/A57/A72.
@@ -160,6 +197,43 @@
cbz x0, slave_cpu
br x0 /* branch to the given address */
#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_ARM_SMP)
+ mrs x0, mpidr_el1
+ and x0, x0, #0xfff
+ cmp x0, #0
+ beq master_cpu
+
+#ifdef SMP_CPU1
+ cmp x0, #(SMP_CPU1)
+ ldr x1, =(SMP_CPU1_STACK)
+ beq slave_cpu
+#endif
+
+#ifdef SMP_CPU2
+ cmp x0, #(SMP_CPU2)
+ ldr x1, =(SMP_CPU2_STACK)
+ beq slave_cpu
+#endif
+
+#ifdef SMP_CPU3
+ cmp x0, #(SMP_CPU3)
+ ldr x1, =(SMP_CPU3_STACK)
+ beq slave_cpu
+#endif
+ dsb sy
+ isb
+
+loop:
+ wfe
+ b loop
+
+slave_cpu:
+ bic sp, x1, #0xf
+ bl smp_entry
+ b loop
+#endif
+
master_cpu:
bl _main
diff --git a/u-boot/arch/arm/dts/Makefile b/u-boot/arch/arm/dts/Makefile
index b834bc3..0fcc630 100644
--- a/u-boot/arch/arm/dts/Makefile
+++ b/u-boot/arch/arm/dts/Makefile
@@ -453,12 +453,14 @@
dtb-$(CONFIG_ARCH_STI) += stih410-b2260.dtb
# Compile embeded kernel dts to dtb, and put it behind of u-boot.dtb
+ifeq ($(findstring arch/arm/dts/,$(EMBED_KERN_DTB_PATH)),arch/arm/dts/)
EMBED_KERN_DTB_PATH := $(CONFIG_EMBED_KERNEL_DTB_PATH:"%"=%)
EMBED_KERN_DTS_PATH := $(subst dtb,dts, $(EMBED_KERN_DTB_PATH))
ifneq ($(wildcard $(EMBED_KERN_DTS_PATH)),)
EMBED_KERN_DTB=$(shell echo $(EMBED_KERN_DTB_PATH) | awk -F '/' '{ print $$NF }')
dtb-y += $(EMBED_KERN_DTB)
endif
+endif
targets += $(dtb-y)
diff --git a/u-boot/arch/arm/dts/px30-u-boot.dtsi b/u-boot/arch/arm/dts/px30-u-boot.dtsi
index ceda2f4..6c9ac21 100644
--- a/u-boot/arch/arm/dts/px30-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/px30-u-boot.dtsi
@@ -14,6 +14,13 @@
u-boot,spl-boot-order = &emmc, &sdmmc;
stdout-path = &uart2;
};
+
+ secure-otp@ff110000 {
+ compatible = "rockchip,px30-secure-otp";
+ reg = <0x0 0xff110000 0x0 0x4000>;
+ secure_conf = <0xff11C008>;
+ mask_addr = <0xff2d0000>;
+ };
};
&psci {
diff --git a/u-boot/arch/arm/dts/px30.dtsi b/u-boot/arch/arm/dts/px30.dtsi
index e105f4f..bffbbff 100644
--- a/u-boot/arch/arm/dts/px30.dtsi
+++ b/u-boot/arch/arm/dts/px30.dtsi
@@ -288,13 +288,6 @@
status = "disabled";
};
- secure_otp: secure_otp@ff110000 {
- compatible = "rockchip,px30-secure-otp";
- reg = <0x0 0xff110000 0x0 0x4000>;
- secure_conf = <0xff11C008>;
- mask_addr = <0xff2d0000>;
- };
-
gic: interrupt-controller@ff131000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
diff --git a/u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi b/u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi
index ca97e45..b848d5e 100644
--- a/u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rk3036-sdk-u-boot.dtsi
@@ -37,3 +37,31 @@
status = "okay";
};
+&pinctrl {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb2phy {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb_otg {
+ u-boot,dm-pre-reloc;
+};
diff --git a/u-boot/arch/arm/dts/rk3036-sdk.dts b/u-boot/arch/arm/dts/rk3036-sdk.dts
index e881387..8a53690 100644
--- a/u-boot/arch/arm/dts/rk3036-sdk.dts
+++ b/u-boot/arch/arm/dts/rk3036-sdk.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "rk3036.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "SDK-RK3036";
@@ -37,6 +38,19 @@
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
+
+ gpio-keys {
+ u-boot,dm-pre-reloc;
+ compatible = "gpio-keys";
+ status = "okay";
+
+ volume-up {
+ u-boot,dm-pre-reloc;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "Volume Up";
+ gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
+ };
+ };
};
&i2c1 {
diff --git a/u-boot/arch/arm/dts/rk3036.dtsi b/u-boot/arch/arm/dts/rk3036.dtsi
index 10ee7b8..b24a219 100644
--- a/u-boot/arch/arm/dts/rk3036.dtsi
+++ b/u-boot/arch/arm/dts/rk3036.dtsi
@@ -223,6 +223,35 @@
grf: syscon@20008000 {
compatible = "rockchip,rk3036-grf", "syscon";
reg = <0x20008000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ usb2phy: usb2-phy@17c {
+ compatible = "rockchip,rk3036-usb2phy";
+ reg = <0x017c 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
};
usb_otg: usb@10180000 {
diff --git a/u-boot/arch/arm/dts/rk3128-u-boot.dtsi b/u-boot/arch/arm/dts/rk3128-u-boot.dtsi
index 654bf3e..0173a15 100644
--- a/u-boot/arch/arm/dts/rk3128-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rk3128-u-boot.dtsi
@@ -39,6 +39,11 @@
};
};
+&sfc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
&emmc {
u-boot,dm-pre-reloc;
status = "okay";
diff --git a/u-boot/arch/arm/dts/rk3128.dtsi b/u-boot/arch/arm/dts/rk3128.dtsi
index 9e4d387..5ef71de 100644
--- a/u-boot/arch/arm/dts/rk3128.dtsi
+++ b/u-boot/arch/arm/dts/rk3128.dtsi
@@ -222,6 +222,18 @@
reg = <0x20000110 0x24>;
#reset-cells = <1>;
};
+
+ sfc: sfc@1020c000 {
+ compatible ="rockchip,rksfc","rockchip,sfc";
+ reg = <0x1020c000 0x8000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <60000000>;
+ status = "disabled";
+ };
+
nandc: nandc@10500000 {
compatible = "rockchip,rk-nandc";
reg = <0x10500000 0x4000>;
@@ -590,6 +602,8 @@
grf: syscon@20008000 {
compatible = "rockchip,rk3128-grf", "syscon";
reg = <0x20008000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
lvds: lvds {
compatible = "rockchip,rk3126-lvds";
diff --git a/u-boot/arch/arm/dts/rk3308-u-boot.dtsi b/u-boot/arch/arm/dts/rk3308-u-boot.dtsi
index 90ccefe..dc565b1 100644
--- a/u-boot/arch/arm/dts/rk3308-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rk3308-u-boot.dtsi
@@ -14,6 +14,14 @@
stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
};
+
+ secure-otp@ff2a8000 {
+ compatible = "rockchip,rk3308-secure-otp";
+ reg = <0x0 0xff2a8000 0x0 0x4000>;
+ secure_conf = <0xff2b0004>;
+ mask_addr = <0xff540000>;
+ u-boot,dm-pre-reloc;
+ };
};
&psci {
@@ -121,10 +129,6 @@
&saradc {
u-boot,dm-pre-reloc;
status = "okay";
-};
-
-&secure_otp {
- u-boot,dm-pre-reloc;
};
&uart0 {
diff --git a/u-boot/arch/arm/dts/rk3308.dtsi b/u-boot/arch/arm/dts/rk3308.dtsi
index ff989ef..acdb47f 100644
--- a/u-boot/arch/arm/dts/rk3308.dtsi
+++ b/u-boot/arch/arm/dts/rk3308.dtsi
@@ -264,13 +264,6 @@
status = "disabled";
};
- secure_otp: secure_otp@0xff2a8000 {
- compatible = "rockchip,rk3308-secure-otp";
- reg = <0x0 0xff2a8000 0x0 0x4000>;
- secure_conf = <0xff2b0004>;
- mask_addr = <0xff540000>;
- };
-
vop: vop@ff2e0000 {
compatible = "rockchip,rk3308-vop";
reg = <0x0 0xff2e0000 0x0 0x1fc>, <0x0 0xff2e0a00 0x0 0x400>;
diff --git a/u-boot/arch/arm/dts/rk3528-evb.dts b/u-boot/arch/arm/dts/rk3528-evb.dts
new file mode 100644
index 0000000..600601a
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3528-evb.dts
@@ -0,0 +1,31 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3528.dtsi"
+#include "rk3528-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Rockchip RK3528 Evaluation Board";
+ compatible = "rockchip,rk3528-evb", "rockchip,rk3528";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ volumeup-key {
+ u-boot,dm-pre-reloc;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "volume up";
+ press-threshold-microvolt = <9>;
+ };
+ };
+};
diff --git a/u-boot/arch/arm/dts/rk3528-pinctrl.dtsi b/u-boot/arch/arm/dts/rk3528-pinctrl.dtsi
new file mode 100644
index 0000000..063606a
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3528-pinctrl.dtsi
@@ -0,0 +1,1241 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ arm {
+ arm_pins: arm-pins {
+ rockchip,pins =
+ /* arm_avs */
+ <4 RK_PC4 3 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <4 RK_PA0 3 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <4 RK_PC6 3 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <4 RK_PC5 3 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <4 RK_PA2 4 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <4 RK_PA3 4 &pcfg_pull_none>;
+ };
+
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+ };
+
+ can2 {
+ can2m0_pins: can2m0-pins {
+ rockchip,pins =
+ /* can2_rx_m0 */
+ <1 RK_PB3 2 &pcfg_pull_none>,
+ /* can2_tx_m0 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ can2m1_pins: can2m1-pins {
+ rockchip,pins =
+ /* can2_rx_m1 */
+ <3 RK_PA5 5 &pcfg_pull_none>,
+ /* can2_tx_m1 */
+ <3 RK_PA4 5 &pcfg_pull_none>;
+ };
+ };
+
+ can3 {
+ can3m0_pins: can3m0-pins {
+ rockchip,pins =
+ /* can3_rx_m0 */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* can3_tx_m0 */
+ <1 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ can3m1_pins: can3m1-pins {
+ rockchip,pins =
+ /* can3_rx_m1 */
+ <3 RK_PB3 2 &pcfg_pull_none>,
+ /* can3_tx_m1 */
+ <3 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ clkm0_32k_out: clkm0-32k-out {
+ rockchip,pins =
+ /* clkm0_32k_out */
+ <3 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ clkm1_32k_out: clkm1-32k-out {
+ rockchip,pins =
+ /* clkm1_32k_out */
+ <1 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth {
+ eth_pins: eth-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out */
+ <3 RK_PB5 2 &pcfg_pull_none>;
+ };
+ };
+
+ fephy {
+ fephym0_led_dpx: fephym0-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ fephym0_led_link: fephym0-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m0 */
+ <4 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ fephym0_led_spd: fephym0-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m0 */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ fephym1_led_dpx: fephym1-led_dpx {
+ rockchip,pins =
+ /* fephy_led_dpx_m1 */
+ <2 RK_PA4 5 &pcfg_pull_none>;
+ };
+
+ fephym1_led_link: fephym1-led_link {
+ rockchip,pins =
+ /* fephy_led_link_m1 */
+ <2 RK_PA6 5 &pcfg_pull_none>;
+ };
+
+ fephym1_led_spd: fephym1-led_spd {
+ rockchip,pins =
+ /* fephy_led_spd_m1 */
+ <2 RK_PA5 5 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PD5 2 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ fspi_csn0: fspi-csn0 {
+ rockchip,pins =
+ /* fspi_csn0 */
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ fspi_csn1: fspi-csn1 {
+ rockchip,pins =
+ /* fspi_csn1 */
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <4 RK_PC3 3 &pcfg_pull_none>;
+ };
+ };
+
+ hdmi {
+ hdmi_pins: hdmi-pins {
+ rockchip,pins =
+ /* hdmi_tx_cec */
+ <0 RK_PA3 1 &pcfg_pull_none>,
+ /* hdmi_tx_hpd */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* hdmi_tx_scl */
+ <0 RK_PA4 1 &pcfg_pull_none>,
+ /* hdmi_tx_sda */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ hsm {
+ hsmm0_pins: hsmm0-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m0 */
+ <2 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ hsmm1_pins: hsmm1-pins {
+ rockchip,pins =
+ /* hsm_clk_out_m1 */
+ <1 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0m0_xfer: i2c0m0-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m0 */
+ <4 RK_PC4 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m0 */
+ <4 RK_PC3 2 &pcfg_pull_none_smt>;
+ };
+
+ i2c0m1_xfer: i2c0m1-xfer {
+ rockchip,pins =
+ /* i2c0_scl_m1 */
+ <4 RK_PA1 2 &pcfg_pull_none_smt>,
+ /* i2c0_sda_m1 */
+ <4 RK_PA0 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <4 RK_PA3 2 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none_smt>;
+ };
+
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <4 RK_PC5 4 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <4 RK_PC6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PA4 2 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PA5 2 &pcfg_pull_none_smt>;
+ };
+
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <1 RK_PA5 3 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <1 RK_PA6 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <1 RK_PA0 2 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <1 RK_PA1 2 &pcfg_pull_none_smt>;
+ };
+
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <3 RK_PC1 5 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <3 RK_PC3 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ i2c4_xfer: i2c4-xfer {
+ rockchip,pins =
+ /* i2c4_scl */
+ <2 RK_PA0 4 &pcfg_pull_none_smt>,
+ /* i2c4_sda */
+ <2 RK_PA1 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <1 RK_PB2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <1 RK_PB3 3 &pcfg_pull_none_smt>;
+ };
+
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c6 {
+ i2c6m0_xfer: i2c6m0-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m0 */
+ <3 RK_PB2 5 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m0 */
+ <3 RK_PB3 5 &pcfg_pull_none_smt>;
+ };
+
+ i2c6m1_xfer: i2c6m1-xfer {
+ rockchip,pins =
+ /* i2c6_scl_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none_smt>,
+ /* i2c6_sda_m1 */
+ <1 RK_PD7 3 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c7 {
+ i2c7_xfer: i2c7-xfer {
+ rockchip,pins =
+ /* i2c7_scl */
+ <2 RK_PA5 4 &pcfg_pull_none_smt>,
+ /* i2c7_sda */
+ <2 RK_PA6 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ i2s0m0_pins: i2s0m0-pins {
+ rockchip,pins =
+ /* i2s0_lrck_m0 */
+ <3 RK_PB6 1 &pcfg_pull_none>,
+ /* i2s0_mclk_m0 */
+ <3 RK_PB4 1 &pcfg_pull_none>,
+ /* i2s0_sclk_m0 */
+ <3 RK_PB5 1 &pcfg_pull_none>,
+ /* i2s0_sdi_m0 */
+ <3 RK_PB7 1 &pcfg_pull_none>,
+ /* i2s0_sdo_m0 */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ i2s0m1_pins: i2s0m1-pins {
+ rockchip,pins =
+ /* i2s0_lrck_m1 */
+ <1 RK_PB6 1 &pcfg_pull_none>,
+ /* i2s0_mclk_m1 */
+ <1 RK_PB4 1 &pcfg_pull_none>,
+ /* i2s0_sclk_m1 */
+ <1 RK_PB5 1 &pcfg_pull_none>,
+ /* i2s0_sdi_m1 */
+ <1 RK_PB7 1 &pcfg_pull_none>,
+ /* i2s0_sdo_m1 */
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ i2s1_pins: i2s1-pins {
+ rockchip,pins =
+ /* i2s1_lrck */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* i2s1_mclk */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* i2s1_sclk */
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ /* i2s1_sdi0 */
+ <4 RK_PB4 1 &pcfg_pull_none>,
+ /* i2s1_sdi1 */
+ <4 RK_PB3 1 &pcfg_pull_none>,
+ /* i2s1_sdi2 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* i2s1_sdi3 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* i2s1_sdo0 */
+ <4 RK_PA7 1 &pcfg_pull_none>,
+ /* i2s1_sdo1 */
+ <4 RK_PB0 1 &pcfg_pull_none>,
+ /* i2s1_sdo2 */
+ <4 RK_PB1 1 &pcfg_pull_none>,
+ /* i2s1_sdo3 */
+ <4 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m0 */
+ <2 RK_PA2 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m0 */
+ <2 RK_PA3 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m0 */
+ <2 RK_PA4 2 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m0 */
+ <2 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_cpu_tck_m1 */
+ <4 RK_PD0 2 &pcfg_pull_none>,
+ /* jtag_cpu_tms_m1 */
+ <4 RK_PC7 2 &pcfg_pull_none>,
+ /* jtag_mcu_tck_m1 */
+ <4 RK_PD0 3 &pcfg_pull_none>,
+ /* jtag_mcu_tms_m1 */
+ <4 RK_PC7 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ pciem0_pins: pciem0-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m0 */
+ <3 RK_PA6 5 &pcfg_pull_none>,
+ /* pcie_perstn_m0 */
+ <3 RK_PB0 5 &pcfg_pull_none>,
+ /* pcie_waken_m0 */
+ <3 RK_PA7 5 &pcfg_pull_none>;
+ };
+
+ pciem1_pins: pciem1-pins {
+ rockchip,pins =
+ /* pcie_clkreqn_m1 */
+ <1 RK_PA0 4 &pcfg_pull_none>,
+ /* pcie_perstn_m1 */
+ <1 RK_PA2 4 &pcfg_pull_none>,
+ /* pcie_waken_m1 */
+ <1 RK_PA1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ pdm_clk0: pdm-clk0 {
+ rockchip,pins =
+ /* pdm_clk0 */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ pdm_clk1: pdm-clk1 {
+ rockchip,pins =
+ /* pdm_clk1 */
+ <4 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ pdm_sdi0: pdm-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0 */
+ <4 RK_PB2 3 &pcfg_pull_none>;
+ };
+
+ pdm_sdi1: pdm-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1 */
+ <4 RK_PB1 3 &pcfg_pull_none>;
+ };
+
+ pdm_sdi2: pdm-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2 */
+ <4 RK_PB3 3 &pcfg_pull_none>;
+ };
+
+ pdm_sdi3: pdm-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3 */
+ <4 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <4 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PA2 5 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <4 RK_PC4 1 &pcfg_pull_none>;
+ };
+
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PA3 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <4 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <1 RK_PA7 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_m0 */
+ <4 RK_PC6 1 &pcfg_pull_none>;
+ };
+
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_m1 */
+ <2 RK_PA4 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <4 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <1 RK_PA4 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <4 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <3 RK_PC3 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <4 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <1 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ pwm6m2_pins: pwm6m2-pins {
+ rockchip,pins =
+ /* pwm6_m2 */
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_m0 */
+ <4 RK_PC2 1 &pcfg_pull_none>;
+ };
+
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_m1 */
+ <1 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ pwr {
+ pwr_pins: pwr-pins {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <4 RK_PC2 2 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <4 RK_PB6 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref {
+ refm0_pins: refm0-pins {
+ rockchip,pins =
+ /* ref_clk_out_m0 */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ refm1_pins: refm1-pins {
+ rockchip,pins =
+ /* ref_clk_out_m1 */
+ <3 RK_PC3 6 &pcfg_pull_none>;
+ };
+ };
+
+ rgmii {
+ rgmii_miim: rgmii-miim {
+ rockchip,pins =
+ /* rgmii_mdc */
+ <3 RK_PB6 2 &pcfg_pull_none>,
+ /* rgmii_mdio */
+ <3 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ rgmii_rx_bus2: rgmii-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0 */
+ <3 RK_PA3 2 &pcfg_pull_none>,
+ /* rgmii_rxd1 */
+ <3 RK_PA2 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_crs */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ rgmii_tx_bus2: rgmii-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0 */
+ <3 RK_PA1 2 &pcfg_pull_none>,
+ /* rgmii_txd1 */
+ <3 RK_PA0 2 &pcfg_pull_none>,
+ /* rgmii_txen */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ rgmii_rgmii_clk: rgmii-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk */
+ <3 RK_PA5 2 &pcfg_pull_none>,
+ /* rgmii_txclk */
+ <3 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ rgmii_rgmii_bus: rgmii-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2 */
+ <3 RK_PA7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3 */
+ <3 RK_PA6 2 &pcfg_pull_none>,
+ /* rgmii_txd2 */
+ <3 RK_PB1 2 &pcfg_pull_none>,
+ /* rgmii_txd3 */
+ <3 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ rgmii_clk: rgmii-clk {
+ rockchip,pins =
+ /* rgmii_clk */
+ <3 RK_PB4 2 &pcfg_pull_none>;
+ };
+ rgmii_txer: rgmii-txer {
+ rockchip,pins =
+ /* rgmii_txer */
+ <3 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ scr {
+ scrm0_pins: scrm0-pins {
+ rockchip,pins =
+ /* scr_clk_m0 */
+ <1 RK_PA2 3 &pcfg_pull_none>,
+ /* scr_data_m0 */
+ <1 RK_PA1 3 &pcfg_pull_none>,
+ /* scr_detn_m0 */
+ <1 RK_PA0 3 &pcfg_pull_none>,
+ /* scr_rstn_m0 */
+ <1 RK_PA3 3 &pcfg_pull_none>;
+ };
+
+ scrm1_pins: scrm1-pins {
+ rockchip,pins =
+ /* scr_clk_m1 */
+ <2 RK_PA5 3 &pcfg_pull_none>,
+ /* scr_data_m1 */
+ <2 RK_PA3 4 &pcfg_pull_none>,
+ /* scr_detn_m1 */
+ <2 RK_PA6 3 &pcfg_pull_none>,
+ /* scr_rstn_m1 */
+ <2 RK_PA4 4 &pcfg_pull_none>;
+ };
+ };
+
+ sdio0 {
+ sdio0_bus4: sdio0-bus4 {
+ rockchip,pins =
+ /* sdio0_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio0_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio0_clk: sdio0-clk {
+ rockchip,pins =
+ /* sdio0_clk */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio0_cmd: sdio0-cmd {
+ rockchip,pins =
+ /* sdio0_cmd */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio0_det: sdio0-det {
+ rockchip,pins =
+ /* sdio0_det */
+ <1 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ sdio0_pwren: sdio0-pwren {
+ rockchip,pins =
+ /* sdio0_pwren */
+ <1 RK_PA7 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdio1 {
+ sdio1_bus4: sdio1-bus4 {
+ rockchip,pins =
+ /* sdio1_d0 */
+ <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d1 */
+ <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d2 */
+ <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdio1_d3 */
+ <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio1_clk: sdio1-clk {
+ rockchip,pins =
+ /* sdio1_clk */
+ <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio1_cmd: sdio1-cmd {
+ rockchip,pins =
+ /* sdio1_cmd */
+ <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdio1_det: sdio1-det {
+ rockchip,pins =
+ /* sdio1_det */
+ <3 RK_PB3 1 &pcfg_pull_up>;
+ };
+
+ sdio1_pwren: sdio1-pwren {
+ rockchip,pins =
+ /* sdio1_pwren */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc_pins: sdmmc-pins {
+ sdmmc_bus4: sdmmc-bus4 {
+ rockchip,pins =
+ /* sdmmc_d0 */
+ <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d1 */
+ <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d2 */
+ <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc_d3 */
+ <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc_clk: sdmmc-clk {
+ rockchip,pins =
+ /* sdmmc_clk */
+ <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc_cmd: sdmmc-cmd {
+ rockchip,pins =
+ /* sdmmc_cmd */
+ <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc_det: sdmmc-det {
+ rockchip,pins =
+ /* sdmmc_detn */
+ <2 RK_PA6 1 &pcfg_pull_up>;
+ };
+
+ sdmmc_pwren: sdmmc-pwren {
+ rockchip,pins =
+ /* sdmmc_pwren */
+ <4 RK_PA1 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ spdifm0_pins: spdifm0-pins {
+ rockchip,pins =
+ /* spdif_tx_m0 */
+ <4 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ spdifm1_pins: spdifm1-pins {
+ rockchip,pins =
+ /* spdif_tx_m1 */
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ spdifm2_pins: spdifm2-pins {
+ rockchip,pins =
+ /* spdif_tx_m2 */
+ <3 RK_PC3 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0_pins: spi0-pins {
+ rockchip,pins =
+ /* spi0_clk */
+ <4 RK_PB4 2 &pcfg_pull_none>,
+ /* spi0_miso */
+ <4 RK_PB3 2 &pcfg_pull_none>,
+ /* spi0_mosi */
+ <4 RK_PB2 2 &pcfg_pull_none>;
+ };
+
+ spi0_csn0: spi0-csn0 {
+ rockchip,pins =
+ /* spi0_csn0 */
+ <4 RK_PB6 2 &pcfg_pull_none>;
+ };
+ spi0_csn1: spi0-csn1 {
+ rockchip,pins =
+ /* spi0_csn1 */
+ <4 RK_PC1 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ spi1_pins: spi1-pins {
+ rockchip,pins =
+ /* spi1_clk */
+ <1 RK_PB6 2 &pcfg_pull_none>,
+ /* spi1_miso */
+ <1 RK_PC0 2 &pcfg_pull_none>,
+ /* spi1_mosi */
+ <1 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ spi1_csn0: spi1-csn0 {
+ rockchip,pins =
+ /* spi1_csn0 */
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ spi1_csn1: spi1-csn1 {
+ rockchip,pins =
+ /* spi1_csn1 */
+ <1 RK_PC2 1 &pcfg_pull_none>;
+ };
+ };
+
+ tsi0 {
+ tsi0_pins: tsi0-pins {
+ rockchip,pins =
+ /* tsi0_clkin */
+ <3 RK_PB2 3 &pcfg_pull_none>,
+ /* tsi0_d0 */
+ <3 RK_PB1 3 &pcfg_pull_none>,
+ /* tsi0_d1 */
+ <3 RK_PB5 3 &pcfg_pull_none>,
+ /* tsi0_d2 */
+ <3 RK_PB6 3 &pcfg_pull_none>,
+ /* tsi0_d3 */
+ <3 RK_PB7 3 &pcfg_pull_none>,
+ /* tsi0_d4 */
+ <3 RK_PA3 3 &pcfg_pull_none>,
+ /* tsi0_d5 */
+ <3 RK_PA2 3 &pcfg_pull_none>,
+ /* tsi0_d6 */
+ <3 RK_PA1 3 &pcfg_pull_none>,
+ /* tsi0_d7 */
+ <3 RK_PA0 3 &pcfg_pull_none>,
+ /* tsi0_fail */
+ <3 RK_PC0 3 &pcfg_pull_none>,
+ /* tsi0_sync */
+ <3 RK_PB4 3 &pcfg_pull_none>,
+ /* tsi0_valid */
+ <3 RK_PB3 3 &pcfg_pull_none>;
+ };
+ };
+
+ tsi1 {
+ tsi1_pins: tsi1-pins {
+ rockchip,pins =
+ /* tsi1_clkin */
+ <3 RK_PA5 3 &pcfg_pull_none>,
+ /* tsi1_d0 */
+ <3 RK_PA4 3 &pcfg_pull_none>,
+ /* tsi1_sync */
+ <3 RK_PA7 3 &pcfg_pull_none>,
+ /* tsi1_valid */
+ <3 RK_PA6 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <4 RK_PC7 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <4 RK_PD0 1 &pcfg_pull_up>;
+ };
+
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <2 RK_PA0 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <2 RK_PA1 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <4 RK_PA7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <4 RK_PA6 2 &pcfg_pull_up>;
+ };
+
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <4 RK_PC6 2 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <4 RK_PC5 2 &pcfg_pull_up>;
+ };
+
+ uart1_ctsn: uart1-ctsn {
+ rockchip,pins =
+ /* uart1_ctsn */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+ uart1_rtsn: uart1-rtsn {
+ rockchip,pins =
+ /* uart1_rtsn */
+ <4 RK_PA5 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <3 RK_PA0 1 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <3 RK_PA1 1 &pcfg_pull_up>;
+ };
+
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <3 RK_PA3 1 &pcfg_pull_none>;
+ };
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <3 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <1 RK_PB0 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <1 RK_PB1 1 &pcfg_pull_up>;
+ };
+
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <1 RK_PB3 1 &pcfg_pull_none>;
+ };
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <4 RK_PB0 2 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <4 RK_PB1 2 &pcfg_pull_up>;
+ };
+
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <4 RK_PB7 3 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <4 RK_PC0 3 &pcfg_pull_up>;
+ };
+
+ uart3_ctsn: uart3-ctsn {
+ rockchip,pins =
+ /* uart3_ctsn */
+ <4 RK_PA3 3 &pcfg_pull_none>;
+ };
+ uart3_rtsn: uart3-rtsn {
+ rockchip,pins =
+ /* uart3_rtsn */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ uart4_xfer: uart4-xfer {
+ rockchip,pins =
+ /* uart4_rx */
+ <2 RK_PA2 3 &pcfg_pull_up>,
+ /* uart4_tx */
+ <2 RK_PA3 3 &pcfg_pull_up>;
+ };
+
+ uart4_ctsn: uart4-ctsn {
+ rockchip,pins =
+ /* uart4_ctsn */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+ uart4_rtsn: uart4-rtsn {
+ rockchip,pins =
+ /* uart4_rtsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <1 RK_PA2 2 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <1 RK_PA3 2 &pcfg_pull_up>;
+ };
+
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PA6 2 &pcfg_pull_none>;
+ };
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <1 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <1 RK_PD4 2 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <1 RK_PD7 2 &pcfg_pull_up>;
+ };
+
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <1 RK_PD2 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <3 RK_PC3 4 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <3 RK_PC1 4 &pcfg_pull_up>;
+ };
+
+ uart6_ctsn: uart6-ctsn {
+ rockchip,pins =
+ /* uart6_ctsn */
+ <3 RK_PA4 4 &pcfg_pull_none>;
+ };
+ uart6_rtsn: uart6-rtsn {
+ rockchip,pins =
+ /* uart6_rtsn */
+ <3 RK_PA5 4 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <3 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <3 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <3 RK_PB0 4 &pcfg_pull_none>;
+ };
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <3 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PB3 4 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PB2 4 &pcfg_pull_up>;
+ };
+
+ uart7m1_ctsn: uart7m1-ctsn {
+ rockchip,pins =
+ /* uart7m1_ctsn */
+ <1 RK_PB0 4 &pcfg_pull_none>;
+ };
+ uart7m1_rtsn: uart7m1-rtsn {
+ rockchip,pins =
+ /* uart7m1_rtsn */
+ <1 RK_PB1 4 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/u-boot/arch/arm/dts/rk3528-u-boot.dtsi b/u-boot/arch/arm/dts/rk3528-u-boot.dtsi
new file mode 100644
index 0000000..7d09361
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3528-u-boot.dtsi
@@ -0,0 +1,206 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = &sdmmc, &sdhci, &spi_nand, &spi_nor;
+ };
+
+ secure-otp@ffcd0000 {
+ compatible = "rockchip,rk3528-secure-otp";
+ reg = <0x0 0xffcd0000 0x0 0x4000>;
+ secure_conf = <0xff4500c0>;
+ mask_addr = <0x0>;
+ cru_rst_addr = <0xff4a8080>;
+ u-boot,dm-spl;
+ status = "okay";
+ };
+
+};
+
+&grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&ioc_grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&cru {
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&crypto {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&rng {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&psci {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&sfc {
+ u-boot,dm-spl;
+ /delete-property/ pinctrl-names;
+ /delete-property/ pinctrl-0;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi_nand: flash@0 {
+ u-boot,dm-spl;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <75000000>;
+ };
+
+ spi_nor: flash@1 {
+ u-boot,dm-spl;
+ compatible = "jedec,spi-nor";
+ label = "sfc_nor";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ /delete-property/ assigned-clocks;
+ /delete-property/ assigned-clock-rates;
+ /delete-property/ pinctrl-names;
+ /delete-property/ pinctrl-0;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+
+&sdmmc {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&saradc {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&u2phy_otg {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usb2phy {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&firmware {
+ u-boot,dm-spl;
+};
+
+&scmi {
+ u-boot,dm-spl;
+};
+
+&scmi_clk {
+ u-boot,dm-spl;
+};
+
+&scmi_shmem {
+ u-boot,dm-spl;
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-spl;
+};
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&gpio2 {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_none_drv_level_1 {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_none_drv_level_2 {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_drv_level_1 {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_up {
+ u-boot,dm-spl;
+};
+
+&pcfg_pull_none {
+ u-boot,dm-spl;
+};
+
+&sdmmc_pins {
+ u-boot,dm-spl;
+};
+
+&sdmmc_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc_det {
+ u-boot,dm-spl;
+};
diff --git a/u-boot/arch/arm/dts/rk3528.dtsi b/u-boot/arch/arm/dts/rk3528.dtsi
new file mode 100644
index 0000000..3177904
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3528.dtsi
@@ -0,0 +1,2184 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3528-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rk3528-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include <dt-bindings/suspend/rockchip-rk3528.h>
+#include <dt-bindings/thermal/thermal.h>
+#include <dt-bindings/display/rockchip-tve.h>
+
+/ {
+ compatible = "rockchip,rk3528";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &sfc;
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP1>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ clocks = <&scmi_clk SCMI_CLK_CPU>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ cpu-idle-states = <&CPU_SLEEP1>;
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ CPU_SLEEP0: cpu-sleep0 {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ status = "disabled";
+ };
+
+ CPU_SLEEP1: cpu-sleep {
+ compatible = "arm,idle-state";
+ local-timer-stop;
+ arm,psci-suspend-param = <0x0010000>;
+ entry-latency-us = <120>;
+ exit-latency-us = <250>;
+ min-residency-us = <900>;
+ status = "okay";
+ };
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ rockchip,pvtm-voltage-sel = <
+ 0 1310 0
+ 1311 1340 1
+ 1341 1370 2
+ 1371 1400 3
+ 1401 1430 4
+ 1431 1460 5
+ 1461 9999 6
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x18>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <1416000>;
+ rockchip,pvtm-volt = <900000>;
+ rockchip,pvtm-ref-temp = <40>;
+ rockchip,pvtm-temp-prop = <0 0>;
+ rockchip,pvtm-thermal-zone = "soc-thermal";
+ rockchip,grf = <&grf>;
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <825000 825000 1100000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <825000 825000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <825000 825000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <825000 825000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <875000 875000 1100000>;
+ opp-microvolt-L1 = <862500 862500 1100000>;
+ opp-microvolt-L2 = <850000 850000 1100000>;
+ opp-microvolt-L3 = <837500 837500 1100000>;
+ opp-microvolt-L4 = <837500 837500 1100000>;
+ opp-microvolt-L5 = <837500 837500 1100000>;
+ opp-microvolt-L6 = <825000 825000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1416000000 {
+ opp-hz = /bits/ 64 <1416000000>;
+ opp-microvolt = <937500 937500 1100000>;
+ opp-microvolt-L1 = <925000 925000 1100000>;
+ opp-microvolt-L2 = <912500 912500 1100000>;
+ opp-microvolt-L3 = <900000 900000 1100000>;
+ opp-microvolt-L4 = <900000 900000 1100000>;
+ opp-microvolt-L5 = <900000 900000 1100000>;
+ opp-microvolt-L6 = <887500 887500 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1608000000 {
+ opp-hz = /bits/ 64 <1608000000>;
+ opp-microvolt = <1012500 1012500 1100000>;
+ opp-microvolt-L1 = <1000000 1000000 1100000>;
+ opp-microvolt-L2 = <987500 987500 1100000>;
+ opp-microvolt-L3 = <975000 975000 1100000>;
+ opp-microvolt-L4 = <962500 962500 1100000>;
+ opp-microvolt-L5 = <950000 950000 1100000>;
+ opp-microvolt-L6 = <937500 937500 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <1062500 1062500 1100000>;
+ opp-microvolt-L1 = <1050000 1050000 1100000>;
+ opp-microvolt-L2 = <1037500 1037500 1100000>;
+ opp-microvolt-L3 = <1025000 1025000 1100000>;
+ opp-microvolt-L4 = <1012500 1012500 1100000>;
+ opp-microvolt-L5 = <1000000 1000000 1100000>;
+ opp-microvolt-L6 = <987500 987500 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-2016000000 {
+ opp-hz = /bits/ 64 <2016000000>;
+ opp-microvolt = <1100000 1100000 1100000>;
+ opp-microvolt-L1 = <1087500 1087500 1100000>;
+ opp-microvolt-L2 = <1075000 1075000 1100000>;
+ opp-microvolt-L3 = <1062500 1062500 1100000>;
+ opp-microvolt-L4 = <1050000 1050000 1100000>;
+ opp-microvolt-L5 = <1037500 1037500 1100000>;
+ opp-microvolt-L6 = <1025000 1025000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ cpuinfo {
+ compatible = "rockchip,cpuinfo";
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
+ firmware: firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&scmi_shmem>;
+ arm,smc-id = <0x82000010>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ mpp_srv: mpp-srv {
+ compatible = "rockchip,mpp-service";
+ rockchip,taskqueue-count = <5>;
+ rockchip,resetgroup-count = <5>;
+ status = "disabled";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ rockchip_suspend: rockchip-suspend {
+ compatible = "rockchip,pm-rk3528";
+ status = "disabled";
+ rockchip,sleep-debug-en = <0>;
+ rockchip,sleep-mode-config = <
+ (0
+ | RKPM_SLP_ARMPD
+ )
+ >;
+ rockchip,wakeup-config = <
+ (0
+ | RKPM_CPU0_WKUP_EN
+ | RKPM_GPIO_WKUP_EN
+ )
+ >;
+ };
+
+ rockchip_system_monitor: rockchip-system-monitor {
+ compatible = "rockchip,system-monitor";
+
+ rockchip,thermal-zone = "soc-thermal";
+ };
+
+ thermal_zones: thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ trips {
+ soc_crit: soc-crit {
+ /* millicelsius */
+ temperature = <115000>;
+ /* millicelsius */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ scmi_shmem: scmi-shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ };
+
+ pcie2x1: pcie@fe4f0000 {
+ compatible = "rockchip,rk3528-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>,
+ <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>,
+ <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>,
+ <&cru PCLK_PCIE_PHY>;
+ clock-names = "aclk", "hclk_slv",
+ "hclk_dbi", "pclk_cru",
+ "aux", "pclk",
+ "pipe";
+ device_type = "pci";
+ interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
+ <0 0 0 2 &pcie2x1_intc 1>,
+ <0 0 0 3 &pcie2x1_intc 2>,
+ <0 0 0 4 &pcie2x1_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ num-viewport = <4>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy_pu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
+ 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
+ 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
+ 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe4f0000 0x0 0x10000>,
+ <0x1 0x40000000 0x0 0x400000>;
+ reg-names = "pcie-apb", "pcie-dbi";
+ resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>,
+ <&cru SRST_PRESETN_CRU_PCIE>;
+ reset-names = "pcie", "periph", "preset_cru";
+ status = "disabled";
+
+ pcie2x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>;
+ };
+ };
+
+ usbdrd30: usbdrd {
+ compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>,
+ <&cru ACLK_USB3OTG>;
+ clock-names = "ref_clk", "suspend_clk",
+ "bus_clk";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: dwc3@fe500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe500000 0x0 0x400000>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ resets = <&cru SRST_ARESETN_USB3OTG>;
+ reset-names = "usb3-otg";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1u2-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,xhci-trb-ent-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ quirk-skip-phy-init;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@fed01000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xfed01000 0 0x1000>,
+ <0x0 0xfed02000 0 0x2000>,
+ <0x0 0xfed04000 0 0x2000>,
+ <0x0 0xfed06000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ usb_host0_ehci: usb@ff100000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xff100000 0x0 0x40000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST>,
+ <&cru HCLK_USBHOST_ARB>,
+ <&usb2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@ff140000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xff140000 0x0 0x40000>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USBHOST>,
+ <&cru HCLK_USBHOST_ARB>,
+ <&usb2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ debug: debug@ff190000 {
+ compatible = "rockchip,debug";
+ reg = <0x0 0xff190000 0x0 0x1000>,
+ <0x0 0xff192000 0x0 0x1000>,
+ <0x0 0xff194000 0x0 0x1000>,
+ <0x0 0xff196000 0x0 0x1000>;
+ };
+
+ qos_crypto_a: qos@ff200000 {
+ compatible = "syscon";
+ reg = <0x0 0xff200000 0x0 0x20>;
+ };
+
+ qos_crypto_p: qos@ff200080 {
+ compatible = "syscon";
+ reg = <0x0 0xff200080 0x0 0x20>;
+ };
+
+ qos_dcf: qos@ff200100 {
+ compatible = "syscon";
+ reg = <0x0 0xff200100 0x0 0x20>;
+ };
+
+ qos_dft2apb: qos@ff200200 {
+ compatible = "syscon";
+ reg = <0x0 0xff200200 0x0 0x20>;
+ };
+
+ qos_dma2ddr: qos@ff200280 {
+ compatible = "syscon";
+ reg = <0x0 0xff200280 0x0 0x20>;
+ };
+
+ qos_dmac: qos@ff200300 {
+ compatible = "syscon";
+ reg = <0x0 0xff200300 0x0 0x20>;
+ };
+
+ qos_keyreader: qos@ff200380 {
+ compatible = "syscon";
+ reg = <0x0 0xff200380 0x0 0x20>;
+ };
+
+ qos_cpu: qos@ff210000 {
+ compatible = "syscon";
+ reg = <0x0 0xff210000 0x0 0x20>;
+ };
+
+ qos_debug: qos@ff210080 {
+ compatible = "syscon";
+ reg = <0x0 0xff210080 0x0 0x20>;
+ };
+
+ qos_gpu_m0: qos@ff220000 {
+ compatible = "syscon";
+ reg = <0x0 0xff220000 0x0 0x20>;
+ };
+
+ qos_gpu_m1: qos@ff220080 {
+ compatible = "syscon";
+ reg = <0x0 0xff220080 0x0 0x20>;
+ };
+
+ qos_pmu_mcu: qos@ff240000 {
+ compatible = "syscon";
+ reg = <0x0 0xff240000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@ff250000 {
+ compatible = "syscon";
+ reg = <0x0 0xff250000 0x0 0x20>;
+ };
+
+ qos_rkvenc: qos@ff260000 {
+ compatible = "syscon";
+ reg = <0x0 0xff260000 0x0 0x20>;
+ };
+
+ qos_gmac0: qos@ff270000 {
+ compatible = "syscon";
+ reg = <0x0 0xff270000 0x0 0x20>;
+ };
+
+ qos_hdcp: qos@ff270080 {
+ compatible = "syscon";
+ reg = <0x0 0xff270080 0x0 0x20>;
+ };
+
+ qos_jpegdec: qos@ff270100 {
+ compatible = "syscon";
+ reg = <0x0 0xff270100 0x0 0x20>;
+ };
+
+ qos_rga2_m0ro: qos@ff270200 {
+ compatible = "syscon";
+ reg = <0x0 0xff270200 0x0 0x20>;
+ };
+
+ qos_rga2_m0wo: qos@ff270280 {
+ compatible = "syscon";
+ reg = <0x0 0xff270280 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@ff270300 {
+ compatible = "syscon";
+ reg = <0x0 0xff270300 0x0 0x20>;
+ };
+
+ qos_usb2host: qos@ff270380 {
+ compatible = "syscon";
+ reg = <0x0 0xff270380 0x0 0x20>;
+ };
+
+ qos_vdpp: qos@ff270480 {
+ compatible = "syscon";
+ reg = <0x0 0xff270480 0x0 0x20>;
+ };
+
+ qos_vop: qos@ff270500 {
+ compatible = "syscon";
+ reg = <0x0 0xff270500 0x0 0x20>;
+ };
+
+ qos_emmc: qos@ff280000 {
+ compatible = "syscon";
+ reg = <0x0 0xff280000 0x0 0x20>;
+ };
+
+ qos_fspi: qos@ff280080 {
+ compatible = "syscon";
+ reg = <0x0 0xff280080 0x0 0x20>;
+ };
+
+ qos_gmac1: qos@ff280100 {
+ compatible = "syscon";
+ reg = <0x0 0xff280100 0x0 0x20>;
+ };
+
+ qos_pcie: qos@ff280180 {
+ compatible = "syscon";
+ reg = <0x0 0xff280180 0x0 0x20>;
+ };
+
+ qos_sdio0: qos@ff280200 {
+ compatible = "syscon";
+ reg = <0x0 0xff280200 0x0 0x20>;
+ };
+
+ qos_sdio1: qos@ff280280 {
+ compatible = "syscon";
+ reg = <0x0 0xff280280 0x0 0x20>;
+ };
+
+ qos_tsp: qos@ff280300 {
+ compatible = "syscon";
+ reg = <0x0 0xff280300 0x0 0x20>;
+ };
+
+ qos_usb3otg: qos@ff280380 {
+ compatible = "syscon";
+ reg = <0x0 0xff280380 0x0 0x20>;
+ };
+
+ qos_vpu: qos@ff280400 {
+ compatible = "syscon";
+ reg = <0x0 0xff280400 0x0 0x20>;
+ };
+
+ /*
+ * Merge all GRF, each independent GRF offset is shown as bellow:
+ * CORE_GRF: 0xff300000
+ * GPU_GRF: 0xff310000
+ * RKVENC_GRF: 0xff320000
+ * DDR_GRF: 0xff330000
+ * VPU_GRF: 0xff340000
+ * COMBO_PIPE_PHY_GRF: 0xff348000
+ * RKVDEC_GRF: 0xff350000
+ * VO_GRF: 0xff360000
+ * PMU_GRF: 0xff370000
+ * SYS_GRF: 0xff380000
+ */
+ grf: syscon@ff300000 {
+ compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff300000 0x0 0x90000>;
+
+ grf_cru: grf-clock-controller {
+ compatible = "rockchip,rk3528-grf-cru";
+ #clock-cells = <1>;
+ };
+
+ reboot_mode: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x70200>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
+ mode-charge = <BOOT_CHARGING>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-ums = <BOOT_UMS>;
+ mode-panic = <BOOT_PANIC>;
+ mode-watchdog = <BOOT_WATCHDOG>;
+ };
+ };
+
+ cru: clock-controller@ff4a0000 {
+ compatible = "rockchip,rk3528-cru";
+ reg = <0x0 0xff4a0000 0x0 0x30000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ assigned-clocks =
+ <&cru XIN_OSC0_DIV>,
+ <&cru PLL_GPLL>,
+ <&cru PLL_PPLL>,
+ <&cru PLL_CPLL>,
+ <&cru ARMCLK>,
+ <&cru CLK_MATRIX_250M_SRC>,
+ <&cru CLK_MATRIX_500M_SRC>,
+ <&cru CLK_MATRIX_50M_SRC>,
+ <&cru CLK_MATRIX_100M_SRC>,
+ <&cru CLK_MATRIX_150M_SRC>,
+ <&cru CLK_MATRIX_200M_SRC>,
+ <&cru CLK_MATRIX_300M_SRC>,
+ <&cru CLK_MATRIX_339M_SRC>,
+ <&cru CLK_MATRIX_400M_SRC>,
+ <&cru CLK_MATRIX_600M_SRC>,
+ <&cru CLK_PPLL_50M_MATRIX>,
+ <&cru CLK_PPLL_100M_MATRIX>,
+ <&cru CLK_PPLL_125M_MATRIX>,
+ <&cru ACLK_BUS_VOPGL_ROOT>;
+
+ assigned-clock-rates =
+ <32768>,
+ <1188000000>,
+ <1000000000>,
+ <996000000>,
+ <408000000>,
+ <250000000>,
+ <500000000>,
+ <50000000>,
+ <100000000>,
+ <150000000>,
+ <200000000>,
+ <300000000>,
+ <340000000>,
+ <400000000>,
+ <600000000>,
+ <50000000>,
+ <100000000>,
+ <125000000>,
+ <500000000>;
+ };
+
+ ioc_grf: syscon@ff540000 {
+ compatible = "rockchip,rk3528-ioc-grf", "syscon";
+ reg = <0x0 0xff540000 0x0 0x40000>;
+ };
+
+ pmu: power-management@ff600000 {
+ compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff600000 0x0 0x2000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3528-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* These power domains are grouped by VD_GPU */
+ pd_gpu@RK3528_PD_GPU {
+ reg = <RK3528_PD_GPU>;
+ clocks = <&cru ACLK_GPU_MALI>,
+ <&cru PCLK_GPU_ROOT>;
+ pm_qos = <&qos_gpu_m0>,
+ <&qos_gpu_m1>;
+ };
+ /* These power domains are grouped by VD_LOGIC */
+ pd_rkvdec@RK3528_PD_RKVDEC {
+ reg = <RK3528_PD_RKVDEC>;
+ };
+ pd_rkvenc@RK3528_PD_RKVENC {
+ reg = <RK3528_PD_RKVENC>;
+ };
+ pd_vo@RK3528_PD_VO {
+ reg = <RK3528_PD_VO>;
+ };
+ pd_vpu@RK3528_PD_VPU {
+ reg = <RK3528_PD_VPU>;
+ };
+ };
+ };
+
+ mailbox: mailbox@ff630000 {
+ compatible = "rockchip,rk3528-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff630000 0x0 0x200>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ gpu: gpu@ff700000 {
+ compatible = "arm,mali-450";
+ reg = <0x0 0xff700000 0x0 0x40000>;
+
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "Mali_GP_IRQ",
+ "Mali_GP_MMU_IRQ",
+ "IRQPP",
+ "Mali_PP0_IRQ",
+ "Mali_PP0_MMU_IRQ",
+ "Mali_PP1_IRQ",
+ "Mali_PP1_MMU_IRQ";
+ clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>,
+ <&cru PCLK_GPU_ROOT>;
+ clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu";
+ assigned-clocks = <&scmi_clk SCMI_CLK_GPU>;
+ assigned-clock-rates = <300000000>;
+ power-domains = <&power RK3528_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ status = "disabled";
+
+ gpu_power_model: power_model {
+ compatible = "arm,mali-simple-power-model";
+ voltage = <900>;
+ frequency = <500>;
+ static-power = <300>;
+ dynamic-power = <396>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&gpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ rockchip,pvtm-voltage-sel = <
+ 0 820 0
+ 821 840 1
+ 841 860 2
+ 861 880 3
+ 881 900 4
+ 901 9999 5
+ >;
+ rockchip,pvtm-pvtpll;
+ rockchip,pvtm-offset = <0x10018>;
+ rockchip,pvtm-sample-time = <1100>;
+ rockchip,pvtm-freq = <700000>;
+ rockchip,pvtm-volt = <900000>;
+ rockchip,pvtm-ref-temp = <40>;
+ rockchip,pvtm-temp-prop = <0 0>;
+ rockchip,pvtm-thermal-zone = "soc-thermal";
+ rockchip,grf = <&grf>;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ };
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ opp-microvolt = <825000 825000 1000000>;
+ opp-microvolt-L0 = <850000 850000 1000000>;
+ opp-microvolt-L1 = <837500 837500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ opp-microvolt-L1 = <887500 887500 1000000>;
+ opp-microvolt-L2 = <875000 875000 1000000>;
+ opp-microvolt-L3 = <862500 862500 1000000>;
+ opp-microvolt-L4 = <850000 850000 1000000>;
+ opp-microvolt-L5 = <837500 837500 1000000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ rkvdec: rkvdec@ff740100 {
+ compatible = "rockchip,rkv-decoder-v2";
+ reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>;
+ reg-names = "regs", "link";
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
+ rockchip,normal-rates = <340000000>, <0>, <600000000>;
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
+ assigned-clock-rates = <340000000>, <600000000>;
+ resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>,
+ <&cru SRST_RESETN_HEVC_CA_RKVDEC>;
+ reset-names = "video_a", "video_h", "video_hevc_cabac";
+ power-domains = <&power RK3528_PD_RKVDEC>;
+ iommus = <&rkvdec_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ rockchip,task-capacity = <16>;
+ status = "disabled";
+ };
+
+ rkvdec_mmu: iommu@ff740800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvdec_mmu";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>;
+ clock-names = "aclk", "iface", "clk_hevc_cabac";
+ power-domains = <&power RK3528_PD_RKVDEC>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rkvenc: rkvenc@ff780000 {
+ compatible = "rockchip,rkv-encoder-v2";
+ reg = <0x0 0xff780000 0x0 0x6000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc";
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ rockchip,normal-rates = <300000000>, <0>, <300000000>;
+ resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>,
+ <&cru SRST_RESETN_CORE_RKVENC>;
+ reset-names = "video_a", "video_h", "video_core";
+ assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>;
+ assigned-clock-rates = <300000000>, <300000000>;
+ power-domains = <&power RK3528_PD_RKVENC>;
+ iommus = <&rkvenc_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <1>;
+ rockchip,resetgroup-node = <1>;
+ status = "disabled";
+ };
+
+ rkvenc_mmu: iommu@ff78f000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff78f000 0x0 0x40>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvenc_mmu";
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3528_PD_RKVENC>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ vdpu: vdpu@ff7c0400 {
+ compatible = "rockchip,vpu-decoder-v2";
+ reg = <0x0 0xff7c0400 0x0 0x400>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
+ reset-names = "shared_video_a", "shared_video_h";
+ power-domains = <&power RK3528_PD_VPU>;
+ iommus = <&vdpu_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,resetgroup-node = <2>;
+ status = "disabled";
+ };
+
+ vdpu_mmu: iommu@ff7c0800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff7c0800 0x0 0x40>;
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vdpu_mmu";
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ power-domains = <&power RK3528_PD_VPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ avsd: avsd_plus@ff7c1000 {
+ compatible = "rockchip,avs-plus-decoder";
+ reg = <0x0 0xff7c1000 0x0 0x200>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>;
+ reset-names = "shared_video_a", "shared_video_h";
+ iommus = <&vdpu_mmu>;
+ power-domains = <&power RK3528_PD_VPU>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,resetgroup-node = <2>;
+ status = "disabled";
+ };
+
+ vop: vop@ff840000 {
+ compatible = "rockchip,rk3528-vop";
+ reg = <0x0 0xff840000 0x0 0x3000>,
+ <0x0 0xff845000 0x0 0x1000>,
+ <0x0 0xff846400 0x0 0x800>;
+ reg-names = "regs",
+ "gamma_lut",
+ "acm_regs";
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP0>,
+ <&cru DCLK_VOP1>;
+ clock-names = "aclk_vop",
+ "hclk_vop",
+ "dclk_vp0",
+ "dclk_vp1";
+ assigned-clocks = <&cru DCLK_VOP0>;
+ assigned-clock-parents = <&hdmiphy>;
+ iommus = <&vop_mmu>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vp0_out_hdmi: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vp1_out_tve: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&tve_in_vp1>;
+ };
+ };
+ };
+ };
+
+ vop_mmu: iommu@ff847e00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff847e00 0x0 0x100>;
+ interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ rockchip,disable-device-link-resume;
+ rockchip,shootdown-entire;
+ status = "disabled";
+ };
+
+ rga2: rga@ff850000 {
+ compatible = "rockchip,rga2_core0";
+ reg = <0x0 0xff850000 0x0 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga2_irq";
+ clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>;
+ clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
+ iommus = <&rga2_mmu>;
+ status = "disabled";
+ };
+
+ rga2_mmu: iommu@ff850f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff850f00 0x0 0x100>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga2_mmu";
+ clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ iep: iep@ff860000 {
+ compatible = "rockchip,iep-v2";
+ reg = <0x0 0xff860000 0x0 0x500>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
+ clock-names = "aclk", "hclk", "sclk";
+ rockchip,normal-rates = <340000000>, <0>, <340000000>;
+ assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
+ assigned-clock-rates = <340000000>, <340000000>;
+ resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
+ <&cru SRST_RESETN_CORE_VDPP>;
+ reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <3>;
+ rockchip,resetgroup-node = <3>;
+ power-domains = <&power RK3528_PD_VO>;
+ iommus = <&iep_mmu>;
+ status = "disabled";
+ };
+
+ iep_mmu: iommu@ff860800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff860800 0x0 0x100>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "iep_mmu";
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3528_PD_VO>;
+ status = "disabled";
+ };
+
+ vdpp: vdpp@ff861000 {
+ compatible = "rockchip,vdpp-v1";
+ reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>;
+ reg-names = "vdpp_regs", "zme_regs";
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>;
+ clock-names = "aclk", "hclk", "sclk";
+ rockchip,normal-rates = <340000000>, <0>, <340000000>;
+ assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>;
+ assigned-clock-rates = <340000000>, <340000000>;
+ resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>,
+ <&cru SRST_RESETN_CORE_VDPP>;
+ reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s";
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <3>;
+ rockchip,resetgroup-node = <3>;
+ power-domains = <&power RK3528_PD_VO>;
+ iommus = <&iep_mmu>;
+ status = "disabled";
+ };
+
+ jpegd: jpegd@ff870000 {
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
+ reg = <0x0 0xff870000 0x0 0x400>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,disable-auto-freq;
+ resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>;
+ reset-names = "video_a", "video_h";
+ power-domains = <&power RK3528_PD_VO>;
+ iommus = <&jpegd_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <4>;
+ rockchip,resetgroup-node = <4>;
+ status = "disabled";
+ };
+
+ jpegd_mmu: iommu@ff870480 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff870480 0x0 0x40>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpegd_mmu";
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>;
+ power-domains = <&power RK3528_PD_VO>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ tve: tve@ff880000 {
+ compatible = "rockchip,rk3528-tve";
+ reg = <0x0 0xff880000 0x0 0x4000>,
+ <0x0 0xffde0000 0x0 0x300>;
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_CVBS>,
+ <&cru PCLK_VCDCPHY>,
+ <&cru DCLK_CVBS>,
+ <&cru DCLK_4X_CVBS>;
+ clock-names = "hclk",
+ "pclk_vdac",
+ "dclk",
+ "dclk_4x";
+ rockchip,lumafilter0 = <0x000a0ffa>;
+ rockchip,lumafilter1 = <0x0ff4001a>;
+ rockchip,lumafilter2 = <0x00110fd2>;
+ rockchip,lumafilter3 = <0x0fe80051>;
+ rockchip,lumafilter4 = <0x001a0f74>;
+ rockchip,lumafilter5 = <0x0fe600ec>;
+ rockchip,lumafilter6 = <0x0ffa0e43>;
+ rockchip,lumafilter7 = <0x08200527>;
+ rockchip,tve-upsample = <DCLK_UPSAMPLEx4>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tve_in_vp1: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp1_out_tve>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ hdcp2: hdcp2@ff8c0000 {
+ compatible = "rockchip,rk3528-hdmi-hdcp2";
+ reg = <0x0 0xff8c0000 0x0 0x2000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>,
+ <&cru HCLK_HDCP>;
+ clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi";
+ status = "disabled";
+ };
+
+ hdmi: hdmi@ff8d0000 {
+ compatible = "rockchip,rk3528-dw-hdmi";
+ reg = <0x0 0xff8d0000 0x0 0x20000>,
+ <0x0 0xff610000 0x0 0x200>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_HDMI>,
+ <&cru CLK_SFR_HDMI>,
+ <&cru CLK_CEC_HDMI>;
+ clock-names = "iahb", "isfr", "cec";
+ reg-io-width = <4>;
+ rockchip,grf = <&grf>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ phys = <&hdmiphy>;
+ phy-names = "hdmi";
+ #sound-dai-cells = <0>;
+ hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_hdmi>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ can0: can@ff960000 {
+ compatible = "rockchip,rk3528-can";
+ reg = <0x0 0xff960000 0x0 0x100>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_CAN0>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_RESETN_CAN0>, <&cru SRST_PRESETN_CAN0>;
+ reset-names = "can", "can-apb";
+ status = "disabled";
+ };
+
+ can1: can@ff970000 {
+ compatible = "rockchip,rk3528-can";
+ reg = <0x0 0xff970000 0x0 0x100>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_CAN1>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_RESETN_CAN1>, <&cru SRST_PRESETN_CAN1>;
+ reset-names = "can", "can-apb";
+ status = "disabled";
+ };
+
+ can2: can@ff980000 {
+ compatible = "rockchip,rk3528-can";
+ reg = <0x0 0xff980000 0x0 0x100>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_CAN2>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_RESETN_CAN2>, <&cru SRST_PRESETN_CAN2>;
+ reset-names = "can", "can-apb";
+ status = "disabled";
+ };
+
+ can3: can@ff990000 {
+ compatible = "rockchip,rk3528-can";
+ reg = <0x0 0xff990000 0x0 0x100>;
+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru CLK_CAN3>;
+ assigned-clock-rates = <198000000>;
+ clocks = <&cru CLK_CAN3>, <&cru PCLK_CAN3>;
+ clock-names = "baudclk", "apb_pclk";
+ resets = <&cru SRST_RESETN_CAN3>, <&cru SRST_PRESETN_CAN3>;
+ reset-names = "can", "can-apb";
+ status = "disabled";
+ };
+
+ spi0: spi@ff9c0000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff9c0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 25>, <&dmac 24>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>;
+ status = "disabled";
+ };
+
+ spi1: spi@ff9d0000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff9d0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 31>, <&dmac 30>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff9f0000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f0000 0x0 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 9>, <&dmac 8>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff9f8000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff9f8000 0x0 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 11>, <&dmac 10>;
+ status = "disabled";
+ };
+
+ uart2: serial@ffa00000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa00000 0x0 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 13>, <&dmac 12>;
+ status = "disabled";
+ };
+
+ uart3: serial@ffa08000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa08000 0x0 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 15>, <&dmac 14>;
+ status = "disabled";
+ };
+
+ uart4: serial@ffa10000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa10000 0x0 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 17>, <&dmac 16>;
+ status = "disabled";
+ };
+
+ uart5: serial@ffa18000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa18000 0x0 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 19>, <&dmac 18>;
+ status = "disabled";
+ };
+
+ uart6: serial@ffa20000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa20000 0x0 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 21>, <&dmac 20>;
+ status = "disabled";
+ };
+
+ uart7: serial@ffa28000 {
+ compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xffa28000 0x0 0x100>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 23>, <&dmac 22>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@ffa50000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa50000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffa58000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa58000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffa60000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa60000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffa68000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa68000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffa70000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa70000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ffa78000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa78000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@ffa80000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa80000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@ffa88000 {
+ compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa88000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c7_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@ffa90000 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m0_pins>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@ffa90010 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1m0_pins>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@ffa90020 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m0_pins>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@ffa90030 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa90030 0x0 0x10>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m0_pins>;
+ clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm4: pwm@ffa98000 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@ffa98010 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@ffa98020 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@ffa98030 {
+ compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xffa98030 0x0 0x10>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7m0_pins>;
+ clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ rktimer: timer@ffab0000 {
+ compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer";
+ reg = <0x0 0xffab0000 0x0 0x20>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ wdt: watchdog@ffac0000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xffac0000 0x0 0x100>;
+ clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ tsadc: tsadc@ffad0000 {
+ compatible = "rockchip,rk3528-tsadc";
+ reg = <0x0 0xffad0000 0x0 0x400>;
+ rockchip,grf = <&grf>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
+ assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
+ assigned-clock-rates = <1200000>, <12000000>;
+ resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>;
+ reset-names = "tsadc", "tsadc-apb";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <120000>;
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "disabled";
+ };
+
+ saradc: saradc@ffae0000 {
+ compatible = "rockchip,rk3528-saradc";
+ reg = <0x0 0xffae0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_PRESETN_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ sai3: sai@ffb70000 {
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
+ reg = <0x0 0xffb70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 5>;
+ dma-names = "tx";
+ resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>;
+ reset-names = "m", "h";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sai0: sai@ffb80000 {
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
+ reg = <0x0 0xffb80000 0x0 0x1000>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 1>, <&dmac 0>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0m0_pins>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sai2: sai@ffb90000 {
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
+ reg = <0x0 0xffb90000 0x0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 4>;
+ dma-names = "tx";
+ resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>;
+ reset-names = "m", "h";
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sai1: sai@ffba0000 {
+ compatible = "rockchip,rk3528-sai", "rockchip,sai-v1";
+ reg = <0x0 0xffba0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 3>, <&dmac 2>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1_pins>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm: pdm@ffbb0000 {
+ compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm";
+ reg = <0x0 0xffbb0000 0x0 0x1000>;
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 6>;
+ dma-names = "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pdm_clk0
+ &pdm_clk1
+ &pdm_sdi0
+ &pdm_sdi1
+ &pdm_sdi2
+ &pdm_sdi3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_8ch: spdif@ffbc0000 {
+ compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xffbc0000 0x0 0x1000>;
+ interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 7>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm0_pins>;
+ status = "disabled";
+ };
+
+ gmac0: ethernet@ffbd0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbd0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&grf>;
+ clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>,
+ <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>,
+ <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "mac_clk_rx", "mac_clk_tx",
+ "pclk_mac", "aclk_mac";
+ resets = <&cru SRST_ARESETN_MAC_VO>;
+ reset-names = "stmmaceth";
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+
+ phy-mode = "rmii";
+ clock_in_out = "input";
+ phy-handle = <&rmii0_phy>;
+
+ nvmem-cells = <&macphy_bgs>;
+ nvmem-cell-names = "bgs";
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ rmii0_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ clocks = <&cru CLK_MACPHY>;
+ resets = <&cru SRST_RESETN_MACPHY>;
+ phy-is-integrated;
+ pinctrl-names = "default";
+ pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>;
+ nvmem-cells = <&macphy_txlevel>;
+ nvmem-cell-names = "txlevel";
+ };
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ gmac1: ethernet@ffbe0000 {
+ compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffbe0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&grf>;
+ clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>,
+ <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac";
+ resets = <&cru SRST_ARESETN_MAC>;
+ reset-names = "stmmaceth";
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&gmac1_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
+
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac1_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac1_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac1_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ sdhci: mmc@ffbf0000 {
+ compatible = "rockchip,rk3528-dwcmshc";
+ reg = <0x0 0xffbf0000 0x0 0x10000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>;
+ assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+ clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>,
+ <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>,
+ <&cru SRST_TRESETN_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sfc: spi@ffc00000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xffc00000 0x0 0x4000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdio0: mmc@ffc10000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc10000 0x0 0x4000>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>,
+ <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ resets = <&cru SRST_HRESETN_SDIO0>;
+ reset-names = "reset";
+ rockchip,use-v2-tuning;
+ status = "disabled";
+ };
+
+ sdio1: mmc@ffc20000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc20000 0x0 0x4000>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>,
+ <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ resets = <&cru SRST_HRESETN_SDIO1>;
+ reset-names = "reset";
+ rockchip,use-v2-tuning;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc30000 {
+ compatible = "rockchip,rk3528-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xffc30000 0x0 0x4000>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>,
+ <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ resets = <&cru SRST_HRESETN_SDMMC0>;
+ reset-names = "reset";
+ rockchip,use-v2-tuning;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
+ status = "disabled";
+ };
+
+ crypto: crypto@ffc40000 {
+ compatible = "rockchip,crypto-v4";
+ reg = <0x0 0xffc40000 0x0 0x2000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>,
+ <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
+ clock-names = "aclk", "hclk", "sclk", "pka";
+ assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>;
+ assigned-clock-rates = <300000000>, <300000000>;
+ resets = <&cru SRST_RESETN_CORE_CRYPTO>;
+ reset-names = "crypto-rst";
+ status = "disabled";
+ };
+
+ rng: rng@ffc50000 {
+ compatible = "rockchip,rkrng";
+ reg = <0x0 0xffc50000 0x0 0x200>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk SCMI_HCLK_TRNG>;
+ clock-names = "hclk_trng";
+ resets = <&cru SRST_HRESETN_TRNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ otp: otp@ffce0000 {
+ compatible = "rockchip,rk3528-otp";
+ reg = <0x0 0xffce0000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
+ <&cru PCLK_OTPC_NS>;
+ clock-names = "usr", "sbpi", "apb";
+ resets = <&cru SRST_RESETN_USER_OTPC_NS>,
+ <&cru SRST_RESETN_SBPI_OTPC_NS>,
+ <&cru SRST_PRESETN_OTPC_NS>;
+ reset-names = "usr", "sbpi", "apb";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ otp_cpu_version: cpu-version@8 {
+ reg = <0x08 0x1>;
+ bits = <3 3>;
+ };
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+ cpu_leakage: cpu-leakage@1a {
+ reg = <0x1a 0x1>;
+ };
+ log_leakage: log-leakage@1b {
+ reg = <0x1b 0x1>;
+ };
+ gpu_leakage: gpu-leakage@1c {
+ reg = <0x1c 0x1>;
+ };
+ macphy_bgs: macphy-bgs@2d {
+ reg = <0x2d 0x1>;
+ };
+ macphy_txlevel: macphy-txlevel@2e {
+ reg = <0x2e 0x2>;
+ };
+ };
+
+ dmac: dma-controller@ffd60000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xffd60000 0x0 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
+ hwlock: hwspinlock@ffd70000 {
+ compatible = "rockchip,hwspinlock";
+ reg = <0x0 0xffd70000 0x0 0x100>;
+ #hwlock-cells = <1>;
+ status = "disabled";
+ };
+
+ combphy_pu: phy@ffdc0000 {
+ compatible = "rockchip,rk3528-naneng-combphy";
+ reg = <0x0 0xffdc0000 0x0 0x10000>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>;
+ clock-names = "refclk", "apbclk", "pipe_clk";
+ assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&grf>;
+ rockchip,pipe-phy-grf = <&grf>;
+ status = "disabled";
+ };
+
+ usb2phy: usb2-phy@ffdf0000 {
+ compatible = "rockchip,rk3528-usb2phy";
+ reg = <0x0 0xffdf0000 0x0 0x10000>;
+ clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>;
+ clock-names = "phyclk", "apb_pclk";
+ #clock-cells = <0>;
+ rockchip,usbgrf = <&grf>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid",
+ "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+
+ hdmiphy: hdmiphy@ffe00000 {
+ compatible = "rockchip,rk3528-hdmi-phy";
+ reg = <0x0 0xffe00000 0x0 0x10000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ #phy-cells = <0>;
+ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>;
+ clock-names = "sysclk", "refclk";
+ #clock-cells = <0>;
+ clock-output-names = "clk_hdmiphy_pixel_io";
+ status = "disabled";
+ };
+
+ acodec: acodec@ffe10000 {
+ compatible = "rockchip,rk3528-codec";
+ reg = <0x0 0xffe10000 0x0 0x1000>;
+ #sound-dai-cells = <0>;
+ clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>;
+ clock-names = "pclk", "mclk";
+ resets = <&cru SRST_PRESETN_ACODEC>;
+ reset-names = "acodec";
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3528-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff610000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff610000 0x0 0x200>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ffaf0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffaf0000 0x0 0x200>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ffb00000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb00000 0x0 0x200>;
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffb10000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb10000 0x0 0x200>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffb20000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffb20000 0x0 0x200>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3528-pinctrl.dtsi"
diff --git a/u-boot/arch/arm/dts/rk3562-evb.dts b/u-boot/arch/arm/dts/rk3562-evb.dts
new file mode 100644
index 0000000..070e7d8
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3562-evb.dts
@@ -0,0 +1,31 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+/dts-v1/;
+#include "rk3562.dtsi"
+#include "rk3562-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Rockchip RK3562 Evaluation Board";
+ compatible = "rockchip,rk3562-evb", "rockchip,rk3562";
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc0 1>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ u-boot,dm-pre-reloc;
+ status = "okay";
+
+ volumeup-key {
+ u-boot,dm-pre-reloc;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "volume up";
+ press-threshold-microvolt = <9>;
+ };
+ };
+};
diff --git a/u-boot/arch/arm/dts/rk3562-pinctrl.dtsi b/u-boot/arch/arm/dts/rk3562-pinctrl.dtsi
new file mode 100644
index 0000000..d92da5c
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3562-pinctrl.dtsi
@@ -0,0 +1,1872 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ cam {
+ camm0_pins: camm0-pins {
+ rockchip,pins =
+ /* cam_clk0_out_m0 */
+ <3 RK_PB2 2 &pcfg_pull_none>,
+ /* cam_clk1_out_m0 */
+ <3 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ camm1_pins: camm1-pins {
+ rockchip,pins =
+ /* cam_clk0_out_m1 */
+ <4 RK_PB1 3 &pcfg_pull_none>,
+ /* cam_clk1_out_m1 */
+ <4 RK_PB7 3 &pcfg_pull_none>;
+ };
+
+ cam_clk2_out: cam-clk2-out {
+ rockchip,pins =
+ /* cam_clk2_out */
+ <3 RK_PB4 2 &pcfg_pull_none>;
+ };
+ cam_clk3_out: cam-clk3-out {
+ rockchip,pins =
+ /* cam_clk3_out */
+ <3 RK_PB5 2 &pcfg_pull_none>;
+ };
+ };
+
+ can0 {
+ can0m0_pins: can0m0-pins {
+ rockchip,pins =
+ /* can0_rx_m0 */
+ <3 RK_PA1 4 &pcfg_pull_none>,
+ /* can0_tx_m0 */
+ <3 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ can0m1_pins: can0m1-pins {
+ rockchip,pins =
+ /* can0_rx_m1 */
+ <3 RK_PB7 6 &pcfg_pull_none>,
+ /* can0_tx_m1 */
+ <3 RK_PB6 6 &pcfg_pull_none>;
+ };
+
+ can0m2_pins: can0m2-pins {
+ rockchip,pins =
+ /* can0_rx_m2 */
+ <0 RK_PC7 2 &pcfg_pull_none>,
+ /* can0_tx_m2 */
+ <0 RK_PC6 2 &pcfg_pull_none>;
+ };
+ };
+
+ can1 {
+ can1m0_pins: can1m0-pins {
+ rockchip,pins =
+ /* can1_rx_m0 */
+ <1 RK_PB7 4 &pcfg_pull_none>,
+ /* can1_tx_m0 */
+ <1 RK_PC0 5 &pcfg_pull_none>;
+ };
+
+ can1m1_pins: can1m1-pins {
+ rockchip,pins =
+ /* can1_rx_m1 */
+ <0 RK_PC1 4 &pcfg_pull_none>,
+ /* can1_tx_m1 */
+ <0 RK_PC0 4 &pcfg_pull_none>;
+ };
+ };
+
+ clk {
+ clk_32k_in: clk-32k-in {
+ rockchip,pins =
+ /* clk_32k_in */
+ <0 RK_PB0 1 &pcfg_pull_none>;
+ };
+ };
+
+ clk0 {
+ clk0_32k_out: clk0-32k-out {
+ rockchip,pins =
+ /* clk0_32k_out */
+ <0 RK_PB0 2 &pcfg_pull_none>;
+ };
+ };
+
+ clk1 {
+ clk1_32k_out: clk1-32k-out {
+ rockchip,pins =
+ /* clk1_32k_out */
+ <2 RK_PA1 3 &pcfg_pull_none>;
+ };
+ };
+
+ cpu {
+ cpu_pins: cpu-pins {
+ rockchip,pins =
+ /* cpu_avs */
+ <0 RK_PB7 3 &pcfg_pull_none>;
+ };
+ };
+
+ dsm {
+ dsm_pins: dsm-pins {
+ rockchip,pins =
+ /* dsm_aud_ln */
+ <1 RK_PB4 5 &pcfg_pull_none>,
+ /* dsm_aud_lp */
+ <1 RK_PB3 5 &pcfg_pull_none>,
+ /* dsm_aud_rn */
+ <1 RK_PB6 6 &pcfg_pull_none>,
+ /* dsm_aud_rp */
+ <1 RK_PB5 6 &pcfg_pull_none>;
+ };
+ };
+
+ emmc {
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clk */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ emmc_strb: emmc-strb {
+ rockchip,pins =
+ /* emmc_strb */
+ <1 RK_PB2 1 &pcfg_pull_none>;
+ };
+ };
+
+ eth {
+ ethm0_pins: ethm0-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out_m0 */
+ <4 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ ethm1_pins: ethm1-pins {
+ rockchip,pins =
+ /* eth_clk_25m_out_m1 */
+ <2 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ fspi {
+ fspi_pins: fspi-pins {
+ rockchip,pins =
+ /* fspi_clk */
+ <1 RK_PB1 2 &pcfg_pull_none>,
+ /* fspi_d0 */
+ <1 RK_PA0 2 &pcfg_pull_none>,
+ /* fspi_d1 */
+ <1 RK_PA1 2 &pcfg_pull_none>,
+ /* fspi_d2 */
+ <1 RK_PA2 2 &pcfg_pull_none>,
+ /* fspi_d3 */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+
+ fspi_csn0: fspi-csn0 {
+ rockchip,pins =
+ /* fspi_csn0 */
+ <1 RK_PB0 2 &pcfg_pull_none>;
+ };
+ fspi_csn1: fspi-csn1 {
+ rockchip,pins =
+ /* fspi_csn1 */
+ <1 RK_PB2 2 &pcfg_pull_none>;
+ };
+ };
+
+ gpu {
+ gpu_pins: gpu-pins {
+ rockchip,pins =
+ /* gpu_avs */
+ <0 RK_PC0 3 &pcfg_pull_none>;
+ };
+ };
+
+ i2c0 {
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB1 1 &pcfg_pull_none_smt>,
+ /* i2c0_sda */
+ <0 RK_PB2 1 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c1 {
+ i2c1m0_xfer: i2c1m0-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m0 */
+ <0 RK_PB3 1 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m0 */
+ <0 RK_PB4 1 &pcfg_pull_none_smt>;
+ };
+
+ i2c1m1_xfer: i2c1m1-xfer {
+ rockchip,pins =
+ /* i2c1_scl_m1 */
+ <4 RK_PB4 5 &pcfg_pull_none_smt>,
+ /* i2c1_sda_m1 */
+ <4 RK_PB5 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c2 {
+ i2c2m0_xfer: i2c2m0-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m0 */
+ <0 RK_PB5 1 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m0 */
+ <0 RK_PB6 1 &pcfg_pull_none_smt>;
+ };
+
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins =
+ /* i2c2_scl_m1 */
+ <3 RK_PD2 5 &pcfg_pull_none_smt>,
+ /* i2c2_sda_m1 */
+ <3 RK_PD3 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c3 {
+ i2c3m0_xfer: i2c3m0-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m0 */
+ <3 RK_PA0 1 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m0 */
+ <3 RK_PA1 1 &pcfg_pull_none_smt>;
+ };
+
+ i2c3m1_xfer: i2c3m1-xfer {
+ rockchip,pins =
+ /* i2c3_scl_m1 */
+ <4 RK_PA5 5 &pcfg_pull_none_smt>,
+ /* i2c3_sda_m1 */
+ <4 RK_PA6 5 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c4 {
+ i2c4m0_xfer: i2c4m0-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m0 */
+ <3 RK_PB6 5 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m0 */
+ <3 RK_PB7 5 &pcfg_pull_none_smt>;
+ };
+
+ i2c4m1_xfer: i2c4m1-xfer {
+ rockchip,pins =
+ /* i2c4_scl_m1 */
+ <0 RK_PA5 2 &pcfg_pull_none_smt>,
+ /* i2c4_sda_m1 */
+ <0 RK_PA4 2 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2c5 {
+ i2c5m0_xfer: i2c5m0-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m0 */
+ <3 RK_PC2 1 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m0 */
+ <3 RK_PC3 1 &pcfg_pull_none_smt>;
+ };
+
+ i2c5m1_xfer: i2c5m1-xfer {
+ rockchip,pins =
+ /* i2c5_scl_m1 */
+ <1 RK_PC7 4 &pcfg_pull_none_smt>,
+ /* i2c5_sda_m1 */
+ <1 RK_PD0 4 &pcfg_pull_none_smt>;
+ };
+ };
+
+ i2s0 {
+ i2s0m0_lrck: i2s0m0-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m0 */
+ <3 RK_PA4 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_mclk: i2s0m0-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m0 */
+ <3 RK_PA2 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sclk: i2s0m0-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m0 */
+ <3 RK_PA3 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdi0: i2s0m0-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0_m0 */
+ <3 RK_PB1 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdi1: i2s0m0-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1_m0 */
+ <3 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdi2: i2s0m0-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2_m0 */
+ <3 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdi3: i2s0m0-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3_m0 */
+ <3 RK_PA6 2 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdo0: i2s0m0-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0_m0 */
+ <3 RK_PA5 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdo1: i2s0m0-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1_m0 */
+ <3 RK_PA6 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdo2: i2s0m0-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2_m0 */
+ <3 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ i2s0m0_sdo3: i2s0m0-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3_m0 */
+ <3 RK_PB0 1 &pcfg_pull_none>;
+ };
+
+ i2s0m1_lrck: i2s0m1-lrck {
+ rockchip,pins =
+ /* i2s0_lrck_m1 */
+ <1 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_mclk: i2s0m1-mclk {
+ rockchip,pins =
+ /* i2s0_mclk_m1 */
+ <1 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sclk: i2s0m1-sclk {
+ rockchip,pins =
+ /* i2s0_sclk_m1 */
+ <1 RK_PC5 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdi0: i2s0m1-sdi0 {
+ rockchip,pins =
+ /* i2s0_sdi0_m1 */
+ <1 RK_PC1 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdi1: i2s0m1-sdi1 {
+ rockchip,pins =
+ /* i2s0_sdi1_m1 */
+ <1 RK_PC2 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdi2: i2s0m1-sdi2 {
+ rockchip,pins =
+ /* i2s0_sdi2_m1 */
+ <1 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdi3: i2s0m1-sdi3 {
+ rockchip,pins =
+ /* i2s0_sdi3_m1 */
+ <1 RK_PD4 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdo0: i2s0m1-sdo0 {
+ rockchip,pins =
+ /* i2s0_sdo0_m1 */
+ <1 RK_PC3 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdo1: i2s0m1-sdo1 {
+ rockchip,pins =
+ /* i2s0_sdo1_m1 */
+ <1 RK_PD1 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdo2: i2s0m1-sdo2 {
+ rockchip,pins =
+ /* i2s0_sdo2_m1 */
+ <1 RK_PD2 3 &pcfg_pull_none>;
+ };
+
+ i2s0m1_sdo3: i2s0m1-sdo3 {
+ rockchip,pins =
+ /* i2s0_sdo3_m1 */
+ <2 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ i2s1 {
+ i2s1m0_lrck: i2s1m0-lrck {
+ rockchip,pins =
+ /* i2s1_lrck_m0 */
+ <3 RK_PC6 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_mclk: i2s1m0-mclk {
+ rockchip,pins =
+ /* i2s1_mclk_m0 */
+ <3 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sclk: i2s1m0-sclk {
+ rockchip,pins =
+ /* i2s1_sclk_m0 */
+ <3 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdi0: i2s1m0-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0_m0 */
+ <3 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdi1: i2s1m0-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1_m0 */
+ <3 RK_PD1 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdi2: i2s1m0-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2_m0 */
+ <3 RK_PD2 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdi3: i2s1m0-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3_m0 */
+ <3 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdo0: i2s1m0-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0_m0 */
+ <3 RK_PC7 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdo1: i2s1m0-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1_m0 */
+ <4 RK_PB4 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdo2: i2s1m0-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2_m0 */
+ <4 RK_PB5 2 &pcfg_pull_none>;
+ };
+
+ i2s1m0_sdo3: i2s1m0-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3_m0 */
+ <4 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ i2s1m1_lrck: i2s1m1-lrck {
+ rockchip,pins =
+ /* i2s1_lrck_m1 */
+ <3 RK_PB4 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_mclk: i2s1m1-mclk {
+ rockchip,pins =
+ /* i2s1_mclk_m1 */
+ <3 RK_PB2 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sclk: i2s1m1-sclk {
+ rockchip,pins =
+ /* i2s1_sclk_m1 */
+ <3 RK_PB3 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdi0: i2s1m1-sdi0 {
+ rockchip,pins =
+ /* i2s1_sdi0_m1 */
+ <3 RK_PC1 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdi1: i2s1m1-sdi1 {
+ rockchip,pins =
+ /* i2s1_sdi1_m1 */
+ <3 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdi2: i2s1m1-sdi2 {
+ rockchip,pins =
+ /* i2s1_sdi2_m1 */
+ <3 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdi3: i2s1m1-sdi3 {
+ rockchip,pins =
+ /* i2s1_sdi3_m1 */
+ <3 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdo0: i2s1m1-sdo0 {
+ rockchip,pins =
+ /* i2s1_sdo0_m1 */
+ <3 RK_PB5 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdo1: i2s1m1-sdo1 {
+ rockchip,pins =
+ /* i2s1_sdo1_m1 */
+ <3 RK_PB6 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdo2: i2s1m1-sdo2 {
+ rockchip,pins =
+ /* i2s1_sdo2_m1 */
+ <3 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ i2s1m1_sdo3: i2s1m1-sdo3 {
+ rockchip,pins =
+ /* i2s1_sdo3_m1 */
+ <3 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+
+ i2s2 {
+ i2s2m0_lrck: i2s2m0-lrck {
+ rockchip,pins =
+ /* i2s2_lrck_m0 */
+ <1 RK_PD6 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_mclk: i2s2m0-mclk {
+ rockchip,pins =
+ /* i2s2_mclk_m0 */
+ <2 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sclk: i2s2m0-sclk {
+ rockchip,pins =
+ /* i2s2_sclk_m0 */
+ <1 RK_PD5 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdi: i2s2m0-sdi {
+ rockchip,pins =
+ /* i2s2_sdi_m0 */
+ <2 RK_PA0 1 &pcfg_pull_none>;
+ };
+
+ i2s2m0_sdo: i2s2m0-sdo {
+ rockchip,pins =
+ /* i2s2_sdo_m0 */
+ <1 RK_PD7 1 &pcfg_pull_none>;
+ };
+
+ i2s2m1_lrck: i2s2m1-lrck {
+ rockchip,pins =
+ /* i2s2_lrck_m1 */
+ <4 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ i2s2m1_mclk: i2s2m1-mclk {
+ rockchip,pins =
+ /* i2s2_mclk_m1 */
+ <3 RK_PD6 3 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sclk: i2s2m1-sclk {
+ rockchip,pins =
+ /* i2s2_sclk_m1 */
+ <4 RK_PB1 4 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdi: i2s2m1-sdi {
+ rockchip,pins =
+ /* i2s2_sdi_m1 */
+ <3 RK_PD4 4 &pcfg_pull_none>;
+ };
+
+ i2s2m1_sdo: i2s2m1-sdo {
+ rockchip,pins =
+ /* i2s2_sdo_m1 */
+ <3 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ isp {
+ isp_pins: isp-pins {
+ rockchip,pins =
+ /* isp_flash_trigin */
+ <3 RK_PC1 2 &pcfg_pull_none>,
+ /* isp_flash_trigout */
+ <3 RK_PC3 2 &pcfg_pull_none>,
+ /* isp_prelight_trigout */
+ <3 RK_PC2 2 &pcfg_pull_none>;
+ };
+ };
+
+ jtag {
+ jtagm0_pins: jtagm0-pins {
+ rockchip,pins =
+ /* jtag_cpu_mcu_tck_m0 */
+ <0 RK_PD1 2 &pcfg_pull_none>,
+ /* jtag_cpu_mcu_tms_m0 */
+ <0 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ jtagm1_pins: jtagm1-pins {
+ rockchip,pins =
+ /* jtag_cpu_mcu_tck_m1 */
+ <1 RK_PB5 2 &pcfg_pull_none>,
+ /* jtag_cpu_mcu_tms_m1 */
+ <1 RK_PB6 2 &pcfg_pull_none>;
+ };
+ };
+
+ npu {
+ npu_pins: npu-pins {
+ rockchip,pins =
+ /* npu_avs */
+ <0 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ pcie20 {
+ pcie20m0_pins: pcie20m0-pins {
+ rockchip,pins =
+ /* pcie20_clkreqn_m0 */
+ <0 RK_PA6 1 &pcfg_pull_none>,
+ /* pcie20_perstn_m0 */
+ <0 RK_PB5 2 &pcfg_pull_none>,
+ /* pcie20_waken_m0 */
+ <0 RK_PB6 2 &pcfg_pull_none>;
+ };
+
+ pcie20m1_pins: pcie20m1-pins {
+ rockchip,pins =
+ /* pcie20_clkreqn_m1 */
+ <3 RK_PA6 4 &pcfg_pull_none>,
+ /* pcie20_perstn_m1 */
+ <3 RK_PB0 4 &pcfg_pull_none>,
+ /* pcie20_waken_m1 */
+ <3 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ pcie20_buttonrstn: pcie20-buttonrstn {
+ rockchip,pins =
+ /* pcie20_buttonrstn */
+ <0 RK_PB0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pdm {
+ pdmm0_clk0: pdmm0-clk0 {
+ rockchip,pins =
+ /* pdm_clk0_m0 */
+ <3 RK_PA6 3 &pcfg_pull_none>;
+ };
+
+ pdmm0_clk1: pdmm0-clk1 {
+ rockchip,pins =
+ /* pdm_clk1_m0 */
+ <3 RK_PA2 3 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi0: pdmm0-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0_m0 */
+ <3 RK_PB1 2 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi1: pdmm0-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1_m0 */
+ <3 RK_PB0 3 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi2: pdmm0-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2_m0 */
+ <3 RK_PA7 3 &pcfg_pull_none>;
+ };
+
+ pdmm0_sdi3: pdmm0-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3_m0 */
+ <3 RK_PA0 3 &pcfg_pull_none>;
+ };
+
+ pdmm1_clk0: pdmm1-clk0 {
+ rockchip,pins =
+ /* pdm_clk0_m1 */
+ <4 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ pdmm1_clk1: pdmm1-clk1 {
+ rockchip,pins =
+ /* pdm_clk1_m1 */
+ <4 RK_PB1 5 &pcfg_pull_none>;
+ };
+
+ pdmm1_sdi0: pdmm1-sdi0 {
+ rockchip,pins =
+ /* pdm_sdi0_m1 */
+ <4 RK_PA7 4 &pcfg_pull_none>;
+ };
+
+ pdmm1_sdi1: pdmm1-sdi1 {
+ rockchip,pins =
+ /* pdm_sdi1_m1 */
+ <4 RK_PB0 4 &pcfg_pull_none>;
+ };
+
+ pdmm1_sdi2: pdmm1-sdi2 {
+ rockchip,pins =
+ /* pdm_sdi2_m1 */
+ <4 RK_PA5 4 &pcfg_pull_none>;
+ };
+
+ pdmm1_sdi3: pdmm1-sdi3 {
+ rockchip,pins =
+ /* pdm_sdi3_m1 */
+ <4 RK_PA6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins =
+ <0 RK_PA3 0 &pcfg_pull_up>;
+ };
+
+ soc_slppin_gpio: soc-slppin-gpio {
+ rockchip,pins =
+ <0 RK_PA2 0 &pcfg_output_low>;
+ };
+
+ soc_slppin_slp: soc-slppin-slp {
+ rockchip,pins =
+ <0 RK_PA2 1 &pcfg_pull_none>;
+ };
+ };
+
+ pmu {
+ pmu_pins: pmu-pins {
+ rockchip,pins =
+ /* pmu_debug */
+ <0 RK_PA5 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm0 {
+ pwm0m0_pins: pwm0m0-pins {
+ rockchip,pins =
+ /* pwm0_m0 */
+ <0 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ pwm0m1_pins: pwm0m1-pins {
+ rockchip,pins =
+ /* pwm0_m1 */
+ <1 RK_PC5 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm1 {
+ pwm1m0_pins: pwm1m0-pins {
+ rockchip,pins =
+ /* pwm1_m0 */
+ <0 RK_PC4 2 &pcfg_pull_none>;
+ };
+
+ pwm1m1_pins: pwm1m1-pins {
+ rockchip,pins =
+ /* pwm1_m1 */
+ <1 RK_PC6 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm2 {
+ pwm2m0_pins: pwm2m0-pins {
+ rockchip,pins =
+ /* pwm2_m0 */
+ <0 RK_PC5 2 &pcfg_pull_none>;
+ };
+
+ pwm2m1_pins: pwm2m1-pins {
+ rockchip,pins =
+ /* pwm2_m1 */
+ <1 RK_PC7 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm3 {
+ pwm3m0_pins: pwm3m0-pins {
+ rockchip,pins =
+ /* pwm3_m0 */
+ <0 RK_PA7 1 &pcfg_pull_none>;
+ };
+
+ pwm3m1_pins: pwm3m1-pins {
+ rockchip,pins =
+ /* pwm3_m1 */
+ <1 RK_PD0 3 &pcfg_pull_none>;
+ };
+ };
+
+ pwm4 {
+ pwm4m0_pins: pwm4m0-pins {
+ rockchip,pins =
+ /* pwm4_m0 */
+ <0 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ pwm4m1_pins: pwm4m1-pins {
+ rockchip,pins =
+ /* pwm4_m1 */
+ <1 RK_PD1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm5 {
+ pwm5m0_pins: pwm5m0-pins {
+ rockchip,pins =
+ /* pwm5_m0 */
+ <0 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ pwm5m1_pins: pwm5m1-pins {
+ rockchip,pins =
+ /* pwm5_m1 */
+ <1 RK_PD2 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm6 {
+ pwm6m0_pins: pwm6m0-pins {
+ rockchip,pins =
+ /* pwm6_m0 */
+ <0 RK_PC1 2 &pcfg_pull_none>;
+ };
+
+ pwm6m1_pins: pwm6m1-pins {
+ rockchip,pins =
+ /* pwm6_m1 */
+ <1 RK_PD3 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm7 {
+ pwm7m0_pins: pwm7m0-pins {
+ rockchip,pins =
+ /* pwm7_m0 */
+ <0 RK_PC0 2 &pcfg_pull_none>;
+ };
+
+ pwm7m1_pins: pwm7m1-pins {
+ rockchip,pins =
+ /* pwm7_m1 */
+ <1 RK_PD4 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm8 {
+ pwm8m0_pins: pwm8m0-pins {
+ rockchip,pins =
+ /* pwm8_m0 */
+ <3 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ pwm8m1_pins: pwm8m1-pins {
+ rockchip,pins =
+ /* pwm8_m1 */
+ <1 RK_PC1 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm9 {
+ pwm9m0_pins: pwm9m0-pins {
+ rockchip,pins =
+ /* pwm9_m0 */
+ <3 RK_PA5 2 &pcfg_pull_none>;
+ };
+
+ pwm9m1_pins: pwm9m1-pins {
+ rockchip,pins =
+ /* pwm9_m1 */
+ <1 RK_PC2 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm10 {
+ pwm10m0_pins: pwm10m0-pins {
+ rockchip,pins =
+ /* pwm10_m0 */
+ <1 RK_PB5 5 &pcfg_pull_none>;
+ };
+
+ pwm10m1_pins: pwm10m1-pins {
+ rockchip,pins =
+ /* pwm10_m1 */
+ <1 RK_PC3 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm11 {
+ pwm11m0_pins: pwm11m0-pins {
+ rockchip,pins =
+ /* pwm11_m0 */
+ <1 RK_PB6 5 &pcfg_pull_none>;
+ };
+
+ pwm11m1_pins: pwm11m1-pins {
+ rockchip,pins =
+ /* pwm11_m1 */
+ <1 RK_PC4 4 &pcfg_pull_none>;
+ };
+ };
+
+ pwm12 {
+ pwm12m0_pins: pwm12m0-pins {
+ rockchip,pins =
+ /* pwm12_m0 */
+ <4 RK_PA1 4 &pcfg_pull_none>;
+ };
+
+ pwm12m1_pins: pwm12m1-pins {
+ rockchip,pins =
+ /* pwm12_m1 */
+ <3 RK_PB4 5 &pcfg_pull_none>;
+ };
+ };
+
+ pwm13 {
+ pwm13m0_pins: pwm13m0-pins {
+ rockchip,pins =
+ /* pwm13_m0 */
+ <4 RK_PA4 3 &pcfg_pull_none>;
+ };
+
+ pwm13m1_pins: pwm13m1-pins {
+ rockchip,pins =
+ /* pwm13_m1 */
+ <3 RK_PB5 5 &pcfg_pull_none>;
+ };
+ };
+
+ pwm14 {
+ pwm14m0_pins: pwm14m0-pins {
+ rockchip,pins =
+ /* pwm14_m0 */
+ <3 RK_PC5 4 &pcfg_pull_none>;
+ };
+
+ pwm14m1_pins: pwm14m1-pins {
+ rockchip,pins =
+ /* pwm14_m1 */
+ <1 RK_PD7 5 &pcfg_pull_none>;
+ };
+ };
+
+ pwm15 {
+ pwm15m0_pins: pwm15m0-pins {
+ rockchip,pins =
+ /* pwm15_m0 */
+ <3 RK_PC6 4 &pcfg_pull_none>;
+ };
+
+ pwm15m1_pins: pwm15m1-pins {
+ rockchip,pins =
+ /* pwm15_m1 */
+ <2 RK_PA0 5 &pcfg_pull_none>;
+ };
+ };
+
+ pwr {
+ pwr_pins: pwr-pins {
+ rockchip,pins =
+ /* pwr_ctrl0 */
+ <0 RK_PA2 1 &pcfg_pull_none>,
+ /* pwr_ctrl1 */
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ };
+
+ ref {
+ ref_pins: ref-pins {
+ rockchip,pins =
+ /* ref_clk_out */
+ <0 RK_PA0 1 &pcfg_pull_none>;
+ };
+ };
+
+ rgmii {
+ rgmiim0_miim: rgmiim0-miim {
+ rockchip,pins =
+ /* rgmii_mdc_m0 */
+ <4 RK_PB2 2 &pcfg_pull_none>,
+ /* rgmii_mdio_m0 */
+ <4 RK_PB3 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_rx_er: rgmiim0-rx_er {
+ rockchip,pins =
+ /* rgmii_rxer_m0 */
+ <4 RK_PB0 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_rx_bus2: rgmiim0-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0_m0 */
+ <4 RK_PA5 2 &pcfg_pull_none>,
+ /* rgmii_rxd1_m0 */
+ <4 RK_PA6 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_m0 */
+ <4 RK_PA7 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_tx_bus2: rgmiim0-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0_m0 */
+ <4 RK_PA2 2 &pcfg_pull_none>,
+ /* rgmii_txd1_m0 */
+ <4 RK_PA3 2 &pcfg_pull_none>,
+ /* rgmii_txen_m0 */
+ <4 RK_PA4 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_rgmii_clk: rgmiim0-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk_m0 */
+ <4 RK_PA1 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m0 */
+ <3 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_rgmii_bus: rgmiim0-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2_m0 */
+ <3 RK_PD7 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m0 */
+ <4 RK_PA0 2 &pcfg_pull_none>,
+ /* rgmii_txd2_m0 */
+ <3 RK_PD4 2 &pcfg_pull_none>,
+ /* rgmii_txd3_m0 */
+ <3 RK_PD5 2 &pcfg_pull_none>;
+ };
+
+ rgmiim0_clk: rgmiim0-clk {
+ rockchip,pins =
+ /* rgmiim0_clk */
+ <4 RK_PB7 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_miim: rgmiim1-miim {
+ rockchip,pins =
+ /* rgmii_mdc_m1 */
+ <1 RK_PC7 2 &pcfg_pull_none>,
+ /* rgmii_mdio_m1 */
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_rx_er: rgmiim1-rx_er {
+ rockchip,pins =
+ /* rgmii_rxer_m1 */
+ <2 RK_PA0 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_rx_bus2: rgmiim1-rx_bus2 {
+ rockchip,pins =
+ /* rgmii_rxd0_m1 */
+ <1 RK_PD4 2 &pcfg_pull_none>,
+ /* rgmii_rxd1_m1 */
+ <1 RK_PD7 2 &pcfg_pull_none>,
+ /* rgmii_rxdv_m1 */
+ <1 RK_PD6 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_tx_bus2: rgmiim1-tx_bus2 {
+ rockchip,pins =
+ /* rgmii_txd0_m1 */
+ <1 RK_PD1 2 &pcfg_pull_none>,
+ /* rgmii_txd1_m1 */
+ <1 RK_PD2 2 &pcfg_pull_none>,
+ /* rgmii_txen_m1 */
+ <1 RK_PD3 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_rgmii_clk: rgmiim1-rgmii_clk {
+ rockchip,pins =
+ /* rgmii_rxclk_m1 */
+ <1 RK_PC6 2 &pcfg_pull_none>,
+ /* rgmii_txclk_m1 */
+ <1 RK_PC3 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_rgmii_bus: rgmiim1-rgmii_bus {
+ rockchip,pins =
+ /* rgmii_rxd2_m1 */
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ /* rgmii_rxd3_m1 */
+ <1 RK_PC5 2 &pcfg_pull_none>,
+ /* rgmii_txd2_m1 */
+ <1 RK_PC1 2 &pcfg_pull_none>,
+ /* rgmii_txd3_m1 */
+ <1 RK_PC2 2 &pcfg_pull_none>;
+ };
+
+ rgmiim1_clk: rgmiim1-clk {
+ rockchip,pins =
+ /* rgmiim1_clk */
+ <1 RK_PD5 2 &pcfg_pull_none>;
+ };
+ };
+
+ rmii {
+ rmii_pins: rmii-pins {
+ rockchip,pins =
+ /* rmii_clk */
+ <1 RK_PD5 5 &pcfg_pull_none>,
+ /* rmii_mdc */
+ <1 RK_PC7 5 &pcfg_pull_none>,
+ /* rmii_mdio */
+ <1 RK_PD0 5 &pcfg_pull_none>,
+ /* rmii_rxd0 */
+ <1 RK_PD4 5 &pcfg_pull_none>,
+ /* rmii_rxd1 */
+ <1 RK_PD7 6 &pcfg_pull_none>,
+ /* rmii_rxdv_crs */
+ <1 RK_PD6 5 &pcfg_pull_none>,
+ /* rmii_rxer */
+ <2 RK_PA0 6 &pcfg_pull_none>,
+ /* rmii_txd0 */
+ <1 RK_PD1 5 &pcfg_pull_none>,
+ /* rmii_txd1 */
+ <1 RK_PD2 5 &pcfg_pull_none>,
+ /* rmii_txen */
+ <1 RK_PD3 5 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc0_pins: sdmmc0-pins {
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PC0 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ /* sdmmc0_detn */
+ <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ sdmmc0_pwren: sdmmc0-pwren {
+ rockchip,pins =
+ /* sdmmc0_pwren */
+ <0 RK_PA5 1 &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc1 {
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PC1 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PC2 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PC3 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>;
+ };
+
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ /* sdmmc1_detn */
+ <1 RK_PD0 1 &pcfg_pull_up>;
+ };
+
+ sdmmc1_pwren: sdmmc1-pwren {
+ rockchip,pins =
+ /* sdmmc1_pwren */
+ <1 RK_PC7 1 &pcfg_pull_none>;
+ };
+ };
+
+ spdif {
+ spdifm0_pins: spdifm0-pins {
+ rockchip,pins =
+ /* spdif_tx_m0 */
+ <3 RK_PA1 3 &pcfg_pull_none>;
+ };
+
+ spdifm1_pins: spdifm1-pins {
+ rockchip,pins =
+ /* spdif_tx_m1 */
+ <0 RK_PB7 4 &pcfg_pull_none>;
+ };
+
+ spdifm2_pins: spdifm2-pins {
+ rockchip,pins =
+ /* spdif_tx_m2 */
+ <1 RK_PB7 2 &pcfg_pull_none>;
+ };
+ };
+
+ spi0 {
+ spi0m0_pins: spi0m0-pins {
+ rockchip,pins =
+ /* spi0_clk_m0 */
+ <0 RK_PC3 3 &pcfg_pull_none>,
+ /* spi0_miso_m0 */
+ <0 RK_PC5 3 &pcfg_pull_none>,
+ /* spi0_mosi_m0 */
+ <0 RK_PC4 3 &pcfg_pull_none>;
+ };
+
+ spi0m0_csn0: spi0m0-csn0 {
+ rockchip,pins =
+ /* spi0m0_csn0 */
+ <0 RK_PC2 3 &pcfg_pull_none>;
+ };
+ spi0m0_csn1: spi0m0-csn1 {
+ rockchip,pins =
+ /* spi0m0_csn1 */
+ <0 RK_PB7 1 &pcfg_pull_none>;
+ };
+
+ spi0m1_pins: spi0m1-pins {
+ rockchip,pins =
+ /* spi0_clk_m1 */
+ <3 RK_PB5 4 &pcfg_pull_none>,
+ /* spi0_miso_m1 */
+ <3 RK_PC0 4 &pcfg_pull_none>,
+ /* spi0_mosi_m1 */
+ <3 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ spi0m1_csn0: spi0m1-csn0 {
+ rockchip,pins =
+ /* spi0m1_csn0 */
+ <3 RK_PB7 4 &pcfg_pull_none>;
+ };
+ spi0m1_csn1: spi0m1-csn1 {
+ rockchip,pins =
+ /* spi0m1_csn1 */
+ <3 RK_PB6 4 &pcfg_pull_none>;
+ };
+ };
+
+ spi1 {
+ spi1m0_pins: spi1m0-pins {
+ rockchip,pins =
+ /* spi1_clk_m0 */
+ <3 RK_PD6 4 &pcfg_pull_none>,
+ /* spi1_miso_m0 */
+ <4 RK_PA3 4 &pcfg_pull_none>,
+ /* spi1_mosi_m0 */
+ <4 RK_PA2 4 &pcfg_pull_none>;
+ };
+
+ spi1m0_csn0: spi1m0-csn0 {
+ rockchip,pins =
+ /* spi1m0_csn0 */
+ <3 RK_PD7 4 &pcfg_pull_none>;
+ };
+ spi1m0_csn1: spi1m0-csn1 {
+ rockchip,pins =
+ /* spi1m0_csn1 */
+ <4 RK_PA0 4 &pcfg_pull_none>;
+ };
+
+ spi1m1_pins: spi1m1-pins {
+ rockchip,pins =
+ /* spi1_clk_m1 */
+ <1 RK_PC0 4 &pcfg_pull_none>,
+ /* spi1_miso_m1 */
+ <1 RK_PB4 4 &pcfg_pull_none>,
+ /* spi1_mosi_m1 */
+ <1 RK_PB3 4 &pcfg_pull_none>;
+ };
+
+ spi1m1_csn0: spi1m1-csn0 {
+ rockchip,pins =
+ /* spi1m1_csn0 */
+ <1 RK_PB6 4 &pcfg_pull_none>;
+ };
+ spi1m1_csn1: spi1m1-csn1 {
+ rockchip,pins =
+ /* spi1m1_csn1 */
+ <1 RK_PB5 4 &pcfg_pull_none>;
+ };
+ };
+
+ spi2 {
+ spi2m0_pins: spi2m0-pins {
+ rockchip,pins =
+ /* spi2_clk_m0 */
+ <4 RK_PB6 4 &pcfg_pull_none>,
+ /* spi2_miso_m0 */
+ <3 RK_PD2 4 &pcfg_pull_none>,
+ /* spi2_mosi_m0 */
+ <3 RK_PD3 4 &pcfg_pull_none>;
+ };
+
+ spi2m0_csn0: spi2m0-csn0 {
+ rockchip,pins =
+ /* spi2m0_csn0 */
+ <4 RK_PB5 4 &pcfg_pull_none>;
+ };
+ spi2m0_csn1: spi2m0-csn1 {
+ rockchip,pins =
+ /* spi2m0_csn1 */
+ <4 RK_PB4 4 &pcfg_pull_none>;
+ };
+
+ spi2m1_pins: spi2m1-pins {
+ rockchip,pins =
+ /* spi2_clk_m1 */
+ <2 RK_PA1 4 &pcfg_pull_none>,
+ /* spi2_miso_m1 */
+ <2 RK_PA0 4 &pcfg_pull_none>,
+ /* spi2_mosi_m1 */
+ <1 RK_PD7 4 &pcfg_pull_none>;
+ };
+
+ spi2m1_csn0: spi2m1-csn0 {
+ rockchip,pins =
+ /* spi2m1_csn0 */
+ <1 RK_PD6 4 &pcfg_pull_none>;
+ };
+ spi2m1_csn1: spi2m1-csn1 {
+ rockchip,pins =
+ /* spi2m1_csn1 */
+ <1 RK_PD5 4 &pcfg_pull_none>;
+ };
+ };
+
+ tsadc {
+ tsadcm0_pins: tsadcm0-pins {
+ rockchip,pins =
+ /* tsadc_shut_m0 */
+ <0 RK_PA1 1 &pcfg_pull_none>;
+ };
+
+ tsadcm1_pins: tsadcm1-pins {
+ rockchip,pins =
+ /* tsadc_shut_m1 */
+ <0 RK_PA2 2 &pcfg_pull_none>;
+ };
+
+ tsadc_shut_org: tsadc-shut-org {
+ rockchip,pins =
+ /* tsadc_shut_org */
+ <0 RK_PA1 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0m0_xfer: uart0m0-xfer {
+ rockchip,pins =
+ /* uart0_rx_m0 */
+ <0 RK_PD0 1 &pcfg_pull_up>,
+ /* uart0_tx_m0 */
+ <0 RK_PD1 1 &pcfg_pull_up>;
+ };
+
+ uart0m1_xfer: uart0m1-xfer {
+ rockchip,pins =
+ /* uart0_rx_m1 */
+ <1 RK_PB3 2 &pcfg_pull_up>,
+ /* uart0_tx_m1 */
+ <1 RK_PB4 2 &pcfg_pull_up>;
+ };
+ };
+
+ uart1 {
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <1 RK_PD1 1 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <1 RK_PD2 1 &pcfg_pull_up>;
+ };
+
+ uart1m0_ctsn: uart1m0-ctsn {
+ rockchip,pins =
+ /* uart1m0_ctsn */
+ <1 RK_PD4 1 &pcfg_pull_none>;
+ };
+ uart1m0_rtsn: uart1m0-rtsn {
+ rockchip,pins =
+ /* uart1m0_rtsn */
+ <1 RK_PD3 1 &pcfg_pull_none>;
+ };
+
+ uart1m1_xfer: uart1m1-xfer {
+ rockchip,pins =
+ /* uart1_rx_m1 */
+ <4 RK_PA6 3 &pcfg_pull_up>,
+ /* uart1_tx_m1 */
+ <4 RK_PA5 3 &pcfg_pull_up>;
+ };
+
+ uart1m1_ctsn: uart1m1-ctsn {
+ rockchip,pins =
+ /* uart1m1_ctsn */
+ <4 RK_PB0 3 &pcfg_pull_none>;
+ };
+ uart1m1_rtsn: uart1m1-rtsn {
+ rockchip,pins =
+ /* uart1m1_rtsn */
+ <4 RK_PA7 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart2 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins =
+ /* uart2_rx_m0 */
+ <0 RK_PC1 1 &pcfg_pull_up>,
+ /* uart2_tx_m0 */
+ <0 RK_PC0 1 &pcfg_pull_up>;
+ };
+
+ uart2m0_ctsn: uart2m0-ctsn {
+ rockchip,pins =
+ /* uart2m0_ctsn */
+ <0 RK_PC2 1 &pcfg_pull_none>;
+ };
+ uart2m0_rtsn: uart2m0-rtsn {
+ rockchip,pins =
+ /* uart2m0_rtsn */
+ <0 RK_PC3 1 &pcfg_pull_none>;
+ };
+
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA1 2 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA0 2 &pcfg_pull_up>;
+ };
+
+ uart2m1_ctsn: uart2m1-ctsn {
+ rockchip,pins =
+ /* uart2m1_ctsn */
+ <3 RK_PA2 2 &pcfg_pull_none>;
+ };
+ uart2m1_rtsn: uart2m1-rtsn {
+ rockchip,pins =
+ /* uart2m1_rtsn */
+ <3 RK_PA3 2 &pcfg_pull_none>;
+ };
+ };
+
+ uart3 {
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <4 RK_PB5 6 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <4 RK_PB4 6 &pcfg_pull_up>;
+ };
+
+ uart3m0_ctsn: uart3m0-ctsn {
+ rockchip,pins =
+ /* uart3m0_ctsn */
+ <4 RK_PB6 3 &pcfg_pull_none>;
+ };
+ uart3m0_rtsn: uart3m0-rtsn {
+ rockchip,pins =
+ /* uart3m0_rtsn */
+ <3 RK_PD1 4 &pcfg_pull_none>;
+ };
+
+ uart3m1_xfer: uart3m1-xfer {
+ rockchip,pins =
+ /* uart3_rx_m1 */
+ <3 RK_PC0 3 &pcfg_pull_up>,
+ /* uart3_tx_m1 */
+ <3 RK_PB7 3 &pcfg_pull_up>;
+ };
+
+ uart3m1_ctsn: uart3m1-ctsn {
+ rockchip,pins =
+ /* uart3m1_ctsn */
+ <3 RK_PB6 3 &pcfg_pull_none>;
+ };
+ uart3m1_rtsn: uart3m1-rtsn {
+ rockchip,pins =
+ /* uart3m1_rtsn */
+ <3 RK_PC1 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart4 {
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PD1 3 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PD0 3 &pcfg_pull_up>;
+ };
+
+ uart4m0_ctsn: uart4m0-ctsn {
+ rockchip,pins =
+ /* uart4m0_ctsn */
+ <3 RK_PC5 3 &pcfg_pull_none>;
+ };
+ uart4m0_rtsn: uart4m0-rtsn {
+ rockchip,pins =
+ /* uart4m0_rtsn */
+ <3 RK_PC6 3 &pcfg_pull_none>;
+ };
+
+ uart4m1_xfer: uart4m1-xfer {
+ rockchip,pins =
+ /* uart4_rx_m1 */
+ <1 RK_PD5 3 &pcfg_pull_up>,
+ /* uart4_tx_m1 */
+ <1 RK_PD6 3 &pcfg_pull_up>;
+ };
+
+ uart4m1_ctsn: uart4m1-ctsn {
+ rockchip,pins =
+ /* uart4m1_ctsn */
+ <2 RK_PA0 3 &pcfg_pull_none>;
+ };
+ uart4m1_rtsn: uart4m1-rtsn {
+ rockchip,pins =
+ /* uart4m1_rtsn */
+ <1 RK_PD7 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart5 {
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <1 RK_PB7 3 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <1 RK_PC0 3 &pcfg_pull_up>;
+ };
+
+ uart5m0_ctsn: uart5m0-ctsn {
+ rockchip,pins =
+ /* uart5m0_ctsn */
+ <1 RK_PB5 3 &pcfg_pull_none>;
+ };
+ uart5m0_rtsn: uart5m0-rtsn {
+ rockchip,pins =
+ /* uart5m0_rtsn */
+ <1 RK_PB6 3 &pcfg_pull_none>;
+ };
+
+ uart5m1_xfer: uart5m1-xfer {
+ rockchip,pins =
+ /* uart5_rx_m1 */
+ <3 RK_PA7 5 &pcfg_pull_up>,
+ /* uart5_tx_m1 */
+ <3 RK_PA6 5 &pcfg_pull_up>;
+ };
+
+ uart5m1_ctsn: uart5m1-ctsn {
+ rockchip,pins =
+ /* uart5m1_ctsn */
+ <3 RK_PA0 5 &pcfg_pull_none>;
+ };
+ uart5m1_rtsn: uart5m1-rtsn {
+ rockchip,pins =
+ /* uart5m1_rtsn */
+ <3 RK_PA1 5 &pcfg_pull_none>;
+ };
+ };
+
+ uart6 {
+ uart6m0_xfer: uart6m0-xfer {
+ rockchip,pins =
+ /* uart6_rx_m0 */
+ <0 RK_PC7 1 &pcfg_pull_up>,
+ /* uart6_tx_m0 */
+ <0 RK_PC6 1 &pcfg_pull_up>;
+ };
+
+ uart6m0_ctsn: uart6m0-ctsn {
+ rockchip,pins =
+ /* uart6m0_ctsn */
+ <0 RK_PC4 1 &pcfg_pull_none>;
+ };
+ uart6m0_rtsn: uart6m0-rtsn {
+ rockchip,pins =
+ /* uart6m0_rtsn */
+ <0 RK_PC5 1 &pcfg_pull_none>;
+ };
+
+ uart6m1_xfer: uart6m1-xfer {
+ rockchip,pins =
+ /* uart6_rx_m1 */
+ <4 RK_PB0 5 &pcfg_pull_up>,
+ /* uart6_tx_m1 */
+ <4 RK_PA7 5 &pcfg_pull_up>;
+ };
+
+ uart6m1_ctsn: uart6m1-ctsn {
+ rockchip,pins =
+ /* uart6m1_ctsn */
+ <4 RK_PA2 3 &pcfg_pull_none>;
+ };
+ uart6m1_rtsn: uart6m1-rtsn {
+ rockchip,pins =
+ /* uart6m1_rtsn */
+ <4 RK_PA3 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart7 {
+ uart7m0_xfer: uart7m0-xfer {
+ rockchip,pins =
+ /* uart7_rx_m0 */
+ <3 RK_PC7 3 &pcfg_pull_up>,
+ /* uart7_tx_m0 */
+ <3 RK_PC4 3 &pcfg_pull_up>;
+ };
+
+ uart7m0_ctsn: uart7m0-ctsn {
+ rockchip,pins =
+ /* uart7m0_ctsn */
+ <3 RK_PD2 3 &pcfg_pull_none>;
+ };
+ uart7m0_rtsn: uart7m0-rtsn {
+ rockchip,pins =
+ /* uart7m0_rtsn */
+ <3 RK_PD3 3 &pcfg_pull_none>;
+ };
+
+ uart7m1_xfer: uart7m1-xfer {
+ rockchip,pins =
+ /* uart7_rx_m1 */
+ <1 RK_PB3 3 &pcfg_pull_up>,
+ /* uart7_tx_m1 */
+ <1 RK_PB4 3 &pcfg_pull_up>;
+ };
+ };
+
+ uart8 {
+ uart8m0_xfer: uart8m0-xfer {
+ rockchip,pins =
+ /* uart8_rx_m0 */
+ <3 RK_PB3 3 &pcfg_pull_up>,
+ /* uart8_tx_m0 */
+ <3 RK_PB2 3 &pcfg_pull_up>;
+ };
+
+ uart8m0_ctsn: uart8m0-ctsn {
+ rockchip,pins =
+ /* uart8m0_ctsn */
+ <3 RK_PB4 3 &pcfg_pull_none>;
+ };
+ uart8m0_rtsn: uart8m0-rtsn {
+ rockchip,pins =
+ /* uart8m0_rtsn */
+ <3 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ uart8m1_xfer: uart8m1-xfer {
+ rockchip,pins =
+ /* uart8_rx_m1 */
+ <3 RK_PD5 3 &pcfg_pull_up>,
+ /* uart8_tx_m1 */
+ <3 RK_PD4 3 &pcfg_pull_up>;
+ };
+
+ uart8m1_ctsn: uart8m1-ctsn {
+ rockchip,pins =
+ /* uart8m1_ctsn */
+ <3 RK_PD7 3 &pcfg_pull_none>;
+ };
+ uart8m1_rtsn: uart8m1-rtsn {
+ rockchip,pins =
+ /* uart8m1_rtsn */
+ <4 RK_PA0 3 &pcfg_pull_none>;
+ };
+ };
+
+ uart9 {
+ uart9m0_xfer: uart9m0-xfer {
+ rockchip,pins =
+ /* uart9_rx_m0 */
+ <4 RK_PB3 3 &pcfg_pull_up>,
+ /* uart9_tx_m0 */
+ <4 RK_PB2 3 &pcfg_pull_up>;
+ };
+
+ uart9m0_ctsn: uart9m0-ctsn {
+ rockchip,pins =
+ /* uart9m0_ctsn */
+ <4 RK_PB4 3 &pcfg_pull_none>;
+ };
+ uart9m0_rtsn: uart9m0-rtsn {
+ rockchip,pins =
+ /* uart9m0_rtsn */
+ <4 RK_PB5 3 &pcfg_pull_none>;
+ };
+
+ uart9m1_xfer: uart9m1-xfer {
+ rockchip,pins =
+ /* uart9_rx_m1 */
+ <3 RK_PC3 3 &pcfg_pull_up>,
+ /* uart9_tx_m1 */
+ <3 RK_PC2 3 &pcfg_pull_up>;
+ };
+ };
+
+ vo {
+ vo_pins: vo-pins {
+ rockchip,pins =
+ /* vo_lcdc_clk */
+ <4 RK_PB7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d0 */
+ <4 RK_PA4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d1 */
+ <4 RK_PA5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d2 */
+ <4 RK_PB2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d3 */
+ <3 RK_PC4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d4 */
+ <3 RK_PC5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d5 */
+ <3 RK_PC6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d6 */
+ <3 RK_PC7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d7 */
+ <3 RK_PD0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d8 */
+ <4 RK_PA6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d9 */
+ <4 RK_PA7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d10 */
+ <3 RK_PD1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d11 */
+ <3 RK_PD2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d12 */
+ <3 RK_PD3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d13 */
+ <3 RK_PD4 1 &pcfg_pull_none>,
+ /* vo_lcdc_d14 */
+ <3 RK_PD5 1 &pcfg_pull_none>,
+ /* vo_lcdc_d15 */
+ <3 RK_PD6 1 &pcfg_pull_none>,
+ /* vo_lcdc_d16 */
+ <4 RK_PB0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d17 */
+ <4 RK_PB1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d18 */
+ <4 RK_PB3 1 &pcfg_pull_none>,
+ /* vo_lcdc_d19 */
+ <3 RK_PD7 1 &pcfg_pull_none>,
+ /* vo_lcdc_d20 */
+ <4 RK_PA0 1 &pcfg_pull_none>,
+ /* vo_lcdc_d21 */
+ <4 RK_PA1 1 &pcfg_pull_none>,
+ /* vo_lcdc_d22 */
+ <4 RK_PA2 1 &pcfg_pull_none>,
+ /* vo_lcdc_d23 */
+ <4 RK_PA3 1 &pcfg_pull_none>,
+ /* vo_lcdc_den */
+ <4 RK_PB6 1 &pcfg_pull_none>,
+ /* vo_lcdc_hsync */
+ <4 RK_PB4 1 &pcfg_pull_none>,
+ /* vo_lcdc_vsync */
+ <4 RK_PB5 1 &pcfg_pull_none>;
+ };
+ };
+};
diff --git a/u-boot/arch/arm/dts/rk3562-u-boot.dtsi b/u-boot/arch/arm/dts/rk3562-u-boot.dtsi
new file mode 100644
index 0000000..98c2e70
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3562-u-boot.dtsi
@@ -0,0 +1,203 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = &sdmmc0, &sdhci, &spi_nand, &spi_nor;
+ };
+
+ secure-otp@ff920000 {
+ compatible = "rockchip,rk3562-secure-otp";
+ reg = <0x0 0xff920000 0x0 0x4000>;
+ secure_conf = <0xff020034>;
+ mask_addr = <0x0>;
+ cru_rst_addr = <0xff130438>;
+ u-boot,dm-spl;
+ status = "okay";
+ };
+};
+
+&sys_grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&ioc_grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&pmu_grf {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&usbphy_grf {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&firmware {
+ u-boot,dm-spl;
+};
+
+&scmi {
+ u-boot,dm-spl;
+};
+
+&scmi_clk {
+ u-boot,dm-spl;
+};
+
+&scmi_shmem {
+ u-boot,dm-spl;
+};
+
+&cru {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&crypto {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&rng {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&uart2 {
+ clock-frequency = <24000000>;
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&saradc0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&psci {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ u-boot,dm-spl;
+ /delete-property/ pinctrl-names;
+ /delete-property/ pinctrl-0;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
+ fixed-emmc-driver-type = <1>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ u-boot,dm-spl;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
+ status = "okay";
+};
+
+&sdmmc0_pins {
+ u-boot,dm-spl;
+};
+
+&sdmmc0_bus4 {
+ u-boot,dm-spl;
+};
+
+&sdmmc0_clk {
+ u-boot,dm-spl;
+};
+
+&sdmmc0_cmd {
+ u-boot,dm-spl;
+};
+
+&sdmmc0_det {
+ u-boot,dm-spl;
+};
+
+&sfc {
+ u-boot,dm-spl;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi_nand: flash@0 {
+ u-boot,dm-spl;
+ compatible = "spi-nand";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <80000000>;
+ };
+
+ spi_nor: flash@1 {
+ u-boot,dm-spl;
+ compatible = "jedec,spi-nor";
+ label = "sfc_nor";
+ reg = <0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <80000000>;
+ };
+};
+
+&pinctrl {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&gpio0 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio3 {
+ u-boot,dm-pre-reloc;
+};
+
+&gpio4 {
+ u-boot,dm-pre-reloc;
+};
+
+&pcfg_pull_up_drv_level_2 {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&pcfg_pull_up {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
+&u2phy {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&u2phy_otg {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/u-boot/arch/arm/dts/rk3562.dtsi b/u-boot/arch/arm/dts/rk3562.dtsi
new file mode 100644
index 0000000..af9d278
--- /dev/null
+++ b/u-boot/arch/arm/dts/rk3562.dtsi
@@ -0,0 +1,2325 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <dt-bindings/clock/rk3562-cru.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/power/rk3562-power.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/soc/rockchip-system-status.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/ {
+ compatible = "rockchip,rk3562";
+
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ csi2dphy0 = &csi2_dphy0;
+ csi2dphy1 = &csi2_dphy1;
+ csi2dphy2 = &csi2_dphy2;
+ csi2dphy3 = &csi2_dphy3;
+ csi2dphy4 = &csi2_dphy4;
+ csi2dphy5 = &csi2_dphy5;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ rkcif_mipi_lvds0= &rkcif_mipi_lvds;
+ rkcif_mipi_lvds1= &rkcif_mipi_lvds1;
+ rkcif_mipi_lvds2= &rkcif_mipi_lvds2;
+ rkcif_mipi_lvds3= &rkcif_mipi_lvds3;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ serial6 = &uart6;
+ serial7 = &uart7;
+ serial8 = &uart8;
+ serial9 = &uart9;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &sfc;
+ };
+
+ clocks {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ xin32k: xin32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "xin32k";
+ };
+
+ xin24m: xin24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ };
+
+ aclk_vepu: aclk_vepu@ff100324 {
+ compatible = "rockchip,rk3562-clock-gate-link";
+ reg = <0 0xff100324 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_ISP>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vdpu: aclk_vdpu@ff100328 {
+ compatible = "rockchip,rk3562-clock-gate-link";
+ reg = <0 0xff100328 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_TOP_VIO>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vi_isp: aclk_vi_isp@ff10032c {
+ compatible = "rockchip,rk3562-clock-gate-link";
+ reg = <0 0xff10032c 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_TOP_VIO>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_vo: aclk_vo@ff100334 {
+ compatible = "rockchip,rk3562-clock-gate-link";
+ reg = <0 0xff100334 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_TOP_VIO>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+
+ aclk_rga_jdec: aclk_rga_jdec@ff100338 {
+ compatible = "rockchip,rk3562-clock-gate-link";
+ reg = <0 0xff100338 0 0x10>;
+ clock-names = "link";
+ clocks = <&cru ACLK_VOP>;
+ #power-domain-cells = <1>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: cpu0-opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ nvmem-cells = <&cpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ opp-408000000 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ clock-latency-ns = <40000>;
+ opp-suspend;
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-816000000 {
+ opp-hz = /bits/ 64 <816000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1008000000 {
+ opp-hz = /bits/ 64 <1008000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <900000 900000 1100000>;
+ clock-latency-ns = <40000>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ cpuinfo {
+ compatible = "rockchip,cpuinfo";
+ nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>;
+ nvmem-cell-names = "id", "cpu-version", "cpu-code";
+ };
+
+ /* dphy0 full mode */
+ csi2_dphy0: csi2-dphy0 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ /* dphy0 split mode 01 */
+ csi2_dphy1: csi2-dphy1 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ /* dphy0 split mode 23 */
+ csi2_dphy2: csi2-dphy2 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy0_hw>;
+ status = "disabled";
+ };
+
+ /* dphy1 full mode */
+ csi2_dphy3: csi2-dphy3 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ /* dphy1 split mode 01 */
+ csi2_dphy4: csi2-dphy4 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ /* dphy1 split mode 23 */
+ csi2_dphy5: csi2-dphy5 {
+ compatible = "rockchip,rk3562-csi2-dphy";
+ rockchip,hw = <&csi2_dphy1_hw>;
+ status = "disabled";
+ };
+
+ display_subsystem: display-subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ status = "disabled";
+ };
+
+ firmware: firmware {
+ scmi: scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&scmi_shmem>;
+ arm,smc-id = <0x82000010>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+ };
+ };
+
+ mpp_srv: mpp-srv {
+ compatible = "rockchip,mpp-service";
+ rockchip,taskqueue-count = <3>;
+ rockchip,resetgroup-count = <3>;
+ status = "disabled";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ rkcif_mipi_lvds: rkcif-mipi-lvds {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1: rkcif-mipi-lvds1 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds1>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2: rkcif-mipi-lvds2 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds2>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3: rkcif-mipi-lvds3 {
+ compatible = "rockchip,rkcif-mipi-lvds";
+ rockchip,hw = <&rkcif>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 {
+ compatible = "rockchip,rkcif-sditf";
+ rockchip,cif = <&rkcif_mipi_lvds3>;
+ status = "disabled";
+ };
+
+ rkisp_vir0: rkisp-vir0 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp>;
+ status = "disabled";
+ };
+
+ rkisp_vir1: rkisp-vir1 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp>;
+ status = "disabled";
+ };
+
+ rkisp_vir2: rkisp-vir2 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp>;
+ status = "disabled";
+ };
+
+ rkisp_vir3: rkisp-vir3 {
+ compatible = "rockchip,rkisp-vir";
+ rockchip,hw = <&rkisp>;
+ status = "disabled";
+ };
+
+ thermal_zones: thermal-zones {
+ soc_thermal: soc-thermal {
+ polling-delay-passive = <20>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&tsadc 0>;
+ trips {
+ soc_crit: soc-crit {
+ /* millicelsius */
+ temperature = <115000>;
+ /* millicelsius */
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ scmi_shmem: scmi-shmem@10f000 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x0010f000 0x0 0x100>;
+ };
+
+ usbdrd30: usbdrd {
+ compatible = "rockchip,rk3562-dwc3", "rockchip,rk3399-dwc3";
+ clocks = <&cru CLK_USB3OTG_REF>, <&cru CLK_USB3OTG_SUSPEND>,
+ <&cru ACLK_USB3OTG>, <&cru PCLK_PHP>;
+ clock-names = "ref", "suspend", "bus", "pipe_clk";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usbdrd_dwc3: usb@fe500000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xfe500000 0x0 0x400000>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ dr_mode = "otg";
+ phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>;
+ phy-names = "usb2-phy", "usb3-phy";
+ phy_type = "utmi_wide";
+ power-domains = <&power RK3562_PD_PHP>;
+ resets = <&cru SRST_USB3OTG>;
+ reset-names = "usb3-otg";
+ snps,dis_enblslpm_quirk;
+ snps,dis-u1-entry-quirk;
+ snps,dis-u2-entry-quirk;
+ snps,dis-u2-freeclk-exists-quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ snps,dis_rxdet_inp3_quirk;
+ quirk-skip-phy-init;
+ status = "disabled";
+ };
+ };
+
+ gic: interrupt-controller@fe901000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x0 0xfe901000 0 0x1000>,
+ <0x0 0xfe902000 0 0x2000>,
+ <0x0 0xfe904000 0 0x2000>,
+ <0x0 0xfe906000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ usb_host0_ehci: usb@fed00000 {
+ compatible = "generic-ehci";
+ reg = <0x0 0xfed00000 0x0 0x40000>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
+ <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ usb_host0_ohci: usb@fed40000 {
+ compatible = "generic-ohci";
+ reg = <0x0 0xfed40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_USB2HOST>, <&cru HCLK_USB2HOST_ARB>,
+ <&u2phy>;
+ clock-names = "usbhost", "arbiter", "utmi";
+ phys = <&u2phy_host>;
+ phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ qos_dma2ddr: qos@fee03800 {
+ compatible = "syscon";
+ reg = <0x0 0xfee03800 0x0 0x20>;
+ };
+
+ qos_mcu: qos@fee10000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee10000 0x0 0x20>;
+ };
+
+ qos_dft_apb: qos@fee10100 {
+ compatible = "syscon";
+ reg = <0x0 0xfee10100 0x0 0x20>;
+ };
+
+ qos_gmac: qos@fee10200 {
+ compatible = "syscon";
+ reg = <0x0 0xfee10200 0x0 0x20>;
+ };
+
+ qos_mac100: qos@fee10300 {
+ compatible = "syscon";
+ reg = <0x0 0xfee10300 0x0 0x20>;
+ };
+
+ qos_dcf: qos@fee10400 {
+ compatible = "syscon";
+ reg = <0x0 0xfee10400 0x0 0x20>;
+ };
+
+ qos_cpu: qos@fee20000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee20000 0x0 0x20>;
+ };
+
+ qos_daplite_apb: qos@fee20100 {
+ compatible = "syscon";
+ reg = <0x0 0xfee20100 0x0 0x20>;
+ };
+
+ qos_gpu: qos@fee30000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee30000 0x0 0x20>;
+ };
+
+ qos_npu: qos@fee40000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee40000 0x0 0x20>;
+ };
+
+ qos_rkvdec: qos@fee50000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee50000 0x0 0x20>;
+ };
+
+ qos_vepu: qos@fee60000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee60000 0x0 0x20>;
+ };
+
+ qos_isp: qos@fee70000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee70000 0x0 0x20>;
+ };
+
+ qos_vicap: qos@fee70100 {
+ compatible = "syscon";
+ reg = <0x0 0xfee70100 0x0 0x20>;
+ };
+
+ qos_vop: qos@fee80000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee80000 0x0 0x20>;
+ };
+
+ qos_jpeg: qos@fee90000 {
+ compatible = "syscon";
+ reg = <0x0 0xfee90000 0x0 0x20>;
+ };
+
+ qos_rga_rd: qos@fee90100 {
+ compatible = "syscon";
+ reg = <0x0 0xfee90100 0x0 0x20>;
+ };
+
+ qos_rga_wr: qos@fee90200 {
+ compatible = "syscon";
+ reg = <0x0 0xfee90200 0x0 0x20>;
+ };
+
+ qos_pcie: qos@feea0000 {
+ compatible = "syscon";
+ reg = <0x0 0xfeea0000 0x0 0x20>;
+ };
+
+ qos_usb3: qos@feea0100 {
+ compatible = "syscon";
+ reg = <0x0 0xfeea0100 0x0 0x20>;
+ };
+
+ qos_crypto_apb: qos@feeb0000 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0000 0x0 0x20>;
+ };
+
+ qos_crypto: qos@feeb0100 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0100 0x0 0x20>;
+ };
+
+ qos_dmac: qos@feeb0200 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0200 0x0 0x20>;
+ };
+
+ qos_emmc: qos@feeb0300 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0300 0x0 0x20>;
+ };
+
+ qos_fspi: qos@feeb0400 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0400 0x0 0x20>;
+ };
+
+ qos_rkdma: qos@feeb0500 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0500 0x0 0x20>;
+ };
+
+ qos_sdmmc0: qos@feeb0600 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0600 0x0 0x20>;
+ };
+
+ qos_sdmmc1: qos@feeb0700 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0700 0x0 0x20>;
+ };
+
+ qos_usb2: qos@feeb0800 {
+ compatible = "syscon";
+ reg = <0x0 0xfeeb0800 0x0 0x20>;
+ };
+
+ pmu_grf: syscon@ff010000 {
+ compatible = "rockchip,rk3562-pmu-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff010000 0x0 0x10000>;
+
+ reboot_mode: reboot-mode {
+ compatible = "syscon-reboot-mode";
+ offset = <0x200>;
+ mode-bootloader = <BOOT_BL_DOWNLOAD>;
+ mode-charge = <BOOT_CHARGING>;
+ mode-fastboot = <BOOT_FASTBOOT>;
+ mode-loader = <BOOT_BL_DOWNLOAD>;
+ mode-normal = <BOOT_NORMAL>;
+ mode-recovery = <BOOT_RECOVERY>;
+ mode-ums = <BOOT_UMS>;
+ mode-panic = <BOOT_PANIC>;
+ mode-watchdog = <BOOT_WATCHDOG>;
+ };
+ };
+
+ sys_grf: syscon@ff030000 {
+ compatible = "rockchip,rk3562-sys-grf", "syscon", "simple-mfd";
+ reg = <0x0 0xff030000 0x0 0x10000>;
+
+ lvds: lvds {
+ compatible = "rockchip,rk3562-lvds";
+ phys = <&video_phy>;
+ phy-names = "phy";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_lvds>;
+ status = "disabled";
+ };
+
+ lvds_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_lvds>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ rgb: rgb {
+ compatible = "rockchip,rk3562-rgb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&vo_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rgb_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_rgb>;
+ status = "disabled";
+ };
+
+ rgb_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_rgb>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
+ peri_grf: syscon@ff040000 {
+ compatible = "rockchip,rk3562-peri-grf", "syscon";
+ reg = <0x0 0xff040000 0x0 0x10000>;
+ };
+
+ ioc_grf: syscon@ff060000 {
+ compatible = "rockchip,rk3562-ioc-grf", "syscon";
+ reg = <0x0 0xff060000 0x0 0x30000>;
+ };
+
+ usbphy_grf: syscon@ff090000 {
+ compatible = "rockchip,rk3562-usbphy-grf", "syscon";
+ reg = <0x0 0xff090000 0x0 0x8000>;
+ };
+
+ pipephy_grf: syscon@ff098000 {
+ compatible = "rockchip,rk3562-pipephy-grf", "syscon";
+ reg = <0x0 0xff098000 0x0 0x8000>;
+ };
+
+ cru: clock-controller@ff100000 {
+ compatible = "rockchip,rk3562-cru";
+ reg = <0x0 0xff100000 0x0 0x40000>;
+ rockchip,grf = <&sys_grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ assigned-clocks =
+ <&cru PLL_GPLL>, <&cru PLL_CPLL>,
+ <&cru ARMCLK>;
+ assigned-clock-rates =
+ <1188000000>, <1000000000>,
+ <600000000>;
+ };
+
+ i2c0: i2c@ff200000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xff200000 0x0 0x1000>;
+ clocks = <&cru CLK_PMU0_I2C0>, <&cru PCLK_PMU0_I2C0>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ uart0: serial@ff210000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff210000 0x0 0x100>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_PMU1_UART0>, <&cru PCLK_PMU1_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 0>;
+ status = "disabled";
+ };
+
+ spi0: spi@ff220000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff220000 0x0 0x1000>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>, <&cru PCLK_PMU1_SPI0>;
+ clock-names = "spiclk", "apb_pclk", "sclk_in";
+ dmas = <&dmac 13>, <&dmac 12>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0m0_csn0 &spi0m0_csn1 &spi0m0_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ pwm0: pwm@ff230000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm0m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm1: pwm@ff230010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm1m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm2: pwm@ff230020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm2m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm3: pwm@ff230030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff230030 0x0 0x10>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm3m0_pins>;
+ clocks = <&cru CLK_PMU1_PWM0>, <&cru PCLK_PMU1_PWM0>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pmu: power-management@ff258000 {
+ compatible = "rockchip,rk3562-pmu", "syscon", "simple-mfd";
+ reg = <0x0 0xff258000 0x0 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rk3562-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* These power domains are grouped by VD_GPU */
+ pd_gpu@RK3562_PD_GPU {
+ reg = <RK3562_PD_GPU>;
+ pm_qos = <&qos_gpu>;
+ };
+ /* These power domains are grouped by VD_NPU */
+ pd_npu@RK3562_PD_NPU {
+ reg = <RK3562_PD_NPU>;
+ pm_qos = <&qos_npu>;
+ };
+ /* These power domains are grouped by VD_LOGIC */
+ pd_vdpu@RK3562_PD_VDPU {
+ reg = <RK3562_PD_VDPU>;
+ pm_qos = <&qos_rkvdec>;
+ };
+ pd_vi@RK3562_PD_VI {
+ reg = <RK3562_PD_VI>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pm_qos = <&qos_isp>,
+ <&qos_vicap>;
+
+ pd_vepu@RK3562_PD_VEPU {
+ reg = <RK3562_PD_VEPU>;
+ pm_qos = <&qos_vepu>;
+ };
+ };
+ pd_vo@RK3562_PD_VO {
+ reg = <RK3562_PD_VO>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pm_qos = <&qos_vop>;
+
+ pd_rga@RK3562_PD_RGA {
+ reg = <RK3562_PD_RGA>;
+ pm_qos = <&qos_rga_rd>,
+ <&qos_rga_wr>,
+ <&qos_jpeg>;
+ };
+ };
+ pd_php@RK3562_PD_PHP {
+ reg = <RK3562_PD_PHP>;
+ pm_qos = <&qos_pcie>,
+ <&qos_usb3>;
+ };
+ };
+ };
+
+ pmu_mailbox: mailbox@ff290000 {
+ compatible = "rockchip,rk3562-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xff290000 0x0 0x200>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU1_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ rknpu: npu@ff300000 {
+ compatible = "rockchip,rk3562-rknpu";
+ reg = <0x0 0xff300000 0x0 0x10000>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
+ clock-names = "aclk", "hclk";
+ assigned-clocks = <&cru ACLK_RKNN>;
+ assigned-clock-rates = <600000000>;
+ resets = <&cru SRST_A_RKNN>, <&cru SRST_H_RKNN>;
+ reset-names = "srst_a", "srst_h";
+ power-domains = <&power RK3562_PD_NPU>;
+ iommus = <&rknpu_mmu>;
+ status = "disabled";
+ };
+
+ rknpu_mmu: iommu@ff30b000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff30b000 0x0 0x40>;
+ interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rknpu_mmu";
+ clocks = <&cru ACLK_RKNN>, <&cru HCLK_RKNN>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3562_PD_NPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ gpu: gpu@ff320000 {
+ compatible = "arm,mali-bifrost";
+ reg = <0x0 0xff320000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "GPU", "MMU", "JOB";
+
+ upthreshold = <40>;
+ downdifferential = <10>;
+
+ clocks = <&cru CLK_GPU>, <&cru CLK_GPU_BRG>;
+ clock-names = "clk_gpu", "clk_gpu_brg";
+ power-domains = <&power RK3562_PD_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
+ #cooling-cells = <2>;
+
+ status = "disabled";
+ };
+
+ gpu_opp_table: gpu-opp-table {
+ compatible = "operating-points-v2";
+
+ nvmem-cells = <&gpu_leakage>;
+ nvmem-cell-names = "leakage";
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+ opp-400000000 {
+ opp-hz = /bits/ 64 <400000000>;
+ opp-microvolt = <900000 900000 1000000>;
+ };
+ };
+
+ rkvdec: rkvdec@ff340100 {
+ compatible = "rockchip,rkv-decoder-vdpu382", "rockchip,rkv-decoder-v2";
+ reg = <0x0 0xff340100 0x0 0x400>, <0x0 0xff340000 0x0 0x100>;
+ reg-names = "regs", "link";
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
+ clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac";
+ rockchip,normal-rates = <198000000>, <0>, <396000000>;
+ assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_RKVDEC_HEVC_CA>;
+ assigned-clock-rates = <198000000>, <396000000>;
+ resets = <&cru SRST_A_RKVDEC>, <&cru SRST_H_RKVDEC>,
+ <&cru SRST_RKVDEC_HEVC_CA>;
+ reset-names = "video_a", "video_h", "video_hevc_cabac";
+ power-domains = <&power RK3562_PD_VDPU>;
+ iommus = <&rkvdec_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ rockchip,task-capacity = <16>;
+ status = "disabled";
+ };
+
+ rkvdec_mmu: iommu@ff340800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff340800 0x0 0x40>, <0x0 0xff340900 0x0 0x40>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvdec_mmu";
+ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3562_PD_VDPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rkvenc: rkvenc@ff360000 {
+ compatible = "rockchip,rkv-encoder-vepu540c", "rockchip,rkv-encoder-v2";
+ reg = <0x0 0xff360000 0x0 0x6000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "irq_rkvenc";
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ rockchip,normal-rates = <297000000>, <0>, <297000000>;
+ resets = <&cru SRST_A_RKVENC>, <&cru SRST_H_RKVENC>,
+ <&cru SRST_RKVENC_CORE>;
+ reset-names = "video_a", "video_h", "video_core";
+ assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_RKVENC_CORE>;
+ assigned-clock-rates = <297000000>, <297000000>;
+ power-domains = <&power RK3562_PD_VEPU>;
+ iommus = <&rkvenc_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <1>;
+ rockchip,resetgroup-node = <1>;
+ status = "disabled";
+ };
+
+ rkvenc_mmu: iommu@ff36f000 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff36f000 0x0 0x40>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rkvenc_mmu";
+ clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3562_PD_VEPU>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ mipi0_csi2: mipi0-csi2@ff380000 {
+ compatible = "rockchip,rk3562-mipi-csi2";
+ reg = <0x0 0xff380000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSIHOST0>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSIHOST0>;
+ reset-names = "srst_csihost_p";
+ status = "disabled";
+ };
+
+ mipi1_csi2: mipi1-csi2@ff390000 {
+ compatible = "rockchip,rk3562-mipi-csi2";
+ reg = <0x0 0xff390000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSIHOST1>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSIHOST1>;
+ reset-names = "srst_csihost_p";
+ status = "disabled";
+ };
+
+ mipi2_csi2: mipi2-csi2@ff3a0000 {
+ compatible = "rockchip,rk3562-mipi-csi2";
+ reg = <0x0 0xff3a0000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSIHOST2>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSIHOST2>;
+ reset-names = "srst_csihost_p";
+ status = "disabled";
+ };
+
+ mipi3_csi2: mipi3-csi2@ff3b0000 {
+ compatible = "rockchip,rk3562-mipi-csi2";
+ reg = <0x0 0xff3b0000 0x0 0x10000>;
+ reg-names = "csihost_regs";
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "csi-intr1", "csi-intr2";
+ clocks = <&cru PCLK_CSIHOST3>;
+ clock-names = "pclk_csi2host";
+ resets = <&cru SRST_P_CSIHOST3>;
+ reset-names = "srst_csihost_p";
+ status = "disabled";
+ };
+
+ csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 {
+ compatible = "rockchip,rk3562-csi2-dphy-hw";
+ reg = <0x0 0xff3c0000 0x0 0x10000>;
+ clocks = <&cru PCLK_CSIPHY0>;
+ clock-names = "pclk";
+ resets = <&cru SRST_P_CSIPHY0>;
+ reset-names = "srst_p_csiphy0";
+ rockchip,grf = <&sys_grf>;
+ status = "disabled";
+ };
+
+ csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 {
+ compatible = "rockchip,rk3562-csi2-dphy-hw";
+ reg = <0x0 0xff3d0000 0x0 0x10000>;
+ clocks = <&cru PCLK_CSIPHY1>;
+ clock-names = "pclk";
+ resets = <&cru SRST_P_CSIPHY1>;
+ reset-names = "srst_p_csiphy1";
+ rockchip,grf = <&sys_grf>;
+ status = "disabled";
+ };
+
+ rkcif: rkcif@ff3e0000 {
+ compatible = "rockchip,rk3562-cif";
+ reg = <0x0 0xff3e0000 0x0 0x800>;
+ reg-names = "cif_regs";
+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cif-intr";
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>;
+ clock-names = "aclk_cif", "hclk_cif", "dclk_cif";
+ resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>,
+ <&cru SRST_I0_VICAP>, <&cru SRST_I1_VICAP>, <&cru SRST_I2_VICAP>,
+ <&cru SRST_I3_VICAP>;
+ reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d",
+ "rst_cif_i0", "rst_cif_i1", "rst_cif_i2",
+ "rst_cif_i3";
+ power-domains = <&power RK3562_PD_VI>;
+ rockchip,grf = <&sys_grf>;
+ iommus = <&rkcif_mmu>;
+ status = "disabled";
+ };
+
+ rkcif_mmu: iommu@ff3e0800 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff3e0800 0x0 0x100>;
+ interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cif_mmu";
+ clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>;
+ clock-names = "aclk", "iface";
+ power-domains = <&power RK3562_PD_VI>;
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ rkisp: isp@ff3f0000 {
+ compatible = "rockchip,rk3562-rkisp";
+ reg = <0x0 0xff3f0000 0x0 0x7f00>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mipi_irq", "mi_irq", "isp_irq";
+ clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru CLK_ISP>;
+ clock-names = "aclk_isp", "hclk_isp", "clk_isp_core";
+ power-domains = <&power RK3562_PD_VI>;
+ iommus = <&rkisp_mmu>;
+ status = "disabled";
+ };
+
+ rkisp_mmu: iommu@ff3f7f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff3f7f00 0x0 0x100>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "isp_mmu";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
+ clock-names = "aclk", "iface";
+ rockchip,disable-mmu-reset;
+ #iommu-cells = <0>;
+ power-domains = <&power RK3562_PD_VI>;
+ status = "disabled";
+ };
+
+ vop: vop@ff400000 {
+ compatible = "rockchip,rk3562-vop";
+ reg = <0x0 0xff400000 0x0 0x2000>, <0x0 0xff405000 0x0 0x1000>;
+ reg-names = "regs", "gamma_lut";
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru DCLK_VOP1>;
+ clock-names = "aclk_vop",
+ "hclk_vop",
+ "dclk_vp0",
+ "dclk_vp1";
+ resets = <&cru SRST_A_VOP>,
+ <&cru SRST_H_VOP>,
+ <&cru SRST_D_VOP>,
+ <&cru SRST_D_VOP1>;
+ reset-names = "axi",
+ "ahb",
+ "dclk_vp0",
+ "dclk_vp1";
+ iommus = <&vop_mmu>;
+ power-domains = <&power RK3562_PD_VO>;
+ rockchip,grf = <&sys_grf>;
+ status = "disabled";
+
+ vop_out: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ vp0_out_rgb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&rgb_in_vp0>;
+ };
+
+ vp0_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_vp0>;
+ };
+
+ vp0_out_lvds: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&lvds_in_vp0>;
+ };
+ };
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ vp1_out_rgb: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&rgb_in_vp1>;
+ };
+
+ vp1_out_dsi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&dsi_in_vp1>;
+ };
+
+ vp1_out_lvds: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&lvds_in_vp1>;
+ };
+ };
+ };
+ };
+
+ vop_mmu: iommu@ff407e00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff407e00 0x0 0x100>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "vop_mmu";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ rockchip,disable-device-link-resume;
+ rockchip,shootdown-entire;
+ status = "disabled";
+ };
+
+ rga2: rga@ff440000 {
+ compatible = "rockchip,rga2_core0";
+ reg = <0x0 0xff440000 0x0 0x1000>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga2_irq";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
+ clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2";
+ iommus = <&rga2_mmu>;
+ power-domains = <&power RK3562_PD_RGA>;
+ status = "disabled";
+ };
+
+ rga2_mmu: iommu@ff440f00 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff440f00 0x0 0x100>;
+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "rga2_mmu";
+ clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>;
+ clock-names = "aclk", "iface";
+ #iommu-cells = <0>;
+ power-domains = <&power RK3562_PD_RGA>;
+ status = "disabled";
+ };
+
+ jpegd: jpegd@ff450000 {
+ compatible = "rockchip,rkv-jpeg-decoder-v1";
+ reg = <0x0 0xff450000 0x0 0x400>;
+ interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,disable-auto-freq;
+ resets = <&cru SRST_A_JDEC>, <&cru SRST_H_JDEC>;
+ reset-names = "video_a", "video_h";
+ power-domains = <&power RK3562_PD_RGA>;
+ iommus = <&jpegd_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <2>;
+ rockchip,resetgroup-node = <2>;
+ status = "disabled";
+ };
+
+ jpegd_mmu: iommu@ff450480 {
+ compatible = "rockchip,iommu-v2";
+ reg = <0x0 0xff450480 0x0 0x40>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "jpegd_mmu";
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
+ power-domains = <&power RK3562_PD_RGA>;
+ #iommu-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2x1: pcie@ff500000 {
+ compatible = "rockchip,rk3562-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x0 0xff>;
+ clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
+ <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
+ <&cru CLK_PCIE20_AUX>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie2x1_intc 0>,
+ <0 0 0 2 &pcie2x1_intc 1>,
+ <0 0 0 3 &pcie2x1_intc 2>,
+ <0 0 0 4 &pcie2x1_intc 3>;
+ linux,pci-domain = <0>;
+ num-ib-windows = <8>;
+ num-viewport = <8>;
+ num-ob-windows = <2>;
+ max-link-speed = <2>;
+ num-lanes = <1>;
+ phys = <&combphy_pu PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000
+ 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000
+ 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000
+ 0xc3000000 0x3 0x00000000 0x3 0x00000000 0x0 0x40000000>;
+ reg = <0x0 0xfe000000 0x0 0x400000>,
+ <0x0 0xff500000 0x0 0x10000>;
+ reg-names = "pcie-dbi", "pcie-apb";
+ resets = <&cru SRST_PCIE20_POWERUP>;
+ reset-names = "pipe";
+ status = "disabled";
+
+ pcie2x1_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ };
+ };
+
+ spi1: spi@ff640000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff640000 0x0 0x1000>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 15>, <&dmac 14>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m0_csn0 &spi1m0_csn1 &spi1m0_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ spi2: spi@ff650000 {
+ compatible = "rockchip,rk3066-spi";
+ reg = <0x0 0xff650000 0x0 0x1000>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac 17>, <&dmac 16>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi2m0_csn0 &spi2m0_csn1 &spi2m0_pins>;
+ num-cs = <2>;
+ status = "disabled";
+ };
+
+ uart1: serial@ff670000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff670000 0x0 0x100>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 1>, <&dmac 10>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff680000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff680000 0x0 0x100>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 2>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff690000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff690000 0x0 0x100>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 3>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff6a0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6a0000 0x0 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff6b0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6b0000 0x0 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 5>, <&dmac 11>;
+ status = "disabled";
+ };
+
+ uart6: serial@ff6c0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6c0000 0x0 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 6>;
+ status = "disabled";
+ };
+
+ uart7: serial@ff6d0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6d0000 0x0 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 7>;
+ status = "disabled";
+ };
+
+ uart8: serial@ff6e0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6e0000 0x0 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 8>;
+ status = "disabled";
+ };
+
+ uart9: serial@ff6f0000 {
+ compatible = "rockchip,rk3562-uart", "snps,dw-apb-uart";
+ reg = <0x0 0xff6f0000 0x0 0x100>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
+ clock-names = "baudclk", "apb_pclk";
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ dmas = <&dmac 9>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@ff700000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm4m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm5: pwm@ff700010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm5m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm6: pwm@ff700020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm6m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm7: pwm@ff700030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff700030 0x0 0x10>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm7m0_pins>;
+ clocks = <&cru CLK_PWM1_PERI>, <&cru PCLK_PWM1_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm8: pwm@ff710000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm8m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm9: pwm@ff710010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm9m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm10: pwm@ff710020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm10m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm11: pwm@ff710030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff710030 0x0 0x10>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm11m0_pins>;
+ clocks = <&cru CLK_PWM2_PERI>, <&cru PCLK_PWM2_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm12: pwm@ff720000 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720000 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm12m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm13: pwm@ff720010 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720010 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm13m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm14: pwm@ff720020 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720020 0x0 0x10>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm14m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ pwm15: pwm@ff720030 {
+ compatible = "rockchip,rk3562-pwm", "rockchip,rk3328-pwm";
+ reg = <0x0 0xff720030 0x0 0x10>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
+ pinctrl-names = "active";
+ pinctrl-0 = <&pwm15m0_pins>;
+ clocks = <&cru CLK_PWM3_PERI>, <&cru PCLK_PWM3_PERI>;
+ clock-names = "pwm", "pclk";
+ status = "disabled";
+ };
+
+ saradc0: saradc@ff730000 {
+ compatible = "rockchip,rk3562-saradc";
+ reg = <0x0 0xff730000 0x0 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ u2phy: usb2-phy@ff740000 {
+ compatible = "rockchip,rk3562-usb2phy";
+ reg = <0x0 0xff740000 0x0 0x10000>;
+ clocks = <&cru CLK_USB2PHY_REF>, <&cru PCLK_USB2PHY>;
+ clock-names = "phyclk", "pclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ rockchip,usbgrf = <&usbphy_grf>;
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id", "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
+ };
+
+ combphy_pu: phy@ff750000 {
+ compatible = "rockchip,rk3562-naneng-combphy";
+ reg = <0x0 0xff750000 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = <&cru CLK_PIPEPHY_REF>, <&cru PCLK_PIPEPHY>,
+ <&cru PCLK_PHP>;
+ clock-names = "refclk", "apbclk", "pipe_clk";
+ assigned-clocks = <&cru CLK_PIPEPHY_REF>;
+ assigned-clock-rates = <100000000>;
+ resets = <&cru SRST_P_PIPEPHY>, <&cru SRST_PIPEPHY>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <&peri_grf>;
+ rockchip,pipe-phy-grf = <&pipephy_grf>;
+ status = "disabled";
+ };
+
+ sai0: sai@ff800000 {
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
+ reg = <0x0 0xff800000 0x0 0x1000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 19>, <&dmac 18>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s0m0_lrck
+ &i2s0m0_sclk
+ &i2s0m0_sdi0
+ &i2s0m0_sdo0
+ &i2s0m0_sdo1
+ &i2s0m0_sdo2
+ &i2s0m0_sdo3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sai1: sai@ff810000 {
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
+ reg = <0x0 0xff810000 0x0 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 21>, <&dmac 20>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m0_lrck
+ &i2s1m0_sclk
+ &i2s1m0_sdi0
+ &i2s1m0_sdi1
+ &i2s1m0_sdi2
+ &i2s1m0_sdi3
+ &i2s1m0_sdo0
+ &i2s1m0_sdo1
+ &i2s1m0_sdo2
+ &i2s1m0_sdo3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sai2: sai@ff820000 {
+ compatible = "rockchip,rk3562-sai", "rockchip,sai-v1";
+ reg = <0x0 0xff820000 0x0 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>;
+ clock-names = "mclk", "hclk";
+ dmas = <&dmac 23>, <&dmac 22>;
+ dma-names = "tx", "rx";
+ resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
+ reset-names = "m", "h";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s2m0_lrck
+ &i2s2m0_sclk
+ &i2s2m0_sdi
+ &i2s2m0_sdo>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ pdm: pdm@ff830000 {
+ compatible = "rockchip,rk3562-pdm", "rockchip,pdm";
+ reg = <0x0 0xff830000 0x0 0x1000>;
+ clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
+ clock-names = "pdm_clk", "pdm_hclk";
+ dmas = <&dmac 31>;
+ dma-names = "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pdmm0_clk0
+ &pdmm0_clk1
+ &pdmm0_sdi0
+ &pdmm0_sdi1
+ &pdmm0_sdi2
+ &pdmm0_sdi3>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ spdif_8ch: spdif@ff840000 {
+ compatible = "rockchip,rk3562-spdif", "rockchip,rk3568-spdif";
+ reg = <0x0 0xff840000 0x0 0x1000>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&dmac 30>;
+ dma-names = "tx";
+ clock-names = "mclk", "hclk";
+ clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
+ #sound-dai-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdifm0_pins>;
+ status = "disabled";
+ };
+
+ acdcdig_dsm: codec-digital@ff850000 {
+ compatible = "rockchip,rk3562-codec-digital", "rockchip,codec-digital-v1";
+ reg = <0x0 0xff850000 0x0 0x1000>;
+ clocks = <&cru CLK_DSM>, <&cru HCLK_DSM>;
+ clock-names = "dac", "pclk";
+ resets = <&cru SRST_DSM>;
+ reset-names = "reset" ;
+ rockchip,grf = <&sys_grf>;
+ rockchip,pwm-output-mode;
+ pinctrl-names = "default";
+ pinctrl-0 = <&dsm_pins>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
+ sfc: spi@ff860000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xff860000 0x0 0x10000>;
+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <100000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ sdhci: mmc@ff870000 {
+ compatible = "rockchip,rk3562-dwcmshc", "rockchip,rk3528-dwcmshc";
+ reg = <0x0 0xff870000 0x0 0x10000>;
+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru BCLK_EMMC>, <&cru CCLK_EMMC>;
+ assigned-clock-rates = <200000000>, <200000000>;
+ clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
+ <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
+ <&cru TMCLK_EMMC>;
+ clock-names = "core", "bus", "axi", "block", "timer";
+ resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ <&cru SRST_T_EMMC>;
+ reset-names = "core", "bus", "axi", "block", "timer";
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdmmc0: mmc@ff880000 {
+ compatible = "rockchip,rk3562-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff880000 0x0 0x10000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>,
+ <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_H_SDMMC0>;
+ reset-names = "reset";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ sdmmc1: mmc@ff890000 {
+ compatible = "rockchip,rk3562-dw-mshc",
+ "rockchip,rk3288-dw-mshc";
+ reg = <0x0 0xff890000 0x0 0x10000>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <150000000>;
+ clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>,
+ <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ resets = <&cru SRST_H_SDMMC1>;
+ reset-names = "reset";
+ fifo-depth = <0x100>;
+ status = "disabled";
+ };
+
+ crypto: crypto@ff8a0000 {
+ compatible = "rockchip,crypto-v4";
+ reg = <0x0 0xff8a0000 0x0 0x2000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>,
+ <&scmi_clk ACLK_CRYPTO>, <&scmi_clk HCLK_CRYPTO>,
+ <&scmi_clk PCLK_CRYPTO>;
+ clock-names = "sclk", "pka", "aclk", "pclk", "pclk";
+ assigned-clocks = <&scmi_clk CLK_CORE_CRYPTO>, <&scmi_clk CLK_PKA_CRYPTO>;
+ assigned-clock-rates = <200000000>, <300000000>;
+ resets = <&cru SRST_CORE_CRYPTO>;
+ reset-names = "crypto-rst";
+ status = "disabled";
+ };
+
+ rng: rng@ff8e0000 {
+ compatible = "rockchip,rkrng";
+ reg = <0x0 0xff8e0000 0x0 0x200>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk HCLK_RK_RNG_NS>;
+ clock-names = "hclk_trng";
+ resets = <&cru SRST_H_RK_RNG_NS>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ otp: otp@ff930000 {
+ compatible = "rockchip,rk3562-otp";
+ reg = <0x0 0xff930000 0x0 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>,
+ <&cru PCLK_OTPC_NS>, <&cru CLK_OTPC_ARB>,
+ <&cru PCLK_OTPPHY>;
+ clock-names = "usr", "sbpi", "apb", "arb", "phy";
+ resets = <&cru SRST_USER_OTPC_NS>, <&cru SRST_SBPI_OTPC_NS>,
+ <&cru SRST_P_OTPC_NS>, <&cru SRST_OTPC_ARB>,
+ <&cru SRST_P_OTPPHY>;
+ reset-names = "usr", "sbpi", "apb", "arb", "phy";
+
+ /* Data cells */
+ cpu_code: cpu-code@2 {
+ reg = <0x02 0x2>;
+ };
+ otp_cpu_version: cpu-version@8 {
+ reg = <0x08 0x1>;
+ bits = <3 3>;
+ };
+ otp_id: id@a {
+ reg = <0x0a 0x10>;
+ };
+ cpu_leakage: cpu-leakage@1a {
+ reg = <0x1a 0x1>;
+ };
+ log_leakage: log-leakage@1b {
+ reg = <0x1b 0x1>;
+ };
+ npu_leakage: npu-leakage@1c {
+ reg = <0x1c 0x1>;
+ };
+ gpu_leakage: gpu-leakage@1d {
+ reg = <0x1d 0x1>;
+ };
+ };
+
+ dmac: dma-controller@ff990000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x0 0xff990000 0x0 0x4000>;
+ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ };
+
+ hwlock: hwspinlock@ff9e0000 {
+ compatible = "rockchip,hwspinlock";
+ reg = <0x0 0xff9e0000 0x0 0x100>;
+ #hwlock-cells = <1>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@ffa00000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa00000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@ffa10000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa10000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@ffa20000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa20000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@ffa30000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa30000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@ffa40000 {
+ compatible = "rockchip,rk3562-i2c", "rockchip,rk3399-i2c";
+ reg = <0x0 0xffa40000 0x0 0x1000>;
+ clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
+ clock-names = "i2c", "pclk";
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c5m0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ wdt: watchdog@ffa60000 {
+ compatible = "snps,dw-wdt";
+ reg = <0x0 0xffa60000 0x0 0x100>;
+ clocks = <&cru CLK_WDTNS>, <&cru PCLK_WDTNS>;
+ clock-names = "tclk", "pclk";
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ tsadc: tsadc@ffa70000 {
+ compatible = "rockchip,rk3562-tsadc";
+ reg = <0x0 0xffa70000 0x0 0x400>;
+ rockchip,grf = <&sys_grf>;
+ interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>;
+ clock-names = "tsadc", "tsadc_tsen", "apb_pclk";
+ assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>;
+ assigned-clock-rates = <1200000>, <12000000>;
+ resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>, <&cru SRST_TSADCPHY>;
+ reset-names = "tsadc", "tsadc-apb", "tsadc-phy";
+ #thermal-sensor-cells = <1>;
+ rockchip,hw-tshut-temp = <120000>;
+ rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
+ rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
+ status = "disabled";
+ };
+
+ gmac0: ethernet@ffa80000 {
+ compatible = "rockchip,rk3562-gmac", "snps,dwmac-4.20a";
+ reg = <0x0 0xffa80000 0x0 0x10000>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php_grf = <&ioc_grf>;
+ clocks = <&cru CLK_GMAC_125M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
+ <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac";
+ resets = <&cru SRST_A_GMAC>;
+ reset-names = "stmmaceth";
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&gmac0_stmmac_axi_setup>;
+ snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
+ snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
+ status = "disabled";
+
+ mdio0: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ gmac0_stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ gmac0_mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ gmac0_mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
+ saradc1: saradc@ffaa0000 {
+ compatible = "rockchip,rk3562-saradc";
+ reg = <0x0 0xffaa0000 0x0 0x100>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC_VCCIO156>, <&cru PCLK_SARADC_VCCIO156>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_P_SARADC_VCCIO156>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ mailbox: mailbox@ffae0000 {
+ compatible = "rockchip,rk3562-mailbox",
+ "rockchip,rk3368-mailbox";
+ reg = <0x0 0xffae0000 0x0 0x200>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_MAILBOX>;
+ clock-names = "pclk_mailbox";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ dsi: dsi@ffb10000 {
+ compatible = "rockchip,rk3562-mipi-dsi";
+ reg = <0x0 0xffb10000 0x0 0x10000>;
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_DSITX>;
+ clock-names = "pclk";
+ resets = <&cru SRST_P_DSITX>;
+ reset-names = "apb";
+ phys = <&video_phy>;
+ phy-names = "dphy";
+ rockchip,grf = <&sys_grf>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in: port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dsi_in_vp0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vp0_out_dsi>;
+ status = "disabled";
+ };
+
+ dsi_in_vp1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vp1_out_dsi>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+
+ video_phy: phy@ffb20000 {
+ compatible = "rockchip,rk3562-dsi-dphy", "rockchip,rk3562-video-phy",
+ "rockchip,rk3568-dsi-dphy", "rockchip,rk3568-video-phy";
+ reg = <0x0 0xffb20000 0x0 0x10000>,
+ <0x0 0xffb10000 0x0 0x10000>;
+ reg-names = "phy", "host";
+ clocks = <&cru CLK_MIPIDSIPHY_REF>,
+ <&cru PCLK_DSIPHY>, <&cru PCLK_DSITX>;
+ clock-names = "ref", "pclk", "pclk_host";
+ #clock-cells = <0>;
+ resets = <&cru SRST_P_DSIPHY>;
+ reset-names = "apb";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ gmac1: ethernet@ffb30000 {
+ compatible = "rockchip,rk3562-gmac";
+ reg = <0x0 0xffb30000 0x0 0x10000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&sys_grf>;
+ rockchip,php_grf = <&ioc_grf>;
+ clocks = <&cru CLK_GMAC_50M_CRU_I>, <&cru CLK_GMAC_50M_CRU_I>,
+ <&cru PCLK_GMAC>, <&cru ACLK_GMAC>;
+ clock-names = "stmmaceth", "clk_mac_ref",
+ "pclk_mac", "aclk_mac";
+ resets = <&cru SRST_A_MAC100>;
+ reset-names = "stmmaceth";
+ status = "disabled";
+
+ mdio1: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk3562-pinctrl";
+ rockchip,grf = <&ioc_grf>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio0: gpio@ff260000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff260000 0x0 0x100>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PMU0_GPIO0>, <&cru DBCLK_PMU0_GPIO0>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 0 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff620000 0x0 0x100>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PERI_GPIO1>, <&cru DCLK_PERI_GPIO1>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 32 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xff630000 0x0 0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_PERI_GPIO2>, <&cru DCLK_PERI_GPIO2>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 64 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@ffac0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffac0000 0x0 0x100>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3_VCCIO156>, <&cru DCLK_BUS_GPIO3>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 96 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@ffad0000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x0 0xffad0000 0x0 0x100>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4_VCCIO156>, <&cru DCLK_BUS_GPIO4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl 0 128 32>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rk3562-pinctrl.dtsi"
diff --git a/u-boot/arch/arm/dts/rk3568-u-boot.dtsi b/u-boot/arch/arm/dts/rk3568-u-boot.dtsi
index 3eb3937..a0678e3 100644
--- a/u-boot/arch/arm/dts/rk3568-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rk3568-u-boot.dtsi
@@ -17,6 +17,15 @@
stdout-path = &uart2;
u-boot,spl-boot-order = &sdmmc0, &sdhci, &nandc0, &spi_nand, &spi_nor;
};
+
+ secure-otp@fe3a0000 {
+ compatible = "rockchip,rk3568-secure-otp";
+ reg = <0x0 0xfe3a0000 0x0 0x4000>;
+ secure_conf = <0xfdd18008>;
+ mask_addr = <0xfe880000>;
+ cru_rst_addr = <0xfdd20470>;
+ u-boot,dm-spl;
+ };
};
&psci {
@@ -25,7 +34,7 @@
};
&crypto {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
&uart2 {
@@ -37,12 +46,12 @@
};
&grf {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
status = "okay";
};
&pmugrf {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
status = "okay";
};
@@ -87,12 +96,12 @@
};
&cru {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
status = "okay";
};
&pmucru {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
status = "okay";
};
@@ -132,7 +141,7 @@
};
&saradc {
- u-boot,dm-spl;
+ u-boot,dm-pre-reloc;
status = "okay";
};
@@ -194,7 +203,7 @@
};
};
-&gmac0_clkin{
+&gmac0_clkin {
u-boot,dm-pre-reloc;
};
@@ -391,15 +400,15 @@
};
&gpio2 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
&pcfg_pull_none_drv_level_1 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
&pcfg_pull_none_drv_level_2 {
- u-boot,dm-pre-reloc;
+ u-boot,dm-spl;
};
@@ -416,10 +425,6 @@
};
&pcfg_pull_none {
- u-boot,dm-pre-reloc;
-};
-
-&secure_otp {
u-boot,dm-spl;
};
diff --git a/u-boot/arch/arm/dts/rk3568.dtsi b/u-boot/arch/arm/dts/rk3568.dtsi
index 910161c..060a31b 100644
--- a/u-boot/arch/arm/dts/rk3568.dtsi
+++ b/u-boot/arch/arm/dts/rk3568.dtsi
@@ -1892,14 +1892,6 @@
status = "disabled";
};
- secure_otp: secure_otp@fe3a0000 {
- compatible = "rockchip,rk3568-secure-otp";
- reg = <0x0 0xfe3a0000 0x0 0x4000>;
- secure_conf = <0xfdd18008>;
- mask_addr = <0xfe880000>;
- cru_rst_addr = <0xfdd20470>;
- };
-
i2s0_8ch: i2s@fe400000 {
compatible = "rockchip,rk3568-i2s-tdm";
reg = <0x0 0xfe400000 0x0 0x1000>;
diff --git a/u-boot/arch/arm/dts/rk3588-u-boot.dtsi b/u-boot/arch/arm/dts/rk3588-u-boot.dtsi
index 3fe8054..d0b82f6 100644
--- a/u-boot/arch/arm/dts/rk3588-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rk3588-u-boot.dtsi
@@ -173,7 +173,8 @@
&sdhci {
bus-width = <8>;
u-boot,dm-spl;
- mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ mmc-hs400-enhanced-strobe;
non-removable;
status = "okay";
};
diff --git a/u-boot/arch/arm/dts/rk3588.dtsi b/u-boot/arch/arm/dts/rk3588.dtsi
index 8a13e8e..fbffe36 100644
--- a/u-boot/arch/arm/dts/rk3588.dtsi
+++ b/u-boot/arch/arm/dts/rk3588.dtsi
@@ -34,6 +34,8 @@
resets = <&cru SRST_A_USB3OTG1>;
reset-names = "usb3-otg";
dr_mode = "host";
+ phys = <&u2phy1_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -69,6 +71,8 @@
compatible = "rockchip,rk3588-usb2phy";
reg = <0x4000 0x10>;
interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
+ reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
diff --git a/u-boot/arch/arm/dts/rk3588s.dtsi b/u-boot/arch/arm/dts/rk3588s.dtsi
index 53ccfba..ebe8761 100644
--- a/u-boot/arch/arm/dts/rk3588s.dtsi
+++ b/u-boot/arch/arm/dts/rk3588s.dtsi
@@ -44,6 +44,11 @@
spi3 = &spi3;
spi4 = &spi4;
spi5 = &sfc;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
};
cpus {
@@ -253,6 +258,8 @@
resets = <&cru SRST_A_USB3OTG0>;
reset-names = "usb3-otg";
dr_mode = "otg";
+ phys = <&u2phy0_otg>;
+ phy-names = "usb2-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1-entry-quirk;
@@ -270,6 +277,8 @@
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
@@ -280,6 +289,8 @@
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>;
clock-names = "usbhost", "arbiter";
+ phys = <&u2phy2_host>;
+ phy-names = "usb2-phy";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
@@ -290,6 +301,8 @@
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
@@ -300,6 +313,8 @@
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>;
clock-names = "usbhost", "arbiter";
+ phys = <&u2phy3_host>;
+ phy-names = "usb2-phy";
power-domains = <&power RK3588_PD_USB>;
status = "disabled";
};
@@ -406,6 +421,8 @@
compatible = "rockchip,rk3588-usb2phy";
reg = <0x0 0x10>;
interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
+ reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
@@ -429,6 +446,8 @@
compatible = "rockchip,rk3588-usb2phy";
reg = <0x8000 0x10>;
interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
+ reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
@@ -452,6 +471,8 @@
compatible = "rockchip,rk3588-usb2phy";
reg = <0xc000 0x10>;
interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
+ reset-names = "phy", "apb";
clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
clock-names = "phyclk";
#clock-cells = <0>;
diff --git a/u-boot/arch/arm/dts/rv1106-evb2.dts b/u-boot/arch/arm/dts/rv1106-evb2.dts
index ffc431c..71ad07b 100644
--- a/u-boot/arch/arm/dts/rv1106-evb2.dts
+++ b/u-boot/arch/arm/dts/rv1106-evb2.dts
@@ -7,6 +7,7 @@
#include "rv1106.dtsi"
#include "rv1106-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
/ {
model = "Rockchip RV1106 EVB2 Board";
@@ -15,6 +16,22 @@
chosen {
stdout-path = &uart2;
u-boot,spl-boot-order = &spi_nor, &emmc;
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+ u-boot,dm-spl;
+ status = "okay";
+
+ volumeup-key {
+ u-boot,dm-spl;
+ linux,code = <KEY_VOLUMEUP>;
+ label = "volume up";
+ press-threshold-microvolt = <17578>;
+ };
};
};
@@ -63,6 +80,11 @@
status = "disabled";
};
+&saradc {
+ u-boot,dm-spl;
+ status = "okay";
+};
+
&sdmmc {
/delete-property/ u-boot,dm-spl;
status = "disabled";
diff --git a/u-boot/arch/arm/dts/rv1106-u-boot.dtsi b/u-boot/arch/arm/dts/rv1106-u-boot.dtsi
index 6196dba..b0632e9 100644
--- a/u-boot/arch/arm/dts/rv1106-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rv1106-u-boot.dtsi
@@ -15,7 +15,7 @@
u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
};
- secure_otp: secure_otp@ff3fd8000 {
+ secure-otp@ff3fd8000 {
compatible = "rockchip,rv1106-secure-otp";
reg = <0xff3d8000 0x4000>;
secure_conf = <0xff07a018>;
@@ -112,8 +112,28 @@
u-boot,dm-spl;
};
+&gpio0 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&gpio2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
&gpio3 {
u-boot,dm-spl;
+ status = "okay";
+};
+
+&gpio4 {
+ u-boot,dm-pre-reloc;
status = "okay";
};
@@ -159,3 +179,23 @@
spi-max-frequency = <100000000>;
};
};
+
+&u2phy {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&u2phy_otg {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usbdrd {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&usbdrd_dwc3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/u-boot/arch/arm/dts/rv1106.dtsi b/u-boot/arch/arm/dts/rv1106.dtsi
index 1ac96f8..fed453e 100644
--- a/u-boot/arch/arm/dts/rv1106.dtsi
+++ b/u-boot/arch/arm/dts/rv1106.dtsi
@@ -492,7 +492,7 @@
};
saradc: saradc@ff3c0000 {
- compatible = "rockchip,rk3588-saradc";
+ compatible = "rockchip,rv1106-saradc";
reg = <0xff3c0000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
diff --git a/u-boot/arch/arm/dts/rv1126-u-boot.dtsi b/u-boot/arch/arm/dts/rv1126-u-boot.dtsi
index 2bd1d6f..d3c98a8 100644
--- a/u-boot/arch/arm/dts/rv1126-u-boot.dtsi
+++ b/u-boot/arch/arm/dts/rv1126-u-boot.dtsi
@@ -15,10 +15,12 @@
u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc;
};
- secure_otp: secure_otp@0xff5d0000 {
+ secure-otp@ff5d0000 {
compatible = "rockchip,rv1126-secure-otp";
reg = <0xff5d0000 0x4000>;
secure_conf = <0xfe0a0008>;
+ u-boot,dm-spl;
+ status = "okay";
};
};
@@ -147,11 +149,6 @@
};
&hw_decompress {
- u-boot,dm-spl;
- status = "okay";
-};
-
-&secure_otp {
u-boot,dm-spl;
status = "okay";
};
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h b/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h
index bc1395e..063fd6b 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/boot_mode.h
@@ -23,6 +23,8 @@
#define BOOT_UMS (REBOOT_FLAG + 12)
/* enter dfu download mode */
#define BOOT_DFU (REBOOT_FLAG + 13)
+/* reboot system quiescent */
+#define BOOT_QUIESCENT (REBOOT_FLAG + 14)
/* enter bootrom download mode */
#define BOOT_BROM_DOWNLOAD 0xEF08A53C
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/clock.h b/u-boot/arch/arm/include/asm/arch-rockchip/clock.h
index cabe1d5..8487615 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/clock.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/clock.h
@@ -12,6 +12,13 @@
#define RKCLK_PLL_MODE_NORMAL 1
#define RKCLK_PLL_MODE_DEEP 2
+/*
+ * PLL flags
+ */
+#define ROCKCHIP_PLL_SYNC_RATE BIT(0)
+/* normal mode only. now only for pll_rk3036, pll_rk3328 type */
+#define ROCKCHIP_PLL_FIXED_MODE BIT(1)
+
enum {
ROCKCHIP_SYSCON_NOC,
ROCKCHIP_SYSCON_GRF,
@@ -29,6 +36,7 @@
ROCKCHIP_SYSCON_PIPE_PHY2_GRF,
ROCKCHIP_SYSCON_VOP_GRF,
ROCKCHIP_SYSCON_VO_GRF,
+ ROCKCHIP_SYSCON_IOC,
};
/* Standard Rockchip clock numbers */
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
new file mode 100644
index 0000000..3576b03
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3528.h
@@ -0,0 +1,396 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3528_H
+#define _ASM_ARCH_CRU_RK3528_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1200 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (996 * MHz)
+#define PPLL_HZ (1000 * MHz)
+
+/* RK3528 pll id */
+enum rk3528_pll_id {
+ APLL,
+ CPLL,
+ GPLL,
+ PPLL,
+ DPLL,
+ PLL_COUNT,
+};
+
+struct rk3528_clk_info {
+ unsigned long id;
+ char *name;
+};
+
+struct rk3528_clk_priv {
+ struct rk3528_cru *cru;
+ struct rk3528_sysgrf *grf;
+ ulong ppll_hz;
+ ulong gpll_hz;
+ ulong cpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3528_pll {
+ unsigned int con0;
+ unsigned int con1;
+ unsigned int con2;
+ unsigned int con3;
+ unsigned int con4;
+ unsigned int reserved0[3];
+};
+
+struct rk3528_cru {
+ uint32_t apll_con[5];
+ uint32_t reserved0014[3];
+ uint32_t cpll_con[5];
+ uint32_t reserved0034[11];
+ uint32_t gpll_con[5];
+ uint32_t reserved0074[51+32];
+ uint32_t reserved01c0[48];
+ uint32_t mode_con[1];
+ uint32_t reserved0284[31];
+ uint32_t clksel_con[91];
+ uint32_t reserved046c[229];
+ uint32_t gate_con[46];
+ uint32_t reserved08b8[82];
+ uint32_t softrst_con[47];
+ uint32_t reserved0abc[81];
+ uint32_t glb_cnt_th;
+ uint32_t glb_rst_st;
+ uint32_t glb_srst_fst;
+ uint32_t glb_srst_snd;
+ uint32_t glb_rst_con;
+ uint32_t reserved0c14[6];
+ uint32_t corewfi_con;
+ uint32_t reserved0c30[15604];
+
+ /* pmucru */
+ uint32_t reserved10000[192];
+ uint32_t pmuclksel_con[3];
+ uint32_t reserved1030c[317];
+ uint32_t pmugate_con[3];
+ uint32_t reserved1080c[125];
+ uint32_t pmusoftrst_con[3];
+ uint32_t reserved10a08[7550+8191];
+
+ /* pciecru */
+ uint32_t reserved20000[32];
+ uint32_t ppll_con[5];
+ uint32_t reserved20094[155];
+ uint32_t pcieclksel_con[2];
+ uint32_t reserved20308[318];
+ uint32_t pciegate_con;
+};
+check_member(rk3528_cru, pciegate_con, 0x20800);
+
+struct rk3528_grf_clk_priv {
+ struct rk3528_grf *grf;
+};
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3528_PMU_CRU_BASE 0x10000
+#define RK3528_PCIE_CRU_BASE 0x20000
+#define RK3528_DDRPHY_CRU_BASE 0x28000
+#define RK3528_PLL_CON(x) ((x) * 0x4)
+#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
+#define RK3528_MODE_CON 0x280
+#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
+#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
+#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
+#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
+
+#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
+#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
+#define RK3528_DIV_PCLK_DBG_MASK 0x1f
+#define RK3528_DIV_PCLK_DBG_SHIFT 1
+
+enum {
+ /* CRU_CLKSEL_CON00 */
+ CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
+ CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON01 */
+ CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
+ CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
+ CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON02 */
+ CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
+ CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
+ CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
+ CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON03 */
+ CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
+ CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
+ CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
+ CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
+ CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
+ CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
+ CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
+
+ /* PMUCRU_CLKSEL_CON00 */
+ CLK_I2C2_SEL_SHIFT = 0,
+ CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
+
+ /* PCIE_CRU_CLKSEL_CON01 */
+ PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
+ PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
+ PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON32 */
+ DCLK_VOP_SRC0_SEL_SHIFT = 10,
+ DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
+ DCLK_VOP_SRC0_DIV_SHIFT = 2,
+ DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON33 */
+ DCLK_VOP_SRC1_SEL_SHIFT = 8,
+ DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
+ DCLK_VOP_SRC1_DIV_SHIFT = 0,
+ DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON43 */
+ CLK_CORE_CRYPTO_SEL_SHIFT = 14,
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+ ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
+ ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON44 */
+ CLK_PWM0_SEL_SHIFT = 6,
+ CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
+ CLK_PWM1_SEL_SHIFT = 8,
+ CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
+ CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
+ CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
+ CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
+ CLK_PKA_CRYPTO_SEL_SHIFT = 0,
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
+ CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
+ CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
+ CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
+ CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
+ CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON61 */
+ SCLK_SFC_DIV_SHIFT = 6,
+ SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
+ SCLK_SFC_SEL_SHIFT = 12,
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
+ SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
+ SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
+ SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON62 */
+ CCLK_SRC_EMMC_DIV_SHIFT = 0,
+ CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
+ CCLK_SRC_EMMC_SEL_SHIFT = 6,
+ CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_SHIFT = 8,
+ BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON63 */
+ CLK_I2C3_SEL_SHIFT = 12,
+ CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
+ CLK_I2C5_SEL_SHIFT = 14,
+ CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
+ CLK_SPI1_SEL_SHIFT = 10,
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON64 */
+ CLK_I2C6_SEL_SHIFT = 0,
+ CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON74 */
+ CLK_SARADC_DIV_SHIFT = 0,
+ CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
+ CLK_TSADC_DIV_SHIFT = 3,
+ CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
+ CLK_TSADC_TSEN_DIV_SHIFT = 8,
+ CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON79 */
+ CLK_I2C1_SEL_SHIFT = 9,
+ CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
+ CLK_I2C0_SEL_SHIFT = 11,
+ CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
+ CLK_SPI0_SEL_SHIFT = 13,
+ CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON83 */
+ ACLK_VOP_ROOT_DIV_SHIFT = 12,
+ ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
+ ACLK_VOP_ROOT_SEL_SHIFT = 15,
+ ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON84 */
+ DCLK_VOP0_SEL_SHIFT = 0,
+ DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
+ DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
+ DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
+ ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
+ ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
+ DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
+ DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
+
+ /* CRU_CLKSEL_CON85 */
+ CLK_I2C4_SEL_SHIFT = 13,
+ CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
+ CLK_I2C7_SEL_SHIFT = 0,
+ CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
+ CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
+ CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
+ CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
+ CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
+ CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
+ CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
+ CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
+ CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
+ CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
+ BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
+ BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
+ BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
+ BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
+ CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
+ CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
+ CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON04 */
+ CLK_UART0_SRC_DIV_SHIFT = 5,
+ CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON05 */
+ CLK_UART0_FRAC_DIV_SHIFT = 0,
+ CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON06 */
+ SCLK_UART0_SRC_SEL_SHIFT = 0,
+ SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
+ CLK_UART1_SRC_DIV_SHIFT = 2,
+ CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON07 */
+ CLK_UART1_FRAC_DIV_SHIFT = 0,
+ CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON08 */
+ SCLK_UART1_SRC_SEL_SHIFT = 0,
+ SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
+ CLK_UART2_SRC_DIV_SHIFT = 2,
+ CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON09 */
+ CLK_UART2_FRAC_DIV_SHIFT = 0,
+ CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON10 */
+ SCLK_UART2_SRC_SEL_SHIFT = 0,
+ SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
+ CLK_UART3_SRC_DIV_SHIFT = 2,
+ CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON11 */
+ CLK_UART3_FRAC_DIV_SHIFT = 0,
+ CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON12 */
+ SCLK_UART3_SRC_SEL_SHIFT = 0,
+ SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
+ CLK_UART4_SRC_DIV_SHIFT = 2,
+ CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON13 */
+ CLK_UART4_FRAC_DIV_SHIFT = 0,
+ CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON14 */
+ SCLK_UART4_SRC_SEL_SHIFT = 0,
+ SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
+ CLK_UART5_SRC_DIV_SHIFT = 2,
+ CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON15 */
+ CLK_UART5_FRAC_DIV_SHIFT = 0,
+ CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON16 */
+ SCLK_UART5_SRC_SEL_SHIFT = 0,
+ SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
+ CLK_UART6_SRC_DIV_SHIFT = 2,
+ CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON17 */
+ CLK_UART6_FRAC_DIV_SHIFT = 0,
+ CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON18 */
+ SCLK_UART6_SRC_SEL_SHIFT = 0,
+ SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
+ CLK_UART7_SRC_DIV_SHIFT = 2,
+ CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON19 */
+ CLK_UART7_FRAC_DIV_SHIFT = 0,
+ CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
+ /* CRU_CLKSEL_CON20 */
+ SCLK_UART7_SRC_SEL_SHIFT = 0,
+ SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
+ SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
+ SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
+ SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
+
+ /* CRU_CLKSEL_CON60 */
+ CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
+ CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
+ /* CRU_CLKSEL_CON66 */
+ CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
+ CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
+ /* CRU_CLKSEL_CON84 */
+ CLK_GMAC0_SRC_DIV_SHIFT = 3,
+ CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
+};
+
+#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h
new file mode 100644
index 0000000..db67e14
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/cru_rk3562.h
@@ -0,0 +1,416 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author:
+ * Elaine Zhang <zhangqing@rock-chips.com>
+ * Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _ASM_ARCH_CRU_RK3562_H
+#define _ASM_ARCH_CRU_RK3562_H
+
+#define MHz 1000000
+#define KHz 1000
+#define OSC_HZ (24 * MHz)
+
+#define CPU_PVTPLL_HZ (1008 * MHz)
+#define APLL_HZ (600 * MHz)
+#define GPLL_HZ (1188 * MHz)
+#define CPLL_HZ (1000 * MHz)
+#define HPLL_HZ (1000 * MHz)
+
+/* RK3562 pll id */
+enum rk3562_pll_id {
+ APLL,
+ GPLL,
+ VPLL,
+ HPLL,
+ CPLL,
+ DPLL,
+ PLL_COUNT,
+};
+
+struct rk3562_clk_info {
+ unsigned long id;
+ char *name;
+};
+
+struct rk3562_clk_priv {
+ struct rk3562_cru *cru;
+ ulong gpll_hz;
+ ulong vpll_hz;
+ ulong hpll_hz;
+ ulong cpll_hz;
+ ulong armclk_hz;
+ ulong armclk_enter_hz;
+ ulong armclk_init_hz;
+ bool sync_kernel;
+ bool set_armclk_rate;
+};
+
+struct rk3562_cru {
+ /* top cru */
+ uint32_t apll_con[5];
+ uint32_t reserved0014[19];
+ uint32_t gpll_con[5];
+ uint32_t reserved0074[3];
+ uint32_t vpll_con[5];
+ uint32_t reserved0094[3];
+ uint32_t hpll_con[5];
+ uint32_t reserved00b4[19];
+ uint32_t clksel_con[48];
+ uint32_t reserved01c0[80];
+ uint32_t gate_con[28];
+ uint32_t reserved370[36];
+ uint32_t softrst_con[28];
+ uint32_t reserved0470[100];
+ uint32_t mode_con[1];
+ uint32_t reserved0604[3];
+ uint32_t glb_cnt_th;
+ uint32_t glb_srst_fst;
+ uint32_t glb_srst_snd;
+ uint32_t glb_rst_con;
+ uint32_t glb_rst_st;
+ unsigned int sdmmc0_con[2];
+ unsigned int sdmmc1_con[2];
+ uint32_t reserved0634[2];
+ unsigned int emmc_con[1];
+ uint32_t reserved0640[15984];
+
+ /* pmu0 cru */
+ uint32_t reserved10000[64];
+ uint32_t pmu0clksel_con[4];
+ uint32_t reserved10110[28];
+ uint32_t pmu0gate_con[3];
+ uint32_t reserved1018c[29];
+ uint32_t pmu0softrst_con[3];
+ uint32_t reserved1020c[8061];
+
+ /* pmu1 cru */
+ uint32_t reserved18000[16];
+ uint32_t cpll_con[5];
+ uint32_t reserved18054[43];
+ uint32_t pmu1clksel_con[7];
+ uint32_t reserved1811c[25];
+ uint32_t pmu1gate_con[4];
+ uint32_t reserved18190[28];
+ uint32_t pmu1softrst_con[3];
+ uint32_t reserved1820c[93];
+ uint32_t pmu1mode_con[1];
+ uint32_t reserved18384[7967];
+
+ /* ddr cru */
+ uint32_t reserved20000[64];
+ uint32_t ddrclksel_con[2];
+ uint32_t reserved20108[30];
+ uint32_t ddrgate_con[2];
+ uint32_t reserved20188[30];
+ uint32_t ddrsoftrst_con[2];
+ uint32_t reserved20208[8062];
+
+ /* subddr cru */
+ uint32_t reserved28000[8];
+ uint32_t dpll_con[5];
+ uint32_t reserved28034[51];
+ uint32_t sudbddrclksel_con[1];
+ uint32_t reserved28104[31];
+ uint32_t subddrgate_con[1];
+ uint32_t reserved28184[31];
+ uint32_t sudbddrsoftrst_con[1];
+ uint32_t reserved28204[95];
+ uint32_t subddrmode_con[1];
+ uint32_t reserved28384[7967];
+
+ /* peri cru */
+ uint32_t reserved30000[64];
+ uint32_t periclksel_con[48];
+ uint32_t reserved301c0[80];
+ uint32_t perigate_con[18];
+ uint32_t reserved30348[46];
+ uint32_t perisoftrst_con[18];
+ uint32_t reserved30448[143];
+};
+check_member(rk3562_cru, reserved0640[0], 0x00640);
+check_member(rk3562_cru, reserved1020c[0], 0x1020c);
+check_member(rk3562_cru, reserved18384[0], 0x18384);
+check_member(rk3562_cru, reserved20208[0], 0x20208);
+check_member(rk3562_cru, reserved28384[0], 0x28384);
+check_member(rk3562_cru, reserved30448[0], 0x30448);
+
+struct pll_rate_table {
+ unsigned long rate;
+ unsigned int fbdiv;
+ unsigned int postdiv1;
+ unsigned int refdiv;
+ unsigned int postdiv2;
+ unsigned int dsmpd;
+ unsigned int frac;
+};
+
+#define RK3562_PMU0_CRU_BASE 0x10000
+#define RK3562_PMU1_CRU_BASE 0x18000
+#define RK3562_DDR_CRU_BASE 0x20000
+#define RK3562_SUBDDR_CRU_BASE 0x28000
+#define RK3562_PERI_CRU_BASE 0x30000
+
+#define RK3562_PLL_CON(x) ((x) * 0x4)
+#define RK3562_PMU1_PLL_CON(x) ((x) * 0x4 + RK3562_PMU1_CRU_BASE + 0x40)
+#define RK3562_SUBDDR_PLL_CON(x) ((x) * 0x4 + RK3562_SUBDDR_CRU_BASE + 0x20)
+#define RK3562_MODE_CON 0x600
+#define RK3562_PMU1_MODE_CON (RK3562_PMU1_CRU_BASE + 0x380)
+#define RK3562_SUBDDR_MODE_CON (RK3562_SUBDDR_CRU_BASE + 0x380)
+#define RK3562_GLB_SRST_FST 0x614
+#define RK3562_GLB_SRST_SND 0x618
+#define RK3562_GLB_RST_CON 0x61c
+#define RK3562_GLB_RST_ST 0x620
+
+enum {
+ /* CRU_CLKSEL_CON10 */
+ CLK_CORE_PRE_DIV_SHIFT = 0,
+ CLK_CORE_PRE_DIV_MASK = 0x1f << CLK_CORE_PRE_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON11 */
+ ACLK_CORE_PRE_DIV_SHIFT = 0,
+ ACLK_CORE_PRE_DIV_MASK = 0x7 << ACLK_CORE_PRE_DIV_SHIFT,
+ CLK_SCANHS_ACLKM_CORE_DIV_SHIFT = 8,
+ CLK_SCANHS_ACLKM_CORE_DIV_MASK = 0x7 << CLK_SCANHS_ACLKM_CORE_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON12 */
+ PCLK_DBG_PRE_DIV_SHIFT = 0,
+ PCLK_DBG_PRE_DIV_MASK = 0xf << PCLK_DBG_PRE_DIV_SHIFT,
+ CLK_SCANHS_PCLK_DBG_DIV_SHIFT = 8,
+ CLK_SCANHS_PCLK_DBG_DIV_MASK = 0xf << CLK_SCANHS_PCLK_DBG_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON28 */
+ ACLK_VOP_DIV_SHIFT = 0,
+ ACLK_VOP_DIV_MASK = 0x1f << ACLK_VOP_DIV_SHIFT,
+ ACLK_VOP_SEL_SHIFT = 6,
+ ACLK_VOP_SEL_MASK = 0x3 << ACLK_VOP_SEL_SHIFT,
+ ACLK_VOP_SEL_GPLL = 0,
+ ACLK_VOP_SEL_CPLL,
+ ACLK_VOP_SEL_VPLL,
+ ACLK_VOP_SEL_HPLL,
+
+ /* CRU_CLKSEL_CON30 */
+ DCLK_VOP_DIV_SHIFT = 0,
+ DCLK_VOP_DIV_MASK = 0xff << DCLK_VOP_DIV_SHIFT,
+ DCLK_VOP_SEL_SHIFT = 14,
+ DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
+ DCLK_VOP_SEL_GPLL = 0,
+ DCLK_VOP_SEL_HPLL,
+ DCLK_VOP_SEL_VPLL,
+ DCLK_VOP_SEL_APLL,
+
+ /* CRU_CLKSEL_CON31 */
+ DCLK_VOP1_DIV_SHIFT = 0,
+ DCLK_VOP1_DIV_MASK = 0xff << DCLK_VOP1_DIV_SHIFT,
+ DCLK_VOP1_SEL_SHIFT = 14,
+ DCLK_VOP1_SEL_MASK = 0x3 << DCLK_VOP1_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON40 */
+ ACLK_BUS_DIV_SHIFT = 0,
+ ACLK_BUS_DIV_MASK = 0x1f << ACLK_BUS_DIV_SHIFT,
+ ACLK_BUS_SEL_SHIFT = 7,
+ ACLK_BUS_SEL_MASK = 0x1 << ACLK_BUS_SEL_SHIFT,
+ ACLK_BUS_SEL_GPLL = 0,
+ ACLK_BUS_SEL_CPLL,
+ HCLK_BUS_DIV_SHIFT = 8,
+ HCLK_BUS_DIV_MASK = 0x3f << HCLK_BUS_DIV_SHIFT,
+ HCLK_BUS_SEL_SHIFT = 15,
+ HCLK_BUS_SEL_MASK = 0x1 << HCLK_BUS_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON41 */
+ PCLK_BUS_DIV_SHIFT = 0,
+ PCLK_BUS_DIV_MASK = 0x1f << PCLK_BUS_DIV_SHIFT,
+ PCLK_BUS_SEL_SHIFT = 7,
+ PCLK_BUS_SEL_MASK = 0x1 << PCLK_BUS_SEL_SHIFT,
+ CLK_I2C_SEL_SHIFT = 8,
+ CLK_I2C_SEL_MASK = 0x3 << CLK_I2C_SEL_SHIFT,
+ CLK_I2C_SEL_200M = 0,
+ CLK_I2C_SEL_100M,
+ CLK_I2C_SEL_50M,
+ CLK_I2C_SEL_24M,
+ DCLK_BUS_GPIO_SEL_SHIFT = 15,
+ DCLK_BUS_GPIO_SEL_MASK = 0x1 << DCLK_BUS_GPIO_SEL_SHIFT,
+
+ /* CRU_CLKSEL_CON43 */
+ CLK_TSADC_DIV_SHIFT = 0,
+ CLK_TSADC_DIV_MASK = 0x7ff << CLK_TSADC_DIV_SHIFT,
+ CLK_TSADC_TSEN_DIV_SHIFT = 11,
+ CLK_TSADC_TSEN_DIV_MASK = 0x1f << CLK_TSADC_TSEN_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON44 */
+ CLK_SARADC_VCCIO156_DIV_SHIFT = 0,
+ CLK_SARADC_VCCIO156_DIV_MASK = 0xfff << CLK_SARADC_VCCIO156_DIV_SHIFT,
+
+ /* CRU_CLKSEL_CON45 */
+ CLK_GMAC_125M_SEL_SHIFT = 8,
+ CLK_GMAC_125M_SEL_MASK = 0x1 << CLK_GMAC_125M_SEL_SHIFT,
+ CLK_GMAC_125M = 0,
+ CLK_GMAC_24M,
+ CLK_GMAC_50M_SEL_SHIFT = 7,
+ CLK_GMAC_50M_SEL_MASK = 0x1 << CLK_GMAC_50M_SEL_SHIFT,
+ CLK_GMAC_50M = 0,
+
+ /* CRU_CLKSEL_CON46 */
+ CLK_GMAC_ETH_OUT2IO_SEL_SHIFT = 7,
+ CLK_GMAC_ETH_OUT2IO_SEL_MASK = 0x1 << CLK_GMAC_ETH_OUT2IO_SEL_SHIFT,
+ CLK_GMAC_ETH_OUT2IO_GPLL = 0,
+ CLK_GMAC_ETH_OUT2IO_CPLL,
+ CLK_GMAC_ETH_OUT2IO_DIV_SHIFT = 0,
+ CLK_GMAC_ETH_OUT2IO_DIV_MASK = 0x7f,
+
+ /* PMU0CRU_CLKSEL_CON03 */
+ CLK_PMU0_I2C0_DIV_SHIFT = 8,
+ CLK_PMU0_I2C0_DIV_MASK = 0x1f << CLK_PMU0_I2C0_DIV_SHIFT,
+ CLK_PMU0_I2C0_SEL_SHIFT = 14,
+ CLK_PMU0_I2C0_SEL_MASK = 0x3 << CLK_PMU0_I2C0_SEL_SHIFT,
+ CLK_PMU0_I2C0_SEL_200M = 0,
+ CLK_PMU0_I2C0_SEL_24M,
+ CLK_PMU0_I2C0_SEL_32K,
+
+ /* PMU1CRU_CLKSEL_CON02 */
+ CLK_PMU1_UART0_SRC_DIV_SHIFT = 0,
+ CLK_PMU1_UART0_SRC_DIV_MASK = 0xf << CLK_PMU1_UART0_SRC_DIV_SHIFT,
+ CLK_PMU1_UART0_SEL_SHIFT = 6,
+ CLK_PMU1_UART0_SEL_MASK = 0x3 << CLK_PMU1_UART0_SEL_SHIFT,
+
+ /* PMU1CRU_CLKSEL_CON04 */
+ CLK_PMU1_SPI0_DIV_SHIFT = 0,
+ CLK_PMU1_SPI0_DIV_MASK = 0x3 << CLK_PMU1_SPI0_DIV_SHIFT,
+ CLK_PMU1_SPI0_SEL_SHIFT = 6,
+ CLK_PMU1_SPI0_SEL_MASK = 0x3 << CLK_PMU1_SPI0_SEL_SHIFT,
+ CLK_PMU1_SPI0_SEL_200M = 0,
+ CLK_PMU1_SPI0_SEL_24M,
+ CLK_PMU1_SPI0_SEL_32K,
+ CLK_PMU1_PWM0_DIV_SHIFT = 8,
+ CLK_PMU1_PWM0_DIV_MASK = 0x3 << CLK_PMU1_PWM0_DIV_SHIFT,
+ CLK_PMU1_PWM0_SEL_SHIFT = 14,
+ CLK_PMU1_PWM0_SEL_MASK = 0x3 << CLK_PMU1_PWM0_SEL_SHIFT,
+ CLK_PMU1_PWM0_SEL_200M = 0,
+ CLK_PMU1_PWM0_SEL_24M,
+ CLK_PMU1_PWM0_SEL_32K,
+
+ /* PERICRU_CLKSEL_CON00 */
+ ACLK_PERI_DIV_SHIFT = 0,
+ ACLK_PERI_DIV_MASK = 0x1f << ACLK_PERI_DIV_SHIFT,
+ ACLK_PERI_SEL_SHIFT = 7,
+ ACLK_PERI_SEL_MASK = 0x1 << ACLK_PERI_SEL_SHIFT,
+ ACLK_PERI_SEL_GPLL = 0,
+ ACLK_PERI_SEL_CPLL,
+ HCLK_PERI_DIV_SHIFT = 8,
+ HCLK_PERI_DIV_MASK = 0x3f << HCLK_PERI_DIV_SHIFT,
+ HCLK_PERI_SEL_SHIFT = 15,
+ HCLK_PERI_SEL_MASK = 0x1 << HCLK_PERI_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON01 */
+ PCLK_PERI_DIV_SHIFT = 0,
+ PCLK_PERI_DIV_MASK = 0x1f << PCLK_PERI_DIV_SHIFT,
+ PCLK_PERI_SEL_SHIFT = 7,
+ PCLK_PERI_SEL_MASK = 0x1 << PCLK_PERI_SEL_SHIFT,
+ CLK_SAI0_SRC_DIV_SHIFT = 8,
+ CLK_SAI0_SRC_DIV_MASK = 0x3f << CLK_SAI0_SRC_DIV_SHIFT,
+ CLK_SAI0_SRC_SEL_SHIFT = 14,
+ CLK_SAI0_SRC_SEL_MASK = 0x3 << CLK_SAI0_SRC_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON16 */
+ CCLK_SDMMC0_DIV_SHIFT = 0,
+ CCLK_SDMMC0_DIV_MASK = 0xff << CCLK_SDMMC0_DIV_SHIFT,
+ CCLK_SDMMC0_SEL_SHIFT = 14,
+ CCLK_SDMMC0_SEL_MASK = 0x3 << CCLK_SDMMC0_SEL_SHIFT,
+ CCLK_SDMMC_SEL_GPLL = 0,
+ CCLK_SDMMC_SEL_CPLL,
+ CCLK_SDMMC_SEL_24M,
+ CCLK_SDMMC_SEL_HPLL,
+
+ /* PERICRU_CLKSEL_CON17 */
+ CCLK_SDMMC1_DIV_SHIFT = 0,
+ CCLK_SDMMC1_DIV_MASK = 0xff << CCLK_SDMMC1_DIV_SHIFT,
+ CCLK_SDMMC1_SEL_SHIFT = 14,
+ CCLK_SDMMC1_SEL_MASK = 0x3 << CCLK_SDMMC1_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON18 */
+ CCLK_EMMC_DIV_SHIFT = 0,
+ CCLK_EMMC_DIV_MASK = 0xff << CCLK_EMMC_DIV_SHIFT,
+ CCLK_EMMC_SEL_SHIFT = 14,
+ CCLK_EMMC_SEL_MASK = 0x3 << CCLK_EMMC_SEL_SHIFT,
+ CCLK_EMMC_SEL_GPLL = 0,
+ CCLK_EMMC_SEL_CPLL,
+ CCLK_EMMC_SEL_24M,
+ CCLK_EMMC_SEL_HPLL,
+
+ /* PERICRU_CLKSEL_CON19 */
+ BCLK_EMMC_DIV_SHIFT = 8,
+ BCLK_EMMC_DIV_MASK = 0x7f << BCLK_EMMC_DIV_SHIFT,
+ BCLK_EMMC_SEL_SHIFT = 15,
+ BCLK_EMMC_SEL_MASK = 0x1 << BCLK_EMMC_SEL_SHIFT,
+ BCLK_EMMC_SEL_GPLL = 0,
+ BCLK_EMMC_SEL_CPLL,
+
+ /* PERICRU_CLKSEL_CON20 */
+ SCLK_SFC_DIV_SHIFT = 0,
+ SCLK_SFC_DIV_MASK = 0xff << SCLK_SFC_DIV_SHIFT,
+ SCLK_SFC_SEL_SHIFT = 8,
+ SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
+ SCLK_SFC_SRC_SEL_GPLL = 0,
+ SCLK_SFC_SRC_SEL_CPLL,
+ SCLK_SFC_SRC_SEL_24M,
+ CLK_SPI1_SEL_SHIFT = 12,
+ CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
+ CLK_SPI_SEL_200M = 0,
+ CLK_SPI_SEL_100M,
+ CLK_SPI_SEL_50M,
+ CLK_SPI_SEL_24M,
+ CLK_SPI2_SEL_SHIFT = 14,
+ CLK_SPI2_SEL_MASK = 0x3 << CLK_SPI2_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON21 */
+ CLK_UART_SRC_DIV_SHIFT = 0,
+ CLK_UART_SRC_DIV_MASK = 0x7f << CLK_UART_SRC_DIV_SHIFT,
+ CLK_UART_SRC_SEL_SHIFT = 8,
+ CLK_UART_SRC_SEL_MASK = 0x1 << CLK_UART_SRC_SEL_SHIFT,
+ CLK_UART_SRC_SEL_GPLL = 0,
+ CLK_UART_SRC_SEL_CPLL,
+ CLK_UART_SEL_SHIFT = 14,
+ CLK_UART_SEL_MASK = 0x3 << CLK_UART_SEL_SHIFT,
+ CLK_UART_SEL_SRC = 0,
+ CLK_UART_SEL_FRAC,
+ CLK_UART_SEL_XIN24M,
+
+ /* PERICRU_CLKSEL_CON22 */
+ CLK_UART_FRAC_NUMERATOR_SHIFT = 16,
+ CLK_UART_FRAC_NUMERATOR_MASK = 0xffff << 16,
+ CLK_UART_FRAC_DENOMINATOR_SHIFT = 0,
+ CLK_UART_FRAC_DENOMINATOR_MASK = 0xffff,
+
+ /* PERICRU_CLKSEL_CON40 */
+ CLK_PWM1_PERI_SEL_SHIFT = 0,
+ CLK_PWM1_PERI_SEL_MASK = 0x3 << CLK_PWM1_PERI_SEL_SHIFT,
+ CLK_PWM_SEL_100M = 0,
+ CLK_PWM_SEL_50M,
+ CLK_PWM_SEL_24M,
+ CLK_PWM2_PERI_SEL_SHIFT = 6,
+ CLK_PWM2_PERI_SEL_MASK = 0x3 << CLK_PWM2_PERI_SEL_SHIFT,
+ CLK_PWM3_PERI_SEL_SHIFT = 8,
+ CLK_PWM3_PERI_SEL_MASK = 0x3 << CLK_PWM3_PERI_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON43 */
+ CLK_CORE_CRYPTO_SEL_SHIFT = 0,
+ CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
+ CLK_CORE_CRYPTO_SEL_200M = 0,
+ CLK_CORE_CRYPTO_SEL_100M,
+ CLK_CORE_CRYPTO_SEL_24M,
+ CLK_PKA_CRYPTO_SEL_SHIFT = 6,
+ CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
+ CLK_PKA_CRYPTO_SEL_300M = 0,
+ CLK_PKA_CRYPTO_SEL_200M,
+ CLK_PKA_CRYPTO_SEL_100M,
+ CLK_PKA_CRYPTO_SEL_24M,
+ TCLK_PERI_WDT_SEL_SHIFT = 15,
+ TCLK_PERI_WDT_SEL_MASK = 0x1 << TCLK_PERI_WDT_SEL_SHIFT,
+
+ /* PERICRU_CLKSEL_CON46 */
+ CLK_SARADC_DIV_SHIFT = 0,
+ CLK_SARADC_DIV_MASK = 0xfff << CLK_SARADC_DIV_SHIFT,
+};
+#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/fit.h b/u-boot/arch/arm/include/asm/arch-rockchip/fit.h
index d10d2f2..36971ef 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/fit.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/fit.h
@@ -14,7 +14,7 @@
int fit_image_pre_process(const void *fit);
int fit_image_fail_process(const void *fit);
-int fit_image_init_resource(void);
int fit_image_read_dtb(void *fdt_addr);
+ulong fit_image_init_resource(struct blk_desc *dev_desc);
#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h
new file mode 100644
index 0000000..222fcbd
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3528.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3528_H
+#define _ASM_ARCH_GRF_RK3528_H
+
+#include <common.h>
+
+struct rk3528_grf {
+ uint32_t reserved0[0x40018 / 4];
+
+ /* vpugrf*/
+ uint32_t gmac1_con0; /* Address Offset: 0x40018 */
+ uint32_t gmac1_con1; /* Address Offset: 0x4001c */
+ uint32_t reserved1[(0x60018 - 0x4001c) / 4 - 1];
+
+ /* vogrf */
+ uint32_t gmac0_con; /* Address Offset: 0x60018 */
+ uint32_t macphy_con0; /* Address Offset: 0x6001c */
+ uint32_t macphy_con1; /* Address Offset: 0x60020 */
+ uint32_t sdmmc_con0; /* Address Offset: 0x60024 */
+ uint32_t sdmmc_con1; /* Address Offset: 0x60028 */
+ uint32_t reserved2[(0x70000 - 0x60028) / 4 - 1];
+
+ /* pmugrf */
+ uint32_t soc_con[8]; /* Address Offset: 0x70000 */
+ uint32_t soc_status; /* Address Offset: 0x70020 */
+ uint32_t reserved3[3]; /* Address Offset: 0x70024 */
+ uint32_t pmuio_vsel; /* Address Offset: 0x70030 */
+ uint32_t reserved4[3]; /* Address Offset: 0x70034 */
+ uint32_t mem_con; /* Address Offset: 0x70040 */
+ uint32_t reserved5[47]; /* Address Offset: 0x70044 */
+ uint32_t rstfunc_status; /* Address Offset: 0x70100 */
+ uint32_t rstfunc_clr; /* Address Offset: 0x70104 */
+ uint32_t reserved6[62]; /* Address Offset: 0x70108 */
+ uint32_t os_reg0; /* Address Offset: 0x70200 */
+ uint32_t os_reg1; /* Address Offset: 0x70204 */
+ uint32_t os_reg2; /* Address Offset: 0x70208 */
+ uint32_t os_reg3; /* Address Offset: 0x7020C */
+ uint32_t os_reg4; /* Address Offset: 0x70210 */
+ uint32_t os_reg5; /* Address Offset: 0x70214 */
+ uint32_t os_reg6; /* Address Offset: 0x70218 */
+ uint32_t os_reg7; /* Address Offset: 0x7021C */
+ uint32_t os_reg8; /* Address Offset: 0x70220 */
+ uint32_t os_reg9; /* Address Offset: 0x70224 */
+ uint32_t os_reg10; /* Address Offset: 0x70228 */
+ uint32_t os_reg11; /* Address Offset: 0x7022C */
+ uint32_t os_reg12; /* Address Offset: 0x70230 */
+ uint32_t os_reg13; /* Address Offset: 0x70234 */
+ uint32_t os_reg14; /* Address Offset: 0x70238 */
+ uint32_t os_reg15; /* Address Offset: 0x7023C */
+ uint32_t os_reg16; /* Address Offset: 0x70240 */
+ uint32_t os_reg17; /* Address Offset: 0x70244 */
+ uint32_t os_reg18; /* Address Offset: 0x70248 */
+ uint32_t os_reg19; /* Address Offset: 0x7024C */
+ uint32_t os_reg20; /* Address Offset: 0x70250 */
+ uint32_t os_reg21; /* Address Offset: 0x70254 */
+ uint32_t os_reg22; /* Address Offset: 0x70258 */
+ uint32_t os_reg23; /* Address Offset: 0x7025C */
+ uint32_t reserved7[(0x80000 - 0x7025C) / 4 - 1];
+
+ uint32_t grf_sys_con[2]; /* Address Offset: 0x80000 */
+ uint32_t reserved8[2]; /* Address Offset: 0x80008 */
+ uint32_t grf_sys_status; /* Address Offset: 0x80010 */
+ uint32_t reserved9[3]; /* Address Offset: 0x80014 */
+ uint32_t grf_biu_con[2]; /* Address Offset: 0x80020 */
+ uint32_t reserved10[2]; /* Address Offset: 0x80028 */
+ uint32_t grf_biu_status[3]; /* Address Offset: 0x80030 */
+ uint32_t reserved11[17]; /* Address Offset: 0x8003C */
+ uint32_t grf_sys_mem_con[5]; /* Address Offset: 0x80080 */
+ uint32_t reserved12[59]; /* Address Offset: 0x80094 */
+ uint32_t grf_soc_code; /* Address Offset: 0x80180 */
+ uint32_t reserved13[3]; /* Address Offset: 0x80184 */
+ uint32_t grf_soc_version; /* Address Offset: 0x80190 */
+ uint32_t reserved14[3]; /* Address Offset: 0x80194 */
+ uint32_t grf_chip_id; /* Address Offset: 0x801A0 */
+ uint32_t reserved15[3]; /* Address Offset: 0x801A4 */
+ uint32_t grf_chip_version; /* Address Offset: 0x801B0 */
+ uint32_t reserved16[(0x10000 - 0x81b0) / 4 - 1];
+
+};
+
+check_member(rk3528_grf, sdmmc_con1, 0x60028);
+check_member(rk3528_grf, os_reg23, 0x7025C);
+check_member(rk3528_grf, grf_chip_version, 0x801B0);
+
+#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h
new file mode 100644
index 0000000..31d5fad
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/grf_rk3562.h
@@ -0,0 +1,76 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_GRF_RK3562_H
+#define _ASM_ARCH_GRF_RK3562_H
+
+#include <common.h>
+
+struct rk3562_pmu_grf {
+ /* pmugrf */
+ uint32_t reserved1[(0x0100 - 0x0000) / 4]; /* address offset: 0x0000 */
+ uint32_t soc_con[13]; /* address offset: 0x0100 */
+ uint32_t soc_status[1]; /* address offset: 0x0134 */
+ uint32_t reserved2[(0x0180 - 0x0134) / 4 - 1]; /* address offset: 0x0138 */
+ uint32_t pvtm_con[1]; /* address offset: 0x0180 */
+ uint32_t reserved3[(0x0200 - 0x0180) / 4 - 1]; /* address offset: 0x0184 */
+ uint32_t os_reg[12]; /* address offset: 0x0200 */
+ uint32_t reset_function_status; /* address offset: 0x0230 */
+ uint32_t reset_function_clr; /* address offset: 0x0234 */
+ uint32_t reserved4[(0x0380 - 0x0234) / 4 - 1]; /* address offset: 0x0238 */
+ uint32_t sig_detect_con; /* address offset: 0x0380 */
+ uint32_t reserved5[(0x0390 - 0x0380) / 4 - 1]; /* address offset: 0x0384 */
+ uint32_t sig_detect_status; /* address offset: 0x0390 */
+ uint32_t reserved6[(0x03a0 - 0x0390) / 4 - 1]; /* address offset: 0x0394 */
+ uint32_t sig_detect_status_clear; /* address offset: 0x03a0 */
+ uint32_t reserved7[(0x03b0 - 0x03a0) / 4 - 1]; /* address offset: 0x03a4 */
+ uint32_t sdmmc_det_counter; /* address offset: 0x03b0 */
+};
+
+check_member(rk3562_pmu_grf, sdmmc_det_counter, 0x03b0);
+
+struct rk3562_grf {
+ /* sysgrf */
+ uint32_t reserved1[(0x0400 - 0x0000) / 4]; /* address offset: 0x0000 */
+ uint32_t soc_con[7]; /* address offset: 0x0400 */
+ uint32_t reserved2[(0x0430 - 0x0400) / 4 - 7]; /* address offset: 0x041c */
+ uint32_t soc_status[3]; /* address offset: 0x0430 */
+ uint32_t reserved3; /* address offset: 0x043c */
+ uint32_t biu_con[2]; /* address offset: 0x0440 */
+ uint32_t reserved4[(0x0460 - 0x0440) / 4 - 2]; /* address offset: 0x0448 */
+ uint32_t ram_con; /* address offset: 0x0460 */
+ uint32_t core_ram_con; /* address offset: 0x0464 */
+ uint32_t reserved5[(0x0500 - 0x0464) / 4 - 1]; /* address offset: 0x0468 */
+ uint32_t cpu_con[2]; /* address offset: 0x0500 */
+ uint32_t reserved6[(0x0510 - 0x0500) / 4 - 2]; /* address offset: 0x0508 */
+ uint32_t cpu_status[2]; /* address offset: 0x0510 */
+ uint32_t reserved7[(0x0520 - 0x0510) / 4 - 2]; /* address offset: 0x0518 */
+ uint32_t vi_con[2]; /* address offset: 0x0520 */
+ uint32_t reserved8[(0x0530 - 0x0520) / 4 - 2]; /* address offset: 0x0528 */
+ uint32_t vi_status[1]; /* address offset: 0x0530 */
+ uint32_t reserved9[(0x0570 - 0x0530) / 4 - 1]; /* address offset: 0x0534 */
+ uint32_t gpu_con[2]; /* address offset: 0x0570 */
+ uint32_t reserved10[(0x0580 - 0x0570) / 4 - 2]; /* address offset: 0x0578 */
+ uint32_t tsadc_con; /* address offset: 0x0580 */
+ uint32_t reserved11[(0x05d0 - 0x0580) / 4 - 1]; /* address offset: 0x0584 */
+ uint32_t vo_con[2]; /* address offset: 0x05d0 */
+ uint32_t reserved12[(0x0600 - 0x05d0) / 4 - 2]; /* address offset: 0x05d8 */
+ uint32_t top_pvtpll_con[4]; /* address offset: 0x0600 */
+ uint32_t top_pvtpll_status[2]; /* address offset: 0x0610 */
+ uint32_t reserved13[(0x0620 - 0x0610) / 4 - 2]; /* address offset: 0x0618 */
+ uint32_t cpu_pvtpll_con[4]; /* address offset: 0x0620 */
+ uint32_t cpu_pvtpll_status[2]; /* address offset: 0x0630 */
+ uint32_t reserved14[(0x0640 - 0x0630) / 4 - 2]; /* address offset: 0x0638 */
+ uint32_t gpu_pvtpll_con[4]; /* address offset: 0x0640 */
+ uint32_t gpu_pvtpll_status[2]; /* address offset: 0x0650 */
+ uint32_t reserved15[(0x0660 - 0x0650) / 4 - 2]; /* address offset: 0x0658 */
+ uint32_t npu_pvtpll_con[4]; /* address offset: 0x0660 */
+ uint32_t npu_pvtpll_status[2]; /* address offset: 0x0670 */
+ uint32_t reserved16[(0x0800 - 0x0670) / 4 - 2]; /* address offset: 0x0678 */
+ uint32_t chip_id; /* address offset: 0x0800 */
+};
+check_member(rk3562_grf, chip_id, 0x0800);
+
+#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h
new file mode 100644
index 0000000..74c6116
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3528.h
@@ -0,0 +1,196 @@
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_IOC_RK3528_H
+#define _ASM_ARCH_IOC_RK3528_H
+
+#include <common.h>
+
+struct rk3528_gpio0_ioc {
+ uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x0000 */
+ uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x0004 */
+ uint32_t reserved0008[62]; /* Address Offset: 0x0008 */
+ uint32_t gpio0a_ds[3]; /* Address Offset: 0x0100 */
+ uint32_t reserved010c[61]; /* Address Offset: 0x010C */
+ uint32_t gpio0a_pull; /* Address Offset: 0x0200 */
+ uint32_t reserved0204[63]; /* Address Offset: 0x0204 */
+ uint32_t gpio0a_ie; /* Address Offset: 0x0300 */
+ uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
+ uint32_t gpio0a_smt; /* Address Offset: 0x0400 */
+ uint32_t reserved0404[63]; /* Address Offset: 0x0404 */
+ uint32_t gpio0a_sus; /* Address Offset: 0x0500 */
+ uint32_t reserved0504[63]; /* Address Offset: 0x0504 */
+ uint32_t gpio0a_sl; /* Address Offset: 0x0600 */
+ uint32_t reserved0604[63]; /* Address Offset: 0x0604 */
+ uint32_t gpio0a_od; /* Address Offset: 0x0700 */
+ uint32_t vcc5vio_ctrl; /* Address Offset: 0x0704 */
+};
+check_member(rk3528_gpio0_ioc, vcc5vio_ctrl, 0x0704);
+
+struct rk3528_gpio1_ioc {
+ uint32_t reserved0000[8]; /* Address Offset: 0x0000 */
+ uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0020 */
+ uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0024 */
+ uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0028 */
+ uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x002C */
+ uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0030 */
+ uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0034 */
+ uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0038 */
+ uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x003C */
+ uint32_t reserved0040[56]; /* Address Offset: 0x0040 */
+ uint32_t gpio1a_ds[4]; /* Address Offset: 0x0120 */
+ uint32_t gpio1b_ds[4]; /* Address Offset: 0x0130 */
+ uint32_t gpio1c_ds[4]; /* Address Offset: 0x0140 */
+ uint32_t gpio1d_ds[4]; /* Address Offset: 0x0150 */
+ uint32_t reserved0160[44]; /* Address Offset: 0x0160 */
+ uint32_t gpio1a_pull; /* Address Offset: 0x0210 */
+ uint32_t gpio1b_pull; /* Address Offset: 0x0214 */
+ uint32_t gpio1c_pull; /* Address Offset: 0x0218 */
+ uint32_t gpio1d_pull; /* Address Offset: 0x021C */
+ uint32_t reserved0220[60]; /* Address Offset: 0x0220 */
+ uint32_t gpio1a_ie; /* Address Offset: 0x0310 */
+ uint32_t gpio1b_ie; /* Address Offset: 0x0314 */
+ uint32_t gpio1c_ie; /* Address Offset: 0x0318 */
+ uint32_t gpio1d_ie; /* Address Offset: 0x031C */
+ uint32_t reserved0320[60]; /* Address Offset: 0x0320 */
+ uint32_t gpio1a_smt; /* Address Offset: 0x0410 */
+ uint32_t gpio1b_smt; /* Address Offset: 0x0414 */
+ uint32_t gpio1c_smt; /* Address Offset: 0x0418 */
+ uint32_t gpio1d_smt; /* Address Offset: 0x041C */
+ uint32_t reserved0420[60]; /* Address Offset: 0x0420 */
+ uint32_t gpio1a_sus; /* Address Offset: 0x0510 */
+ uint32_t gpio1b_sus; /* Address Offset: 0x0514 */
+ uint32_t gpio1c_sus; /* Address Offset: 0x0518 */
+ uint32_t gpio1d_sus; /* Address Offset: 0x051C */
+ uint32_t reserved0520[60]; /* Address Offset: 0x0520 */
+ uint32_t gpio1a_sl; /* Address Offset: 0x0610 */
+ uint32_t gpio1b_sl; /* Address Offset: 0x0614 */
+ uint32_t gpio1c_sl; /* Address Offset: 0x0618 */
+ uint32_t gpio1d_sl; /* Address Offset: 0x061C */
+ uint32_t reserved0620[60]; /* Address Offset: 0x0620 */
+ uint32_t gpio1a_od; /* Address Offset: 0x0710 */
+ uint32_t gpio1b_od; /* Address Offset: 0x0714 */
+ uint32_t gpio1c_od; /* Address Offset: 0x0718 */
+ uint32_t gpio1d_od; /* Address Offset: 0x071C */
+ uint32_t reserved0720[60]; /* Address Offset: 0x0720 */
+ uint32_t vccio0_poc; /* Address Offset: 0x0810 */
+ uint32_t reserved0814[3]; /* Address Offset: 0x0814 */
+ uint32_t vccio1_poc; /* Address Offset: 0x0820 */
+};
+check_member(rk3528_gpio1_ioc, vccio1_poc, 0x0820);
+
+struct rk3528_gpio2_ioc {
+ uint32_t reserved0000[16]; /* Address Offset: 0x0000 */
+ uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0040 */
+ uint32_t gpio2a_iomux_sel_h; /* Address Offset: 0x0044 */
+ uint32_t reserved0048[70]; /* Address Offset: 0x0048 */
+ uint32_t gpio2a_ds[4]; /* Address Offset: 0x0160 */
+ uint32_t reserved0170[44]; /* Address Offset: 0x0170 */
+ uint32_t gpio2a_pull; /* Address Offset: 0x0220 */
+ uint32_t reserved0224[63]; /* Address Offset: 0x0224 */
+ uint32_t gpio2a_ie; /* Address Offset: 0x0320 */
+ uint32_t reserved0324[63]; /* Address Offset: 0x0324 */
+ uint32_t gpio2a_smt; /* Address Offset: 0x0420 */
+ uint32_t reserved0424[63]; /* Address Offset: 0x0424 */
+ uint32_t gpio2a_sus; /* Address Offset: 0x0520 */
+ uint32_t reserved0524[63]; /* Address Offset: 0x0524 */
+ uint32_t gpio2a_sl; /* Address Offset: 0x0620 */
+ uint32_t reserved0624[63]; /* Address Offset: 0x0624 */
+ uint32_t gpio2a_od; /* Address Offset: 0x0720 */
+ uint32_t reserved0724[67]; /* Address Offset: 0x0724 */
+ uint32_t vccio2_poc; /* Address Offset: 0x0830 */
+};
+check_member(rk3528_gpio2_ioc, vccio2_poc, 0x0830);
+
+struct rk3528_gpio3_ioc {
+ uint32_t reserved0000[24]; /* Address Offset: 0x0000 */
+ uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x0060 */
+ uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x0064 */
+ uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x0068 */
+ uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x006C */
+ uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x0070 */
+ uint32_t reserved0074[71]; /* Address Offset: 0x0074 */
+ uint32_t gpio3a_ds[4]; /* Address Offset: 0x0190 */
+ uint32_t gpio3b_ds[4]; /* Address Offset: 0x01A0 */
+ uint32_t gpio3c_ds[2]; /* Address Offset: 0x01B0 */
+ uint32_t reserved01b8[30]; /* Address Offset: 0x01B8 */
+ uint32_t gpio3a_pull; /* Address Offset: 0x0230 */
+ uint32_t gpio3b_pull; /* Address Offset: 0x0234 */
+ uint32_t gpio3c_pull; /* Address Offset: 0x0238 */
+ uint32_t reserved023c[61]; /* Address Offset: 0x023C */
+ uint32_t gpio3a_ie; /* Address Offset: 0x0330 */
+ uint32_t gpio3b_ie; /* Address Offset: 0x0334 */
+ uint32_t gpio3c_ie; /* Address Offset: 0x0338 */
+ uint32_t reserved033c[61]; /* Address Offset: 0x033C */
+ uint32_t gpio3a_smt; /* Address Offset: 0x0430 */
+ uint32_t gpio3b_smt; /* Address Offset: 0x0434 */
+ uint32_t gpio3c_smt; /* Address Offset: 0x0438 */
+ uint32_t reserved043c[61]; /* Address Offset: 0x043C */
+ uint32_t gpio3a_sus; /* Address Offset: 0x0530 */
+ uint32_t gpio3b_sus; /* Address Offset: 0x0534 */
+ uint32_t gpio3c_sus; /* Address Offset: 0x0538 */
+ uint32_t reserved053c[61]; /* Address Offset: 0x053C */
+ uint32_t gpio3a_sl; /* Address Offset: 0x0630 */
+ uint32_t gpio3b_sl; /* Address Offset: 0x0634 */
+ uint32_t gpio3c_sl; /* Address Offset: 0x0638 */
+ uint32_t reserved063c[61]; /* Address Offset: 0x063C */
+ uint32_t gpio3a_od; /* Address Offset: 0x0730 */
+ uint32_t gpio3b_od; /* Address Offset: 0x0734 */
+ uint32_t gpio3c_od; /* Address Offset: 0x0738 */
+ uint32_t reserved073c[65]; /* Address Offset: 0x073C */
+ uint32_t vccio3_poc; /* Address Offset: 0x0840 */
+};
+check_member(rk3528_gpio3_ioc, vccio3_poc, 0x0840);
+
+struct rk3528_gpio4_ioc {
+ uint32_t reserved0000[32]; /* Address Offset: 0x0000 */
+ uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x0080 */
+ uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x0084 */
+ uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x0088 */
+ uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x008C */
+ uint32_t gpio4c_iomux_sel_l; /* Address Offset: 0x0090 */
+ uint32_t gpio4c_iomux_sel_h; /* Address Offset: 0x0094 */
+ uint32_t gpio4d_iomux_sel_l; /* Address Offset: 0x0098 */
+ uint32_t reserved009c[73]; /* Address Offset: 0x009C */
+ uint32_t gpio4a_ds[4]; /* Address Offset: 0x01C0 */
+ uint32_t gpio4b_ds[4]; /* Address Offset: 0x01D0 */
+ uint32_t gpio4c_ds[4]; /* Address Offset: 0x01E0 */
+ uint32_t gpio4d_ds[1]; /* Address Offset: 0x01F0 */
+ uint32_t reserved01f4[19]; /* Address Offset: 0x01F4 */
+ uint32_t gpio4a_pull; /* Address Offset: 0x0240 */
+ uint32_t gpio4b_pull; /* Address Offset: 0x0244 */
+ uint32_t gpio4c_pull; /* Address Offset: 0x0248 */
+ uint32_t gpio4d_pull; /* Address Offset: 0x024C */
+ uint32_t reserved0250[60]; /* Address Offset: 0x0250 */
+ uint32_t gpio4a_ie; /* Address Offset: 0x0340 */
+ uint32_t gpio4b_ie; /* Address Offset: 0x0344 */
+ uint32_t gpio4c_ie; /* Address Offset: 0x0348 */
+ uint32_t gpio4d_ie; /* Address Offset: 0x034C */
+ uint32_t reserved0350[60]; /* Address Offset: 0x0350 */
+ uint32_t gpio4a_smt; /* Address Offset: 0x0440 */
+ uint32_t gpio4b_smt; /* Address Offset: 0x0444 */
+ uint32_t gpio4c_smt; /* Address Offset: 0x0448 */
+ uint32_t gpio4d_smt; /* Address Offset: 0x044C */
+ uint32_t reserved0450[60]; /* Address Offset: 0x0450 */
+ uint32_t gpio4a_sus; /* Address Offset: 0x0540 */
+ uint32_t gpio4b_sus; /* Address Offset: 0x0544 */
+ uint32_t gpio4c_sus; /* Address Offset: 0x0548 */
+ uint32_t gpio4d_sus; /* Address Offset: 0x054C */
+ uint32_t reserved0550[60]; /* Address Offset: 0x0550 */
+ uint32_t gpio4a_sl; /* Address Offset: 0x0640 */
+ uint32_t gpio4b_sl; /* Address Offset: 0x0644 */
+ uint32_t gpio4c_sl; /* Address Offset: 0x0648 */
+ uint32_t gpio4d_sl; /* Address Offset: 0x064C */
+ uint32_t reserved0650[60]; /* Address Offset: 0x0650 */
+ uint32_t gpio4a_od; /* Address Offset: 0x0740 */
+ uint32_t gpio4b_od; /* Address Offset: 0x0744 */
+ uint32_t gpio4c_od; /* Address Offset: 0x0748 */
+ uint32_t gpio4d_od; /* Address Offset: 0x074C */
+ uint32_t reserved0750[64]; /* Address Offset: 0x0750 */
+ uint32_t vccio4_poc; /* Address Offset: 0x0850 */
+};
+check_member(rk3528_gpio4_ioc, vccio4_poc, 0x0850);
+#endif
+
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h
new file mode 100644
index 0000000..efe5729
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/ioc_rk3562.h
@@ -0,0 +1,211 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _ASM_ARCH_IOC_RK3562_H
+#define _ASM_ARCH_IOC_RK3562_H
+
+#include <common.h>
+
+struct rk3562_ioc {
+ uint32_t gpio1a_iomux_sel_l; /* Address Offset: 0x0000 */
+ uint32_t gpio1a_iomux_sel_h; /* Address Offset: 0x0004 */
+ uint32_t gpio1b_iomux_sel_l; /* Address Offset: 0x0008 */
+ uint32_t gpio1b_iomux_sel_h; /* Address Offset: 0x000C */
+ uint32_t gpio1c_iomux_sel_l; /* Address Offset: 0x0010 */
+ uint32_t gpio1c_iomux_sel_h; /* Address Offset: 0x0014 */
+ uint32_t gpio1d_iomux_sel_l; /* Address Offset: 0x0018 */
+ uint32_t gpio1d_iomux_sel_h; /* Address Offset: 0x001C */
+ uint32_t gpio2a_iomux_sel_l; /* Address Offset: 0x0020 */
+ uint32_t reserved0024[23]; /* Address Offset: 0x0024 */
+ uint32_t gpio1a_p; /* Address Offset: 0x0080 */
+ uint32_t gpio1b_p; /* Address Offset: 0x0084 */
+ uint32_t gpio1c_p; /* Address Offset: 0x0088 */
+ uint32_t gpio1d_p; /* Address Offset: 0x008C */
+ uint32_t gpio2a_p; /* Address Offset: 0x0090 */
+ uint32_t reserved0094[11]; /* Address Offset: 0x0094 */
+ uint32_t gpio1a_ie; /* Address Offset: 0x00C0 */
+ uint32_t gpio1b_ie; /* Address Offset: 0x00C4 */
+ uint32_t gpio1c_ie; /* Address Offset: 0x00C8 */
+ uint32_t gpio1d_ie; /* Address Offset: 0x00CC */
+ uint32_t gpio2a_ie; /* Address Offset: 0x00D0 */
+ uint32_t reserved00d4[11]; /* Address Offset: 0x00D4 */
+ uint32_t gpio1a_od; /* Address Offset: 0x0100 */
+ uint32_t gpio1b_od; /* Address Offset: 0x0104 */
+ uint32_t gpio1c_od; /* Address Offset: 0x0108 */
+ uint32_t gpio1d_od; /* Address Offset: 0x010C */
+ uint32_t gpio2a_od; /* Address Offset: 0x0110 */
+ uint32_t reserved0114[11]; /* Address Offset: 0x0114 */
+ uint32_t gpio1a_sus; /* Address Offset: 0x0140 */
+ uint32_t gpio1b_sus; /* Address Offset: 0x0144 */
+ uint32_t gpio1c_sus; /* Address Offset: 0x0148 */
+ uint32_t gpio1d_sus; /* Address Offset: 0x014C */
+ uint32_t gpio2a_sus; /* Address Offset: 0x0150 */
+ uint32_t reserved0154[11]; /* Address Offset: 0x0154 */
+ uint32_t gpio1a_sl; /* Address Offset: 0x0180 */
+ uint32_t gpio1b_sl; /* Address Offset: 0x0184 */
+ uint32_t gpio1c_sl; /* Address Offset: 0x0188 */
+ uint32_t gpio1d_sl; /* Address Offset: 0x018C */
+ uint32_t gpio2a_sl; /* Address Offset: 0x0190 */
+ uint32_t reserved0194[27]; /* Address Offset: 0x0194 */
+ uint32_t gpio1a_ds0; /* Address Offset: 0x0200 */
+ uint32_t gpio1a_ds1; /* Address Offset: 0x0204 */
+ uint32_t gpio1a_ds2; /* Address Offset: 0x0208 */
+ uint32_t gpio1a_ds3; /* Address Offset: 0x020C */
+ uint32_t gpio1b_ds0; /* Address Offset: 0x0210 */
+ uint32_t gpio1b_ds1; /* Address Offset: 0x0214 */
+ uint32_t gpio1b_ds2; /* Address Offset: 0x0218 */
+ uint32_t gpio1b_ds3; /* Address Offset: 0x021C */
+ uint32_t gpio1c_ds0; /* Address Offset: 0x0220 */
+ uint32_t gpio1c_ds1; /* Address Offset: 0x0224 */
+ uint32_t gpio1c_ds2; /* Address Offset: 0x0228 */
+ uint32_t gpio1c_ds3; /* Address Offset: 0x022C */
+ uint32_t gpio1d_ds0; /* Address Offset: 0x0230 */
+ uint32_t gpio1d_ds1; /* Address Offset: 0x0234 */
+ uint32_t gpio1d_ds2; /* Address Offset: 0x0238 */
+ uint32_t gpio1d_ds3; /* Address Offset: 0x023C */
+ uint32_t gpio2a_ds0; /* Address Offset: 0x0240 */
+ uint32_t reserved0244[47]; /* Address Offset: 0x0244 */
+ uint32_t io_vsel0; /* Address Offset: 0x0300 */
+ uint32_t reserved0304[63]; /* Address Offset: 0x0304 */
+ uint32_t mac1_io_con0; /* Address Offset: 0x0400 */
+ uint32_t mac1_io_con1; /* Address Offset: 0x0404 */
+ uint32_t reserved0408[62]; /* Address Offset: 0x0408 */
+ uint32_t sdcard0_io_con; /* Address Offset: 0x0500 */
+ uint32_t jtag_m1_con; /* Address Offset: 0x0504 */
+ uint32_t reserved0508[16078]; /* Address Offset: 0x0508 */
+ uint32_t gpio3a_iomux_sel_l; /* Address Offset: 0x10040 */
+ uint32_t gpio3a_iomux_sel_h; /* Address Offset: 0x10044 */
+ uint32_t gpio3b_iomux_sel_l; /* Address Offset: 0x10048 */
+ uint32_t gpio3b_iomux_sel_h; /* Address Offset: 0x1004C */
+ uint32_t gpio3c_iomux_sel_l; /* Address Offset: 0x10050 */
+ uint32_t gpio3c_iomux_sel_h; /* Address Offset: 0x10054 */
+ uint32_t gpio3d_iomux_sel_l; /* Address Offset: 0x10058 */
+ uint32_t gpio3d_iomux_sel_h; /* Address Offset: 0x1005C */
+ uint32_t gpio4a_iomux_sel_l; /* Address Offset: 0x10060 */
+ uint32_t gpio4a_iomux_sel_h; /* Address Offset: 0x10064 */
+ uint32_t gpio4b_iomux_sel_l; /* Address Offset: 0x10068 */
+ uint32_t gpio4b_iomux_sel_h; /* Address Offset: 0x1006C */
+ uint32_t reserved10070[12]; /* Address Offset: 0x10070 */
+ uint32_t gpio3a_p; /* Address Offset: 0x100A0 */
+ uint32_t gpio3b_p; /* Address Offset: 0x100A4 */
+ uint32_t gpio3c_p; /* Address Offset: 0x100A8 */
+ uint32_t gpio3d_p; /* Address Offset: 0x100AC */
+ uint32_t gpio4a_p; /* Address Offset: 0x100B0 */
+ uint32_t gpio4b_p; /* Address Offset: 0x100B4 */
+ uint32_t reserved100b8[10]; /* Address Offset: 0x100B8 */
+ uint32_t gpio3a_ie; /* Address Offset: 0x100E0 */
+ uint32_t gpio3b_ie; /* Address Offset: 0x100E4 */
+ uint32_t gpio3c_ie; /* Address Offset: 0x100E8 */
+ uint32_t gpio3d_ie; /* Address Offset: 0x100EC */
+ uint32_t gpio4a_ie; /* Address Offset: 0x100F0 */
+ uint32_t gpio4b_ie; /* Address Offset: 0x100F4 */
+ uint32_t reserved100f8[10]; /* Address Offset: 0x100F8 */
+ uint32_t gpio3a_od; /* Address Offset: 0x10120 */
+ uint32_t gpio3b_od; /* Address Offset: 0x10124 */
+ uint32_t gpio3c_od; /* Address Offset: 0x10128 */
+ uint32_t gpio3d_od; /* Address Offset: 0x1012C */
+ uint32_t gpio4a_od; /* Address Offset: 0x10130 */
+ uint32_t gpio4b_od; /* Address Offset: 0x10134 */
+ uint32_t reserved10138[10]; /* Address Offset: 0x10138 */
+ uint32_t gpio3a_sus; /* Address Offset: 0x10160 */
+ uint32_t gpio3b_sus; /* Address Offset: 0x10164 */
+ uint32_t gpio3c_sus; /* Address Offset: 0x10168 */
+ uint32_t gpio3d_sus; /* Address Offset: 0x1016C */
+ uint32_t gpio4a_sus; /* Address Offset: 0x10170 */
+ uint32_t gpio4b_sus; /* Address Offset: 0x10174 */
+ uint32_t reserved10178[10]; /* Address Offset: 0x10178 */
+ uint32_t gpio3a_sl; /* Address Offset: 0x101A0 */
+ uint32_t gpio3b_sl; /* Address Offset: 0x101A4 */
+ uint32_t gpio3c_sl; /* Address Offset: 0x101A8 */
+ uint32_t gpio3d_sl; /* Address Offset: 0x101AC */
+ uint32_t gpio4a_sl; /* Address Offset: 0x101B0 */
+ uint32_t gpio4b_sl; /* Address Offset: 0x101B4 */
+ uint32_t reserved101b8[50]; /* Address Offset: 0x101B8 */
+ uint32_t gpio3a_ds0; /* Address Offset: 0x10280 */
+ uint32_t gpio3a_ds1; /* Address Offset: 0x10284 */
+ uint32_t gpio3a_ds2; /* Address Offset: 0x10288 */
+ uint32_t gpio3a_ds3; /* Address Offset: 0x1028C */
+ uint32_t gpio3b_ds0; /* Address Offset: 0x10290 */
+ uint32_t gpio3b_ds1; /* Address Offset: 0x10294 */
+ uint32_t gpio3b_ds2; /* Address Offset: 0x10298 */
+ uint32_t gpio3b_ds3; /* Address Offset: 0x1029C */
+ uint32_t gpio3c_ds0; /* Address Offset: 0x102A0 */
+ uint32_t gpio3c_ds1; /* Address Offset: 0x102A4 */
+ uint32_t gpio3c_ds2; /* Address Offset: 0x102A8 */
+ uint32_t gpio3c_ds3; /* Address Offset: 0x102AC */
+ uint32_t gpio3d_ds0; /* Address Offset: 0x102B0 */
+ uint32_t gpio3d_ds1; /* Address Offset: 0x102B4 */
+ uint32_t gpio3d_ds2; /* Address Offset: 0x102B8 */
+ uint32_t gpio3d_ds3; /* Address Offset: 0x102BC */
+ uint32_t gpio4a_ds0; /* Address Offset: 0x102C0 */
+ uint32_t gpio4a_ds1; /* Address Offset: 0x102C4 */
+ uint32_t gpio4a_ds2; /* Address Offset: 0x102C8 */
+ uint32_t gpio4a_ds3; /* Address Offset: 0x102CC */
+ uint32_t gpio4b_ds0; /* Address Offset: 0x102D0 */
+ uint32_t gpio4b_ds1; /* Address Offset: 0x102D4 */
+ uint32_t gpio4b_ds2; /* Address Offset: 0x102D8 */
+ uint32_t gpio4b_ds3; /* Address Offset: 0x102DC */
+ uint32_t reserved102e0[8]; /* Address Offset: 0x102E0 */
+ uint32_t io_vsel1; /* Address Offset: 0x10300 */
+ uint32_t reserved10304[63]; /* Address Offset: 0x10304 */
+ uint32_t mac0_io_con0; /* Address Offset: 0x10400 */
+ uint32_t mac0_io_con1; /* Address Offset: 0x10404 */
+ uint32_t reserved10408[62]; /* Address Offset: 0x10408 */
+ uint32_t vo_io_con; /* Address Offset: 0x10500 */
+ uint32_t reserved10504[35]; /* Address Offset: 0x10504 */
+ uint32_t saradc1_con; /* Address Offset: 0x10590 */
+ uint32_t reserved10594[16027]; /* Address Offset: 0x10594 */
+ uint32_t gpio0a_iomux_sel_l; /* Address Offset: 0x20000 */
+ uint32_t gpio0a_iomux_sel_h; /* Address Offset: 0x20004 */
+ uint32_t gpio0b_iomux_sel_l; /* Address Offset: 0x20008 */
+ uint32_t gpio0b_iomux_sel_h; /* Address Offset: 0x2000C */
+ uint32_t gpio0c_iomux_sel_l; /* Address Offset: 0x20010 */
+ uint32_t gpio0c_iomux_sel_h; /* Address Offset: 0x20014 */
+ uint32_t gpio0d_iomux_sel_l; /* Address Offset: 0x20018 */
+ uint32_t reserved2001c; /* Address Offset: 0x2001C */
+ uint32_t gpio0a_p; /* Address Offset: 0x20020 */
+ uint32_t gpio0b_p; /* Address Offset: 0x20024 */
+ uint32_t gpio0c_p; /* Address Offset: 0x20028 */
+ uint32_t gpio0d_p; /* Address Offset: 0x2002C */
+ uint32_t gpio0a_ie; /* Address Offset: 0x20030 */
+ uint32_t gpio0b_ie; /* Address Offset: 0x20034 */
+ uint32_t gpio0c_ie; /* Address Offset: 0x20038 */
+ uint32_t gpio0d_ie; /* Address Offset: 0x2003C */
+ uint32_t gpio0a_od; /* Address Offset: 0x20040 */
+ uint32_t gpio0b_od; /* Address Offset: 0x20044 */
+ uint32_t gpio0c_od; /* Address Offset: 0x20048 */
+ uint32_t gpio0d_od; /* Address Offset: 0x2004C */
+ uint32_t gpio0a_sus; /* Address Offset: 0x20050 */
+ uint32_t gpio0b_sus; /* Address Offset: 0x20054 */
+ uint32_t gpio0c_sus; /* Address Offset: 0x20058 */
+ uint32_t gpio0d_sus; /* Address Offset: 0x2005C */
+ uint32_t gpio0a_sl; /* Address Offset: 0x20060 */
+ uint32_t gpio0b_sl; /* Address Offset: 0x20064 */
+ uint32_t gpio0c_sl; /* Address Offset: 0x20068 */
+ uint32_t gpio0d_sl; /* Address Offset: 0x2006C */
+ uint32_t gpio0a_ds0; /* Address Offset: 0x20070 */
+ uint32_t gpio0a_ds1; /* Address Offset: 0x20074 */
+ uint32_t gpio0a_ds2; /* Address Offset: 0x20078 */
+ uint32_t gpio0a_ds3; /* Address Offset: 0x2007C */
+ uint32_t gpio0b_ds0; /* Address Offset: 0x20080 */
+ uint32_t gpio0b_ds1; /* Address Offset: 0x20084 */
+ uint32_t gpio0b_ds2; /* Address Offset: 0x20088 */
+ uint32_t gpio0b_ds3; /* Address Offset: 0x2008C */
+ uint32_t gpio0c_ds0; /* Address Offset: 0x20090 */
+ uint32_t gpio0c_ds1; /* Address Offset: 0x20094 */
+ uint32_t gpio0c_ds2; /* Address Offset: 0x20098 */
+ uint32_t gpio0c_ds3; /* Address Offset: 0x2009C */
+ uint32_t gpio0d_ds0; /* Address Offset: 0x200A0 */
+ uint32_t reserved200a4[23]; /* Address Offset: 0x200A4 */
+ uint32_t jtag_m0_con; /* Address Offset: 0x20100 */
+ uint32_t uart_io_con; /* Address Offset: 0x20104 */
+ uint32_t reserved20108[16]; /* Address Offset: 0x20108 */
+ uint32_t io_vsel2; /* Address Offset: 0x20148 */
+ uint32_t xin_con; /* Address Offset: 0x2014C */
+};
+check_member(rk3562_ioc, xin_con, 0x2014c);
+
+#endif
+
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h b/u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h
new file mode 100644
index 0000000..dcfd657
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/pcie_ep_boot.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_PCIE_EP_BOOT_H
+#define __ASM_PCIE_EP_BOOT_H
+
+void rockchip_pcie_ep_init(void);
+void rockchip_pcie_ep_get_firmware(void);
+#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h b/u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h
index 8b6701c..aa6cb0b 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/resource_img.h
@@ -11,55 +11,42 @@
#define MAX_FILE_NAME_LEN 220
#define MAX_HASH_LEN 32
-#define ROOT_COMPAT_PROP_OFFSET 0x4c /* Property: "/compatible" */
#define DTB_SUFFIX ".dtb"
struct resource_file {
char name[MAX_FILE_NAME_LEN];
+ uint32_t blk_start;
+ uint32_t blk_offset;
char hash[MAX_HASH_LEN];
uint32_t hash_size;
- uint32_t f_offset; /* Sector offset */
- uint32_t f_size; /* Bytes */
+ uint32_t size; /* in byte */
+ bool in_ram;
struct list_head link;
- struct list_head dtbs;
- /* Sector base of resource when ram=false, byte base when ram=true */
- uint32_t rsce_base;
- bool ram;
};
-extern struct list_head entrys_head;
-extern struct list_head entrys_dtbs_head;
+extern struct list_head entry_head;
/*
- * resource_image_check_header - check resource image header
+ * resource_setup_ram_list() - setup resource file list by given resource image.
*
- * @rsce_hdr: resource file hdr
+ * @dev_desc: boot device
+ * @hdr: resource file hdr
*
- * return 0 on header okay, otherwise failed
+ * return 0 on success, otherwise fail.
*/
-int resource_image_check_header(void *rsce_hdr);
+int resource_setup_ram_list(struct blk_desc *dev_desc, void *hdr);
/*
- * resource_create_ram_list - create resource file list by data from memory
- *
- * @dev_desc: blk dev descritpion
- * @rsce_hdr: resource file hdr
- *
- * return 0 on header okay, otherwise failed
- */
-int resource_create_ram_list(struct blk_desc *dev_desc, void *rsce_hdr);
-
-/*
- * rockchip_read_resource_file - read file from resource partition
+ * rockchip_read_resource_file() - read file from resource.
*
* @buf: destination buf to store file data
* @name: file name
- * @offset: blocks offset in the file, 1 block = 512 bytes
- * @len: the size(by bytes) of file to read.
+ * @blk_offset: blocks offset in the file, 1 block = 512 bytes
+ * @len: the size(by bytes) of file to read
*
- * return negative num on failed, otherwise the file size
+ * return the length of read data.
*/
-int rockchip_read_resource_file(void *buf, const char *name, int offset, int len);
+int rockchip_read_resource_file(void *buf, const char *name, int blk_offset, int len);
/*
* rockchip_read_resource_dtb() - read dtb file
@@ -69,43 +56,5 @@
* @hash_size: hash value length
*/
int rockchip_read_resource_dtb(void *fdt_addr, char **hash, int *hash_size);
-
-/*
- * resource_init_list - init resource list of android image from storage
- */
-int resource_init_list(void);
-
-/*
- * resource_replace_entry - replace resource entry, override if find exist one
- */
-int resource_replace_entry(const char *f_name, uint32_t base,
- uint32_t f_offset, uint32_t f_size);
-
-/*
- * resource_read_logo_bmps() - read logo bmp from "logo" partition
- */
-int resource_read_logo_bmps(void);
-
-/*
- * resource_read_hwid_dtb() - read hwid dtb
- */
-struct resource_file *resource_read_hwid_dtb(void);
-
-/*
- * resource_is_empty() - return if resource is empty
- */
-int resource_is_empty(void);
-
-/*
- * resource_traverse_init_list() - traverse all image(android/fit/uimage)
- */
-int resource_traverse_init_list(void);
-
-/*
- * board_resource_dtb_accepted() - check if this dtb is accepted
- *
- * return 0 if not accepted, otherwise accepted.
- */
-int board_resource_dtb_accepted(char *dtb_name);
#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h b/u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h
index e31f485..2a8799d 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/rk_meta.h
@@ -64,7 +64,7 @@
#define ITEM_SIZE (1 * 1024)
#define MAX_CMDLINE_LENGTH (1024 / 2)
#define MAX_HEAD_SIZE 4
-#define MAX_META_SEGMENT_SIZE (16 * 1024)
+#define MAX_META_SEGMENT_SIZE (64 * 1024)
#define BACKUP_META_SIZE (MAX_META_SEGMENT_SIZE / 2)
#define META_INFO_HEAD_OFFSET 0
#define META_INFO_SIZE ITEM_SIZE
@@ -80,13 +80,17 @@
#define APP_PARAM_OFFSET (AE_TABLE_OFFSET + AE_TABLE_MAX_SIZE)
#define APP_PARAM_MAX_SIZE ITEM_SIZE
+#define SECONDARY_SENSOR_INIT_OFFSET (APP_PARAM_OFFSET + APP_PARAM_MAX_SIZE)
+#define SECONDARY_SENSOR_INIT_MAX_SIZE ITEM_SIZE
+
#define SENSOR_IQ_BIN_OFFSET (MAX_META_SEGMENT_SIZE)
#define SENSOR_IQ_BIN_MAX_SIZE (320 * 1024)
-#define MAX_META_BIN_SIZE (MAX_META_SEGMENT_SIZE + SENSOR_IQ_BIN_MAX_SIZE)
-#define META_SIZE MAX_META_BIN_SIZE
-/* 512 - sizeof(tag/load/size/comp_type/comp_size/comp_off/crc32/meta_flags) */
-#define META_HEAD_RESERVED_SIZE (120*4)
+#define SECONDARY_SENSOR_IQ_BIN_OFFSET (SENSOR_IQ_BIN_OFFSET + SENSOR_IQ_BIN_MAX_SIZE)
+#define SECONDARY_SENSOR_IQ_BIN_MAX_SIZE (SENSOR_IQ_BIN_MAX_SIZE)
+
+/* 512 - sizeof(tag/load/size/comp_type/comp_size/comp_off/crc32/meta_flags/iq_item_size) */
+#define META_HEAD_RESERVED_SIZE (119*4)
#define META_READ_DONE_FLAG (1 << 0)
#define AE_TABLE_SHARE2KERNEL_OFFSET (PARAM_SHARE2KERNEL_OFFSET)
@@ -100,6 +104,7 @@
uint32_t comp_type;
uint32_t comp_size;
uint32_t comp_off;
+ uint32_t iq_item_size;
uint8_t reserved[META_HEAD_RESERVED_SIZE];
uint32_t crc32;
uint32_t meta_flags;
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h b/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h
index 72db8d9..e5663bf 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/rockchip_smccc.h
@@ -29,6 +29,7 @@
#define SIP_LAST_LOG 0x8200000e
#define SIP_AMP_CFG 0x82000022
#define SIP_HDCP_CONFIG 0x82000025
+#define SIP_MCU_CFG 0x82000028
#define ROCKCHIP_SIP_CONFIG_DRAM_INIT 0x00
#define ROCKCHIP_SIP_CONFIG_DRAM_SET_RATE 0x01
@@ -46,6 +47,19 @@
#define ROCKCHIP_SIP_CONFIG_DRAM_ECC 0x0d
#define ROCKCHIP_SIP_CONFIG_DRAM_GET_FREQ_INFO 0x0e
#define ROCKCHIP_SIP_CONFIG_DRAM_FSP_INIT 0x0f
+
+/* RK_SIP_MCU_CFG child configs, MCU ID */
+#define ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID 0x00
+#define ROCKCHIP_SIP_CONFIG_BUSMCU_1_ID 0x01
+#define ROCKCHIP_SIP_CONFIG_PMUMCU_0_ID 0x10
+#define ROCKCHIP_SIP_CONFIG_DDRMCU_0_ID 0x20
+#define ROCKCHIP_SIP_CONFIG_NPUMCU_0_ID 0x30
+
+/* RK_SIP_MCU_CFG child configs */
+#define ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR 0x01
+#define ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR 0x02
+#define ROCKCHIP_SIP_CONFIG_MCU_SRAM_START_ADDR 0x03
+#define ROCKCHIP_SIP_CONFIG_MCU_EXSRAM_START_ADDR 0x04
/* Rockchip Sip version */
#define SIP_IMPLEMENT_V1 (1)
@@ -100,6 +114,8 @@
int sip_smc_set_suspend_mode(unsigned long ctrl,
unsigned long config1,
unsigned long config2);
+
+int sip_smc_remotectl_config(unsigned long func, unsigned long data);
/*
* sip_smc_amp_cfg() - config AMP
@@ -172,6 +188,13 @@
unsigned long arg1, unsigned long arg2);
/*
+ * sip_smc_mcu_config() - handle mcu.
+ *
+ * @return 0 on success, otherwise failed.
+ */
+int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2);
+
+/*
* psci_cpu_on() - Standard ARM PSCI cpu on call.
*
* @cpuid: cpu id
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h b/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h
new file mode 100644
index 0000000..ce9dacf
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3528.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3528_H
+#define _ASM_ARCH_SDRAM_RK3528_H
+
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+#endif /* _ASM_ARCH_SDRAM_RK3528_H */
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h b/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h
new file mode 100644
index 0000000..3357d8f
--- /dev/null
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/sdram_rk3562.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#ifndef _ASM_ARCH_SDRAM_RK3562_H
+#define _ASM_ARCH_SDRAM_RK3562_H
+
+#include <asm/arch-rockchip/sdram.h>
+#include <asm/arch-rockchip/sdram_common.h>
+
+#endif /* _ASM_ARCH_SDRAM_RK3562_H */
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/uimage.h b/u-boot/arch/arm/include/asm/arch-rockchip/uimage.h
index f409348..a263de2 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/uimage.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/uimage.h
@@ -12,7 +12,6 @@
void *uimage_load_bootables(void);
int uimage_sysmem_free_each(image_header_t *img, u32 ramdisk_sz);
int uimage_sysmem_reserve_each(image_header_t *hdr, u32 *ramdisk_sz);
-int uimage_init_resource(void);
-
+int uimage_init_resource(struct blk_desc *dev_desc);
#endif
diff --git a/u-boot/arch/arm/include/asm/arch-rockchip/vendor.h b/u-boot/arch/arm/include/asm/arch-rockchip/vendor.h
index 2c11030..85570ca 100644
--- a/u-boot/arch/arm/include/asm/arch-rockchip/vendor.h
+++ b/u-boot/arch/arm/include/asm/arch-rockchip/vendor.h
@@ -46,4 +46,7 @@
void *p_data));
int vendor_handle_hdcp(struct vendor_item *vhead);
+
+void vendor_storage_fixup(void *blob);
+
#endif /* _ROCKCHIP_VENDOR_ */
diff --git a/u-boot/arch/arm/include/asm/system.h b/u-boot/arch/arm/include/asm/system.h
index 795d82d..8625375 100644
--- a/u-boot/arch/arm/include/asm/system.h
+++ b/u-boot/arch/arm/include/asm/system.h
@@ -257,6 +257,7 @@
void wait_for_wakeup(void);
void protect_secure_region(void);
void smp_kick_all_cpus(void);
+void smp_entry(u32 cpu);
void flush_l3_cache(void);
void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs);
diff --git a/u-boot/arch/arm/lib/bootm-fdt.c b/u-boot/arch/arm/lib/bootm-fdt.c
index af47974..5ef0e66 100644
--- a/u-boot/arch/arm/lib/bootm-fdt.c
+++ b/u-boot/arch/arm/lib/bootm-fdt.c
@@ -46,6 +46,9 @@
if (ret)
return ret;
+ /* Show "/reserved-memory" */
+ boot_mem_rsv_regions(NULL, blob);
+
#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_OF_LIBFDT)
bd_t *bd = gd->bd;
int bank;
diff --git a/u-boot/arch/arm/lib/bootm.c b/u-boot/arch/arm/lib/bootm.c
index 53f7444..7a94d79 100644
--- a/u-boot/arch/arm/lib/bootm.c
+++ b/u-boot/arch/arm/lib/bootm.c
@@ -22,6 +22,7 @@
#include <asm/byteorder.h>
#include <linux/libfdt.h>
#include <mapmem.h>
+#include <mp_boot.h>
#include <fdt_support.h>
#include <asm/bootm.h>
#include <asm/secure.h>
@@ -80,7 +81,7 @@
*/
static void announce_and_cleanup(bootm_headers_t *images, int fake)
{
- ulong us;
+ ulong us, tt_us;
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
#ifdef CONFIG_BOOTSTAGE_FDT
@@ -108,8 +109,12 @@
cleanup_before_linux();
+#ifdef CONFIG_MP_BOOT
+ mpb_post(4);
+#endif
us = (get_ticks() - gd->sys_start_tick) / (COUNTER_FREQUENCY / 1000000);
- printf("Total: %ld.%ld ms\n", us / 1000, us % 1000);
+ tt_us = get_ticks() / (COUNTER_FREQUENCY / 1000000);
+ printf("Total: %ld.%ld/%ld.%ld ms\n", us / 1000, us % 1000, tt_us / 1000, tt_us % 1000);
printf("\nStarting kernel ...%s\n\n", fake ?
"(fake run for tracing)" : "");
diff --git a/u-boot/arch/arm/lib/crt0_64.S b/u-boot/arch/arm/lib/crt0_64.S
index 27e22f9..5940253 100644
--- a/u-boot/arch/arm/lib/crt0_64.S
+++ b/u-boot/arch/arm/lib/crt0_64.S
@@ -66,42 +66,6 @@
*/
ENTRY(_main)
- /*
- * Enable instruction cache (if required), stack pointer,
- * data access alignment checks and SError.
- */
-#ifdef CONFIG_SPL_BUILD
- mov x1, #CR_I
-#else
- mov x1, #0
-#endif
- switch_el x2, 3f, 2f, 1f
-3: mrs x0, sctlr_el3
- orr x0, x0, x1
- msr sctlr_el3, x0
-#ifndef CONFIG_SUPPORT_USBPLUG
- msr daifclr, #4 /* Enable SError. SCR_EL3.EA=1 was already set in start.S */
-#endif
- b 0f
-2: mrs x0, sctlr_el2
- orr x0, x0, x1
- msr sctlr_el2, x0
-
- mrs x0, hcr_el2
- orr x0, x0, #HCR_EL2_TGE
- orr x0, x0, #HCR_EL2_AMO
-#if CONFIG_IS_ENABLED(IRQ)
- orr x0, x0, #HCR_EL2_IMO
-#endif
- msr hcr_el2, x0
- msr daifclr, #4
- b 0f
-1: mrs x0, sctlr_el1
- orr x0, x0, x1
- msr sctlr_el1, x0
- msr daifclr, #4
-0:
- isb
/*
* Set up initial C runtime environment and call board_init_f(0).
diff --git a/u-boot/arch/arm/mach-rockchip/Kconfig b/u-boot/arch/arm/mach-rockchip/Kconfig
index 0a3c8f4..383503d 100644
--- a/u-boot/arch/arm/mach-rockchip/Kconfig
+++ b/u-boot/arch/arm/mach-rockchip/Kconfig
@@ -381,6 +381,61 @@
endif
+config ROCKCHIP_RK3528
+ bool "Support Rockchip RK3528"
+ select ARM64 if !ARM64_BOOT_AARCH32
+ select GICV2 if !ARM64_BOOT_AARCH32
+ select SUPPORT_TPL if !ARM64_BOOT_AARCH32
+ select SUPPORT_SPL if !ARM64_BOOT_AARCH32
+ select TPL_TINY_FRAMEWORK if TPL
+ select DEBUG_UART_BOARD_INIT
+ imply TPL if !ARM64_BOOT_AARCH32
+ imply SPL if !ARM64_BOOT_AARCH32
+ imply TPL_SERIAL_SUPPORT
+ help
+ The Rockchip RK3528 is a ARM-based SoC with a quad-core Cortex-A53.
+
+if ROCKCHIP_RK3528
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xfe481000
+
+config TPL_MAX_SIZE
+ default 61440
+
+endif
+
+config ROCKCHIP_RK3562
+ bool "Support Rockchip RK3562"
+ select GICV2
+ select ARM64
+ select ARM_SMCCC
+ select SUPPORT_TPL
+ select SUPPORT_SPL
+ select TPL_TINY_FRAMEWORK if TPL
+ select DEBUG_UART_BOARD_INIT
+ imply TPL
+ imply SPL
+ imply TPL_SERIAL_SUPPORT
+ help
+ The Rockchip RK3562 is a ARM-based SoC with a quad-core Cortex-A53.
+
+if ROCKCHIP_RK3562
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl-v8.lds"
+
+config TPL_TEXT_BASE
+ default 0xfe481000
+
+config TPL_MAX_SIZE
+ default 61440
+
+endif
+
config ROCKCHIP_RK3568
bool "Support Rockchip RK3568"
select ARM64 if !ARM64_BOOT_AARCH32
@@ -597,6 +652,8 @@
default 0xff1005c8 if ROCKCHIP_RK3328
default 0xff738200 if ROCKCHIP_RK3368
default 0xff320300 if ROCKCHIP_RK3399
+ default 0xff370200 if ROCKCHIP_RK3528
+ default 0xff010220 if ROCKCHIP_RK3562
default 0xfdc20200 if ROCKCHIP_RK3568
default 0xfd588080 if ROCKCHIP_RK3588
default 0xfe020200 if ROCKCHIP_RK1808
@@ -622,6 +679,8 @@
default 0xff1d0020 if ROCKCHIP_RK3328
default 0xff830020 if ROCKCHIP_RK3368
default 0xff8680a0 if ROCKCHIP_RK3399
+ default 0xff620000 if ROCKCHIP_RK3528
+ default 0xffa90020 if ROCKCHIP_RK3562
default 0xfdd1c020 if ROCKCHIP_RK3568
default 0xfd8c8000 if ROCKCHIP_RK3588
default 0xff590020 if ROCKCHIP_RV1106
@@ -644,6 +703,8 @@
default 0xff091000 if ROCKCHIP_RK3328
default 0xff8c0000 if ROCKCHIP_RK3368
default 0xff8c0000 if ROCKCHIP_RK3399
+ default 0xfe480000 if ROCKCHIP_RK3528
+ default 0xfe480000 if ROCKCHIP_RK3562
default 0xfdcc0000 if ROCKCHIP_RK3568
default 0xff000000 if ROCKCHIP_RK3588
default 0xff6c0000 if ROCKCHIP_RV1106
@@ -813,16 +874,22 @@
- U-Boot: only some necessary U-Boot devices(storage, crypto...) in dm tree.
- kernel: all the devices(except the U-Boot only) in dm tree.
+config EMBED_KERNEL_DTB
+ bool "Enable embedded dtb support"
+ default n
+ help
+ Enable embedded dtb support.
+
config EMBED_KERNEL_DTB_PATH
- string "Embeded kernel dtb file path"
- depends on USING_KERNEL_DTB
+ string "Embedded kernel dtb file path"
+ depends on EMBED_KERNEL_DTB && USING_KERNEL_DTB
default "dts/kern.dtb"
help
This file will auto be appended to the u-boot.bin.
config EMBED_KERNEL_DTB_ALWAYS
- bool "Always using embed kernel dtb"
- depends on USING_KERNEL_DTB
+ bool "Always using embedded kernel dtb"
+ depends on EMBED_KERNEL_DTB && USING_KERNEL_DTB
default n
help
Allow fallback to always use a prepared kernel dtb even USING_KERNEL_DTB
@@ -914,6 +981,16 @@
default y
help
Define a lot of hotkeys for debug.
+
+config ROCKCHIP_CMD
+ string "Rockchip specific command"
+ default ""
+ help
+ It defines a command to be run when the key is pressed if assigned.
+ String format: "cmd key".
+ @cmd: any U-Boot cmd.
+ @key: any key map id, '-' standard for ignore.
+ e.g. "sd_update 115", 115 is KEY_VOLUMEUP.
config GICV2
bool "ARM GICv2"
@@ -1013,14 +1090,16 @@
default 0x0
depends on PSTORE
help
- This select linux pstore buffer address for uboot.
+ This select linux pstore buffer address for U-Boot. When value is
+ 0, U-Boot auto gets this address from preloader atags.
config PERSISTENT_RAM_SIZE
hex "Linux pstore buffer size"
default 0x0
- depends on PSTORE
+ depends on (PERSISTENT_RAM_ADDR != 0)
help
- This select linux pstore buffer size for uboot.
+ This select linux pstore buffer size for U-Boot, the value must be
+ set if PERSISTENT_RAM_ADDR != 0.
source "arch/arm/mach-rockchip/px30/Kconfig"
source "arch/arm/mach-rockchip/rk3036/Kconfig"
@@ -1033,6 +1112,8 @@
source "arch/arm/mach-rockchip/rk3328/Kconfig"
source "arch/arm/mach-rockchip/rk3368/Kconfig"
source "arch/arm/mach-rockchip/rk3399/Kconfig"
+source "arch/arm/mach-rockchip/rk3528/Kconfig"
+source "arch/arm/mach-rockchip/rk3562/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rk3588/Kconfig"
source "arch/arm/mach-rockchip/rk1808/Kconfig"
diff --git a/u-boot/arch/arm/mach-rockchip/Makefile b/u-boot/arch/arm/mach-rockchip/Makefile
index afa18a4..75de030 100644
--- a/u-boot/arch/arm/mach-rockchip/Makefile
+++ b/u-boot/arch/arm/mach-rockchip/Makefile
@@ -49,7 +49,7 @@
obj-$(CONFIG_ROCKCHIP_UIMAGE) += uimage.o
obj-$(CONFIG_ROCKCHIP_SMCCC) += rockchip_smccc.o
obj-$(CONFIG_ROCKCHIP_VENDOR_PARTITION) += vendor.o vendor_misc.o
-obj-$(CONFIG_ROCKCHIP_RESOURCE_IMAGE) += resource_img.o resource_logo.o
+obj-$(CONFIG_ROCKCHIP_RESOURCE_IMAGE) += resource_img.o
obj-$(CONFIG_ROCKCHIP_HWID_DTB) += resource_hwid.o
obj-$(CONFIG_ROCKCHIP_DEBUGGER) += rockchip_debugger.o
endif
@@ -58,6 +58,7 @@
obj-$(CONFIG_RAM) += param.o
obj-$(CONFIG_$(SPL_TPL_)RAM) += sdram.o
obj-$(CONFIG_SPL_KERNEL_BOOT) += spl_resource_img.o
+obj-$(CONFIG_SPL_PCIE_EP_SUPPORT) += spl_pcie_ep_boot.o
obj-$(CONFIG_ROCKCHIP_PX30) += px30/
obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/
@@ -72,6 +73,8 @@
obj-$(CONFIG_ROCKCHIP_RK3328) += rk3328/
obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
+obj-$(CONFIG_ROCKCHIP_RK3528) += rk3528/
+obj-$(CONFIG_ROCKCHIP_RK3562) += rk3562/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RK3588) += rk3588/
obj-$(CONFIG_ROCKCHIP_RK1808) += rk1808/
diff --git a/u-boot/arch/arm/mach-rockchip/board.c b/u-boot/arch/arm/mach-rockchip/board.c
index b3bced5..a539d4b 100644
--- a/u-boot/arch/arm/mach-rockchip/board.c
+++ b/u-boot/arch/arm/mach-rockchip/board.c
@@ -56,6 +56,10 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_ARM64
+static ulong orig_images_ep;
+#endif
+
__weak int rk_board_late_init(void)
{
return 0;
@@ -246,30 +250,48 @@
static int boot_from_udisk(void)
{
struct blk_desc *desc;
- char *devtype;
- char *devnum;
-
- devtype = env_get("devtype");
- devnum = env_get("devnum");
+ struct udevice *dev;
+ int devnum = -1;
+ char buf[32];
/* Booting priority: mmc1 > udisk */
- if (!strcmp(devtype, "mmc") && !strcmp(devnum, "1"))
+ if (!strcmp(env_get("devtype"), "mmc") && !strcmp(env_get("devnum"), "1"))
return 0;
if (!run_command("usb start", -1)) {
- desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
- if (!desc) {
- printf("No usb device found\n");
+ for (blk_first_device(IF_TYPE_USB, &dev);
+ dev;
+ blk_next_device(&dev)) {
+ desc = dev_get_uclass_platdata(dev);
+ printf("Scanning usb %d ...\n", desc->devnum);
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ continue;
+
+ if (desc->lba > 0L && desc->blksz > 0L) {
+ devnum = desc->devnum;
+ break;
+ }
+ }
+ if (devnum < 0) {
+ printf("No usb mass storage found\n");
return -ENODEV;
}
- if (!run_command("rkimgtest usb 0", -1)) {
+ desc = blk_get_devnum_by_type(IF_TYPE_USB, devnum);
+ if (!desc) {
+ printf("No usb %d found\n", devnum);
+ return -ENODEV;
+ }
+
+ snprintf(buf, 32, "rkimgtest usb %d", devnum);
+ if (!run_command(buf, -1)) {
+ snprintf(buf, 32, "%d", devnum);
rockchip_set_bootdev(desc);
env_set("devtype", "usb");
- env_set("devnum", "0");
- printf("Boot from usb 0\n");
+ env_set("devnum", buf);
+ printf("=== Booting from usb %d ===\n", devnum);
} else {
- printf("No usb dev 0 found\n");
+ printf("No available udisk image on usb %d\n", devnum);
return -ENODEV;
}
}
@@ -358,6 +380,8 @@
static void cmdline_handle(void)
{
struct blk_desc *dev_desc;
+ int if_type;
+ int devnum;
param_parse_pubkey_fuse_programmed();
@@ -373,19 +397,51 @@
* rockchip_get_boot_mode() actually only read once,
* we need to update boot mode according to udisk BCB.
*/
- if ((dev_desc->if_type == IF_TYPE_MMC && dev_desc->devnum == 1) ||
- (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0)) {
+ if_type = dev_desc->if_type;
+ devnum = dev_desc->devnum;
+ if ((if_type == IF_TYPE_MMC && devnum == 1) || (if_type == IF_TYPE_USB)) {
if (get_bcb_recovery_msg() == BCB_MSG_RECOVERY_RK_FWUPDATE) {
- if (dev_desc->if_type == IF_TYPE_MMC && dev_desc->devnum == 1) {
+ if (if_type == IF_TYPE_MMC && devnum == 1) {
env_update("bootargs", "sdfwupdate");
- } else if (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0) {
+ } else if (if_type == IF_TYPE_USB) {
env_update("bootargs", "usbfwupdate");
env_set("reboot_mode", "recovery-usb");
}
} else {
- if (dev_desc->if_type == IF_TYPE_USB && dev_desc->devnum == 0)
+ if (if_type == IF_TYPE_USB)
env_set("reboot_mode", "normal");
}
+ }
+
+ if (rockchip_get_boot_mode() == BOOT_MODE_QUIESCENT)
+ env_update("bootargs", "androidboot.quiescent=1 pwm_bl.quiescent=1");
+}
+
+static void scan_run_cmd(void)
+{
+ char *config = CONFIG_ROCKCHIP_CMD;
+ char *cmd, *key;
+
+ key = strchr(config, ' ');
+ if (!key)
+ return;
+
+ cmd = strdup(config);
+ cmd[key - config] = 0;
+ key++;
+
+ if (!strcmp(key, "-")) {
+ run_command(cmd, 0);
+ } else {
+#ifdef CONFIG_DM_KEY
+ ulong map;
+
+ map = simple_strtoul(key, NULL, 10);
+ if (key_is_pressed(key_read(map))) {
+ printf("## Key<%ld> pressed... run cmd '%s'\n", map, cmd);
+ run_command(cmd, 0);
+ }
+#endif
}
}
@@ -398,7 +454,7 @@
rockchip_set_serialno();
#endif
setup_download_mode();
-
+ scan_run_cmd();
#ifdef CONFIG_ROCKCHIP_USB_BOOT
boot_from_udisk();
#endif
@@ -406,7 +462,8 @@
charge_display();
#endif
#ifdef CONFIG_DRM_ROCKCHIP
- rockchip_show_logo();
+ if (rockchip_get_boot_mode() != BOOT_MODE_QUIESCENT)
+ rockchip_show_logo();
#endif
#ifdef CONFIG_ROCKCHIP_EINK_DISPLAY
rockchip_eink_show_uboot_logo();
@@ -458,57 +515,31 @@
printf("Cmd interface: disabled\n");
}
-#if defined(CONFIG_MTD_BLK) && defined(CONFIG_USING_KERNEL_DTB)
-static void board_mtd_blk_map_partitions(void)
-{
- struct blk_desc *dev_desc;
-
- dev_desc = rockchip_get_bootdev();
- if (dev_desc)
- mtd_blk_map_partitions(dev_desc);
-}
-#endif
-
int board_init(void)
{
board_debug_init();
- /* optee select security level */
-#ifdef CONFIG_OPTEE_CLIENT
- trusty_select_security_level();
-#endif
-
#ifdef DEBUG
soc_clk_dump();
#endif
-
-#ifdef CONFIG_USING_KERNEL_DTB
-#ifdef CONFIG_MTD_BLK
- board_mtd_blk_map_partitions();
+#ifdef CONFIG_OPTEE_CLIENT
+ trusty_select_security_level();
#endif
+#ifdef CONFIG_USING_KERNEL_DTB
init_kernel_dtb();
#endif
early_download();
- /*
- * pmucru isn't referenced on some platforms, so pmucru driver can't
- * probe that the "assigned-clocks" is unused.
- */
clks_probe();
#ifdef CONFIG_DM_REGULATOR
- if (regulators_enable_boot_on(is_hotkey(HK_REGULATOR)))
- debug("%s: Can't enable boot on regulator\n", __func__);
+ regulators_enable_boot_on(is_hotkey(HK_REGULATOR));
#endif
-
#ifdef CONFIG_ROCKCHIP_IO_DOMAIN
io_domain_init();
#endif
-
set_armclk_rate();
-
#ifdef CONFIG_DM_DVFS
dvfs_init(true);
#endif
-
#ifdef CONFIG_ANDROID_AB
if (ab_decrease_tries())
printf("Decrease ab tries count fail!\n");
@@ -537,6 +568,10 @@
/* Common fixup for DRM */
#ifdef CONFIG_DRM_ROCKCHIP
rockchip_display_fixup(blob);
+#endif
+
+#ifdef CONFIG_ROCKCHIP_VENDOR_PARTITION
+ vendor_storage_fixup(blob);
#endif
return rk_board_fdt_fixup(blob);
@@ -603,6 +638,9 @@
* But relocation is in board_quiesce_devices() until all decompress
* done, mainly for saving boot time.
*/
+
+ orig_images_ep = images->ep;
+
if (data[10] == 0x00) {
if (round_down(images->ep, SZ_2M) != images->ep)
images->ep = round_down(images->ep, SZ_2M);
@@ -736,9 +774,10 @@
return boot_flags;
}
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <fdt_support.h>
+#if defined(CONFIG_USB_GADGET)
#include <usb.h>
+#if defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <fdt_support.h>
#include <usb/dwc2_udc.h>
static struct dwc2_plat_otg_data otg_data = {
@@ -808,7 +847,17 @@
{
return 0;
}
-#endif
+#elif defined(CONFIG_USB_DWC3_GADGET) /* CONFIG_USB_GADGET_DWC2_OTG */
+#include <dwc3-uboot.h>
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ dwc3_uboot_exit(index);
+ return 0;
+}
+
+#endif /* CONFIG_USB_DWC3_GADGET */
+#endif /* CONFIG_USB_GADGET */
static void bootm_no_reloc(void)
{
@@ -1049,15 +1098,13 @@
#endif
#ifdef CONFIG_ARM64
bootm_headers_t *bootm_images = (bootm_headers_t *)images;
- ulong kernel_addr;
/* relocate kernel after decompress cleanup */
- kernel_addr = env_get_ulong("kernel_addr_r", 16, 0);
- if (kernel_addr != bootm_images->ep) {
- memmove((char *)bootm_images->ep, (const char *)kernel_addr,
+ if (orig_images_ep && orig_images_ep != bootm_images->ep) {
+ memmove((char *)bootm_images->ep, (const char *)orig_images_ep,
bootm_images->os.image_len);
printf("== DO RELOCATE == Kernel from 0x%08lx to 0x%08lx\n",
- kernel_addr, bootm_images->ep);
+ orig_images_ep, bootm_images->ep);
}
#endif
@@ -1109,16 +1156,39 @@
#endif
}
-#ifdef CONFIG_ENVF
- char * sys_bootargs;
+#if defined(CONFIG_ENVF) || defined(CONFIG_ENV_PARTITION)
+ char *part_type[] = { "mtdparts", "blkdevparts" };
+ char *part_list;
+ char *env;
+ int id = 0;
- sys_bootargs = env_get("sys_bootargs");
- if (sys_bootargs) {
- env_update("bootargs", sys_bootargs);
+ env = env_get(part_type[id]);
+ if (!env)
+ env = env_get(part_type[++id]);
+ if (env) {
+ if (!strstr(env, part_type[id])) {
+ part_list = calloc(1, strlen(env) + strlen(part_type[id]) + 2);
+ if (part_list) {
+ strcat(part_list, part_type[id]);
+ strcat(part_list, "=");
+ strcat(part_list, env);
+ }
+ } else {
+ part_list = env;
+ }
+ env_update("bootargs", part_list);
if (dump)
- printf("## sys_bootargs: %s\n\n", sys_bootargs);
+ printf("## parts: %s\n\n", part_list);
+ }
+
+ env = env_get("sys_bootargs");
+ if (env) {
+ env_update("bootargs", env);
+ if (dump)
+ printf("## sys_bootargs: %s\n\n", env);
}
#endif
+
#ifdef CONFIG_MTD_BLK
if (!env_get("mtdparts")) {
char *mtd_par_info = mtd_part_parse(NULL);
@@ -1129,6 +1199,10 @@
}
}
#endif
+
+#ifdef CONFIG_ANDROID_AB
+ ab_update_root_partition();
+#endif
/*
* Initrd fixup: remove unused "initrd=0x...,0x...",
* this for compatible with legacy parameter.txt
diff --git a/u-boot/arch/arm/mach-rockchip/boot_mode.c b/u-boot/arch/arm/mach-rockchip/boot_mode.c
index 61f0e85..6f4858b 100644
--- a/u-boot/arch/arm/mach-rockchip/boot_mode.c
+++ b/u-boot/arch/arm/mach-rockchip/boot_mode.c
@@ -202,6 +202,10 @@
printf("boot mode: watchdog\n");
boot_mode[PL] = BOOT_MODE_WATCHDOG;
break;
+ case BOOT_QUIESCENT:
+ printf("boot mode: quiescent\n");
+ boot_mode[PL] = BOOT_MODE_QUIESCENT;
+ break;
default:
printf("boot mode: None\n");
boot_mode[PL] = BOOT_MODE_UNDEFINE;
diff --git a/u-boot/arch/arm/mach-rockchip/boot_rkimg.c b/u-boot/arch/arm/mach-rockchip/boot_rkimg.c
index 097d976..3e133fb 100644
--- a/u-boot/arch/arm/mach-rockchip/boot_rkimg.c
+++ b/u-boot/arch/arm/mach-rockchip/boot_rkimg.c
@@ -19,6 +19,8 @@
#include <key.h>
#include <mmc.h>
#include <malloc.h>
+#include <mp_boot.h>
+#include <mtd_blk.h>
#include <nvme.h>
#include <scsi.h>
#include <stdlib.h>
@@ -91,6 +93,10 @@
if (done)
return;
+
+#ifdef CONFIG_MP_BOOT
+ mpb_post(0);
+#endif
/* configuration */
if (!param_parse_assign_bootdev(&devtype, &devnum)) {
@@ -269,6 +275,9 @@
printf("PartType: %s\n", part_get_type(dev_desc));
+#ifdef CONFIG_MTD_BLK
+ mtd_blk_map_partitions(dev_desc);
+#endif
return dev_desc;
}
@@ -512,7 +521,7 @@
LOCATE_END,
};
-static int rkimg_traverse_read_dtb(void *fdt, int where)
+static int dtb_scan(void *fdt, int where)
{
if (where == LOCATE_DISTRO) {
#ifdef CONFIG_ROCKCHIP_EARLY_DISTRO_DTB
@@ -557,19 +566,13 @@
int locate, ret;
int size;
- /* init resource list */
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
- resource_traverse_init_list();
-#endif
-
- /* traverse location */
for (locate = 0; locate < LOCATE_END; locate++) {
- ret = rkimg_traverse_read_dtb(fdt, locate);
+ ret = dtb_scan(fdt, locate);
if (!ret)
break;
}
if (ret) {
- printf("No find valid DTB, ret=%d\n", ret);
+ printf("No valid DTB, ret=%d\n", ret);
return ret;
}
@@ -608,7 +611,7 @@
offset = hdr->page_size + ALIGN(hdr->kernel_size, hdr->page_size) +
ALIGN(hdr->ramdisk_size, hdr->page_size);
#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
- ret = resource_create_ram_list(dev_desc, (void *)hdr + offset);
+ ret = resource_setup_ram_list(dev_desc, (void *)hdr + offset);
if (ret)
return ret;
@@ -650,9 +653,9 @@
if (!dev_desc)
return -ENODEV;
- ret = resource_create_ram_list(dev_desc, (void *)data);
+ ret = resource_setup_ram_list(dev_desc, (void *)data);
if (ret) {
- printf("resource_create_ram_list fail, ret=%d\n", ret);
+ printf("resource_setup_ram_list fail, ret=%d\n", ret);
return ret;
}
diff --git a/u-boot/arch/arm/mach-rockchip/chip_info.c b/u-boot/arch/arm/mach-rockchip/chip_info.c
index ee0f9a0..65667ff 100644
--- a/u-boot/arch/arm/mach-rockchip/chip_info.c
+++ b/u-boot/arch/arm/mach-rockchip/chip_info.c
@@ -63,6 +63,10 @@
chip_info[0] = 0x33333236;
#elif defined(CONFIG_ROCKCHIP_PX30)
chip_info[0] = 0x50583330;
+#elif defined(CONFIG_ROCKCHIP_RK3528)
+ chip_info[0] = 0x33353238;
+#elif defined(CONFIG_ROCKCHIP_RK3562)
+ chip_info[0] = 0x33353632;
#elif defined(CONFIG_ROCKCHIP_RK3568)
chip_info[0] = 0x33353638;
#elif defined(CONFIG_ROCKCHIP_RK3588)
diff --git a/u-boot/arch/arm/mach-rockchip/fit.c b/u-boot/arch/arm/mach-rockchip/fit.c
index 9348c76..7c5681a 100644
--- a/u-boot/arch/arm/mach-rockchip/fit.c
+++ b/u-boot/arch/arm/mach-rockchip/fit.c
@@ -142,14 +142,14 @@
{
__maybe_unused int conf_noffset;
disk_partition_t part;
- char *part_name;
+ char *part_name = PART_BOOT;
void *fit, *fdt;
int blk_num;
+#ifndef CONFIG_ANDROID_AB
if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
part_name = PART_RECOVERY;
- else
- part_name = PART_BOOT;
+#endif
if (part_get_info_by_name(dev_desc, part_name, &part) < 0) {
FIT_I("No %s partition\n", part_name);
@@ -201,6 +201,7 @@
printf("%s: ", fdt_get_name(fit, conf_noffset, NULL));
if (fit_config_verify(fit, conf_noffset)) {
puts("\n");
+ /* don't remove this failure handle */
run_command("download", 0);
hang();
}
@@ -246,6 +247,7 @@
{
int ret;
+ /* free for fit_image_fixup_alloc(FIT_FDT_PROP) to re-alloc */
if ((gd->flags & GD_FLG_KDTB_READY) && !gd->fdt_blob_kern)
sysmem_free((phys_addr_t)gd->fdt_blob);
@@ -404,65 +406,45 @@
}
#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
-static int fit_image_load_resource(const void *fit, struct blk_desc *dev_desc,
- disk_partition_t *part, ulong *addr)
+ulong fit_image_init_resource(struct blk_desc *dev_desc)
{
- int offset, size;
- int ret;
- void *data;
-
- ret = fdt_image_get_offset_size(fit, FIT_MULTI_PROP, &offset, &size);
- if (ret)
- return ret;
-
- data = malloc(ALIGN(size, dev_desc->blksz));
- if (!data)
- return -ENOMEM;
-
- *addr = (ulong)data;
-
- return fit_image_load_one(fit, dev_desc, part, FIT_MULTI_PROP,
- data, IS_ENABLED(CONFIG_FIT_SIGNATURE));
-}
-
-int fit_image_init_resource(void)
-{
- struct blk_desc *dev_desc;
disk_partition_t part;
+ void *fit, *buf;
+ int offset, size;
int ret = 0;
- void *fit;
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- FIT_I("No dev_desc!\n");
+ if (!dev_desc)
return -ENODEV;
- }
fit = fit_get_blob(dev_desc, &part, true);
if (!fit)
+ return -EAGAIN;
+
+ ret = fdt_image_get_offset_size(fit, FIT_MULTI_PROP, &offset, &size);
+ if (ret)
return -EINVAL;
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
- ulong rsce;
+ buf = memalign(ARCH_DMA_MINALIGN, ALIGN(size, dev_desc->blksz));
+ if (!buf)
+ return -ENOMEM;
- ret = fit_image_load_resource(fit, dev_desc, &part, &rsce);
+ printf("RESC: '%s', blk@0x%08lx\n", part.name,
+ part.start + ((FIT_ALIGN(fdt_totalsize(fit)) + offset) / dev_desc->blksz));
+ ret = fit_image_load_one(fit, dev_desc, &part, FIT_MULTI_PROP, buf, 1);
+ if (ret)
+ return ret;
+
+ ret = resource_setup_ram_list(dev_desc, buf);
if (ret) {
- FIT_I("Failed to load resource\n");
+ FIT_I("Failed to setup resource ram list, ret=%d\n", ret);
free(fit);
return ret;
}
- ret = resource_create_ram_list(dev_desc, (void *)rsce);
- if (ret) {
- FIT_I("Failed to create resource list\n");
- free(fit);
- return ret;
- }
-#endif
fit_msg(fit);
free(fit);
- return ret;
+ return 0;
}
#else
int fit_image_read_dtb(void *fdt_addr)
diff --git a/u-boot/arch/arm/mach-rockchip/fit_args.sh b/u-boot/arch/arm/mach-rockchip/fit_args.sh
index 6f67965..d92cbf5 100755
--- a/u-boot/arch/arm/mach-rockchip/fit_args.sh
+++ b/u-boot/arch/arm/mach-rockchip/fit_args.sh
@@ -107,7 +107,9 @@
# Base
DARM_BASE=`sed -n "/CONFIG_SYS_SDRAM_BASE=/s/CONFIG_SYS_SDRAM_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
-UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
+if ! grep -q '^CONFIG_FIT_OMIT_UBOOT=y' .config ; then
+ UBOOT_LOAD_ADDR=`sed -n "/CONFIG_SYS_TEXT_BASE=/s/CONFIG_SYS_TEXT_BASE=//p" ${srctree}/include/autoconf.mk|tr -d '\r'`
+fi
# ARCH
U_ARCH="arm"
diff --git a/u-boot/arch/arm/mach-rockchip/fit_misc.c b/u-boot/arch/arm/mach-rockchip/fit_misc.c
index a279f5f..d3a2ad5 100644
--- a/u-boot/arch/arm/mach-rockchip/fit_misc.c
+++ b/u-boot/arch/arm/mach-rockchip/fit_misc.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <boot_rkimg.h>
+#include <malloc.h>
#include <misc.h>
#ifdef CONFIG_SPL_BUILD
#include <spl.h>
@@ -25,7 +26,7 @@
#if CONFIG_IS_ENABLED(FIT_IMAGE_POST_PROCESS)
#define FIT_UNCOMP_HASH_NODENAME "digest"
-#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP)
+#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP) || CONFIG_IS_ENABLED(LZMA)
static int fit_image_get_uncomp_digest(const void *fit, int parent_noffset)
{
const char *name;
@@ -126,8 +127,10 @@
else
misc_decompress_sync(comp);
#else
+#if CONFIG_IS_ENABLED(GZIP)
ret = gunzip((void *)(*load_addr), ALIGN(len, FIT_MAX_SPL_IMAGE_SZ),
(void *)(*src_addr), (void *)(&len));
+#endif
#endif
}
@@ -154,7 +157,7 @@
void board_fit_image_post_process(void *fit, int node, ulong *load_addr,
ulong **src_addr, size_t *src_len, void *spec)
{
-#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP)
+#if CONFIG_IS_ENABLED(MISC_DECOMPRESS) || CONFIG_IS_ENABLED(GZIP) || CONFIG_IS_ENABLED(LZMA)
fit_decomp_image(fit, node, load_addr, src_addr, src_len, spec);
#endif
@@ -169,6 +172,33 @@
}
}
#endif
+
+#ifndef CONFIG_SPL_BUILD
+ if (fit_image_check_type(fit, node, IH_TYPE_FIRMWARE)) {
+ const char *uname;
+ char *old, *new;
+ size_t len;
+
+ uname = fdt_get_name(fit, node, NULL);
+ if (strcmp("bootargs", uname))
+ return;
+
+ old = env_get("bootargs");
+ if (!old)
+ return;
+
+ len = strlen(old) + (*src_len) + 2;
+ new = calloc(1, len);
+ if (new) {
+ strcpy(new, old);
+ strcat(new, " ");
+ strcat(new, (char *)(*src_addr));
+ env_set("bootargs", new);
+ free(new);
+ }
+
+ }
+#endif
}
#endif /* FIT_IMAGE_POST_PROCESS */
/*
diff --git a/u-boot/arch/arm/mach-rockchip/fit_nodes.sh b/u-boot/arch/arm/mach-rockchip/fit_nodes.sh
index be7d46d..4d39ea0 100755
--- a/u-boot/arch/arm/mach-rockchip/fit_nodes.sh
+++ b/u-boot/arch/arm/mach-rockchip/fit_nodes.sh
@@ -27,6 +27,10 @@
# nodes
function gen_uboot_node()
{
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
+ return
+ fi
+
UBOOT="u-boot-nodtb.bin"
echo " uboot {
description = \"U-Boot\";
@@ -53,10 +57,16 @@
algo = \"sha256\";
};
};"
+
+ LOADABLE_UBOOT="\"uboot\", "
}
function gen_fdt_node()
{
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
+ return
+ fi
+
echo " fdt {
description = \"U-Boot dtb\";
data = /incbin/(\"./u-boot.dtb\");
@@ -67,12 +77,19 @@
algo = \"sha256\";
};
};"
+
+ FDT_SIGN=", \"fdt\""
+ FDT="fdt = \"fdt\"${PROP_KERN_DTB};"
};
function gen_kfdt_node()
{
+ if [ -z ${UBOOT_LOAD_ADDR} ]; then
+ return
+ fi
+
KERN_DTB=`sed -n "/CONFIG_EMBED_KERNEL_DTB_PATH=/s/CONFIG_EMBED_KERNEL_DTB_PATH=//p" .config | tr -d '"'`
- if [ -z "${KERN_DTB}" ]; then
+ if [ -z ${KERN_DTB} ]; then
return;
fi
@@ -96,7 +113,7 @@
${srctree}/arch/arm/mach-rockchip/decode_bl31.py
NUM=1
- for ATF in `ls -l bl31_0x*.bin | sort --key=5 -nr | awk '{ print $9 }'`
+ for ATF in `ls -1 -S bl31_0x*.bin`
do
ATF_LOAD_ADDR=`echo ${ATF} | awk -F "_" '{ printf $2 }' | awk -F "." '{ printf $1 }'`
# only atf-1 support compress
@@ -135,7 +152,9 @@
};"
fi
- if [ ${NUM} -gt 1 ]; then
+ if [ ${NUM} -eq 2 ]; then
+ LOADABLE_ATF=${LOADABLE_ATF}"\"atf-${NUM}\""
+ elif [ ${NUM} -gt 2 ]; then
LOADABLE_ATF=${LOADABLE_ATF}", \"atf-${NUM}\""
fi
NUM=`expr ${NUM} + 1`
@@ -152,6 +171,12 @@
# If not AArch32 mode
if ! grep -q '^CONFIG_ARM64_BOOT_AARCH32=y' .config ; then
ENTRY="entry = <"${TEE_LOAD_ADDR}">;"
+
+ # if disable packing tee.bin
+ if ! grep -q '^CONFIG_SPL_OPTEE=y' .config ; then
+ return
+ fi
+
fi
fi
@@ -179,7 +204,7 @@
};"
LOADABLE_OPTEE=", \"optee\""
FIRMWARE_OPTEE="firmware = \"optee\";"
- FIRMWARE_SIGN=", \"firmware\""
+ FIRMWARE_SIGN="\"firmware\""
}
function gen_mcu_node()
@@ -314,8 +339,13 @@
function gen_arm64_configurations()
{
PLATFORM=`sed -n "/CONFIG_DEFAULT_DEVICE_TREE/p" .config | awk -F "=" '{ print $2 }' | tr -d '"'`
-if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
+if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
ALGO_PADDING=" padding = \"pss\";"
+fi
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
+ ALGO_NAME=" algo = \"sha256,rsa4096\";"
+else
+ ALGO_NAME=" algo = \"sha256,rsa2048\";"
fi
echo " };
@@ -325,14 +355,14 @@
description = \"${PLATFORM}\";
rollback-index = <0x0>;
firmware = \"atf-1\";
- loadables = \"uboot\"${LOADABLE_ATF}${LOADABLE_OPTEE}${LOADABLE_OTHER};
+ loadables = ${LOADABLE_UBOOT}${LOADABLE_ATF}${LOADABLE_OPTEE}${LOADABLE_OTHER};
${STANDALONE_MCU}
- fdt = \"fdt\"${PROP_KERN_DTB};
+ ${FDT}
signature {
- algo = \"sha256,rsa2048\";
+ ${ALGO_NAME}
${ALGO_PADDING}
key-name-hint = \"dev\";
- sign-images = \"fdt\", \"firmware\", \"loadables\"${STANDALONE_SIGN};
+ sign-images = \"firmware\", \"loadables\"${FDT_SIGN}${STANDALONE_SIGN};
};
};
};
@@ -343,9 +373,24 @@
function gen_arm_configurations()
{
PLATFORM=`sed -n "/CONFIG_DEFAULT_DEVICE_TREE/p" .config | awk -F "=" '{ print $2 }' | tr -d '"'`
-if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
+if grep -q '^CONFIG_FIT_ENABLE_RSASSA_PSS_SUPPORT=y' .config ; then
ALGO_PADDING=" padding = \"pss\";"
fi
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
+ ALGO_NAME=" algo = \"sha256,rsa4096\";"
+else
+ ALGO_NAME=" algo = \"sha256,rsa2048\";"
+fi
+if [ ! -z "${LOADABLE_UBOOT}" ] || [ ! -z "${LOADABLE_OTHER}" ]; then
+ LOADABLE_UBOOT="\"uboot\""
+ LOADABLES="loadables = ${LOADABLE_UBOOT}${LOADABLE_OTHER};"
+ if [ -z ${FIRMWARE_SIGN} ]; then
+ LOADABLES_SIGN="\"loadables\""
+ else
+ LOADABLES_SIGN=", \"loadables\""
+ fi
+fi
+
echo " };
configurations {
@@ -354,14 +399,14 @@
description = \"${PLATFORM}\";
rollback-index = <0x0>;
${FIRMWARE_OPTEE}
- loadables = \"uboot\"${LOADABLE_OTHER};
+ ${LOADABLES}
${STANDALONE_MCU}
- fdt = \"fdt\"${PROP_KERN_DTB};
+ ${FDT}
signature {
- algo = \"sha256,rsa2048\";
+ ${ALGO_NAME}
${ALGO_PADDING}
key-name-hint = \"dev\";
- sign-images = \"fdt\", \"loadables\"${FIRMWARE_SIGN}${STANDALONE_SIGN};
+ sign-images = ${FIRMWARE_SIGN}${LOADABLES_SIGN}${FDT_SIGN}${STANDALONE_SIGN};
};
};
};
diff --git a/u-boot/arch/arm/mach-rockchip/hotkey.c b/u-boot/arch/arm/mach-rockchip/hotkey.c
index 37a03df..446547c 100644
--- a/u-boot/arch/arm/mach-rockchip/hotkey.c
+++ b/u-boot/arch/arm/mach-rockchip/hotkey.c
@@ -17,10 +17,10 @@
#define CTRL_D 0x04 /* download mde */
#define CTRL_F 0x06 /* fastboot mode */
#define CTRL_I 0x09 /* inicall debug for kernel */
+#define CTRL_L 0x0c /* late shell(cli) on BOOTM_STATE_OS_GO */
#define CTRL_M 0x0d /* memory(sysmem/bidram) */
#define CTRL_P 0x10 /* parameter(cmdline) dump */
#define CTRL_R 0x12 /* regulator initial state dump */
-#define CTRL_S 0x13 /* shell(cli) on BOOTM_STATE_OS_GO */
#define CTRL_T 0x14 /* print fdt */
bool is_hotkey(enum hotkey_t id)
@@ -75,7 +75,7 @@
cli_loop();
break;
case HK_CLI_OS_GO:
- if (gd->console_evt == CTRL_S)
+ if (gd->console_evt == CTRL_L)
cli_loop();
break;
default:
diff --git a/u-boot/arch/arm/mach-rockchip/kernel_dtb.c b/u-boot/arch/arm/mach-rockchip/kernel_dtb.c
old mode 100755
new mode 100644
index 74da167..05e734f
--- a/u-boot/arch/arm/mach-rockchip/kernel_dtb.c
+++ b/u-boot/arch/arm/mach-rockchip/kernel_dtb.c
@@ -16,503 +16,6 @@
DECLARE_GLOBAL_DATA_PTR;
-
-#if 1
-struct display_fixup_data {
- int type;
-
- int delay_prepare;
- int delay_enable;
- int delay_disable;
- int delay_unprepare;
- int delay_reset;
- int delay_init;
- int size_width;
- int size_height;
-
- int clock_frequency;
- int hactive;
- int hfront_porch;
- int hsync_len;
- int hback_porch;
- int vactive;
- int vfront_porch;
- int vsync_len;
- int vback_porch;
- int hsync_active;
- int vsync_active;
- int de_active;
- int pixelclk_active;
-
- /* for DSI Panel */
- int flags;
- int format;
- int lanes;
- int init_cmd_length;
- u8 *init_cmd;
-
- int nodka_lvds;
-};
-enum {
- PANEL_TYPE_DSI,
- PANEL_TYPE_EDP,
- PANEL_TYPE_LVDS,
-};
-
-#define CUSTOM_PARTITION_NAME "baseparameter"
-#define LCD_PARAM_MAX_COUNT 27
-
-int lcdParam[LCD_PARAM_MAX_COUNT];
-char param_buf_temp[4*1024] = {0};
-
-void set_lcdparam_test_edp(struct display_fixup_data *data)
-{
-
- data->type = PANEL_TYPE_DSI;
- data->delay_prepare = 100;
- data->delay_enable = 100;
- data->delay_disable = 100;
- data->delay_unprepare = 100;
- data->delay_reset = 100;
- data->delay_init = 100;
- data->size_width = 240;
- data->size_height = 300;
- data->clock_frequency = 60000000;
- data->hactive = 1024;
- data->hfront_porch = 12;
- data->hsync_len = 16;
- data->hback_porch = 48;
- data->vactive = 600;
- data->vfront_porch = 8;
- data->vsync_len = 4;
- data->vback_porch = 8;
- data->hsync_active = 0;
- data->vsync_active = 0;
- data->de_active = 0;
- data->pixelclk_active = 0;
- data->flags = 0;
- data->format = 0;
- data->lanes = 4;
- *(data->init_cmd + 0) = 0x05;
- *(data->init_cmd + 1) = 0x00;
- *(data->init_cmd + 2) = 0x01;
- *(data->init_cmd + 3) = 0x01;
-
- *(data->init_cmd + 4) = 0x05;
- *(data->init_cmd + 5) = 0x00;
- *(data->init_cmd + 6) = 0x01;
- *(data->init_cmd + 7) = 0x02;
-
- *(data->init_cmd + 8) = 0x05;
- *(data->init_cmd + 9) = 0x00;
- *(data->init_cmd + 10) = 0x01;
- *(data->init_cmd + 11) = 0x03;
-
- *(data->init_cmd + 12) = 0x05;
- *(data->init_cmd + 13) = 0x00;
- *(data->init_cmd + 14) = 0x01;
- *(data->init_cmd + 15) = 0x05;
-
-}
-
-int get_lcdparam_info_from_custom_partition(struct display_fixup_data *data)
-{
-
- struct blk_desc *dev_desc;
- disk_partition_t part_info;
- char *boot_partname = CUSTOM_PARTITION_NAME;
- int ret,i;
-
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("%s: dev_desc is NULL!\n", __func__);
- return -ENODEV;
- }
-
- ret = part_get_info_by_name(dev_desc, boot_partname, &part_info);
- if (ret < 0) {
- printf("%s: failed to get %s part, ret=%d\n",
- __func__, boot_partname, ret);
- /* RKIMG can support part table without 'boot' */
- return -1;
- }
-
- printf("block num: %lu, name %s ,type %s,block size :%lu\n",part_info.size,part_info.name,part_info.type,part_info.blksz);
-
- ret = blk_dread(dev_desc, part_info.start + 512, 1, param_buf_temp);
- if (ret != 1) {
- printf("%s: failed to read screen parameter, ret=%d\n",
- __func__, ret);
- return -1;
- }
-
- for (i = 0; i < LCD_PARAM_MAX_COUNT; i++) {
- lcdParam[i] = param_buf_temp[i * 4];
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 1];
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 2];
- lcdParam[i] = (lcdParam[i] << 8) + param_buf_temp[i * 4 + 3];
- if(lcdParam[i] < 0){
- lcdParam[i] = -lcdParam[i];
- }
- if(lcdParam[i] > 100000 && i != 9){
- lcdParam[i] = 0;
- }
- printf("--get-- lcd_param %d\n",lcdParam[i]);
- }
-
- if(lcdParam[14] == 0 || lcdParam[10] == 0){
- return -1;
- }
- printf("-get- crc32 = 0X%02X%02X%02X%02X\n",
- param_buf_temp[LCD_PARAM_MAX_COUNT * 4], param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 1],
- param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 2], param_buf_temp[LCD_PARAM_MAX_COUNT * 4 + 3]);
-
- data->type = lcdParam[0];
- data->delay_prepare = lcdParam[4];
- data->delay_enable = lcdParam[2];
- data->delay_disable = lcdParam[3];
- data->delay_unprepare = lcdParam[1];
- data->delay_reset = lcdParam[5];
- data->delay_init = lcdParam[6];
- data->size_width = lcdParam[7];
- data->size_height = lcdParam[8];
- data->clock_frequency = lcdParam[9];
- data->hactive = lcdParam[10];
- data->hfront_porch = lcdParam[11];
- data->hsync_len = lcdParam[12];
- data->hback_porch = lcdParam[13];
- data->vactive = lcdParam[14];
- data->vfront_porch = lcdParam[15];
- data->vsync_len = lcdParam[16];
- data->vback_porch = lcdParam[17];
- data->hsync_active = lcdParam[18];
- data->vsync_active = lcdParam[19];
- data->de_active = lcdParam[20];
- data->pixelclk_active = lcdParam[21];
- data->flags = lcdParam[22];
- data->format = lcdParam[23];
- data->lanes = lcdParam[24];
- data->init_cmd_length = lcdParam[25] = 16;
- data->nodka_lvds = lcdParam[26];
- data->init_cmd = malloc(sizeof(*(data->init_cmd)) * data->init_cmd_length);
- for(i = 0; i < data->init_cmd_length; i++){
- *(data->init_cmd + i) = param_buf_temp[100 + i];
- // printf("init cmd = %x\n",param_buf_temp[100 + i]);
-
- }
-
-// set_lcdparam_test_edp(data);
-
- return 0;
-}
-
-#endif
-
-
-static int find_connector_node(const void *blob, int node)
-{
- int phandle, remote;
- int nodedepth;
-
- phandle = fdt_getprop_u32_default_node(blob, node, 0,
- "remote-endpoint", -1);
- remote = fdt_node_offset_by_phandle(blob, phandle);
- nodedepth = fdt_node_depth(blob, remote);
-
- return fdt_supernode_atdepth_offset(blob, remote,
- nodedepth - 3, NULL);
-}
-
-static int get_panel_node(const void *blob, int conn_node)
-{
- int panel, ports, port, ep, remote, ph, nodedepth;
-
- panel = fdt_subnode_offset(blob, conn_node, "panel");
- printf("panel_1=%d\n",panel);
- if (panel > 0) {
- return panel;
- }
-
- ports = fdt_subnode_offset(blob, conn_node, "ports");
- if (ports < 0)
- {
- return -ENODEV;
- }
-
- fdt_for_each_subnode(port, blob, ports) {
- fdt_for_each_subnode(ep, blob, port) {
- ph = fdt_getprop_u32_default_node(blob, ep, 0,
- "remote-endpoint", 0);
- if (!ph)
- continue;
-
- remote = fdt_node_offset_by_phandle(blob, ph);
-
- nodedepth = fdt_node_depth(blob, remote);
- if (nodedepth < 2)
- continue;
-
- panel = fdt_supernode_atdepth_offset(blob, remote,
- nodedepth - 2,
- NULL);
- break;
- }
- }
- printf("panel_2=%d\n",panel);
- return panel;
-}
-
-static int fdt_fixup_node_status(void *blob, int node, enum fdt_status status)
-{
- int ret;
-
-// printf("My fixup %s %d\n", fdt_get_name(blob, node, NULL), status);
-
-set_status:
- ret = fdt_set_node_status(blob, node, status, 0);
- if (ret == -FDT_ERR_NOSPACE) {
- ret = fdt_increase_size(blob, 512);
- if (!ret)
- goto set_status;
- else
- goto err_size;
- } else if (ret < 0) {
- printf("Can't set node status: %s\n", fdt_strerror(ret));
- return ret;
- }
-
- return 0;
-
-err_size:
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
- return ret;
-}
-#if 0
-static int fdt_fixup_panel_init_sequence(void *fdt, int node,const struct display_fixup_data *data)
-{
- #if 0
- u8 init_buf[] = {0x05, 0x00, 0x01, 0x78, 0x15, 0x01, 0x02, 0x03, 0x04, 0x05, 0x05, 0x01, 0x14,0x39, 0x01, 0x03, 0x02, 0x29, 0x11};
- u8 exit_buf[] = {0x05, 0x64, 0x01, 0x29, 0x05, 0x64, 0x01, 0x11};
- #endif
- int ret;
-
-add_seq:
- ret = fdt_setprop(fdt, node, "panel-init-sequence", data->init_cmd, data->init_cmd_length);
- if (ret == -FDT_ERR_NOSPACE) {
- printf(" init sequence FDT_ERR_NOSPACE\n");
- ret = fdt_increase_size(fdt, data->init_cmd_length * 4);//gln the length needs precision
- if (!ret)
- goto add_seq;
- else
- goto err_size;
- } else if (ret < 0) {
- printf("Can't add property: %s\n", fdt_strerror(ret));
- return ret;
- }
-
-#if 0
-add_init_seq:
- ret = fdt_setprop(fdt, node, "panel-init-sequence", init_buf, sizeof(init_buf));
- if (ret == -FDT_ERR_NOSPACE) {
- printf(" init sequence FDT_ERR_NOSPACE\n");
- ret = fdt_increase_size(fdt, 512);//gln the length needs precision
- if (!ret)
- goto add_init_seq;
- else
- goto err_size;
- } else if (ret < 0) {
- printf("Can't add property: %s\n", fdt_strerror(ret));
- return ret;
- }
-add_exit_seq:
- ret = fdt_setprop(fdt, node, "panel-exit-sequence", exit_buf, sizeof(exit_buf));
- if (ret == -FDT_ERR_NOSPACE) {
- printf(" init sequence FDT_ERR_NOSPACE\n");
- ret = fdt_increase_size(fdt, 512);//gln the length needs precision
- if (!ret)
- goto add_exit_seq;
- else
- goto err_size;
- } else if (ret < 0) {
- printf("Can't add property: %s\n", fdt_strerror(ret));
- return ret;
- }
-#endif
-
- return 0;
-
-err_size:
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
- return ret;
-}
-#endif
-
-static int fdt_fixup_setprop_u32(void *fdt, int node, const char *name, u32 data)
-{
- int ret;
-
-set_prop:
- ret = fdt_setprop_u32(fdt, node, name, data);
- if (ret == -FDT_ERR_NOSPACE) {
- ret = fdt_increase_size(fdt, 512);
- if (!ret)
- goto set_prop;
- else
- goto err_size;
- } else if (ret < 0) {
- printf("Can't add property: %s\n", fdt_strerror(ret));
- return ret;
- }
-
- return 0;
-
-err_size:
- printf("Can't increase blob size: %s\n", fdt_strerror(ret));
- return ret;
-}
-
-static void fdt_fixup_display_timing(void *blob, int node,
- const struct display_fixup_data *data)
-{
- fdt_fixup_setprop_u32(blob, node, "clock-frequency", data->clock_frequency);
- fdt_fixup_setprop_u32(blob, node, "hactive", data->hactive);
- fdt_fixup_setprop_u32(blob, node, "hfront-porch", data->hfront_porch);
- fdt_fixup_setprop_u32(blob, node, "hsync-len", data->hsync_len);
- fdt_fixup_setprop_u32(blob, node, "hback-porch", data->hback_porch);
- fdt_fixup_setprop_u32(blob, node, "vactive", data->vactive);
- fdt_fixup_setprop_u32(blob, node, "vfront-porch", data->vfront_porch);
- fdt_fixup_setprop_u32(blob, node, "vsync-len", data->vsync_len);
- fdt_fixup_setprop_u32(blob, node, "vback-porch", data->vback_porch);
- fdt_fixup_setprop_u32(blob, node, "hsync-active", data->hsync_active);
- fdt_fixup_setprop_u32(blob, node, "vsync-active", data->vsync_active);
- fdt_fixup_setprop_u32(blob, node, "de-active", data->de_active);
- fdt_fixup_setprop_u32(blob, node, "pixelclk-active", data->pixelclk_active);
-}
-
-static void fdt_fixup_panel_node(void *blob, int node, const char *name,
- const struct display_fixup_data *data)
-{
-/*
- if (!strcmp(name, "dsi")) {
- fdt_setprop_u32(blob, node, "dsi,flags", data->flags);
- fdt_setprop_u32(blob, node, "dsi,format", data->format);
- fdt_setprop_u32(blob, node, "dsi,lanes", data->lanes);
- fdt_fixup_panel_init_sequence(blob, node,data);
- }
-*/
- fdt_fixup_setprop_u32(blob, node, "prepare-delay-ms", data->delay_prepare);
- fdt_fixup_setprop_u32(blob, node, "enable-delay-ms", data->delay_enable);
- fdt_fixup_setprop_u32(blob, node, "disable-delay-ms", data->delay_disable);
- fdt_fixup_setprop_u32(blob, node, "unprepare-delay-ms", data->delay_unprepare);
- fdt_fixup_setprop_u32(blob, node, "reset-delay-ms", data->delay_reset);
- fdt_fixup_setprop_u32(blob, node, "init-delay-ms", data->delay_init);
- fdt_fixup_setprop_u32(blob, node, "width-mm", data->size_width);
- fdt_fixup_setprop_u32(blob, node, "height-mm", data->size_height);
-
-}
-static void fdt_fixup_nodka_lvds(void *blob, int node,
- const struct display_fixup_data *data)
-{
- if ( data->nodka_lvds != 0 )
- fdt_fixup_setprop_u32(blob, node, "nodka-lvds", data->nodka_lvds);
-}
-
-
-static int fdt_fixup_display_sub_route(void *blob, const char *name,
- enum fdt_status status,
- const struct display_fixup_data *data)
-{
- int route, phandle, connect, connector, panel, dt, timing, route_lvds;
- char path[64];
- char path_lvds[16] = "/panel";
- int ret;
- sprintf(path, "/display-subsystem/route/route-%s", name);
-
-
- route = fdt_path_offset(blob, path);
- printf("route : %d \n",route);
- if (route < 0)
- return route;
-
- route_lvds = fdt_path_offset(blob, path_lvds);
- if (route_lvds < 0)
- {
- printf("can not get route_lvds = %d\n",route_lvds);
- return route_lvds;
- }
- /* fixup lvds gpio channel*/
- fdt_fixup_nodka_lvds(blob, route_lvds, data);
-
- /* fixup route status */
- ret = fdt_fixup_node_status(blob, route, status);
- if (ret < 0)
- return ret;
- phandle = fdt_getprop_u32_default_node(blob, route, 0, "connect", -1);
- if (phandle < 0)
- return phandle;
- connect = fdt_node_offset_by_phandle(blob, phandle);
- if (connect < 0)
- return connect;
- connector = find_connector_node(blob, connect);
- if (connector < 0)
- return connector;
- /* fixup connector status */
- ret = fdt_fixup_node_status(blob, connector, status);
- if (ret < 0)
- return ret;
- if (status != FDT_STATUS_OKAY) {
- return 0;
- }
- panel = get_panel_node(blob, connector);
- if (panel < 0)
- return panel;
- /* fixup panel info */
- fdt_fixup_panel_node(blob, panel, name, data);
- dt = fdt_subnode_offset(blob, panel, "display-timings");
- if (dt < 0) {
- return dt;
- }
- timing = fdt_subnode_offset(blob, dt, "timing");
- if (timing < 0) {
- phandle = fdt_getprop_u32_default_node(blob, dt, 0, "native-mode", -1);
- if (phandle < 0)
- return phandle;
-
- timing = fdt_node_offset_by_phandle(blob, phandle);
- if (timing < 0)
- return timing;
- }
-
- /* fixup panel display timing */
- fdt_fixup_display_timing(blob, timing, data);
- return 0;
-}
-
-static void fdt_fixup_display_route(void *blob, const struct display_fixup_data *data)
-{
- if (data->type == PANEL_TYPE_DSI) {
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_OKAY, data);
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_DISABLED, data);
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_DISABLED, data);
- } else if (data->type == PANEL_TYPE_EDP) {
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_DISABLED, data);
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_OKAY, data);
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_DISABLED, data);
- } else if (data->type == PANEL_TYPE_LVDS) {
- fdt_fixup_display_sub_route(blob, "lvds", FDT_STATUS_OKAY, data);
- fdt_fixup_display_sub_route(blob, "dsi1", FDT_STATUS_DISABLED, data);
- fdt_fixup_display_sub_route(blob, "edp", FDT_STATUS_DISABLED, data);
- }
-}
-
-
-
-
-
-
-
-
-
#ifdef CONFIG_USING_KERNEL_DTB_V2
static int dm_rm_kernel_dev(void)
{
@@ -798,7 +301,6 @@
#endif
ulong fdt_addr = 0;
int ret = -ENODEV;
- struct display_fixup_data fix_data;
printf("DM: v%d\n", IS_ENABLED(CONFIG_USING_KERNEL_DTB_V2) ? 2 : 1);
@@ -815,12 +317,10 @@
return -ENODEV;
}
- if (IS_ENABLED(CONFIG_EMBED_KERNEL_DTB_ALWAYS)) {
- resource_init_list();
- printf("Always embed kernel dtb\n");
- goto dtb_embed;
- }
-
+#ifdef CONFIG_EMBED_KERNEL_DTB_ALWAYS
+ printf("Always embed kernel dtb\n");
+ goto dtb_embed;
+#endif
ret = rockchip_read_dtb_file((void *)fdt_addr);
if (!ret) {
if (!dtb_check_ok((void *)fdt_addr, (void *)gd->fdt_blob)) {
@@ -831,7 +331,10 @@
}
}
+#ifdef CONFIG_EMBED_KERNEL_DTB
+#ifdef CONFIG_EMBED_KERNEL_DTB_ALWAYS
dtb_embed:
+#endif
if (gd->fdt_blob_kern) {
if (!dtb_check_ok((void *)gd->fdt_blob_kern, (void *)gd->fdt_blob)) {
printf("Embedded kernel dtb mismatch this platform!\n");
@@ -850,7 +353,9 @@
memcpy((void *)fdt_addr, gd->fdt_blob_kern,
fdt_totalsize(gd->fdt_blob_kern));
printf("DTB: %s\n", CONFIG_EMBED_KERNEL_DTB_PATH);
- } else {
+ } else
+#endif
+ {
printf("Failed to get kernel dtb, ret=%d\n", ret);
return -ENOENT;
}
@@ -870,8 +375,6 @@
phandles_fixup_cru((void *)gd->fdt_blob);
phandles_fixup_gpio((void *)gd->fdt_blob, (void *)ufdt_blob);
#endif
- if (!get_lcdparam_info_from_custom_partition(&fix_data))
- fdt_fixup_display_route((void *)fdt_addr, &fix_data);
gd->flags |= GD_FLG_KDTB_READY;
gd->of_root_f = gd->of_root;
diff --git a/u-boot/arch/arm/mach-rockchip/make_fit_uboot.sh b/u-boot/arch/arm/mach-rockchip/make_fit_uboot.sh
deleted file mode 100755
index f7ca5e2..0000000
--- a/u-boot/arch/arm/mach-rockchip/make_fit_uboot.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#!/bin/bash
-#
-# Copyright (C) 2022 Rockchip Electronics Co., Ltd
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-source ./${srctree}/arch/arm/mach-rockchip/fit_nodes.sh
-gen_header
-gen_uboot_node
-gen_mcu_node
-gen_kfdt_node
-gen_fdt_node
-gen_loadable_node
-gen_arm_configurations
-
diff --git a/u-boot/arch/arm/mach-rockchip/pstore.c b/u-boot/arch/arm/mach-rockchip/pstore.c
index 6fc371f..18e452c 100644
--- a/u-boot/arch/arm/mach-rockchip/pstore.c
+++ b/u-boot/arch/arm/mach-rockchip/pstore.c
@@ -103,6 +103,8 @@
gd->pstore_addr = t->u.pstore.buf[LOG_UBOOT].addr;
gd->pstore_size = t->u.pstore.buf[LOG_UBOOT].size - sizeof(struct persistent_ram_buffer);
}
+#elif (CONFIG_PERSISTENT_RAM_ADDR == 0 || CONFIG_PERSISTENT_RAM_SIZE == 0)
+ #error: CONFIG_PERSISTENT_RAM_SIZE and CONFIG_PERSISTENT_RAM_ADDR value should not be 0.
#else
gd->pstore_addr = CONFIG_PERSISTENT_RAM_ADDR;
gd->pstore_size = CONFIG_PERSISTENT_RAM_SIZE - sizeof(struct persistent_ram_buffer);
diff --git a/u-boot/arch/arm/mach-rockchip/resource_hwid.c b/u-boot/arch/arm/mach-rockchip/resource_hwid.c
index 200160b..81e9b20 100644
--- a/u-boot/arch/arm/mach-rockchip/resource_hwid.c
+++ b/u-boot/arch/arm/mach-rockchip/resource_hwid.c
@@ -267,13 +267,8 @@
hwid_init_data();
- if (list_empty(&entrys_head)) {
- if (resource_init_list())
- return NULL;
- }
-
- list_for_each(node, &entrys_dtbs_head) {
- file = list_entry(node, struct resource_file, dtbs);
+ list_for_each(node, &entry_head) {
+ file = list_entry(node, struct resource_file, link);
if (!strstr(file->name, DTB_SUFFIX))
continue;
diff --git a/u-boot/arch/arm/mach-rockchip/resource_img.c b/u-boot/arch/arm/mach-rockchip/resource_img.c
index 03557d7..c2f0989 100644
--- a/u-boot/arch/arm/mach-rockchip/resource_img.c
+++ b/u-boot/arch/arm/mach-rockchip/resource_img.c
@@ -4,28 +4,21 @@
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <adc.h>
-#include <android_ab.h>
-#include <android_bootloader.h>
-#include <android_image.h>
#include <boot_rkimg.h>
#include <bmp_layout.h>
#include <malloc.h>
-#include <asm/io.h>
#include <asm/unaligned.h>
-#include <dm/ofnode.h>
+#include <linux/libfdt.h>
#include <linux/list.h>
-#include <asm/arch/fit.h>
-#include <asm/arch/uimage.h>
#include <asm/arch/resource_img.h>
+#include <asm/arch/uimage.h>
+#include <asm/arch/fit.h>
DECLARE_GLOBAL_DATA_PTR;
#define PART_RESOURCE "resource"
#define RESOURCE_MAGIC "RSCE"
#define RESOURCE_MAGIC_SIZE 4
-#define RESOURCE_VERSION 0
-#define CONTENT_VERSION 0
#define ENTRY_TAG "ENTR"
#define ENTRY_TAG_SIZE 4
#define MAX_FILE_NAME_LEN 220
@@ -70,7 +63,7 @@
*/
/**
- * struct resource_image_header
+ * struct resource_img_hdr
*
* @magic: should be "RSCE"
* @version: resource image version, current is 0
@@ -80,7 +73,6 @@
* @e_blks: the size(by block) of the entry in the contents
* @e_num: numbers of the entrys.
*/
-
struct resource_img_hdr {
char magic[4];
uint16_t version;
@@ -96,499 +88,406 @@
char name[MAX_FILE_NAME_LEN];
char hash[MAX_HASH_LEN];
uint32_t hash_size;
- uint32_t f_offset; /* Sector offset */
- uint32_t f_size; /* Bytes */
+ uint32_t blk_offset;
+ uint32_t size; /* in byte */
};
-LIST_HEAD(entrys_head);
-LIST_HEAD(entrys_dtbs_head);
+LIST_HEAD(entry_head);
-__weak int board_resource_dtb_accepted(char *dtb_name)
+static int resource_check_header(struct resource_img_hdr *hdr)
{
- return 1;
+ return memcmp(RESOURCE_MAGIC, hdr->magic, RESOURCE_MAGIC_SIZE);
}
-int resource_image_check_header(void *rsce_hdr)
+static void resource_dump(struct resource_file *f)
{
- struct resource_img_hdr *hdr = rsce_hdr;
- int ret;
-
- ret = memcmp(RESOURCE_MAGIC, hdr->magic, RESOURCE_MAGIC_SIZE);
- if (ret) {
- debug("bad resource image magic: %s\n",
- hdr->magic ? hdr->magic : "none");
- ret = -EINVAL;
- }
-
- debug("resource image header:\n");
- debug("magic:%s\n", hdr->magic);
- debug("version:%d\n", hdr->version);
- debug("c_version:%d\n", hdr->c_version);
- debug("blks:%d\n", hdr->blks);
- debug("c_offset:%d\n", hdr->c_offset);
- debug("e_blks:%d\n", hdr->e_blks);
- debug("e_num:%d\n", hdr->e_nums);
-
- return ret;
+ printf("%s\n", f->name);
+ printf(" blk_start: 0x%08lx\n", (ulong)f->blk_start);
+ printf(" blk_offset: 0x%08lx\n", (ulong)f->blk_offset);
+ printf(" size: 0x%08x\n", f->size);
+ printf(" in_ram: %d\n", f->in_ram);
+ printf(" hash_size: %d\n\n", f->hash_size);
}
-static int add_file_to_list(struct resource_entry *entry, int rsce_base, bool ram)
+static int resource_add_file(const char *name, u32 size,
+ u32 blk_start, u32 blk_offset,
+ char *hash, u32 hash_size,
+ bool in_ram)
{
- struct resource_file *file;
-
- if (memcmp(entry->tag, ENTRY_TAG, ENTRY_TAG_SIZE)) {
- debug("invalid entry tag\n");
- return -ENOENT;
- }
-
- file = malloc(sizeof(*file));
- if (!file) {
- debug("out of memory\n");
- return -ENOMEM;
- }
-
- strcpy(file->name, entry->name);
- file->rsce_base = rsce_base;
- file->f_offset = entry->f_offset;
- file->f_size = entry->f_size;
- file->hash_size = entry->hash_size;
- file->ram = ram;
- memcpy(file->hash, entry->hash, entry->hash_size);
- INIT_LIST_HEAD(&file->dtbs);
- list_add_tail(&file->link, &entrys_head);
- if (strstr(file->name, DTB_SUFFIX) && board_resource_dtb_accepted(file->name))
- list_add_tail(&file->dtbs, &entrys_dtbs_head);
- debug("ENTRY: addr: %p, name: %18s, base: 0x%08x, offset: 0x%08x, size: 0x%08x\n",
- entry, file->name, file->rsce_base, file->f_offset, file->f_size);
-
- return 0;
-}
-
-int resource_replace_entry(const char *f_name, uint32_t base,
- uint32_t f_offset, uint32_t f_size)
-{
- struct resource_entry *entry;
- struct resource_file *file;
+ struct resource_file *f;
struct list_head *node;
+ bool _new = true;
- if (!f_name || !f_size)
- return -EINVAL;
-
- entry = calloc(1, sizeof(*entry));
- if (!entry)
- return -ENOMEM;
-
- strcpy(entry->tag, ENTRY_TAG);
- strcpy(entry->name, f_name);
- entry->f_offset = f_offset;
- entry->f_size = f_size;
- entry->hash_size = 0;
-
- /* Delete exist entry, then add this new */
- list_for_each(node, &entrys_head) {
- file = list_entry(node, struct resource_file, link);
- if (!strcmp(file->name, entry->name)) {
- list_del(&file->link);
- list_del(&file->dtbs);
- free(file);
+ /* old one ? */
+ list_for_each(node, &entry_head) {
+ f = list_entry(node, struct resource_file, link);
+ if (!strcmp(f->name, name)) {
+ _new = false;
break;
}
}
- add_file_to_list(entry, base, false);
- free(entry);
+ if (_new) {
+ f = calloc(1, sizeof(*f));
+ if (!f)
+ return -ENOMEM;
+
+ list_add_tail(&f->link, &entry_head);
+ }
+
+ strcpy(f->name, name);
+ f->size = size;
+ f->in_ram = in_ram;
+ f->blk_start = blk_start;
+ f->blk_offset = blk_offset;
+ f->hash_size = hash_size;
+ memcpy(f->hash, hash, hash_size);
+#ifdef DEBUG
+ resource_dump(f);
+#endif
+ return 0;
+}
+
+static int resource_setup_list(struct blk_desc *desc, ulong blk_start,
+ void *resc_hdr, bool in_ram)
+{
+ struct resource_img_hdr *hdr = resc_hdr;
+ struct resource_entry *et;
+ u32 i, stride;
+ void *pos;
+
+ pos = (void *)hdr + hdr->c_offset * desc->blksz;
+ stride = hdr->e_blks * desc->blksz;
+
+ for (i = 0; i < hdr->e_nums; i++) {
+ et = pos + (i * stride);
+ if (memcmp(et->tag, ENTRY_TAG, ENTRY_TAG_SIZE))
+ continue;
+
+ resource_add_file(et->name, et->size,
+ blk_start, et->blk_offset,
+ et->hash, et->hash_size, in_ram);
+ }
return 0;
}
-int resource_create_ram_list(struct blk_desc *dev_desc, void *rsce_hdr)
+int resource_setup_ram_list(struct blk_desc *desc, void *hdr)
{
- struct resource_img_hdr *hdr = rsce_hdr;
- struct resource_entry *entry;
- int e_num, size;
- void *data;
- int ret = 0;
+ if (!desc)
+ return -ENODEV;
- if (resource_image_check_header(hdr)) {
- ret = -EINVAL;
- goto out;
+ if (resource_check_header(hdr)) {
+ printf("RESC: invalid\n");
+ return -EINVAL;
}
- list_del_init(&entrys_head);
- list_del_init(&entrys_dtbs_head);
- data = (void *)((ulong)hdr + hdr->c_offset * dev_desc->blksz);
- for (e_num = 0; e_num < hdr->e_nums; e_num++) {
- size = e_num * hdr->e_blks * dev_desc->blksz;
- entry = (struct resource_entry *)(data + size);
- add_file_to_list(entry, (ulong)hdr, true);
+ /* @blk_start: set as 'hdr' point addr, to be used in byte */
+ return resource_setup_list(desc, (ulong)hdr, hdr, true);
+}
+
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+/*
+ * Add logo.bmp and logo_kernel.bmp from "logo" parititon
+ *
+ * Provide a "logo" partition for user to store logo.bmp and
+ * logo_kernel.bmp, so that the user can update them from
+ * kernel or user-space dynamically.
+ *
+ * "logo" partition layout, do not change order:
+ *
+ * |----------------------| 0x00
+ * | raw logo.bmp |
+ * |----------------------| -> 512-byte aligned
+ * | raw logo_kernel.bmp |
+ * |----------------------|
+ *
+ * N: the sector count of logo.bmp
+ *
+ * How to generate:
+ * cat logo.bmp > logo.img && truncate -s %512 logo.img && cat logo_kernel.bmp >> logo.img
+ */
+static int resource_setup_logo_bmp(struct blk_desc *desc)
+{
+ struct bmp_header *header;
+ const char *name[] = { "logo.bmp", "logo_kernel.bmp" };
+ disk_partition_t part;
+ u32 blk_offset = 0;
+ u32 filesz;
+ int ret, i;
+
+ if (part_get_info_by_name(desc, PART_LOGO, &part) < 0)
+ return 0;
+
+ header = memalign(ARCH_DMA_MINALIGN, desc->blksz);
+ if (!header)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(name); i++) {
+ if (blk_dread(desc, part.start + blk_offset, 1, header) != 1) {
+ ret = -EIO;
+ break;
+ }
+
+ if (header->signature[0] != 'B' || header->signature[1] != 'M') {
+ ret = -EINVAL;
+ break;
+ }
+
+ filesz = get_unaligned_le32(&header->file_size);
+ ret = resource_add_file(name[i], filesz, part.start, blk_offset,
+ NULL, 0, false);
+ if (ret)
+ break;
+
+ /* move to next file */
+ blk_offset += DIV_ROUND_UP(filesz, desc->blksz);
+
+ printf("LOGO: %s\n", name[i]);
+
}
-out:
- resource_read_logo_bmps();
+
+ free(header);
return ret;
}
-static int resource_create_list(struct blk_desc *dev_desc, int rsce_base)
+static int resource_setup_blk_list(struct blk_desc *desc, ulong blk_start)
{
struct resource_img_hdr *hdr;
- struct resource_entry *entry;
- int blknum, e_num;
- void *data = NULL;
+ int blk_cnt;
int ret = 0;
- int size;
+ void *buf;
- hdr = memalign(ARCH_DMA_MINALIGN, dev_desc->blksz);
+ hdr = memalign(ARCH_DMA_MINALIGN, desc->blksz);
if (!hdr)
return -ENOMEM;
- if (blk_dread(dev_desc, rsce_base, 1, hdr) != 1) {
- printf("Failed to read resource hdr\n");
+ if (blk_dread(desc, blk_start, 1, hdr) != 1) {
ret = -EIO;
- goto err;
+ goto out;
}
- if (resource_image_check_header(hdr)) {
+ if (resource_check_header(hdr)) {
+ printf("RESC: invalid\n");
if (fdt_check_header(hdr)) {
- printf("No valid resource or dtb file\n");
ret = -EINVAL;
- goto err;
+ goto out;
} else {
- free(hdr);
- return resource_replace_entry(DEFAULT_DTB_FILE, rsce_base,
- 0, fdt_totalsize(hdr));
+ /* this is a dtb file */
+ printf("RESC: this is dtb\n");
+ ret = resource_add_file(DEFAULT_DTB_FILE,
+ fdt_totalsize(hdr),
+ blk_start, 0, NULL, 0, false);
+ goto out;
}
}
- blknum = hdr->e_blks * hdr->e_nums;
- data = memalign(ARCH_DMA_MINALIGN, blknum * dev_desc->blksz);
- if (!data) {
+ blk_cnt = hdr->e_blks * hdr->e_nums;
+ hdr = realloc(hdr, (1 + blk_cnt) * desc->blksz);
+ if (!hdr) {
ret = -ENOMEM;
- goto err;
+ goto out;
}
- if (blk_dread(dev_desc, rsce_base + hdr->c_offset,
- blknum, data) != blknum) {
- printf("Failed to read resource entries\n");
+ buf = (void *)hdr + desc->blksz;
+ if (blk_dread(desc, blk_start + hdr->c_offset, blk_cnt, buf) != blk_cnt) {
ret = -EIO;
- goto err;
+ goto out;
}
- /*
- * Add all file into resource file list, and load what we want from
- * storage when we really need it.
- */
- for (e_num = 0; e_num < hdr->e_nums; e_num++) {
- size = e_num * hdr->e_blks * dev_desc->blksz;
- entry = (struct resource_entry *)(data + size);
- add_file_to_list(entry, rsce_base, false);
- }
-
-err:
- if (data)
- free(data);
- if (hdr)
- free(hdr);
-
- resource_read_logo_bmps();
+ resource_setup_list(desc, blk_start, hdr, false);
+ resource_setup_logo_bmp(desc);
+out:
+ free(hdr);
return ret;
}
-static int read_dtb_from_android(struct blk_desc *dev_desc,
- struct andr_img_hdr *hdr,
- ulong rsce_base)
+static int resource_init(struct blk_desc *desc,
+ disk_partition_t *part,
+ ulong blk_offset)
{
- ulong dtb_offset = 0;
- ulong dtb_size = 0;
+ printf("RESC: '%s', blk@0x%08lx\n", part->name, part->start + blk_offset);
- if (!hdr || hdr->header_version <= 1) {
- return 0;
- } else if (hdr->header_version == 2) {
- dtb_offset += hdr->page_size;
- dtb_offset += ALIGN(hdr->kernel_size, hdr->page_size);
- dtb_offset += ALIGN(hdr->ramdisk_size, hdr->page_size);
- dtb_offset += ALIGN(hdr->recovery_dtbo_size, hdr->page_size) +
- ALIGN(hdr->second_size, hdr->page_size);
- dtb_size = hdr->dtb_size;
- } else if (hdr->header_version >= 3) {
- ulong vendor_boot_hdr_size = (hdr->header_version == 3) ?
- VENDOR_BOOT_HDRv3_SIZE : VENDOR_BOOT_HDRv4_SIZE;
+#ifdef CONFIG_ANDROID_AVB
+ char hdr[512];
+ ulong resc_buf = 0;
+ int ret;
- dtb_offset += ALIGN(vendor_boot_hdr_size,
- hdr->vendor_page_size) +
- ALIGN(hdr->vendor_ramdisk_size,
- hdr->vendor_page_size);
- dtb_size = hdr->dtb_size;
+ if (blk_dread(desc, part->start, 1, hdr) != 1)
+ return -EIO;
+
+ /* only handle android boot/recovery.img and resource.img, ignore fit */
+ if (!android_image_check_header((void *)hdr) ||
+ !resource_check_header((void *)hdr)) {
+ ret = android_image_verify_resource((const char *)part->name, &resc_buf);
+ if (ret) {
+ printf("RESC: '%s', avb verify fail: %d\n", part->name, ret);
+ return ret;
+ }
+
+ /*
+ * unlock=0: resc_buf is valid and file was already full load in ram.
+ * unlock=1: resc_buf is 0.
+ */
+ if (resc_buf && !resource_check_header((void *)resc_buf))
+ return resource_setup_ram_list(desc, (void *)resc_buf);
}
+#endif
- if (!dtb_size)
- return 0;
+ return resource_setup_blk_list(desc, part->start + blk_offset);
+}
- /*
- * boot_img_hdr_v234 feature.
- *
- * If dtb position is present, replace the old with new one if
- * we don't need to verify DTB hash from resource.img file entry.
- */
- dtb_offset = DIV_ROUND_UP(dtb_offset, dev_desc->blksz);
- env_update("bootargs", "androidboot.dtb_idx=0");
+static int resource_default(struct blk_desc *desc,
+ disk_partition_t *out_part,
+ ulong *out_blk_offset)
+{
+ disk_partition_t part;
+
+ if (part_get_info_by_name(desc, PART_RESOURCE, &part) < 0)
+ return -ENODEV;
+
+ *out_part = part;
+ *out_blk_offset = 0;
return 0;
}
+#endif
-static int get_resource_base_sector(struct blk_desc *dev_desc,
- struct andr_img_hdr **ret_hdr)
+static int resource_scan(void)
{
+ struct blk_desc *desc = rockchip_get_bootdev();
+ __maybe_unused int ret;
+
+ if (!desc) {
+ printf("RESC: No bootdev\n");
+ return -ENODEV;
+ }
+
+ if (!list_empty(&entry_head))
+ return 0;
+
+#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
+ ret = fit_image_init_resource(desc);
+ if (!ret || ret != -EAGAIN)
+ return ret;
+#endif
+#ifdef CONFIG_ROCKCHIP_UIMAGE
+ ret = uimage_init_resource(desc);
+ if (!ret || ret != -EAGAIN)
+ return ret;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
disk_partition_t part;
- int rsce_base = 0;
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- struct andr_img_hdr *hdr;
- u32 os_ver = 0, os_lvl;
- const char *part_boot = PART_BOOT;
+ ulong blk_offset;
+ char hdr[512];
+ char name[32];
- /*
- * Anyway, we must read android hdr firstly from boot/recovery partition
- * to get the 'os_version' for android_bcb_msg_sector_offset(), in order
- * to confirm BCB message offset of *MISC* partition.
- */
-#ifdef CONFIG_ANDROID_AB
- part_boot = ab_can_find_recovery_part() ? PART_RECOVERY : PART_BOOT;
-#endif
+ /* partition priority: boot/recovery > resource */
+ if (!android_image_init_resource(desc, &part, &blk_offset)) {
+ if (blk_dread(desc, part.start + blk_offset, 1, hdr) != 1)
+ return -EIO;
- if (part_get_info_by_name(dev_desc, part_boot, &part) < 0)
- goto resource_part;
+ if (resource_check_header((void *)hdr)) {
+ strcpy(name, (char *)part.name);
+ if (resource_default(desc, &part, &blk_offset))
+ return -ENOENT;
- hdr = populate_andr_img_hdr(dev_desc, &part);
- if (hdr) {
- os_ver = hdr->os_version >> 11;
- os_lvl = hdr->os_version & ((1U << 11) - 1);
- if (os_ver)
- gd->bd->bi_andr_version = hdr->os_version;
- }
-
-#ifndef CONFIG_ANDROID_AB
- /* Get boot mode from misc and read if recovery mode */
- if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY) {
- if (hdr)
- free(hdr);
-
- if (part_get_info_by_name(dev_desc, PART_RECOVERY, &part) < 0)
- goto resource_part;
-
- hdr = populate_andr_img_hdr(dev_desc, &part);
- if (!hdr)
- goto resource_part;
- }
-#endif
- /* If Android v012, getting resource from second position ! */
- if (hdr) {
- if (os_ver)
- printf("Android %u.%u, Build %u.%u, v%d\n",
- (os_ver >> 14) & 0x7F, (os_ver >> 7) & 0x7F,
- (os_lvl >> 4) + 2000, os_lvl & 0x0F,
- hdr->header_version);
- *ret_hdr = hdr;
- if (hdr->header_version < 3) {
- rsce_base = part.start * dev_desc->blksz;
- rsce_base += hdr->page_size;
- rsce_base += ALIGN(hdr->kernel_size, hdr->page_size);
- rsce_base += ALIGN(hdr->ramdisk_size, hdr->page_size);
- rsce_base = DIV_ROUND_UP(rsce_base, dev_desc->blksz);
- goto finish;
+ printf("RESC: '%s' -> '%s'\n", name, part.name);
}
- }
-resource_part:
-#endif
- /* resource partition */
- if (part_get_info_by_name(dev_desc, PART_RESOURCE, &part) < 0) {
- printf("No resource partition\n");
- return -ENODEV;
} else {
- rsce_base = part.start;
+ if (resource_default(desc, &part, &blk_offset))
+ return -ENOENT;
}
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
-finish:
+
+ /* now, 'part' can be boot/recovery/resource */
+ return resource_init(desc, &part, blk_offset);
#endif
- printf("Found DTB in %s part\n", part.name);
-
- return rsce_base;
+ return -ENOENT;
}
-/*
- * There are: logo/battery pictures and dtb file in the resource image by default.
- *
- * This function does:
- *
- * 1. Get resource image base sector from: boot/recovery(AOSP) > resource(RK)
- * 2. Create resource files list(addition: add logo bmps)
- * 3. Add dtb from android v2 dtb pos, override the old one from resource file
- */
-int resource_init_list(void)
+static struct resource_file *resource_get_file(const char *name)
{
- struct andr_img_hdr *hdr = NULL;
- struct blk_desc *dev_desc;
- int rsce_base;
-
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("No dev_desc!\n");
- return -ENODEV;
- }
-
- rsce_base = get_resource_base_sector(dev_desc, &hdr);
- if (rsce_base > 0) {
- if (resource_create_list(dev_desc, rsce_base))
- printf("Failed to create resource list\n");
- }
-
- /* override the resource dtb with android dtb if need */
- return read_dtb_from_android(dev_desc, hdr, rsce_base);
-}
-
-int resource_is_empty(void)
-{
- return list_empty(&entrys_head);
-}
-
-static struct resource_file *get_file_info(const char *name)
-{
- struct resource_file *file;
+ struct resource_file *f;
struct list_head *node;
- if (list_empty(&entrys_head)) {
- if (resource_init_list())
- return NULL;
- }
+ if (resource_scan())
+ return NULL;
- list_for_each(node, &entrys_head) {
- file = list_entry(node, struct resource_file, link);
- if (!strcmp(file->name, name))
- return file;
+ list_for_each(node, &entry_head) {
+ f = list_entry(node, struct resource_file, link);
+ if (!strcmp(f->name, name))
+ return f;
}
return NULL;
}
-/*
- * read file from resource partition
- * @buf: destination buf to store file data;
- * @name: file name
- * @offset: blocks offset in the file, 1 block = 512 bytes
- * @len: the size(by bytes) of file to read.
- */
-int rockchip_read_resource_file(void *buf, const char *name, int offset, int len)
+int rockchip_read_resource_file(void *buf, const char *name, int blk_offset, int len)
{
- struct resource_file *file;
- struct blk_desc *dev_desc;
- int ret = 0;
- int blks;
- ulong src;
+ struct blk_desc *desc = rockchip_get_bootdev();
+ struct resource_file *f;
+ int blk_cnt;
+ ulong pos;
- file = get_file_info(name);
- if (!file) {
- printf("No file: %s\n", name);
+ if (!desc)
+ return -ENODEV;
+
+ f = resource_get_file(name);
+ if (!f) {
+ printf("No resource file: %s\n", name);
return -ENOENT;
}
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("No dev_desc!\n");
- return -ENODEV;
- }
+ if (len <= 0 || len > f->size)
+ len = f->size;
- if (len <= 0 || len > file->f_size)
- len = file->f_size;
-
- if (file->ram) {
- src = file->rsce_base +
- (file->f_offset + offset) * dev_desc->blksz;
- memcpy(buf, (char *)src, len);
- ret = len;
+ if (f->in_ram) {
+ pos = f->blk_start + (f->blk_offset + blk_offset) * desc->blksz;
+ memcpy(buf, (char *)pos, len);
} else {
- blks = DIV_ROUND_UP(len, dev_desc->blksz);
- ret = blk_dread(dev_desc,
- file->rsce_base + file->f_offset + offset,
- blks, buf);
- ret = (ret != blks) ? -EIO : len;
+ blk_cnt = DIV_ROUND_UP(len, desc->blksz);
+ if (blk_dread(desc,
+ f->blk_start + f->blk_offset + blk_offset,
+ blk_cnt, buf) != blk_cnt)
+ len = -EIO;
}
- return ret;
+ return len;
}
-static struct resource_file *get_default_dtb(void)
-{
- struct resource_file *target_file = NULL;
- struct resource_file *file;
- struct list_head *node;
- int num = 0;
-
- if (list_empty(&entrys_head)) {
- if (resource_init_list())
- return NULL;
- }
-
- list_for_each(node, &entrys_dtbs_head) {
- num++;
- file = list_entry(node, struct resource_file, dtbs);
- if (strcmp(file->name, DEFAULT_DTB_FILE))
- target_file = file;
- }
-
- /*
- * two possible case:
- * case 1. rk-kernel.dtb only
- * case 2. targe_file(s) + rk-kernel.dtb(maybe they are the same),
- * use (last)target_file as result one.
- */
- if (num > 2)
- printf("Error: find duplicate(%d) dtbs\n", num);
-
- return target_file ? : get_file_info(DEFAULT_DTB_FILE);
-}
+extern struct resource_file *resource_read_hwid_dtb(void);
int rockchip_read_resource_dtb(void *fdt_addr, char **hash, int *hash_size)
{
- struct resource_file *file = NULL;
+ struct resource_file *f = NULL;
int ret;
#ifdef CONFIG_ROCKCHIP_HWID_DTB
- file = resource_read_hwid_dtb();
-#endif
- /* If no dtb matches hardware id(GPIO/ADC), use the default */
- if (!file)
- file = get_default_dtb();
+ if (resource_scan())
+ return -ENOENT;
- if (!file)
+ f = resource_read_hwid_dtb();
+#endif
+ /* If no dtb match hardware id(GPIO/ADC), use the default */
+ if (!f)
+ f = resource_get_file(DEFAULT_DTB_FILE);
+
+ if (!f)
return -ENODEV;
- ret = rockchip_read_resource_file(fdt_addr, file->name, 0, 0);
+ ret = rockchip_read_resource_file(fdt_addr, f->name, 0, 0);
if (ret < 0)
return ret;
if (fdt_check_header(fdt_addr))
return -EBADF;
- *hash = file->hash;
- *hash_size = file->hash_size;
- printf("DTB: %s\n", file->name);
+ *hash = f->hash;
+ *hash_size = f->hash_size;
- return 0;
-}
-
-int resource_traverse_init_list(void)
-{
- if (!resource_is_empty())
- return 0;
-
-#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
- if (!fit_image_init_resource())
- return 0;
-#endif
-#ifdef CONFIG_ROCKCHIP_UIMAGE
- if (!uimage_init_resource())
- return 0;
-#endif
- /* Android image is default supported within resource core */
+ printf("DTB: %s\n", f->name);
return 0;
}
@@ -596,30 +495,20 @@
static int do_dump_resource(cmd_tbl_t *cmdtp, int flag,
int argc, char *const argv[])
{
- struct resource_file *file;
+ struct resource_file *f;
struct list_head *node;
- printf("Resources:\n");
- list_for_each(node, &entrys_head) {
- file = list_entry(node, struct resource_file, link);
- printf(" %s: 0x%08x(sector), 0x%08x(bytes)\n",
- file->name, file->rsce_base + file->f_offset, file->f_size);
+ list_for_each(node, &entry_head) {
+ f = list_entry(node, struct resource_file, link);
+ resource_dump(f);
}
-#ifdef CONFIG_ROCKCHIP_HWID_DTB
- printf("DTBs:\n");
- list_for_each(node, &entrys_dtbs_head) {
- file = list_entry(node, struct resource_file, dtbs);
- printf(" %s: 0x%08x(sector),0x%08x(bytes)\n",
- file->name, file->rsce_base + file->f_offset, file->f_size);
- }
-#endif
return 0;
}
U_BOOT_CMD(
dump_resource, 1, 1, do_dump_resource,
- "dump resource list",
+ "dump resource files",
""
);
diff --git a/u-boot/arch/arm/mach-rockchip/resource_logo.c b/u-boot/arch/arm/mach-rockchip/resource_logo.c
deleted file mode 100644
index 7d40ddf..0000000
--- a/u-boot/arch/arm/mach-rockchip/resource_logo.c
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * (C) Copyright 2021 Rockchip Electronics Co., Ltd
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <adc.h>
-#include <boot_rkimg.h>
-#include <bmp_layout.h>
-#include <malloc.h>
-#include <asm/io.h>
-#include <asm/unaligned.h>
-#include <asm/arch/resource_img.h>
-#include <dm/ofnode.h>
-
-static int read_bmp(struct blk_desc *dev_desc, const char *name,
- disk_partition_t *part, uint32_t offset,
- uint32_t *size)
-{
- struct bmp_header *header;
- u32 blk_offset;
- u32 filesz;
- int ret;
-
- blk_offset = DIV_ROUND_UP(offset, dev_desc->blksz);
- header = memalign(ARCH_DMA_MINALIGN, dev_desc->blksz);
- if (!header) {
- ret = -ENOMEM;
- goto out;
- }
-
- if (blk_dread(dev_desc, part->start + blk_offset, 1, header) != 1) {
- ret = -EIO;
- goto out;
- }
-
- if (header->signature[0] != 'B' || header->signature[1] != 'M') {
- ret = -EINVAL;
- goto out;
- }
-
- filesz = get_unaligned_le32(&header->file_size);
- ret = resource_replace_entry(name, part->start, blk_offset, filesz);
- if (!ret) {
- printf("LOGO: %s\n", name);
- if (size)
- *size = filesz;
- }
-out:
- free(header);
-
- return ret;
-}
-
-/*
- * Add logo.bmp and logo_kernel.bmp from "logo" parititon
- *
- * Provide a "logo" partition for user to store logo.bmp and
- * logo_kernel.bmp, so that the user can update them from
- * kernel or user-space dynamically.
- *
- * "logo" partition layout, do not change order:
- *
- * |----------------------| 0x00
- * | raw logo.bmp |
- * |----------------------| N*512-byte aligned
- * | raw logo_kernel.bmp |
- * |----------------------|
- *
- * N: the sector count of logo.bmp
- *
- * How to generate:
- * cat logo.bmp > logo.img && truncate -s %512 logo.img && cat logo_kernel.bmp >> logo.img
- */
-int resource_read_logo_bmps(void)
-{
- struct blk_desc *dev_desc;
- disk_partition_t part;
- u32 filesz;
-
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("No dev_desc!\n");
- return -ENODEV;
- }
-
- if (part_get_info_by_name(dev_desc, PART_LOGO, &part) < 0)
- return -ENODEV;
-
- if (!read_bmp(dev_desc, "logo.bmp", &part, 0, &filesz))
- read_bmp(dev_desc, "logo_kernel.bmp", &part, filesz, NULL);
-
- return 0;
-}
-
diff --git a/u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c b/u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
index 965afde..ea14298 100644
--- a/u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
+++ b/u-boot/arch/arm/mach-rockchip/rk3036/syscon_rk3036.c
@@ -18,4 +18,7 @@
.name = "rk3036_syscon",
.id = UCLASS_SYSCON,
.of_match = rk3036_syscon_ids,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
};
diff --git a/u-boot/arch/arm/mach-rockchip/rk3528/Kconfig b/u-boot/arch/arm/mach-rockchip/rk3528/Kconfig
new file mode 100644
index 0000000..d1ab9f2
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3528/Kconfig
@@ -0,0 +1,17 @@
+if ROCKCHIP_RK3528
+
+config TARGET_EVB_RK3528
+ bool "EVB_RK3528"
+ select BOARD_LATE_INIT
+ help
+ RK3528 EVB is a evaluation board for Rockchp RK3528.
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+source board/rockchip/evb_rk3528/Kconfig
+
+endif
diff --git a/u-boot/arch/arm/mach-rockchip/rk3528/Makefile b/u-boot/arch/arm/mach-rockchip/rk3528/Makefile
new file mode 100644
index 0000000..81f6939
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3528/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2020 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy)
+obj-y += syscon_rk3528.o
+endif
+obj-y += rk3528.o
+obj-y += clk_rk3528.o
diff --git a/u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c b/u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
new file mode 100644
index 0000000..639bf73
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3528/clk_rk3528.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3528.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3528_cru), devp);
+}
+
+#if CONFIG_IS_ENABLED(CLK_SCMI)
+int rockchip_get_scmi_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(scmi_clock), devp);
+}
+#endif
+
+void *rockchip_get_cru(void)
+{
+ struct rk3528_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
diff --git a/u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c b/u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c
new file mode 100644
index 0000000..3aae2e8
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3528/rk3528.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3528.h>
+#include <asm/arch/ioc_rk3528.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FIREWALL_DDR_BASE 0xff2e0000
+#define FW_DDR_MST1_REG 0x44
+#define FW_DDR_MST6_REG 0x58
+#define FW_DDR_MST7_REG 0x5c
+#define FW_DDR_MST11_REG 0x6c
+#define FW_DDR_MST14_REG 0x78
+#define FW_DDR_MST16_REG 0x80
+#define FW_DDR_MST_REG 0xf0
+
+#define VENC_GRF_BASE 0xff320000
+#define VENC_GRF_CON1 0x4
+
+#define VPU_GRF_BASE 0xff340000
+#define VPU_GRF_CON4 0x14
+
+#define PMU_SGRF_BASE 0xff440000
+#define PMU_SGRF_SOC_CON4 0x10
+#define PMU_SGRF_SOC_CON5 0x14
+#define PMU_SGRF_SOC_CON6 0x18
+#define PMU_SGRF_SOC_CON8 0x20
+#define PMU_SGRF_SOC_CON11 0x2c
+
+#define PMU_CRU_BASE 0xff4b0000
+#define PMU_CRU_GATE_CON00 0x800
+#define PMU_CRU_SOFTRST_CON00 0xa00
+
+#define GPIO1C_IOMUX_SEL_H 0x034
+#define GPIO1D_IOMUX_SEL_L 0x038
+#define GPIO1D_IOMUX_SEL_H 0x03c
+
+#define CPU_PRIORITY_REG 0xff210008
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region rk3528_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xfc000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x04000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3528_mem_map;
+#endif
+
+#define GPIO0_IOC_BASE 0xFF540000
+#define GPIO1_IOC_BASE 0xFF560000
+#define GPIO2_IOC_BASE 0xFF570000
+#define GPIO3_IOC_BASE 0xFF560000
+#define GPIO4_IOC_BASE 0xFF550000
+
+#define GPIO1_IOC_GPIO1D_IOMUX_SEL_L (GPIO1_IOC_BASE + 0x38)
+#define GPIO1_IOC_GPIO1C_DS_2 (GPIO1_IOC_BASE + 0x148)
+#define GPIO1_IOC_GPIO1C_DS_3 (GPIO1_IOC_BASE + 0x14C)
+#define GPIO1_IOC_GPIO1D_DS_0 (GPIO1_IOC_BASE + 0x150)
+#define GPIO1_IOC_GPIO1D_DS_1 (GPIO1_IOC_BASE + 0x154)
+#define GPIO1_IOC_GPIO1D_DS_2 (GPIO1_IOC_BASE + 0x158)
+
+/* uart0 iomux */
+/* gpio4c7 */
+#define UART0_RX_M0 1
+#define UART0_RX_M0_OFFSET 12
+#define UART0_RX_M0_ADDR (GPIO4_IOC_BASE + 0x94)
+/* gpio4d0 */
+#define UART0_TX_M0 1
+#define UART0_TX_M0_OFFSET 0
+#define UART0_TX_M0_ADDR (GPIO4_IOC_BASE + 0x98)
+
+/* gpio2a0 */
+#define UART0_RX_M1 2
+#define UART0_RX_M1_OFFSET 0
+#define UART0_RX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
+/* gpio2a1 */
+#define UART0_TX_M1 2
+#define UART0_TX_M1_OFFSET 4
+#define UART0_TX_M1_ADDR (GPIO2_IOC_BASE + 0x40)
+
+/* uart1 iomux */
+/* gpio4a7 */
+#define UART1_RX_M0 2
+#define UART1_RX_M0_OFFSET 12
+#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
+/* gpio4a6 */
+#define UART1_TX_M0 2
+#define UART1_TX_M0_OFFSET 8
+#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x84)
+
+/* gpio4c6 */
+#define UART1_RX_M1 2
+#define UART1_RX_M1_OFFSET 8
+#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
+/* gpio4c5 */
+#define UART1_TX_M1 2
+#define UART1_TX_M1_OFFSET 4
+#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x94)
+
+/* uart2 iomux */
+/* gpio3a0 */
+#define UART2_RX_M0 1
+#define UART2_RX_M0_OFFSET 0
+#define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
+/* gpio3a1 */
+#define UART2_TX_M0 1
+#define UART2_TX_M0_OFFSET 4
+#define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)
+
+/* gpio1b0 */
+#define UART2_RX_M1 1
+#define UART2_RX_M1_OFFSET 0
+#define UART2_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
+/* gpio1b1 */
+#define UART2_TX_M1 1
+#define UART2_TX_M1_OFFSET 4
+#define UART2_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
+
+/* uart3 iomux */
+/* gpio4b0 */
+#define UART3_RX_M0 2
+#define UART3_RX_M0_OFFSET 0
+#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
+/* gpio4b1 */
+#define UART3_TX_M0 2
+#define UART3_TX_M0_OFFSET 4
+#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x88)
+
+/* gpio4b7 */
+#define UART3_RX_M1 3
+#define UART3_RX_M1_OFFSET 12
+#define UART3_RX_M1_ADDR (GPIO4_IOC_BASE + 0x8C)
+/* gpio4c0 */
+#define UART3_TX_M1 3
+#define UART3_TX_M1_OFFSET 0
+#define UART3_TX_M1_ADDR (GPIO4_IOC_BASE + 0x90)
+
+/* uart4 iomux */
+/* gpio2a2 */
+#define UART4_RX_M0 3
+#define UART4_RX_M0_OFFSET 8
+#define UART4_RX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
+/* gpio2a3 */
+#define UART4_TX_M0 3
+#define UART4_TX_M0_OFFSET 12
+#define UART4_TX_M0_ADDR (GPIO2_IOC_BASE + 0x40)
+
+/* uart5 iomux */
+/* gpio1a2 */
+#define UART5_RX_M0 2
+#define UART5_RX_M0_OFFSET 8
+#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
+/* gpio1a3 */
+#define UART5_TX_M0 2
+#define UART5_TX_M0_OFFSET 12
+#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x20)
+
+/* gpio1d4 */
+#define UART5_RX_M1 2
+#define UART5_RX_M1_OFFSET 0
+#define UART5_RX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
+/* gpio1d7 */
+#define UART5_TX_M1 2
+#define UART5_TX_M1_OFFSET 12
+#define UART5_TX_M1_ADDR (GPIO1_IOC_BASE + 0x3c)
+
+/* uart6 iomux */
+/* gpio3a7 */
+#define UART6_RX_M0 4
+#define UART6_RX_M0_OFFSET 12
+#define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
+/* gpio3a6 */
+#define UART6_TX_M0 4
+#define UART6_TX_M0_OFFSET 8
+#define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)
+
+/* gpio3c3 */
+#define UART6_RX_M1 4
+#define UART6_RX_M1_OFFSET 12
+#define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
+/* gpio3c1 */
+#define UART6_TX_M1 4
+#define UART6_TX_M1_OFFSET 4
+#define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)
+
+/* uart7 iomux */
+/* gpio3b3 */
+#define UART7_RX_M0 4
+#define UART7_RX_M0_OFFSET 12
+#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
+/* gpio3b2 */
+#define UART7_TX_M0 4
+#define UART7_TX_M0_OFFSET 8
+#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
+
+/* gpio1b3 */
+#define UART7_RX_M1 4
+#define UART7_RX_M1_OFFSET 12
+#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
+/* gpio1b2 */
+#define UART7_TX_M1 4
+#define UART7_TX_M1_OFFSET 8
+#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x28)
+
+
+#define set_uart_iomux(bits_offset, bits_val, addr) \
+ writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
+
+#define set_uart_iomux_rx(ID, MODE) \
+ set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
+#define set_uart_iomux_tx(ID, MODE) \
+ set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
+
+void board_debug_uart_init(void)
+{
+/* UART 0 */
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART0_M0 Switch iomux */
+ set_uart_iomux_rx(0, 0);
+ set_uart_iomux_tx(0, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART0_M1 Switch iomux */
+ set_uart_iomux_rx(0, 1);
+ set_uart_iomux_tx(0, 1);
+#endif
+/* UART 1 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff9f8000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART1_M0 Switch iomux */
+ set_uart_iomux_rx(1, 0);
+ set_uart_iomux_tx(1, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART1_M1 Switch iomux */
+ set_uart_iomux_rx(1, 1);
+ set_uart_iomux_tx(1, 1);
+#endif
+/* UART 2 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa00000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART2_M0 Switch iomux */
+ set_uart_iomux_rx(2, 0);
+ set_uart_iomux_tx(2, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART2_M1 Switch iomux */
+ set_uart_iomux_rx(2, 1);
+ set_uart_iomux_tx(2, 1);
+#endif
+/* UART 3 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa08000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART3_M0 Switch iomux */
+ set_uart_iomux_rx(3, 0);
+ set_uart_iomux_tx(3, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART3_M1 Switch iomux */
+ set_uart_iomux_rx(3, 1);
+ set_uart_iomux_tx(3, 1);
+#endif
+/* UART 4 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa10000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART4_M0 Switch iomux */
+ set_uart_iomux_rx(4, 0);
+ set_uart_iomux_tx(4, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART4_M1 Switch iomux */
+ set_uart_iomux_rx(4, 1);
+ set_uart_iomux_tx(4, 1);
+#endif
+/* UART 5 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa18000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART5_M0 Switch iomux */
+ set_uart_iomux_rx(5, 0);
+ set_uart_iomux_tx(5, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART5_M1 Switch iomux */
+ set_uart_iomux_rx(5, 1);
+ set_uart_iomux_tx(5, 1);
+#endif
+/* UART 6 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa20000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART6_M0 Switch iomux */
+ set_uart_iomux_rx(6, 0);
+ set_uart_iomux_tx(6, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART6_M1 Switch iomux */
+ set_uart_iomux_rx(6, 1);
+ set_uart_iomux_tx(6, 1);
+#endif
+/* UART 7 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xffa28000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART7_M0 Switch iomux */
+ set_uart_iomux_rx(7, 0);
+ set_uart_iomux_tx(7, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART7_M1 Switch iomux */
+ set_uart_iomux_rx(7, 1);
+ set_uart_iomux_tx(7, 1);
+#endif
+#endif
+}
+
+#ifdef CONFIG_SPL_BUILD
+void rockchip_stimer_init(void)
+{
+ /* If Timer already enabled, don't re-init it */
+ u32 reg = readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+
+ if (reg & 0x1)
+ return;
+
+ asm volatile("msr CNTFRQ_EL0, %0" : : "r" (COUNTER_FREQUENCY));
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x14);
+ writel(0xffffffff, CONFIG_ROCKCHIP_STIMER_BASE + 0x18);
+ dsb();
+ writel(0x1, CONFIG_ROCKCHIP_STIMER_BASE + 0x4);
+}
+#endif
+
+int arch_cpu_init(void)
+{
+#if defined(CONFIG_SPL_BUILD)
+ u32 val;
+
+ /*
+ * Select clk_tx source as default for i2s2/i2s3
+ * Set I2Sx_MCLK as input default
+ *
+ * It's safe to set mclk as input default to avoid high freq glitch
+ * which may make devices work unexpected. And then enabled by
+ * kernel stage or any state where user use it.
+ */
+ writel(0x00020002, VPU_GRF_BASE + VPU_GRF_CON4);
+ writel(0x40004000, VENC_GRF_BASE + VENC_GRF_CON1);
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /* Set the sdmmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG);
+
+ /* Set the crypto to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG);
+
+#if defined(CONFIG_ROCKCHIP_SFC)
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+#endif
+
+#ifndef CONFIG_TPL_BUILD
+ /* Set cpu qos priority, then
+ * Peri > VOP > CPU = RKVDEC/RKVENC/VPU > GPU/RGA/Other
+ */
+ writel(QOS_PRIORITY_LEVEL(2, 2), CPU_PRIORITY_REG);
+#endif
+
+ if (readl(GPIO1_IOC_GPIO1D_IOMUX_SEL_L) == 0x1111) {
+ /*
+ * set the emmc io drive strength:
+ * data and cmd: level 3
+ * clock: level 5
+ */
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_2);
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1C_DS_3);
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_0);
+ writel(0x3F3F0F0F, GPIO1_IOC_GPIO1D_DS_1);
+ writel(0x3F3F3F0F, GPIO1_IOC_GPIO1D_DS_2);
+ }
+
+#elif defined(CONFIG_SUPPORT_USBPLUG)
+ u32 val;
+
+ /* Set the usb to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+ writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST16_REG);
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /* Set emmc iomux */
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
+ writel(0xffff1111, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
+
+#if defined(CONFIG_ROCKCHIP_SFC)
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+ writel(val & 0xFFFF0000uL, FIREWALL_DDR_BASE + FW_DDR_MST7_REG);
+
+ /* Set fspi iomux */
+ writel(0xffff2222, GPIO1_IOC_BASE + GPIO1C_IOMUX_SEL_H);
+ writel(0x000f0002, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_L);
+ writel(0x00f00020, GPIO1_IOC_BASE + GPIO1D_IOMUX_SEL_H);
+#endif
+
+#endif
+ return 0;
+}
+
+#ifdef CONFIG_SPL_BUILD
+int spl_fit_standalone_release(char *id, uintptr_t entry_point)
+{
+ u32 val;
+
+ /* open clk_pmu_mcu_jtag / clk_mcu_32k_en / fclk_mcu_en */
+ writel(0x05800000, PMU_CRU_BASE + PMU_CRU_GATE_CON00);
+ /* set the mcu to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST11_REG);
+ /* writel(0x00000000, FIREWALL_DDR_BASE + FW_DDR_MST_REG); */
+ /* set the mcu to secure */
+ writel(0x00200000, PMU_SGRF_BASE + PMU_SGRF_SOC_CON4);
+ /* open mcu_debug_en / mcu_dclk_en / mcu_hclk_en / mcu_sclk_en */
+ writel(0x000f000f, PMU_SGRF_BASE + PMU_SGRF_SOC_CON5);
+ /* set start addr, mcu_code_addr_start */
+ writel(0xffff0000 | (entry_point >> 16), PMU_SGRF_BASE + PMU_SGRF_SOC_CON6);
+ /* mcu_tcm_addr_start, multiplex pmu sram address */
+ writel(0xffffff10, PMU_SGRF_BASE + PMU_SGRF_SOC_CON11);
+ /* jtag_mcu_m0 gpio2a4/gpio2a5 iomux */
+ /* writel(0x00ff0022, GPIO2_IOC_BASE + 0x44); */
+ /* release the mcu */
+ writel(0x00800000, PMU_CRU_BASE + PMU_CRU_SOFTRST_CON00);
+
+ return 0;
+}
+#endif
+
diff --git a/u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c b/u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
new file mode 100644
index 0000000..d8d40ee
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3528/syscon_rk3528.c
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3528_syscon_ids[] = {
+ { .compatible = "rockchip,rk3528-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3528) = {
+ .name = "rk3528_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3528_syscon_ids,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/u-boot/arch/arm/mach-rockchip/rk3562/Kconfig b/u-boot/arch/arm/mach-rockchip/rk3562/Kconfig
new file mode 100644
index 0000000..9ee97e8
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3562/Kconfig
@@ -0,0 +1,17 @@
+if ROCKCHIP_RK3562
+
+config TARGET_EVB_RK3562
+ bool "EVB_RK3562"
+ select BOARD_LATE_INIT
+ help
+ RK3562 EVB is a evaluation board for Rockchp RK3562.
+
+config SYS_SOC
+ default "rockchip"
+
+config SYS_MALLOC_F_LEN
+ default 0x400
+
+source board/rockchip/evb_rk3562/Kconfig
+
+endif
diff --git a/u-boot/arch/arm/mach-rockchip/rk3562/Makefile b/u-boot/arch/arm/mach-rockchip/rk3562/Makefile
new file mode 100644
index 0000000..e643f8c
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3562/Makefile
@@ -0,0 +1,11 @@
+#
+# (C) Copyright 2022 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+ifneq ($(CONFIG_TPL_BUILD)$(CONFIG_TPL_TINY_FRAMEWORK),yy)
+obj-y += syscon_rk3562.o
+endif
+obj-y += rk3562.o
+obj-y += clk_rk3562.o
diff --git a/u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c b/u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c
new file mode 100644
index 0000000..ff059b7
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3562/clk_rk3562.c
@@ -0,0 +1,41 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3562.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3562_cru), devp);
+}
+
+#if CONFIG_IS_ENABLED(CLK_SCMI)
+int rockchip_get_scmi_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(scmi_clock), devp);
+}
+#endif
+
+void *rockchip_get_cru(void)
+{
+ struct rk3562_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
+
diff --git a/u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c b/u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c
new file mode 100644
index 0000000..e417dee
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3562/rk3562.c
@@ -0,0 +1,661 @@
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3562.h>
+#include <asm/arch/ioc_rk3562.h>
+#include <asm/arch/rk_atags.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/rk3562-cru.h>
+#include <asm/arch-rockchip/rockchip_smccc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define FIREWALL_DDR_BASE 0xfef00000
+#define FW_DDR_MST3_REG 0x2c /* usb */
+#define FW_DDR_MST4_REG 0x30 /* emmc */
+#define FW_DDR_MST5_REG 0x34 /* fspi */
+#define FW_DDR_MST6_REG 0x38 /* sdmmc mcu */
+#define FW_DDR_CON_REG 0x80
+
+#define PMU_GRF_BASE 0xff010000
+#define PMU_GRF_SOC_CON9 0x0124
+
+#define SYS_GRF_BASE 0xff030000
+#define SYS_GRF_SOC_CON5 0x0414
+#define SYS_GRF_SOC_CON6 0x0418
+
+#define PERI_GRF_BASE 0xff040000
+#define PERI_GRF_AUDIO_CON 0x0070
+
+#define PIPEPHY_GRF_BASE 0xff098000
+#define PIPEPHY_PIPE_CON5 0x0014
+
+#define TOP_CRU_BASE 0xff100000
+#define TOP_CRU_GATE_CON23 0x035c
+#define TOP_CRU_SOFTRST_CON23 0x045c
+#define TOP_CRU_CM0_GATEMASK 0x0680
+
+#define PMU0_CRU_BASE 0xff110000
+
+#define PMU1_CRU_BASE 0xff118000
+#define PMU1_CRU_GATE_CON02 0x0188
+#define PMU1_CRU_SOFTRST_CON02 0x0208
+#define PMU1_CRU_CM0_GATEMASK 0x0420
+
+#define PMU_BASE_ADDR 0xff258000
+#define PMU2_BIU_IDLE_SFTCON0 0x110
+#define PMU2_BIU_IDLE_ACK_STS0 0x120
+#define PMU2_BIT_IDLE_STS0 0x128
+#define PMU2_PWR_GATE_SFTCON0 0x210
+#define PMU2_PWR_GATE_STS0 0x230
+#define PMU2_MEM_SD_SFTCON0 0x300
+/* PMU2_PWR_GATE_SFTCON0 */
+#define PD_GPU_DWN_SFTENA BIT(0)
+#define PD_VI_DWN_SFTENA BIT(5)
+#define PD_VO_DWN_SFTENA BIT(6)
+/* PMU2_BIU_IDLE_SFTCON0 */
+#define IDLE_REQ_GPU_SFTENA BIT(1)
+#define IDLE_REQ_VI_SFTENA BIT(3)
+#define IDLE_REQ_VO_SFTENA BIT(4)
+/* PMU2_BIU_IDLE_ACK_STS0 */
+#define IDLE_ACK_GPU BIT(1)
+#define IDLE_ACK_VI BIT(3)
+#define IDLE_ACK_VO BIT(4)
+/* PMU2_BIT_IDLE_STS0 */
+#define IDLE_GPU BIT(1)
+#define IDLE_VI BIT(3)
+#define IDLE_VO BIT(4)
+
+#define CRYPTO_PRIORITY_REG 0xfeeb0108
+#define DCF_PRIORITY_REG 0xfee10408
+#define DMA2DDR_PRIORITY_REG 0xfee03808
+#define DMAC_PRIORITY_REG 0xfeeb0208
+#define EMMC_PRIORITY_REG 0xfeeb0308
+#define FSPI_PRIORITY_REG 0xfeeb0408
+#define GMAC_PRIORITY_REG 0xfee10208
+#define GPU_PRIORITY_REG 0xfee30008
+#define ISP_PRIORITY_REG 0xfee70008
+#define MAC100_PRIORITY_REG 0xfee10308
+#define MCU_PRIORITY_REG 0xfee10008
+#define PCIE_PRIORITY_REG 0xfeea0008
+#define RKDMA_PRIORITY_REG 0xfeeb0508
+#define SDMMC0_PRIORITY_REG 0xfeeb0608
+#define SDMMC1_PRIORITY_REG 0xfeeb0708
+#define USB2_PRIORITY_REG 0xfeeb0808
+#define USB3_PRIORITY_REG 0xfeea0108
+#define VICAP_PRIORITY_REG 0xfee70108
+#define VOP_PRIORITY_REG 0xfee80008
+
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
+
+#ifdef CONFIG_ARM64
+#include <asm/armv8/mmu.h>
+
+static struct mm_region rk3562_mem_map[] = {
+ {
+ .virt = 0x0UL,
+ .phys = 0x0UL,
+ .size = 0xfc000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xfc000000UL,
+ .phys = 0xfc000000UL,
+ .size = 0x04000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = rk3562_mem_map;
+#endif
+
+#define GPIO0_IOC_BASE 0xFF080000
+#define GPIO1_IOC_BASE 0xFF060000
+#define GPIO1A_IOMUX_SEL_L 0x0
+#define GPIO1A_IOMUX_SEL_H 0x4
+#define GPIO1B_IOMUX_SEL_L 0x8
+#define GPIO1_IOC_GPIO1A_DS0 0x200
+#define GPIO1_IOC_GPIO1A_DS1 0x204
+#define GPIO1_IOC_GPIO1B_DS0 0x210
+
+#define GPIO2_IOC_BASE 0xFF060000
+#define GPIO2_IOC_IO_VSEL0 0x300
+/* GPIO2_IOC_IO_VSEL0 */
+#define POC_VCCIO2_VD_3V3 BIT(12)
+
+#define GPIO3_IOC_BASE 0xFF070000
+#define GPIO4_IOC_BASE 0xFF070000
+
+/* UART0 iomux */
+/* gpio0d0_sel */
+#define UART0_RX_M0 1
+#define UART0_RX_M0_OFFSET 0
+#define UART0_RX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
+/* gpio0d1_sel */
+#define UART0_TX_M0 1
+#define UART0_TX_M0_OFFSET 4
+#define UART0_TX_M0_ADDR (GPIO0_IOC_BASE + 0x18)
+
+/* gpio1b3_sel */
+#define UART0_RX_M1 2
+#define UART0_RX_M1_OFFSET 12
+#define UART0_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
+/* gpio1b4_sel */
+#define UART0_TX_M1 2
+#define UART0_TX_M1_OFFSET 0
+#define UART0_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
+
+/* UART1 iomux */
+/* gpio1d1_sel */
+#define UART1_RX_M0 1
+#define UART1_RX_M0_OFFSET 4
+#define UART1_RX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
+/* gpio1d2_sel */
+#define UART1_TX_M0 1
+#define UART1_TX_M0_OFFSET 8
+#define UART1_TX_M0_ADDR (GPIO1_IOC_BASE + 0x18)
+
+/* gpio4a6_sel */
+#define UART1_RX_M1 4
+#define UART1_RX_M1_OFFSET 8
+#define UART1_RX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
+/* gpio4a5_sel */
+#define UART1_TX_M1 4
+#define UART1_TX_M1_OFFSET 4
+#define UART1_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
+
+/* UART2 iomux */
+/* gpio0c1_sel */
+#define UART2_RX_M0 1
+#define UART2_RX_M0_OFFSET 4
+#define UART2_RX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
+/* gpio0c0_sel */
+#define UART2_TX_M0 1
+#define UART2_TX_M0_OFFSET 0
+#define UART2_TX_M0_ADDR (GPIO0_IOC_BASE + 0x10)
+
+/* gpio3a1_sel */
+#define UART2_RX_M1 2
+#define UART2_RX_M1_OFFSET 4
+#define UART2_RX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
+/* gpio3a0_sel */
+#define UART2_TX_M1 2
+#define UART2_TX_M1_OFFSET 0
+#define UART2_TX_M1_ADDR (GPIO3_IOC_BASE + 0x40)
+
+/* UART3 iomux */
+/* gpio4b5_sel */
+#define UART3_RX_M0 7
+#define UART3_RX_M0_OFFSET 4
+#define UART3_RX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
+/* gpio4b4_sel */
+#define UART3_TX_M0 7
+#define UART3_TX_M0_OFFSET 0
+#define UART3_TX_M0_ADDR (GPIO4_IOC_BASE + 0x6C)
+
+/* gpio3c0_sel */
+#define UART3_RX_M1 3
+#define UART3_RX_M1_OFFSET 0
+#define UART3_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
+/* gpio3b7_sel */
+#define UART3_TX_M1 3
+#define UART3_TX_M1_OFFSET 12
+#define UART3_TX_M1_ADDR (GPIO3_IOC_BASE + 0x4C)
+
+/* UART4 iomux */
+/* gpio3d1_sel */
+#define UART4_RX_M0 4
+#define UART4_RX_M0_OFFSET 4
+#define UART4_RX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
+/* gpio3d0_sel */
+#define UART4_TX_M0 4
+#define UART4_TX_M0_OFFSET 0
+#define UART4_TX_M0_ADDR (GPIO3_IOC_BASE + 0x58)
+
+/* gpio1d5_sel */
+#define UART4_RX_M1 3
+#define UART4_RX_M1_OFFSET 4
+#define UART4_RX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
+/* gpio1d6_sel */
+#define UART4_TX_M1 3
+#define UART4_TX_M1_OFFSET 8
+#define UART4_TX_M1_ADDR (GPIO1_IOC_BASE + 0x1C)
+
+/* UART5 iomux */
+/* gpio1b7_sel */
+#define UART5_RX_M0 3
+#define UART5_RX_M0_OFFSET 12
+#define UART5_RX_M0_ADDR (GPIO1_IOC_BASE + 0xC)
+/* gpio1c0_sel */
+#define UART5_TX_M0 3
+#define UART5_TX_M0_OFFSET 0
+#define UART5_TX_M0_ADDR (GPIO1_IOC_BASE + 0x10)
+
+/* gpio3a7_sel */
+#define UART5_RX_M1 5
+#define UART5_RX_M1_OFFSET 12
+#define UART5_RX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
+/* gpio3a6_sel */
+#define UART5_TX_M1 5
+#define UART5_TX_M1_OFFSET 8
+#define UART5_TX_M1_ADDR (GPIO3_IOC_BASE + 0x44)
+
+/* UART6 iomux */
+/* gpio0c7_sel */
+#define UART6_RX_M0 1
+#define UART6_RX_M0_OFFSET 12
+#define UART6_RX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
+/* gpio0c6_sel */
+#define UART6_TX_M0 1
+#define UART6_TX_M0_OFFSET 8
+#define UART6_TX_M0_ADDR (GPIO0_IOC_BASE + 0x14)
+
+/* gpio4b0_sel */
+#define UART6_RX_M1 6
+#define UART6_RX_M1_OFFSET 0
+#define UART6_RX_M1_ADDR (GPIO4_IOC_BASE + 0x68)
+/* gpio4a7_sel */
+#define UART6_TX_M1 6
+#define UART6_TX_M1_OFFSET 12
+#define UART6_TX_M1_ADDR (GPIO4_IOC_BASE + 0x64)
+
+/* UART7 iomux */
+/* gpio3c7_sel */
+#define UART7_RX_M0 4
+#define UART7_RX_M0_OFFSET 12
+#define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
+/* gpio3c4_sel */
+#define UART7_TX_M0 4
+#define UART7_TX_M0_OFFSET 0
+#define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x54)
+
+/* gpio1b3_sel */
+#define UART7_RX_M1 3
+#define UART7_RX_M1_OFFSET 12
+#define UART7_RX_M1_ADDR (GPIO1_IOC_BASE + 0x08)
+/* gpio1b4_sel */
+#define UART7_TX_M1 3
+#define UART7_TX_M1_OFFSET 0
+#define UART7_TX_M1_ADDR (GPIO1_IOC_BASE + 0x0C)
+
+/* UART8 iomux */
+/* gpio3b3_sel */
+#define UART8_RX_M0 3
+#define UART8_RX_M0_OFFSET 12
+#define UART8_RX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
+/* gpio3b2_sel */
+#define UART8_TX_M0 3
+#define UART8_TX_M0_OFFSET 8
+#define UART8_TX_M0_ADDR (GPIO3_IOC_BASE + 0x48)
+
+/* gpio3d5_sel */
+#define UART8_RX_M1 4
+#define UART8_RX_M1_OFFSET 4
+#define UART8_RX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
+/* gpio3d4_sel */
+#define UART8_TX_M1 4
+#define UART8_TX_M1_OFFSET 0
+#define UART8_TX_M1_ADDR (GPIO3_IOC_BASE + 0x5C)
+
+/* UART9 iomux */
+/* gpio4b3_sel */
+#define UART9_RX_M0 4
+#define UART9_RX_M0_OFFSET 12
+#define UART9_RX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
+/* gpio4b2_sel */
+#define UART9_TX_M0 4
+#define UART9_TX_M0_OFFSET 8
+#define UART9_TX_M0_ADDR (GPIO4_IOC_BASE + 0x68)
+
+/* gpio3c3_sel */
+#define UART9_RX_M1 3
+#define UART9_RX_M1_OFFSET 12
+#define UART9_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
+/* gpio3c2_sel */
+#define UART9_TX_M1 3
+#define UART9_TX_M1_OFFSET 8
+#define UART9_TX_M1_ADDR (GPIO3_IOC_BASE + 0x50)
+
+#define set_uart_iomux(bits_offset, bits_val, addr) \
+ writel(GENMASK(bits_offset + 19, bits_offset + 16) | (bits_val << bits_offset) , addr)
+
+#define set_uart_iomux_rx(ID, MODE) \
+ set_uart_iomux(UART##ID##_RX_M##MODE##_OFFSET, UART##ID##_RX_M##MODE, UART##ID##_RX_M##MODE##_ADDR);
+#define set_uart_iomux_tx(ID, MODE) \
+ set_uart_iomux(UART##ID##_TX_M##MODE##_OFFSET, UART##ID##_TX_M##MODE, UART##ID##_TX_M##MODE##_ADDR);
+
+void board_debug_uart_init(void)
+{
+/* UART 0 */
+#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff210000)
+
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART0_M0 Switch iomux */
+ set_uart_iomux_rx(0, 0);
+ set_uart_iomux_tx(0, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART0_M1 Switch iomux */
+ set_uart_iomux_rx(0, 1);
+ set_uart_iomux_tx(0, 1);
+#endif
+/* UART 1 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff670000)
+
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART1_M0 Switch iomux */
+ set_uart_iomux_rx(1, 0);
+ set_uart_iomux_tx(1, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART1_M1 Switch iomux */
+ set_uart_iomux_rx(1, 1);
+ set_uart_iomux_tx(1, 1);
+#endif
+/* UART 2 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff680000)
+
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART2_M0 Switch iomux */
+ set_uart_iomux_rx(2, 0);
+ set_uart_iomux_tx(2, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART2_M1 Switch iomux */
+ set_uart_iomux_rx(2, 1);
+ set_uart_iomux_tx(2, 1);
+#endif
+/* UART 3 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff690000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART3_M0 Switch iomux */
+ set_uart_iomux_rx(3, 0);
+ set_uart_iomux_tx(3, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART3_M1 Switch iomux */
+ set_uart_iomux_rx(3, 1);
+ set_uart_iomux_tx(3, 1);
+#endif
+/* UART 4 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6a0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART4_M0 Switch iomux */
+ set_uart_iomux_rx(4, 0);
+ set_uart_iomux_tx(4, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART4_M1 Switch iomux */
+ set_uart_iomux_rx(4, 1);
+ set_uart_iomux_tx(4, 1);
+#endif
+/* UART 5 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6b0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART5_M0 Switch iomux */
+ set_uart_iomux_rx(5, 0);
+ set_uart_iomux_tx(5, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART5_M1 Switch iomux */
+ set_uart_iomux_rx(5, 1);
+ set_uart_iomux_tx(5, 1);
+#endif
+/* UART 6 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6c0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART6_M0 Switch iomux */
+ set_uart_iomux_rx(6, 0);
+ set_uart_iomux_tx(6, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART6_M1 Switch iomux */
+ set_uart_iomux_rx(6, 1);
+ set_uart_iomux_tx(6, 1);
+#endif
+/* UART 7 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6d0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART7_M0 Switch iomux */
+ set_uart_iomux_rx(7, 0);
+ set_uart_iomux_tx(7, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART7_M1 Switch iomux */
+ set_uart_iomux_rx(7, 1);
+ set_uart_iomux_tx(7, 1);
+#endif
+/* UART 8 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6e0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART8_M0 Switch iomux */
+ set_uart_iomux_rx(8, 0);
+ set_uart_iomux_tx(8, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART8_M1 Switch iomux */
+ set_uart_iomux_rx(8, 1);
+ set_uart_iomux_tx(8, 1);
+#endif
+/* UART 9 */
+#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff6f0000)
+#if defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 0)
+
+ /* UART9_M0 Switch iomux */
+ set_uart_iomux_rx(9, 0);
+ set_uart_iomux_tx(9, 0);
+#elif defined(CONFIG_ROCKCHIP_UART_MUX_SEL_M) && \
+ (CONFIG_ROCKCHIP_UART_MUX_SEL_M == 1)
+
+ /* UART9_M1 Switch iomux */
+ set_uart_iomux_rx(9, 1);
+ set_uart_iomux_tx(9, 1);
+#endif
+#endif
+}
+
+int fit_standalone_release(char *id, uintptr_t entry_point)
+{
+ /* bus m0 configuration: */
+ /* open hclk_dcache / hclk_icache / clk_bus m0 rtc / fclk_bus_m0_core */
+ writel(0x03180000, TOP_CRU_BASE + TOP_CRU_GATE_CON23);
+
+ /* open bus m0 sclk / bus m0 hclk / bus m0 dclk */
+ writel(0x00070000, TOP_CRU_BASE + TOP_CRU_CM0_GATEMASK);
+
+ /* mcu_cache_peripheral_addr */
+ writel(0xa0000000, SYS_GRF_BASE + SYS_GRF_SOC_CON5);
+ writel(0xffb40000, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
+
+ sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
+ ROCKCHIP_SIP_CONFIG_MCU_CODE_START_ADDR,
+ 0xffff0000 | (entry_point >> 16));
+ sip_smc_mcu_config(ROCKCHIP_SIP_CONFIG_BUSMCU_0_ID,
+ ROCKCHIP_SIP_CONFIG_MCU_EXPERI_START_ADDR, 0xffffa000);
+
+ /* release dcache / icache / bus m0 jtag / bus m0 */
+ writel(0x03280000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON23);
+
+ /* release pmu m0 jtag / pmu m0 */
+ /* writel(0x00050000, PMU1_CRU_BASE + PMU1_CRU_SOFTRST_CON02); */
+
+ return 0;
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+static void qos_priority_init(void)
+{
+ u32 delay;
+ u32 i;
+
+ /* power up vo,vi,gpu */
+ rk_clrreg(PMU_BASE_ADDR + PMU2_PWR_GATE_SFTCON0,
+ PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA);
+ delay = 1000;
+ do {
+ udelay(1);
+ delay--;
+ if (delay == 0) {
+ printf("Fail to set domain. PMU2_PWR_GATE_STS0=0x%x\n",
+ readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0));
+ hang();
+ }
+ } while (readl(PMU_BASE_ADDR + PMU2_PWR_GATE_STS0) &
+ (PD_VO_DWN_SFTENA | PD_VI_DWN_SFTENA));
+ /* power up vop memory */
+ for (i = 0; i < 16; i++)
+ rk_clrreg(PMU_BASE_ADDR + PMU2_MEM_SD_SFTCON0, BIT(i));
+
+ /* release vo,vi,gpu idle request */
+ rk_clrreg(PMU_BASE_ADDR + PMU2_BIU_IDLE_SFTCON0,
+ (IDLE_REQ_VO_SFTENA | IDLE_REQ_VI_SFTENA));
+
+ delay = 1000;
+ /* wait ack status */
+ do {
+ udelay(1);
+ delay--;
+ if (delay == 0) {
+ printf("Fail to get ack on domain. PMU2_BIU_IDLE_ACK_STS0=0x%x\n",
+ readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0));
+ hang();
+ }
+ } while (readl(PMU_BASE_ADDR + PMU2_BIU_IDLE_ACK_STS0) &
+ (IDLE_ACK_VO | IDLE_ACK_VI));
+
+ delay = 1000;
+ /* wait idle status */
+ do {
+ udelay(1);
+ delay--;
+ if (delay == 0) {
+ printf("Fail to set idle on domain. PMU2_BIT_IDLE_STS0=0x%x\n",
+ readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0));
+ hang();
+ }
+ } while (readl(PMU_BASE_ADDR + PMU2_BIT_IDLE_STS0) &
+ (IDLE_VO | IDLE_VI));
+
+ /*
+ * modify default qos priority setting, then
+ * Peri > VOP/ISP/VICAP > CPU > GPU/NPU/RKVDEC/RGA/Other
+ * (5) (4) (3) (2)
+ *
+ * NOTE: GPU qos init is in kernel, in case that vdd gpu is off now.
+ */
+ writel(QOS_PRIORITY_LEVEL(5, 5), CRYPTO_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), DMAC_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), EMMC_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), FSPI_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), GMAC_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), MAC100_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), MCU_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), RKDMA_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC0_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), SDMMC1_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), USB2_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(5, 5), USB3_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(4, 4), ISP_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(4, 4), VICAP_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(4, 4), VOP_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(2, 2), DCF_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(2, 2), DMA2DDR_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(2, 2), PCIE_PRIORITY_REG);
+}
+
+int arch_cpu_init(void)
+{
+ u32 val;
+
+ /* Set the emmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG);
+
+ /* Set the sdmmc to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+ writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG);
+
+ /*
+ * Set SAIx_MCLK as input default
+ *
+ * It's safe to set mclk as input default to avoid high freq glitch
+ * which may make devices work unexpected. And then enabled by
+ * kernel stage or any state where user use it.
+ */
+ writel(0x0a100000, PERI_GRF_BASE + PERI_GRF_AUDIO_CON);
+
+ /* Assert reset the pipe phy to save power and de-assert when in use */
+ writel(0x00030001, PIPEPHY_GRF_BASE + PIPEPHY_PIPE_CON5);
+
+#if defined(CONFIG_ROCKCHIP_SFC)
+ /* Set the fspi to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+ writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG);
+
+ /*
+ * Fix fspi io ds level:
+ *
+ * level 2 for 1V8
+ * level 3 for 3V3
+ */
+ if (readl(GPIO1_IOC_BASE + GPIO1A_IOMUX_SEL_L) == 0x2222) {
+ if (readl(GPIO2_IOC_BASE + GPIO2_IOC_IO_VSEL0) & POC_VCCIO2_VD_3V3) {
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
+ writel(0x3f3f0f0f, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
+ } else {
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS0);
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1A_DS1);
+ writel(0x3f3f0707, GPIO1_IOC_BASE + GPIO1_IOC_GPIO1B_DS0);
+ }
+ }
+#endif
+
+ qos_priority_init();
+
+ return 0;
+}
+#endif
diff --git a/u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c b/u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c
new file mode 100644
index 0000000..811c4e3
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/rk3562/syscon_rk3562.c
@@ -0,0 +1,26 @@
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3562_syscon_ids[] = {
+ { .compatible = "rockchip,rk3562-sys-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3562-pmu-grf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { .compatible = "rockchip,rk3562-ioc-grf", .data = ROCKCHIP_SYSCON_IOC },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3562) = {
+ .name = "rk3562_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3562_syscon_ids,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+};
diff --git a/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c b/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
index debd642..ef6df66 100644
--- a/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
+++ b/u-boot/arch/arm/mach-rockchip/rk3568/rk3568.c
@@ -777,6 +777,23 @@
#endif
}
+int fit_standalone_release(char *id, uintptr_t entry_point)
+{
+ /* risc-v configuration: */
+ /* Reset the scr1 */
+ writel(0x04000400, CRU_BASE + CRU_SOFTRST_CON26);
+ udelay(100);
+
+ /* set the scr1 addr */
+ writel((0xffff0000) | (entry_point >> 16), GRF_BASE + GRF_SOC_CON4);
+ udelay(10);
+
+ /* release the scr1 */
+ writel(0x04000000, CRU_BASE + CRU_SOFTRST_CON26);
+
+ return 0;
+}
+
#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
static void qos_priority_init(void)
{
diff --git a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
index 7323d96..678d558 100644
--- a/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/u-boot/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -19,20 +19,31 @@
#define FIREWALL_DDR_BASE 0xfe030000
#define FW_DDR_MST5_REG 0x54
#define FW_DDR_MST13_REG 0x74
+#define FW_DDR_MST19_REG 0x8c
#define FW_DDR_MST21_REG 0x94
#define FW_DDR_MST26_REG 0xa8
#define FW_DDR_MST27_REG 0xac
#define FIREWALL_SYSMEM_BASE 0xfe038000
#define FW_SYSM_MST5_REG 0x54
#define FW_SYSM_MST13_REG 0x74
+#define FW_SYSM_MST19_REG 0x8c
#define FW_SYSM_MST21_REG 0x94
#define FW_SYSM_MST26_REG 0xa8
#define FW_SYSM_MST27_REG 0xac
+#define PMU1_SGRF_BASE 0xfd582000
+#define PMU1_SGRF_SOC_CON0 0x0
+#define PMU1_SGRF_SOC_CON6 0x18
+#define PMU1_SGRF_SOC_CON7 0x1c
+#define PMU1_SGRF_SOC_CON8 0x20
+#define PMU1_SGRF_SOC_CON9 0x24
+#define PMU1_SGRF_SOC_CON10 0x28
+#define PMU1_SGRF_SOC_CON13 0x34
#define SYS_GRF_BASE 0xfd58c000
#define SYS_GRF_SOC_CON6 0x0318
#define USBGRF_BASE 0xfd5ac000
#define USB_GRF_USB3OTG0_CON1 0x001c
#define BUS_SGRF_BASE 0xfd586000
+#define BUS_SGRF_SOC_CON2 0x08
#define BUS_SGRF_FIREWALL_CON18 0x288
#define PMU_BASE 0xfd8d0000
#define PMU_PWR_GATE_SFTCON1 0x8150
@@ -66,14 +77,21 @@
#define EMMC_IOC_GPIO2D_DS_H 0x5c
#define CRU_BASE 0xfd7c0000
+#define CRU_GPLL_CON1 0x01c4
#define CRU_SOFTRST_CON77 0x0b34
+#define CRU_GLB_RST_CON 0x0c10
#define PMU1CRU_BASE 0xfd7f0000
+#define PMU1CRU_SOFTRST_CON00 0x0a00
#define PMU1CRU_SOFTRST_CON03 0x0a0c
#define PMU1CRU_SOFTRST_CON04 0x0a10
#define HDMIRX_NODE_FDT_PATH "/hdmirx-controller@fdee0000"
#define RK3588_PHY_CONFIG 0xfdee00c0
+
+#define VOP_M0_PRIORITY_REG 0xfdf82008
+#define VOP_M1_PRIORITY_REG 0xfdf82208
+#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 7) << 8) | ((l) & 7))
#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>
@@ -865,8 +883,15 @@
secure_reg &= 0xffff0000;
writel(secure_reg, FIREWALL_SYSMEM_BASE + FW_SYSM_MST27_REG);
- /* Select clk_tx source as default for i2s2/i2s3 */
- writel(0x03400340, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
+ /*
+ * Select clk_tx source as default for i2s2/i2s3
+ * Set I2Sx_MCLK as input default
+ *
+ * It's safe to set mclk as input default to avoid high freq glitch
+ * which may make devices work unexpected. And then enabled by
+ * kernel stage or any state where user use it.
+ */
+ writel(0x03c703c7, SYS_GRF_BASE + SYS_GRF_SOC_CON6);
if (readl(BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L) == 0x2222) {
/* Set the fspi m0 io ds level to 55ohm */
@@ -922,7 +947,14 @@
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_L);
writel(0xffff1111, BUS_IOC_BASE + BUS_IOC_GPIO2D_IOMUX_SEL_H);
#endif
-
+ /*
+ * set VOP M0 and VOP M1 to priority 0x303,then
+ * Peri > VOP/MCU > ISP/VICAP > other
+ * Note: VOP priority can only be modified during the u-boot stage,
+ * as VOP default power down, and power up after trust.
+ */
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M0_PRIORITY_REG);
+ writel(QOS_PRIORITY_LEVEL(3, 3), VOP_M1_PRIORITY_REG);
#endif
/* Select usb otg0 phy status to 0 that make rockusb can work at high-speed */
@@ -1245,31 +1277,36 @@
#ifdef CONFIG_SPL_BUILD
int spl_fit_standalone_release(char *id, uintptr_t entry_point)
{
- /* gpll enable */
- writel(0x00f00042, 0xfd7c01c4);
+ u32 val;
+
+ /* pmu m0 configuration: */
+ /* set gpll */
+ writel(0x00f00042, CRU_BASE + CRU_GPLL_CON1);
+ /* set pmu mcu to access ddr memory */
+ val = readl(FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
+ writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST19_REG);
+ /* set pmu mcu to access system memory */
+ val = readl(FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
+ writel(val & 0x000000ff, FIREWALL_SYSMEM_BASE + FW_SYSM_MST19_REG);
+ /* set pmu mcu to secure */
+ writel(0x00080000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON0);
/* set start addr, pmu_mcu_code_addr_start */
- writel(0xFFFF0000 | (entry_point >> 16), 0xFD582024);
- /* pmu_mcu_sram_addr_start */
- writel(0xFFFF2000, 0xFD582028);
- /* pmu_mcu_tcm_addr_start */
- writel(0xFFFF2000, 0xFD582034);
- /* set mcu secure */
- writel(0x00080000, 0xFD582000);
+ writel(0xFFFF0000 | (entry_point >> 16), PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON9);
+ /* set pmu_mcu_sram_addr_start */
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON10);
+ /* set pmu_mcu_tcm_addr_start */
+ writel(0xFFFF2000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON13);
/* set cache cache_peripheral_addr */
- writel(0xffff0000, 0xFD582018);
- writel(0xffffee00, 0xFD58201c);
- writel(0x00ff00ff, 0xFD582020); /* 0xf0000000 ~ 0xfee00000 */
- /* mcupmu access DDR secure control, each bit for a region. */
- writel(0x0000ffff, 0xFE03008C);
- /* mcupmu access DDR secure control, each bit for a region. */
- writel(0x000000ff, 0xFE03808C);
- /* PMU WDT reset system enable */
- writel(0x02000200, 0xFD586008);
- /* WDT trigger global reset. */
- writel(0x08400840, 0xFD7C0C10);
- /* Spl helps to load the mcu image, but not need to release
- * mcu for rk3588.
- */
+ /* 0xf0000000 ~ 0xfee00000 */
+ writel(0xffff0000, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON6);
+ writel(0xffffee00, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON7);
+ writel(0x00ff00ff, PMU1_SGRF_BASE + PMU1_SGRF_SOC_CON8);
+ /* enable PMU WDT reset system */
+ writel(0x02000200, BUS_SGRF_BASE + BUS_SGRF_SOC_CON2);
+ /* select WDT trigger global reset. */
+ writel(0x08400840, CRU_BASE + CRU_GLB_RST_CON);
+ /* release pmu mcu */
+ /* writel(0x20000000, PMU1CRU_BASE + PMU1CRU_SOFTRST_CON00); */
return 0;
}
diff --git a/u-boot/arch/arm/mach-rockchip/rk_meta.c b/u-boot/arch/arm/mach-rockchip/rk_meta.c
index e35391f..8c0cce9 100644
--- a/u-boot/arch/arm/mach-rockchip/rk_meta.c
+++ b/u-boot/arch/arm/mach-rockchip/rk_meta.c
@@ -50,6 +50,7 @@
ulong sector;
char *data;
u64 len;
+ int meta_iq_item_size = 0;
if (part_get_info_by_name(info->dev, part_name, &part_info) <= 0) {
debug("%s: no partition\n", __func__);
@@ -91,32 +92,31 @@
/* load compress data */
data = (char *)COMPRESS_LOAD_ADDR;
+ meta_iq_item_size = meta_p->iq_item_size + meta.comp_size;
if (meta_p->comp_type == META_COMPRESS_TYPE_GZ) {
if (info->read(info, sector + (MAX_META_SEGMENT_SIZE / info->bl_len),
- DIV_ROUND_UP(meta.comp_size, info->bl_len), data)
- != DIV_ROUND_UP(meta.comp_size, info->bl_len)) {
- debug("%s: Failed to read compress data.\n", __func__);
+ DIV_ROUND_UP(meta_iq_item_size, info->bl_len), data)
+ != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) {
+ printf("%s: Failed to read compress data.\n", __func__);
return -EIO;
}
+
+ memcpy((void *)(meta_p->load + SENSOR_IQ_BIN_OFFSET), data, meta_p->iq_item_size);
if (rk_meta_iq_decom((meta_p->load + meta_p->comp_off),
(unsigned long)(data + meta_p->comp_off -
MAX_META_SEGMENT_SIZE),
meta.comp_size, &len)) {
- debug("%s: Failed to decompress.\n", __func__);
+ printf("%s: Failed to decompress.\n", __func__);
return -EIO;
}
- /* update decompress gz's file size */
- unsigned int *p_len = (unsigned int *)
- (meta_p->load + MAX_META_SEGMENT_SIZE + MAX_HEAD_SIZE);
- *p_len = (u32)len;
- /* TODO: update decompress gz's file crc32 */
+
} else {
if (info->read(info, sector + (MAX_META_SEGMENT_SIZE / info->bl_len),
- DIV_ROUND_UP(meta.comp_size, info->bl_len),
+ DIV_ROUND_UP(meta_iq_item_size, info->bl_len),
(void *)(meta_p->load + MAX_META_SEGMENT_SIZE))
- != DIV_ROUND_UP(meta.comp_size, info->bl_len)) {
- debug("%s: Failed to read\n", __func__);
+ != DIV_ROUND_UP(meta_iq_item_size, info->bl_len)) {
+ printf("%s: Failed to read\n", __func__);
return -EIO;
}
}
@@ -125,6 +125,7 @@
flush_cache(meta_p->load, meta_p->size);
rk_meta_process();
+ printf("\nMeta: ok\n");
return 0;
}
diff --git a/u-boot/arch/arm/mach-rockchip/rockchip_smccc.c b/u-boot/arch/arm/mach-rockchip/rockchip_smccc.c
index 0cff596..cd02914 100644
--- a/u-boot/arch/arm/mach-rockchip/rockchip_smccc.c
+++ b/u-boot/arch/arm/mach-rockchip/rockchip_smccc.c
@@ -61,6 +61,15 @@
return res.a0;
}
+int sip_smc_remotectl_config(unsigned long func, unsigned long data)
+{
+ struct arm_smccc_res res;
+
+ res = __invoke_sip_fn_smc(SIP_REMOTECTL_CFG, func, data, 0);
+
+ return res.a0;
+}
+
int sip_smc_amp_cfg(unsigned long func, unsigned long arg0, unsigned long arg1,
unsigned long arg2)
{
@@ -142,3 +151,11 @@
return 0;
}
+
+int sip_smc_mcu_config(unsigned long mcu_id, unsigned long func, unsigned long arg2)
+{
+ struct arm_smccc_res res;
+
+ res = __invoke_sip_fn_smc(SIP_MCU_CFG, mcu_id, func, arg2);
+ return res.a0;
+}
diff --git a/u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c b/u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c
index 76d3d51..cbbd106 100644
--- a/u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c
+++ b/u-boot/arch/arm/mach-rockchip/rv1106/rv1106.c
@@ -7,6 +7,9 @@
#include <boot_rkimg.h>
#include <cli.h>
#include <debug_uart.h>
+#include <miiphy.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/grf_rv1106.h>
@@ -538,15 +541,65 @@
}
#endif
-int rk_board_late_init(void)
-{
-#if defined(CONFIG_CMD_SCRIPT_UPDATE)
- struct blk_desc *desc;
+#if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
+#define GMAC_NODE_FDT_PATH "/ethernet@ffa80000"
+#define RK630_MII_NAME "ethernet@ffa80000"
+#define PHY_ADDR 2
+#define PAGE_SWITCH 0x1f
+#define DISABLE_APS_REG 0x12
+#define DISABLE_APS_VAL 0x4824
+#define PHYAFE_PDCW_REG 0x1c
+#define PHYAFE_PDCW_VAL 0x8880
+#define PD_ANALOG_REG 0x0
+#define PD_ANALOG_VAL 0x3900
+#define RV1106_MACPHY_SHUTDOWN BIT(1)
+#define RV1106_MACPHY_ENABLE_MASK BIT(1)
- desc = rockchip_get_bootdev();
- if (desc && desc->if_type == IF_TYPE_MMC && desc->devnum == 1)
- run_command("sd_update", 0);
-#endif
+static int rk_board_fdt_pwrdn_gmac(const void *blob)
+{
+ void *fdt = (void *)gd->fdt_blob;
+ struct rv1106_grf *grf;
+ int gmac_node;
+
+ /* Turn off GMAC FEPHY to reduce chip power consumption at uboot level,
+ * if the gmac node is disabled at kernel dtb. RV1106/1103 has the
+ * internal gmac phy, u-boot.dtb defines and enables the gmac node
+ * by default, so even if the gmac node of the kernel dts is disabled,
+ * U-Boot will enable and initialize the gmac phy. So it is not okay
+ * to turn off gmac phy by default in arch_cpu_init(), need to turn off
+ * gmac phy in the current function.
+ */
+ gmac_node = fdt_path_offset(gd->fdt_blob, GMAC_NODE_FDT_PATH);
+ if (fdt_stringlist_search(fdt, gmac_node, "status", "disabled") >= 0) {
+ /* switch to page 1 */
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0100);
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, DISABLE_APS_REG,
+ DISABLE_APS_VAL);
+ /* switch to pae 6 */
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0600);
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PHYAFE_PDCW_REG,
+ PHYAFE_PDCW_VAL);
+ /* switch to page 0 */
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PAGE_SWITCH, 0x0000);
+ miiphy_write(RK630_MII_NAME, PHY_ADDR, PD_ANALOG_REG,
+ PD_ANALOG_VAL);
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (grf)
+ rk_clrsetreg(&grf->macphy_con0,
+ RV1106_MACPHY_ENABLE_MASK,
+ RV1106_MACPHY_SHUTDOWN);
+ }
+
return 0;
}
+#endif
+int rk_board_fdt_fixup(const void *blob)
+{
+#if (defined CONFIG_MII || defined CONFIG_CMD_MII || defined CONFIG_PHYLIB)
+ rk_board_fdt_pwrdn_gmac(blob);
+#endif
+
+ return 0;
+}
diff --git a/u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c b/u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c
index 311310d..2f712e2 100644
--- a/u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c
+++ b/u-boot/arch/arm/mach-rockchip/rv1126/rv1126.c
@@ -63,6 +63,9 @@
#define PMU_PWR_DWN_ST (0x108)
#define PMU_PWR_GATE_SFTCON (0x110)
+#define PMU_BUS_IDLE_NPU BIT(18)
+#define PMU_BUS_IDLE_VEPU BIT(9)
+
#define CRU_BASE 0xFF490000
#define CRU_CLKSEL_CON02 0x108
#define CRU_CLKSEL_CON03 0x10c
@@ -548,6 +551,7 @@
* CONFIG_DM_RAMDISK: for ramboot that without SPL.
*/
#if defined(CONFIG_SPL_BUILD) || defined(CONFIG_DM_RAMDISK)
+ u32 pd_st, idle_st;
int delay;
/*
@@ -624,11 +628,7 @@
do {
udelay(1);
delay--;
- if (delay == 0) {
- printf("Fail to set domain.");
- hang();
- }
- } while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
+ } while (delay && readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST));
/* release all idle request */
writel(0xffff0000, PMU_BASE_ADDR + PMU_BUS_IDLE_SFTCON(0));
@@ -639,22 +639,30 @@
do {
udelay(1);
delay--;
- if (delay == 0) {
- printf("Fail to get ack on domain.\n");
- hang();
- }
- } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
+ } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ACK));
delay = 1000;
/* wait idle status */
do {
udelay(1);
delay--;
- if (delay == 0) {
- printf("Fail to set idle on domain.\n");
- hang();
- }
- } while (readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
+ } while (delay && readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST));
+
+ pd_st = readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST);
+ idle_st = readl(PMU_BASE_ADDR + PMU_BUS_IDLE_ST);
+
+ if (pd_st || idle_st) {
+ printf("PMU_PWR_DOWN_ST: 0x%08x\n", pd_st);
+ printf("PMU_BUS_IDLE_ST: 0x%08x\n", idle_st);
+
+ if (idle_st & PMU_BUS_IDLE_NPU)
+ printf("Failed to enable PD_NPU, please check VDD_NPU is supplied\n");
+
+ if (idle_st & PMU_BUS_IDLE_VEPU)
+ printf("Failed to enable PD_VEPU, please check VDD_VEPU is supplied\n");
+
+ hang();
+ }
writel(0x303, USB_HOST_PRIORITY_REG);
writel(0x303, USB_OTG_PRIORITY_REG);
diff --git a/u-boot/arch/arm/mach-rockchip/spl.c b/u-boot/arch/arm/mach-rockchip/spl.c
index 6ee6933..0bf425c 100644
--- a/u-boot/arch/arm/mach-rockchip/spl.c
+++ b/u-boot/arch/arm/mach-rockchip/spl.c
@@ -19,6 +19,7 @@
#ifdef CONFIG_ROCKCHIP_PRELOADER_ATAGS
#include <asm/arch/rk_atags.h>
#endif
+#include <asm/arch/pcie_ep_boot.h>
#include <asm/arch/sdram.h>
#include <asm/arch/boot_mode.h>
#include <asm/arch-rockchip/sys_proto.h>
@@ -175,6 +176,9 @@
printascii("U-Boot SPL board init");
#endif
gd->sys_start_tick = get_ticks();
+#ifdef CONFIG_SPL_PCIE_EP_SUPPORT
+ rockchip_pcie_ep_init();
+#endif
#ifdef CONFIG_SPL_FRAMEWORK
ret = spl_early_init();
if (ret) {
@@ -197,6 +201,9 @@
arch_cpu_init();
rk_board_init_f();
+#ifdef CONFIG_SPL_RAM_DEVICE
+ rockchip_pcie_ep_get_firmware();
+#endif
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
back_to_bootrom(BROM_BOOT_NEXTSTAGE);
#endif
@@ -368,7 +375,10 @@
spl->next_stage = SPL_NEXT_STAGE_KERNEL;
break;
default:
- spl->next_stage = SPL_NEXT_STAGE_UBOOT;
+ if ((reg_boot_mode & REBOOT_FLAG) != REBOOT_FLAG)
+ spl->next_stage = SPL_NEXT_STAGE_KERNEL;
+ else
+ spl->next_stage = SPL_NEXT_STAGE_UBOOT;
}
}
#endif
diff --git a/u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c b/u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c
new file mode 100644
index 0000000..9d3a6a1
--- /dev/null
+++ b/u-boot/arch/arm/mach-rockchip/spl_pcie_ep_boot.c
@@ -0,0 +1,689 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <spl.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/ioc_rk3588.h>
+#include <dt-bindings/clock/rk3588-cru.h>
+#include <pci.h>
+#include <asm/arch/rk_atags.h>
+
+#ifndef CONFIG_SPL_LOAD_FIT_ADDRESS
+#error "SPL_LOAD_FIT_ADDRESS not defined!"
+#endif
+
+#define printep(fmt, ...) \
+ do { \
+ printf("RKEP: %d - ", readl(CONFIG_ROCKCHIP_STIMER_BASE + 0x2c) / 24); \
+ printf(fmt, ##__VA_ARGS__); \
+ } while (0)
+
+#ifdef CONFIG_ROCKCHIP_RK3588
+#define PCIE_SNPS_DBI_BASE 0xf5000000
+#define PCIE_SNPS_APB_BASE 0xfe150000
+#define PCIE_SNPS_IATU_BASE 0xa40300000
+
+#define PCI_RESBAR 0x2e8
+#elif CONFIG_ROCKCHIP_RK3568
+#define PCIE_SNPS_DBI_BASE 0xf6000000
+#define PCIE_SNPS_APB_BASE 0xfe280000
+#define PCIE_SNPS_IATU_BASE 0x3c0b00000
+
+#define PCI_RESBAR 0x2b8
+#else
+#error "this soc is not support pcie ep!"
+#endif
+
+#define RKEP_BAR0_ADDR 0x3c000000
+#define RKEP_BAR2_ADDR CONFIG_SPL_LOAD_FIT_ADDRESS
+#define RKEP_BAR0_CMD_ADDR (RKEP_BAR0_ADDR + 0x400)
+#define RKEP_BOOT_MAGIC 0x524b4550 /* RKEP */
+#define RKEP_CMD_LOADER_RUN 0x524b4501
+
+#define PCI_EXP_LNKCAP 12 /* Link Capabilities */
+#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
+#define PCI_EXP_LNKCTL2_TLS 0x000f
+#define PCI_EXP_LNKCAP_SLS 0x0000000f
+
+#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
+#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
+#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
+
+/* Synopsys-specific PCIe configuration registers */
+#define PCIE_PORT_LINK_CONTROL 0x710
+#define PORT_LINK_MODE_MASK (0x3f << 16)
+#define PORT_LINK_MODE_1_LANES (0x1 << 16)
+#define PORT_LINK_MODE_2_LANES (0x3 << 16)
+#define PORT_LINK_MODE_4_LANES (0x7 << 16)
+#define PORT_LINK_MODE_8_LANES (0xf << 16)
+
+#define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
+#define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
+#define PORT_LOGIC_LINK_WIDTH_MASK (0x1f << 8)
+#define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
+#define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
+#define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
+#define PORT_LOGIC_LINK_WIDTH_8_LANES (0x8 << 8)
+
+#define PCIE_DIRECT_SPEED_CHANGE (0x1 << 17)
+
+#define LINK_WAIT_IATU 10000
+#define PCIE_ATU_ENABLE (0x1 << 31)
+#define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30 | 1 << 19)
+#define PCIE_ATU_UNR_REGION_CTRL1 0x00
+#define PCIE_ATU_UNR_REGION_CTRL2 0x04
+#define PCIE_ATU_CPU_ADDR_LOW 0x14
+#define PCIE_ATU_CPU_ADDR_HIGH 0x18
+
+/* SRNS: Use Separate refclk(internal clock) instead of from RC */
+// #define PCIE_ENABLE_SRNS_PLL_REFCLK
+
+struct rkpcie_cmd {
+ u32 cmd;
+ u32 size;
+ u32 data[6];
+};
+
+/* rkep device mode status definition */
+#define RKEP_MODE_BOOTROM 1
+#define RKEP_MODE_LOADER 2
+#define RKEP_MODE_KERNEL 3
+
+/* Common status */
+#define RKEP_SMODE_INIT 0
+#define RKEP_SMODE_LNKRDY 1
+#define RKEP_SMODE_LNKUP 2
+#define RKEP_SMODE_ERR 0xff
+/* Firmware download status */
+#define RKEP_SMODE_FWDLRDY 0x10
+#define RKEP_SMODE_FWDLDONE 0x11
+/* Application status*/
+#define RKEP_SMODE_APPRDY 0x20
+
+struct rkpcie_boot {
+ /* magic: "RKEP" */
+ u32 magic;
+ u32 version;
+ struct {
+ u16 mode;
+ u16 submode;
+ } devmode;
+ /* Size of ATAGS for cap */
+ u32 cap_size;
+ struct {
+ u8 cmd;
+ u8 status;
+ /* Error code for current CMD */
+ u16 opcode;
+ } cmd_status;
+ u32 reserved[2];
+ /* RK ATAGS, for mem and other info */
+ struct tag cap;
+ /* offset 0x400 */
+ struct rkpcie_cmd cmd;
+};
+
+static void pcie_inbound_config(void)
+{
+ u64 base = PCIE_SNPS_IATU_BASE + 0x100;
+ u32 val;
+ char i;
+
+ /* BAR0: RKEP_BAR0_ADDR */
+ writel(RKEP_BAR0_ADDR, base + PCIE_ATU_CPU_ADDR_LOW);
+ writel(0, base + PCIE_ATU_CPU_ADDR_HIGH);
+ writel(0, base + PCIE_ATU_UNR_REGION_CTRL1);
+ /* PCIE_ATU_UNR_REGION_CTRL2 */
+ writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (0 << 8),
+ base + PCIE_ATU_UNR_REGION_CTRL2);
+ for (i = 0; i < 5; i++) {
+ val = readl(base + PCIE_ATU_UNR_REGION_CTRL2);
+ if (val & PCIE_ATU_ENABLE)
+ break;
+ udelay(LINK_WAIT_IATU);
+ }
+ printep("BAR0: 0x%x\n", RKEP_BAR0_ADDR);
+
+ /* BAR2: RKEP_BAR2_ADDR */
+ writel(RKEP_BAR2_ADDR, base + PCIE_ATU_CPU_ADDR_LOW + 0x200);
+ writel(0, base + PCIE_ATU_CPU_ADDR_HIGH + 0x200);
+ writel(0, base + PCIE_ATU_UNR_REGION_CTRL1 + 0x200);
+ writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | (2 << 8),
+ base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
+ for (i = 0; i < 5; i++) {
+ val = readl(base + PCIE_ATU_UNR_REGION_CTRL2 + 0x200);
+ if (val & PCIE_ATU_ENABLE)
+ break;
+ udelay(LINK_WAIT_IATU);
+ }
+ printep("BAR2: 0x%x%x\n", 0, RKEP_BAR2_ADDR);
+
+ /* BAR4 is wired reg, no need iATU */
+}
+
+static int rockchip_pcie_ep_set_bar_flag(void *dbi_base, u32 barno, int flags)
+{
+ u32 reg;
+
+ reg = PCI_BASE_ADDRESS_0 + (4 * barno);
+
+ /* Disabled the upper 32bits BAR to make a 64bits bar pair */
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
+ writel(0, dbi_base + reg + 0x100000 + 4);
+
+ writel(flags, dbi_base + reg);
+ if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64)
+ writel(0, dbi_base + reg + 4);
+
+ return 0;
+}
+
+static void pcie_bar_init(void *dbi_base)
+{
+ void *resbar_base;
+
+ writel(0, dbi_base + 0x10);
+ writel(0, dbi_base + 0x14);
+ writel(0, dbi_base + 0x18);
+ writel(0, dbi_base + 0x1c);
+ writel(0, dbi_base + 0x20);
+ writel(0, dbi_base + 0x24);
+
+ /* Resize BAR0 to support 4M 32bits */
+ resbar_base = dbi_base + PCI_RESBAR;
+ writel(0xfffff0, resbar_base + 0x4);
+ writel(0x2c0, resbar_base + 0x8);
+ /* BAR2: 64M 64bits */
+ writel(0xfffff0, resbar_base + 0x14);
+ writel(0x6c0, resbar_base + 0x18);
+ /* BAR4: Fixed for EP wired register, 1M 32bits */
+ writel(0xfffff0, resbar_base + 0x24);
+ writel(0xc0, resbar_base + 0x28);
+ /* Set flags */
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 0, PCI_BASE_ADDRESS_MEM_TYPE_32);
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 2,
+ PCI_BASE_ADDRESS_MEM_PREFETCH | PCI_BASE_ADDRESS_MEM_TYPE_64);
+ rockchip_pcie_ep_set_bar_flag(dbi_base, 4, PCI_BASE_ADDRESS_MEM_TYPE_32);
+
+ /* Close bar1 bar3 bar5 */
+ writel(0x0, dbi_base + 0x100000 + 0x14);
+ //writel(0x0, dbi_base + 0x100000 + 0x18);
+ writel(0x0, dbi_base + 0x100000 + 0x1c);
+ //writel(0x0, dbi_base + 0x100000 + 0x20);
+ writel(0x0, dbi_base + 0x100000 + 0x24);
+ /* Close ROM BAR */
+ writel(0x0, dbi_base + 0x100000 + 0x30);
+}
+
+static void pcie_bar0_header_init(void)
+{
+ struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
+
+ bh->magic = RKEP_BOOT_MAGIC;
+ bh->version = 0x100;
+ bh->devmode.mode = RKEP_MODE_LOADER;
+ bh->devmode.submode = RKEP_SMODE_INIT;
+ bh->cap_size = 0;
+
+ memset((char *)RKEP_BAR0_CMD_ADDR, 0, sizeof(struct rkpcie_cmd));
+}
+
+static void pcie_link_set_max_speed(void *dbi_base, u32 link_gen)
+{
+ u32 cap, ctrl2, link_speed;
+ u8 offset = 0x70;
+
+ cap = readl(dbi_base + offset + PCI_EXP_LNKCAP);
+ ctrl2 = readl(dbi_base + offset + PCI_EXP_LNKCTL2);
+ ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
+
+ link_speed = link_gen;
+
+ cap &= ~((u32)PCI_EXP_LNKCAP_SLS);
+ writel(ctrl2 | link_speed, dbi_base + offset + PCI_EXP_LNKCTL2);
+ writel(cap | link_speed, dbi_base + offset + PCI_EXP_LNKCAP);
+}
+
+static void pcie_link_set_lanes(void *dbi_base, u32 lanes)
+{
+ u32 val;
+
+ /* Set the number of lanes */
+ val = readl(dbi_base + PCIE_PORT_LINK_CONTROL);
+ val &= ~PORT_LINK_MODE_MASK;
+ switch (lanes) {
+ case 1:
+ val |= PORT_LINK_MODE_1_LANES;
+ break;
+ case 2:
+ val |= PORT_LINK_MODE_2_LANES;
+ break;
+ case 4:
+ val |= PORT_LINK_MODE_4_LANES;
+ break;
+ default:
+ printf("RKEP: num-lanes %u: invalid value\n", lanes);
+ return;
+ }
+ writel(val, dbi_base + PCIE_PORT_LINK_CONTROL);
+
+ /* Set link width speed control register */
+ val = readl(dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+ val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
+ switch (lanes) {
+ case 1:
+ val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
+ break;
+ case 2:
+ val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
+ break;
+ case 4:
+ val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
+ break;
+ }
+
+ val |= PCIE_DIRECT_SPEED_CHANGE;
+
+ writel(val, dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+}
+
+static void pcie_devmode_update(int mode, int submode)
+{
+ struct rkpcie_boot *bh = (struct rkpcie_boot *)RKEP_BAR0_ADDR;
+
+ bh->devmode.mode = mode;
+ bh->devmode.submode = submode;
+ flush_dcache_range(RKEP_BAR0_ADDR, RKEP_BAR0_ADDR + 64);
+}
+
+#ifdef CONFIG_SPL_RAM_DEVICE
+static void pcie_wait_for_fw(void)
+{
+ struct rkpcie_cmd *cmd = (struct rkpcie_cmd *)(RKEP_BAR0_CMD_ADDR);
+ int val;
+ int i = 0;
+
+ printep("Link ready! Waiting RC to download Firmware:\n");
+ printep("Download uboot.img to BAR2+0\n");
+ printep("Download boot.img to BAR2+0x400000\n");
+ printep("Send CMD_LOADER_RUN to BAR0+0x400\n");
+ while (1) {
+ invalidate_dcache_range(RKEP_BAR0_CMD_ADDR,
+ RKEP_BAR0_CMD_ADDR + 32);
+ val = readl(&cmd->cmd);
+ if (val == RKEP_CMD_LOADER_RUN)
+ break;
+ i++;
+ if (!(i % 10))
+ printep("Waiting for FW, CMD: %x\n", val);
+ mdelay(100);
+ }
+ /* Invalidate Cache for firmware area: BAR2, 64MB */
+ invalidate_dcache_range(RKEP_BAR2_ADDR, RKEP_BAR2_ADDR + 0x4000000);
+ printep("Firmware Download complete!\n");
+}
+
+static void pcie_update_atags(void)
+{
+ struct tag_ram_partition t_ram_part;
+
+ if (!atags_is_available()) {
+ printf("RKEP: No ATAGS data found, create new!\n");
+ atags_destroy();
+ }
+
+ /* ram partition */
+ memset(&t_ram_part, 0, sizeof(t_ram_part));
+ t_ram_part.version = 0;
+ t_ram_part.count = 1;
+ strcpy(t_ram_part.part[0].name, "boot");
+ t_ram_part.part[0].start = RKEP_BAR2_ADDR + 0x400000; /* 4M offset */
+ t_ram_part.part[0].size = 0x3c00000; /* 60M size */
+ atags_set_tag(ATAG_RAM_PARTITION, &t_ram_part);
+}
+
+void rockchip_pcie_ep_get_firmware(void)
+{
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLRDY);
+ pcie_wait_for_fw();
+ pcie_update_atags();
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_FWDLDONE);
+}
+#endif
+
+#ifdef CONFIG_ROCKCHIP_RK3588
+#define BUS_IOC_GPIO3D_IOMUX_SEL_H 0xfd5f807c
+#define GPIO3_BASE 0xfec40000
+#define GPIO3_SWPORT_DR_H (GPIO3_BASE + 0x4)
+#define GPIO3_SWPORT_DDR_H (GPIO3_BASE + 0xc)
+
+static void pcie_board_init(void)
+{
+ /* Enable AU5426 buffer chip on EVB4v10 */
+ /* Set GPIO3D4 to gpio output HIGH mode PCIE20_CLK_PWREN */
+ writel(0xf << 16, BUS_IOC_GPIO3D_IOMUX_SEL_H);
+ writel(0x10001000, GPIO3_SWPORT_DDR_H);
+ writel(0x10001000, GPIO3_SWPORT_DR_H);
+ udelay(100);
+}
+
+#define PHY_MODE_PCIE_AGGREGATION 4 /* PCIe3x4 */
+#define PHY_MODE_PCIE_NANBNB 0 /* P1:PCIe3x2 + P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NANBBI 1 /* P1:PCIe3x2 + P0:PCIe3x1*2 */
+#define PHY_MODE_PCIE_NABINB 2 /* P1:PCIe3x1*2 + P0:PCIe3x2 */
+#define PHY_MODE_PCIE_NABIBI 3 /* P1:PCIe3x1*2 + P0:PCIe3x1*2 */
+
+#define CRU_BASE_ADDR 0xfd7c0000
+#define CRU_SOFTRST_CON32 (CRU_BASE_ADDR + 0x0a80)
+#define CRU_SOFTRST_CON33 (CRU_BASE_ADDR + 0x0a84)
+#define CRU_SOFTRST_CON34 (CRU_BASE_ADDR + 0x0a88)
+#define CRU_GATE_CON32 (CRU_BASE_ADDR + 0x0880)
+#define CRU_GATE_CON33 (CRU_BASE_ADDR + 0x0884)
+#define CRU_GATE_CON34 (CRU_BASE_ADDR + 0x0888)
+#define CRU_GATE_CON38 (CRU_BASE_ADDR + 0x0898)
+#define CRU_GATE_CON39 (CRU_BASE_ADDR + 0x089c)
+#define PHPTOPCRU_BASE_ADDR 0xfd7c8000
+#define PHPTOPCRU_SOFTRST_CON00 (PHPTOPCRU_BASE_ADDR + 0x0a00)
+#define PHPTOPCRU_GATE_CON00 (PHPTOPCRU_BASE_ADDR + 0x0800)
+#define PCIE3PHY_GRF_BASE 0xfd5b8000
+#define RK3588_PCIE3PHY_GRF_CMN_CON0 (PCIE3PHY_GRF_BASE + 0x0000)
+#define PCIE3PHY_GRF_PHY0_CON6 (PCIE3PHY_GRF_BASE + 0x0118)
+#define PCIE3PHY_GRF_PHY1_CON6 (PCIE3PHY_GRF_BASE + 0x0218)
+#define PCIE3PHY_GRF_PHY0_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x1004)
+#define PCIE3PHY_GRF_PHY0_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x1104)
+#define PCIE3PHY_GRF_PHY1_LN0_CON1 (PCIE3PHY_GRF_BASE + 0x2004)
+#define PCIE3PHY_GRF_PHY1_LN1_CON1 (PCIE3PHY_GRF_BASE + 0x2104)
+#define FIREWALL_PCIE_MASTER_SEC 0xfe0300f0
+#define FIREWALL_PCIE_ACCESS 0xfe586040
+#define CRU_PHYREF_ALT_GATE_CON (CRU_BASE_ADDR + 0x0c38)
+#define PMU_PWR_GATE_SFTCON1 0xfd8d8150
+static void pcie_cru_init(void)
+{
+ u32 phy0_mplla, phy1_mplla, t0 = 0, t1 = 0;
+ u32 i, timeout = 500;
+
+ /* Enable power domain: PD_PCIE & PD_PHP */
+ writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
+
+ /* FixMe init 3.0 PHY */
+ /* Phy mode: Aggregation NBNB */
+ writel((0x7 << 16) | PHY_MODE_PCIE_AGGREGATION, RK3588_PCIE3PHY_GRF_CMN_CON0);
+ printep("PHY Mode 0x%x\n", readl(RK3588_PCIE3PHY_GRF_CMN_CON0) & 7);
+ /* Enable clock and sfreset for Controller and PHY */
+ writel(0xffff0000, CRU_SOFTRST_CON32);
+ writel(0xffff0000, CRU_SOFTRST_CON33);
+ writel(0xffff0000, CRU_SOFTRST_CON34);
+ writel(0xffff0000, CRU_GATE_CON32);
+ writel(0xffff0000, CRU_GATE_CON33);
+ writel(0xffff0000, CRU_GATE_CON34);
+ writel(0xffff0000, CRU_GATE_CON38);
+ writel(0xffff0000, CRU_GATE_CON39);
+
+ writel((0x1 << 24), PHPTOPCRU_SOFTRST_CON00);
+ writel(0xffff0000, PHPTOPCRU_GATE_CON00);
+
+ /* PHY Reset */
+ writel((0x1 << 10) | (0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
+
+ udelay(1);
+
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
+ writel(0x000f0000, CRU_PHYREF_ALT_GATE_CON);
+
+ /* PHY0 & PHY1 use internal clock */
+ writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY0_CON6);
+ writel(0x0 | (0x1 << 18), PCIE3PHY_GRF_PHY1_CON6);
+
+ /* phy0_rx0_cmn_refclk_mod */
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN0_CON1);
+ /* phy1_rx0_cmn_refclk_mod */
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY0_LN1_CON1);
+ /* phy0_rx0_cmn_refclk_mod */
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN0_CON1);
+ /* phy1_rx0_cmn_refclk_mod */
+ writel((0x0) | (0x1 << 23), PCIE3PHY_GRF_PHY1_LN1_CON1);
+#endif
+
+ udelay(1000);
+
+ /* Deassert PCIe PMA output clamp mode */
+ writel((0x1 << 8) | (0x1 << 24), RK3588_PCIE3PHY_GRF_CMN_CON0);
+
+ /* Deassert PHY Reset */
+ writel((0x1 << 26), PHPTOPCRU_SOFTRST_CON00);
+
+ /* S-Phy: waiting for phy locked */
+ for (i = 0; i < timeout; i++) {
+ phy0_mplla = readl(PCIE3PHY_GRF_BASE + 0x904);
+ phy1_mplla = readl(PCIE3PHY_GRF_BASE + 0xA04);
+
+ if (phy0_mplla != t0 || phy1_mplla != t1) {
+ printf("RKEP: GRF:904=%x, a04=%x...\n", phy0_mplla, phy1_mplla);
+
+ t0 = phy0_mplla;
+ t1 = phy1_mplla;
+ if (phy0_mplla == 0xF && phy1_mplla == 0xF)
+ break;
+ }
+
+ udelay(10);
+ }
+
+ /* PHY config: no config need for snps3.0phy */
+
+ /* Enable PCIe Access in firewall and master secure mode */
+ writel(0xffff0000, FIREWALL_PCIE_MASTER_SEC);
+ writel(0x01800000, FIREWALL_PCIE_ACCESS);
+}
+#elif CONFIG_ROCKCHIP_RK3568
+
+static void pcie_board_init(void)
+{
+ /* to-do */
+}
+
+static const u16 phy_fw[] = {
+ #include "./../../../drivers/phy/phy-rockchip-snps-pcie3.fw"
+};
+
+#define GRF_PCIE30PHY_RK3568_CON1 0x4
+#define GRF_PCIE30PHY_RK3568_CON3 0xC
+#define GRF_PCIE30PHY_RK3568_CON4 0x10
+#define GRF_PCIE30PHY_RK3568_CON5 0x14
+#define GRF_PCIE30PHY_RK3568_CON6 0x18
+#define GRF_PCIE30PHY_RK3568_CON9 0x24
+#define GRF_PCIE30PHY_RK3568_STATUS0 0x80
+#define RK3568_SRAM_INIT_DONE(reg) ((reg) & BIT(14))
+
+#define PMUCRU_BASE 0xFDD00000
+#define PMUCRU_PMUGATE_CON02 (PMUCRU_BASE + 0x188)
+
+#define CRU_BASE 0xFDD20000
+#define CRU_GATE_CON12 (CRU_BASE + 0x330)
+#define CRU_GATE_CON13 (CRU_BASE + 0x334)
+#define CRU_GATE_CON33 (CRU_BASE + 0x384)
+#define CRU_SOFTRST_CON12 (CRU_BASE + 0x430)
+#define CRU_SOFTRST_CON27 (CRU_BASE + 0x46c)
+
+#define PCIE30_PHY_GRF 0xFDCB8000
+
+void pcie_cru_init(void)
+{
+ u32 i, reg;
+ void __iomem *mmio = (void __iomem *)0xFE8C0000;
+
+ /* Enable phy and controoler clk */
+ writel(0xffff0000, PMUCRU_PMUGATE_CON02);
+ writel(0xffff0000, CRU_GATE_CON12);
+ writel(0xffff0000, CRU_GATE_CON13);
+ writel(0xffff0000, CRU_GATE_CON33);
+ writel(0xffff0000, CRU_SOFTRST_CON27);
+
+ writel(0x40004000, CRU_SOFTRST_CON27);
+ writel(0x80008000, PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
+
+ writel((0x1 << 15) | (0x1 << 31),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
+
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
+ /* use internal clock */
+ writel(0x0 | (0x1 << 31), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON3);
+
+ /* rx0_cmn_refclk_mode disabled */
+ writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON5);
+ /* rx1_cmn_refclk_mode disabled */
+ writel((0x0) | (0x1 << 25), PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON6);
+#endif
+
+ writel((0x0 << 14) | (0x1 << (14 + 16)),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
+ writel((0x0 << 13) | (0x1 << (13 + 16)),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_bypass
+
+ writel(0x40000000, CRU_SOFTRST_CON27);
+
+ udelay(5);
+ printf("RKEP: sram initial\n");
+ while (1) {
+ reg = readl(PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_STATUS0);
+ if (RK3568_SRAM_INIT_DONE(reg))
+ break;
+ }
+ printf("RKEP: sram init done\n");
+
+ writel((0x3 << 8) | (0x3 << (8 + 16)),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9); //map to access sram
+ for (i = 0; i < ARRAY_SIZE(phy_fw); i++)
+ writel(phy_fw[i], mmio + (i << 2));
+
+ printf("RKEP: snps pcie3phy FW update! size %ld\n", ARRAY_SIZE(phy_fw));
+ writel((0x0 << 8) | (0x3 << (8 + 16)),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON9);
+ writel((0x1 << 14) | (0x1 << (14 + 16)),
+ PCIE30_PHY_GRF + GRF_PCIE30PHY_RK3568_CON4); //sdram_ld_done
+
+ writel(0xffff0000, CRU_SOFTRST_CON12);
+ writel(0x100010, PCIE_SNPS_APB_BASE + 0x180);
+
+ udelay(1);
+}
+#endif
+
+static void pcie_ep_init(void)
+{
+ u32 val;
+ void *dbi_base = (void *)PCIE_SNPS_DBI_BASE;
+ u64 apb_base = PCIE_SNPS_APB_BASE;
+ int i, retries = 0;
+
+#ifdef PCIE_ENABLE_SRNS_PLL_REFCLK
+ printep("RefClock in SRNS clock mode\n");
+#else
+ printep("RefClock in common clock_mode\n");
+#endif
+
+ /*
+ * ltssm_enable enhance mode and enable delaying the link training
+ * after Hot Reset
+ */
+ writel(0x120012, apb_base + 0x180);
+
+ /* Unmask pm_turnoff_int */
+ writel(0x04000000, apb_base + 0x18);
+
+ /* PortLorgic DBI_RO_WR_EN */
+ val = readl((dbi_base + 0x8bc));
+ val |= 0x1;
+ writel(val, dbi_base + 0x8bc);
+
+reinit:
+ pcie_bar_init(dbi_base);
+ pcie_inbound_config();
+
+ /* Device PID, DID */
+ writel(0x1d87, dbi_base + 0x00);
+ writel(0x356a, dbi_base + 0x02);
+ /* Device Class: Processing accelerators */
+ writel(0x1200, dbi_base + 0x0a);
+
+ pcie_link_set_max_speed(dbi_base, PCI_EXP_LNKCTL2_TLS_8_0GT);
+
+#ifdef CONFIG_ROCKCHIP_RK3588
+ pcie_link_set_lanes(dbi_base, 4);
+#elif CONFIG_ROCKCHIP_RK3568
+ pcie_link_set_lanes(dbi_base, 2);
+#endif
+
+ /* EP mode */
+ writel(0xf00000, apb_base);
+ udelay(100);
+
+ /* Enable EP mem/io access */
+ val = readl(dbi_base + 0x4);
+ writel(val | 0x6, dbi_base + 0x4);
+
+ if (retries) /* Set app_dly2_done to enable app_ltssm_enable */
+ writel(0x80008, apb_base + 0x180);
+ else /* Enable LTSSM */
+ writel(0xc000c, apb_base);
+ printep("init PCIe fast Link up\n");
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKRDY);
+
+ /* Waiting for Link up */
+ while (1) {
+ val = readl(apb_base + 0x300);
+ if (((val & 0x3ffff) & ((0x3 << 16) | 0x11)) == 0x30011)
+ break;
+ mdelay(1);
+ }
+ printep("Link up %x\n", val);
+ mdelay(3);
+
+ /* Wait for link stable */
+ for (i = 0; i < 10000; i++) {
+ val = readl(apb_base + 0x10);
+ if (val & 0x4) {
+ writel(0x4, apb_base + 0x10);
+ printep("Link is reset, int status misc=%x\n", val);
+ if (retries < 3) {
+ retries++;
+ goto reinit;
+ } else {
+ break;
+ }
+ }
+ udelay(1);
+ }
+ printep("Done\n");
+ pcie_devmode_update(RKEP_MODE_LOADER, RKEP_SMODE_LNKUP);
+}
+
+void rockchip_pcie_ep_init(void)
+{
+ u32 val;
+
+ printf("\nRKEP: Init PCIe EP\n");
+ pcie_bar0_header_init();
+
+#ifdef CONFIG_ROCKCHIP_RK3588
+ writel(0x1 << 23 | 0x1 << 21, PMU_PWR_GATE_SFTCON1);
+ udelay(10);
+#endif
+ /* Re-in pcie initial */
+ val = readl(PCIE_SNPS_APB_BASE + 0x300);
+ if (((val & 0x3ffff) & ((0x3 << 16))) == 0x30000) {
+ printf("RKEP: already link up\n");
+ return;
+ }
+
+ pcie_board_init();
+ /* CRU and PHY Init */
+ pcie_cru_init();
+
+ pcie_ep_init();
+}
diff --git a/u-boot/arch/arm/mach-rockchip/uimage.c b/u-boot/arch/arm/mach-rockchip/uimage.c
index e805b12..e5f8416 100644
--- a/u-boot/arch/arm/mach-rockchip/uimage.c
+++ b/u-boot/arch/arm/mach-rockchip/uimage.c
@@ -12,8 +12,8 @@
#include <asm/arch/resource_img.h>
#include <asm/arch/uimage.h>
-static int uimage_load_one(struct blk_desc *dev_desc, disk_partition_t *part,
- int pos_off, int size, void *dst)
+int uimage_load_one(struct blk_desc *dev_desc, disk_partition_t *part,
+ int pos_off, int size, void *dst)
{
u32 blknum, blkoff;
u32 unused;
@@ -183,31 +183,23 @@
return 0;
}
-int uimage_init_resource(void)
-{
- struct blk_desc *dev_desc;
- disk_partition_t part;
- image_header_t *hdr;
- char *part_name;
- ulong data, offset;
- ulong size;
#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
- ulong dst;
- int idx = 3;
-#endif
- int ret;
+int uimage_init_resource(struct blk_desc *dev_desc)
+{
+ disk_partition_t part;
+ ulong data, offset, size;
+ image_header_t *hdr;
+ char *part_name = PART_BOOT;
+ int ret, idx = 3;
+ void *buf;
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("No dev_desc!\n");
- return ENODEV;
- }
+ if (!dev_desc)
+ return -ENODEV;
+#ifndef CONFIG_ANDROID_AB
if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
part_name = PART_RECOVERY;
- else
- part_name = PART_BOOT;
-
+#endif
if (part_get_info_by_name(dev_desc, part_name, &part) < 0) {
UIMG_I("No %s partition\n", part_name);
return -ENODEV;
@@ -215,35 +207,28 @@
hdr = uimage_get_hdr(dev_desc, &part);
if (!hdr)
- return -ENODEV;
+ return -EAGAIN;
image_multi_getimg(hdr, idx, &data, &size);
offset = data - (ulong)hdr;
free(hdr);
-#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
- ulong fdt_addr;
-
- /* reserve enough space before fdt */
- fdt_addr = env_get_ulong("fdt_addr_r", 16, 0);
- dst = (ulong)fdt_addr -
- ALIGN(size, dev_desc->blksz) - CONFIG_SYS_FDT_PAD;
- ret = uimage_load_one(dev_desc, &part, offset, size, (void *)dst);
- if (ret) {
- UIMG_I("Failed to load resource file, ret=%d\n", ret);
- return ret;
- }
-
- if (!sysmem_alloc_base(MEM_RESOURCE, (phys_addr_t)dst,
- ALIGN(size, RK_BLK_SIZE)))
+ buf = memalign(ARCH_DMA_MINALIGN, ALIGN(size, dev_desc->blksz));
+ if (!buf)
return -ENOMEM;
- ret = resource_create_ram_list(dev_desc, (void *)dst);
+ printf("RESC: '%s', blk@0x%08lx\n", part.name,
+ part.start + (offset / dev_desc->blksz));
+ ret = uimage_load_one(dev_desc, &part, offset, size, buf);
+ if (ret)
+ return ret;
+
+ ret = resource_setup_ram_list(dev_desc, buf);
if (ret) {
- UIMG_I("Failed to create resource list, ret=%d\n", ret);
+ UIMG_I("Failed to setup resource ram list, ret=%d\n", ret);
return ret;
}
-#endif
return 0;
}
+#endif
diff --git a/u-boot/arch/arm/mach-rockchip/vendor.c b/u-boot/arch/arm/mach-rockchip/vendor.c
index fce520d..2a146b7 100644
--- a/u-boot/arch/arm/mach-rockchip/vendor.c
+++ b/u-boot/arch/arm/mach-rockchip/vendor.c
@@ -10,6 +10,7 @@
#include <boot_rkimg.h>
#include <nand.h>
#include <part.h>
+#include <fdt_support.h>
/* tag for vendor check */
#define VENDOR_TAG 0x524B5644
@@ -20,6 +21,9 @@
/* align to 64 bytes */
#define VENDOR_BTYE_ALIGN 0x3F
#define VENDOR_BLOCK_SIZE 512
+
+#define PAGE_ALGIN_SIZE (4096uL)
+#define PAGE_ALGIN_MASK (~(PAGE_ALGIN_SIZE - 1))
/* --- Emmc define --- */
/* Starting address of the Vendor in memory. */
@@ -493,13 +497,14 @@
/* Initialize */
bootdev_type = dev_desc->if_type;
- /* Always use, no need to release */
- buffer = (u8 *)malloc(size);
+ /* Always use, no need to release, align to page size for kerenl reserved memory */
+ buffer = (u8 *)memalign(PAGE_ALGIN_SIZE, size);
if (!buffer) {
printf("[Vendor ERROR]:Malloc failed!\n");
ret = -ENOMEM;
goto out;
}
+
/* Pointer initialization */
vendor_info.hdr = (struct vendor_hdr *)buffer;
vendor_info.item = (struct vendor_item *)(buffer + sizeof(struct vendor_hdr));
@@ -566,6 +571,29 @@
return ret;
}
+void vendor_storage_fixup(void *blob)
+{
+ unsigned long size;
+ unsigned long start;
+ ulong offset;
+
+ /* init vendor storage */
+ if (!bootdev_type) {
+ if (vendor_storage_init() < 0)
+ return;
+ }
+
+ offset = fdt_node_offset_by_compatible(blob, 0, "rockchip,vendor-storage-rm");
+ if (offset >= 0) {
+ start = (unsigned long)vendor_info.hdr;
+ size = (unsigned long)((void *)vendor_info.version2 - (void *)vendor_info.hdr);
+ size += 4;
+ fdt_update_reserved_memory(blob, "rockchip,vendor-storage-rm",
+ (u64)start,
+ (u64)size);
+ }
+}
+
/*
* @id: item id, first 4 id is occupied:
* VENDOR_SN_ID
diff --git a/u-boot/board/rockchip/evb_rk3528/Kconfig b/u-boot/board/rockchip/evb_rk3528/Kconfig
new file mode 100644
index 0000000..d0f6599
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3528/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3528
+
+config SYS_BOARD
+ default "evb_rk3528"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3528"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/u-boot/board/rockchip/evb_rk3528/Makefile b/u-boot/board/rockchip/evb_rk3528/Makefile
new file mode 100644
index 0000000..1fa46e5
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3528/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 Rockchip Electronics Co., Ltd
+#
+
+obj-y += evb_rk3528.o
diff --git a/u-boot/board/rockchip/evb_rk3528/evb_rk3528.c b/u-boot/board/rockchip/evb_rk3528/evb_rk3528.c
new file mode 100644
index 0000000..d0c1e55
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3528/evb_rk3528.c
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = 0xfe500000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .dis_u2_susphy_quirk = 1,
+ .usb2_phyif_utmi_width = 16,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif
diff --git a/u-boot/board/rockchip/evb_rk3562/Kconfig b/u-boot/board/rockchip/evb_rk3562/Kconfig
new file mode 100644
index 0000000..810e563
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3562/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_EVB_RK3562
+
+config SYS_BOARD
+ default "evb_rk3562"
+
+config SYS_VENDOR
+ default "rockchip"
+
+config SYS_CONFIG_NAME
+ default "evb_rk3562"
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+
+endif
diff --git a/u-boot/board/rockchip/evb_rk3562/Makefile b/u-boot/board/rockchip/evb_rk3562/Makefile
new file mode 100644
index 0000000..5b6aff0
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3562/Makefile
@@ -0,0 +1,7 @@
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2022 Rockchip Electronics Co., Ltd
+#
+
+obj-y += evb_rk3562.o
diff --git a/u-boot/board/rockchip/evb_rk3562/evb_rk3562.c b/u-boot/board/rockchip/evb_rk3562/evb_rk3562.c
new file mode 100644
index 0000000..a7be427
--- /dev/null
+++ b/u-boot/board/rockchip/evb_rk3562/evb_rk3562.c
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dwc3-uboot.h>
+#include <usb.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_DWC3
+static struct dwc3_device dwc3_device_data = {
+ .maximum_speed = USB_SPEED_HIGH,
+ .base = 0xfe500000,
+ .dr_mode = USB_DR_MODE_PERIPHERAL,
+ .index = 0,
+ .dis_u2_susphy_quirk = 1,
+ .usb2_phyif_utmi_width = 16,
+};
+
+int usb_gadget_handle_interrupts(void)
+{
+ dwc3_uboot_handle_interrupt(0);
+ return 0;
+}
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ return dwc3_uboot_init(&dwc3_device_data);
+}
+#endif
diff --git a/u-boot/cmd/Kconfig b/u-boot/cmd/Kconfig
index 8273ed1..1efdeae 100644
--- a/u-boot/cmd/Kconfig
+++ b/u-boot/cmd/Kconfig
@@ -1020,6 +1020,13 @@
This provides various sub-commands to initialise and configure the
Turndra tsi148 device. See the command help for full details.
+config CMD_UFS
+ bool "Enable UFS - Universal Flash Subsystem commands"
+ depends on UFS
+ help
+ "This provides commands to initialise and configure universal flash
+ subsystem devices"
+
config CMD_UNIVERSE
bool "universe - Command to set up the Turndra Universe controller"
help
@@ -1181,15 +1188,7 @@
endmenu
-config CMD_MEMTESTER
- bool "Enable memtester for ddr"
- help
- This enables memtester for ddr.
-
-config CMD_DDR_TEST_TOOL
- bool "Enable ddr test tool"
- help
- This enable ddr test tool code.
+source "cmd/ddr_tool/Kconfig"
menu "Misc commands"
diff --git a/u-boot/cmd/Makefile b/u-boot/cmd/Makefile
index 3f71a35..d4c12a3 100644
--- a/u-boot/cmd/Makefile
+++ b/u-boot/cmd/Makefile
@@ -91,8 +91,7 @@
obj-$(CONFIG_ID_EEPROM) += mac.o
obj-$(CONFIG_CMD_MD5SUM) += md5sum.o
obj-$(CONFIG_CMD_MEMORY) += mem.o
-obj-$(CONFIG_CMD_MEMTESTER) += memtester/
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ddr_tool/
+obj-$(CONFIG_CMD_DDR_TOOL) += ddr_tool/
obj-$(CONFIG_CMD_IO) += io.o
obj-$(CONFIG_CMD_MFSL) += mfsl.o
obj-$(CONFIG_CMD_MII) += mii.o
@@ -149,6 +148,7 @@
obj-$(CONFIG_CMD_UNZIP) += unzip.o
obj-$(CONFIG_CMD_LZMADEC) += lzmadec.o
obj-$(CONFIG_CMD_SCRIPT_UPDATE) += script_update.o
+obj-$(CONFIG_CMD_UFS) += ufs.o
obj-$(CONFIG_CMD_USB) += usb.o disk.o
obj-$(CONFIG_CMD_FASTBOOT) += fastboot.o
obj-$(CONFIG_CMD_FS_UUID) += fs_uuid.o
diff --git a/u-boot/cmd/boot_android.c b/u-boot/cmd/boot_android.c
index 98a2893..de6b8e0 100755
--- a/u-boot/cmd/boot_android.c
+++ b/u-boot/cmd/boot_android.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <bootm.h>
#include <command.h>
+#include <mp_boot.h>
#include <android_bootloader_message.h>
#include <android_avb/rk_avb_ops_user.h>
#include <android_avb/avb_atx_ops.h>
@@ -30,6 +31,9 @@
if (argc > 5)
return CMD_RET_USAGE;
+#ifdef CONFIG_MP_BOOT_BOOTM
+ mpb_post(5);
+#endif
if (argc >= 5) {
load_address = simple_strtoul(argv[4], &addr_arg_endp, 16);
if (addr_arg_endp == argv[4] || *addr_arg_endp != '\0')
diff --git a/u-boot/cmd/bootfit.c b/u-boot/cmd/bootfit.c
index a0efec7..3a8b75b 100644
--- a/u-boot/cmd/bootfit.c
+++ b/u-boot/cmd/bootfit.c
@@ -103,7 +103,6 @@
strcat(slot_info, slot_suffix);
env_update("bootargs", slot_info);
- ab_update_root_uuid();
#endif
ret = do_bootm_states(NULL, 0, ARRAY_SIZE(bootm_args), bootm_args,
diff --git a/u-boot/cmd/cache.c b/u-boot/cmd/cache.c
index 37ab345..004dcc2 100644
--- a/u-boot/cmd/cache.c
+++ b/u-boot/cmd/cache.c
@@ -54,7 +54,24 @@
static int do_dcache(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+ ulong start, size;
+
switch (argc) {
+ case 4:
+ start = simple_strtoul(argv[2], NULL, 16);
+ size = simple_strtoul(argv[3], NULL, 16);
+
+ switch (parse_argv(argv[1])) {
+ case 2:
+ printf("flush dcache: 0x%08lx - 0x%08lx\n", start, start + size);
+ flush_dcache_range(start, start + size);
+ break;
+ case 3:
+ printf("invalidate dcache: 0x%08lx - 0x%08lx\n", start, start + size);
+ invalidate_dcache_range(start, start + size);
+ break;
+ }
+ break;
case 2: /* on / off */
switch (parse_argv(argv[1])) {
case 0:
@@ -65,6 +82,9 @@
break;
case 2:
flush_dcache_all();
+ break;
+ case 3:
+ printf("error: dcache invalidate require [start] [size]\n");
break;
}
break;
@@ -80,7 +100,9 @@
static int parse_argv(const char *s)
{
- if (strcmp(s, "flush") == 0)
+ if (strcmp(s, "invalidate") == 0)
+ return 3;
+ else if (strcmp(s, "flush") == 0)
return 2;
else if (strcmp(s, "on") == 0)
return 1;
@@ -99,8 +121,8 @@
);
U_BOOT_CMD(
- dcache, 2, 1, do_dcache,
+ dcache, 4, 1, do_dcache,
"enable or disable data cache",
- "[on, off, flush]\n"
+ "[on, off, flush, invalidate] [start] [size]\n"
" - enable, disable, or flush data (writethrough) cache"
);
diff --git a/u-boot/cmd/ddr_tool/Kconfig b/u-boot/cmd/ddr_tool/Kconfig
new file mode 100644
index 0000000..0c83e8d
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/Kconfig
@@ -0,0 +1,32 @@
+menu "DDR Tool"
+
+config CMD_DDR_TOOL
+ bool "Enable DDR Tool"
+ help
+ This enable ddr tool such as ddr dq eye, ddr test tool, memtester and stressapptest.
+
+config CMD_DDR_DQ_EYE
+ bool "Enable DDR DQ eye fuction"
+ depends on CMD_DDR_TOOL
+ help
+ This enable ddr dq eye fuction.
+
+config CMD_DDR_TEST
+ bool "Enable ddr test tool"
+ depends on CMD_DDR_TOOL
+ help
+ This enable ddr test tool code.
+
+config CMD_MEMTESTER
+ bool "Enable memtester for ddr"
+ depends on CMD_DDR_TOOL
+ help
+ This enables memtester for ddr.
+
+config CMD_STRESSAPPTEST
+ bool "Enable stressapptest for ddr"
+ depends on CMD_DDR_TOOL
+ help
+ This enables stressapptest for ddr.
+
+endmenu
diff --git a/u-boot/cmd/ddr_tool/Makefile b/u-boot/cmd/ddr_tool/Makefile
index 788b400..7fdf4fa 100644
--- a/u-boot/cmd/ddr_tool/Makefile
+++ b/u-boot/cmd/ddr_tool/Makefile
@@ -1,25 +1,12 @@
#
-# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
-# We don't want the bootrom-helper present in a full U-Boot build, as
-# this may have entered from ATF with the stack-pointer pointing to
-# inaccessible/protected memory (and the bootrom-helper assumes that
-# the stack-pointer is valid before switching to the U-Boot stack).
-ifdef CONFIG_ROCKCHIP_PX30
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_px30.o
-endif
-ifdef CONFIG_ROCKCHIP_RK3328
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_rk3328.o
-endif
-ifdef CONFIG_ROCKCHIP_RK1808
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) = ddr_test_rk1808.o
-endif
-ifndef CONFIG_CMD_MEMTESTER
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ../memtester/ddr_tester_common.o
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ../memtester/io_map.o
-endif
-obj-$(CONFIG_CMD_DDR_TEST_TOOL) += ddr_dq_eye.o
+obj-$(CONFIG_CMD_DDR_TOOL) += ddr_tool_common.o ddr_tool_mp.o io_map.o
+obj-$(CONFIG_CMD_DDR_DQ_EYE) += ddr_dq_eye/
+obj-$(CONFIG_CMD_DDR_TEST) += ddr_test/
+obj-$(CONFIG_CMD_MEMTESTER) += memtester/
+obj-$(CONFIG_CMD_STRESSAPPTEST) += stressapptest/
diff --git a/u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile b/u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile
new file mode 100644
index 0000000..60f072a
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/ddr_dq_eye/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_DDR_DQ_EYE) += ddr_dq_eye.o
diff --git a/u-boot/cmd/ddr_tool/ddr_dq_eye.c b/u-boot/cmd/ddr_tool/ddr_dq_eye/ddr_dq_eye.c
similarity index 100%
rename from u-boot/cmd/ddr_tool/ddr_dq_eye.c
rename to u-boot/cmd/ddr_tool/ddr_dq_eye/ddr_dq_eye.c
diff --git a/u-boot/cmd/ddr_tool/ddr_test/Makefile b/u-boot/cmd/ddr_tool/ddr_test/Makefile
new file mode 100644
index 0000000..320a915
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/ddr_test/Makefile
@@ -0,0 +1,20 @@
+#
+# (C) Copyright 2018 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+# We don't want the bootrom-helper present in a full U-Boot build, as
+# this may have entered from ATF with the stack-pointer pointing to
+# inaccessible/protected memory (and the bootrom-helper assumes that
+# the stack-pointer is valid before switching to the U-Boot stack).
+
+ifdef CONFIG_ROCKCHIP_PX30
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_px30.o
+endif
+ifdef CONFIG_ROCKCHIP_RK1808
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_rk1808.o
+endif
+ifdef CONFIG_ROCKCHIP_RK3328
+obj-$(CONFIG_CMD_DDR_TEST) = ddr_test_rk3328.o
+endif
diff --git a/u-boot/cmd/ddr_tool/ddr_test_px30.S b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S
similarity index 99%
rename from u-boot/cmd/ddr_tool/ddr_test_px30.S
rename to u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S
index a6e9854..dc34485 100644
--- a/u-boot/cmd/ddr_tool/ddr_test_px30.S
+++ b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_px30.S
@@ -1814,8 +1814,8 @@
.file 36 "include/log.h"
.file 37 "include/stdio.h"
.file 38 "./arch/arm/include/asm/arch/sdram.h"
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
+ .file 39 "cmd/ddr_tool/io_map.h"
+ .file 40 "cmd/ddr_tool/ddr_tool_common.h"
.file 41 "include/vsprintf.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
diff --git a/u-boot/cmd/ddr_tool/ddr_test_rk1808.S b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S
similarity index 99%
rename from u-boot/cmd/ddr_tool/ddr_test_rk1808.S
rename to u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S
index 156f79f..a1e1217 100644
--- a/u-boot/cmd/ddr_tool/ddr_test_rk1808.S
+++ b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk1808.S
@@ -1604,8 +1604,8 @@
.file 34 "include/log.h"
.file 35 "include/stdio.h"
.file 36 "./arch/arm/include/asm/arch/sdram.h"
- .file 37 "cmd/ddr_tool/../memtester/io_map.h"
- .file 38 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
+ .file 37 "cmd/ddr_tool/io_map.h"
+ .file 38 "cmd/ddr_tool/ddr_tool_common.h"
.file 39 "include/vsprintf.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
diff --git a/u-boot/cmd/ddr_tool/ddr_test_px30.S b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S
similarity index 99%
copy from u-boot/cmd/ddr_tool/ddr_test_px30.S
copy to u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S
index a6e9854..dc34485 100644
--- a/u-boot/cmd/ddr_tool/ddr_test_px30.S
+++ b/u-boot/cmd/ddr_tool/ddr_test/ddr_test_rk3328.S
@@ -1814,8 +1814,8 @@
.file 36 "include/log.h"
.file 37 "include/stdio.h"
.file 38 "./arch/arm/include/asm/arch/sdram.h"
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
+ .file 39 "cmd/ddr_tool/io_map.h"
+ .file 40 "cmd/ddr_tool/ddr_tool_common.h"
.file 41 "include/vsprintf.h"
.section .debug_info,"",@progbits
.Ldebug_info0:
diff --git a/u-boot/cmd/ddr_tool/ddr_test_rk3328.S b/u-boot/cmd/ddr_tool/ddr_test_rk3328.S
deleted file mode 100644
index a6e9854..0000000
--- a/u-boot/cmd/ddr_tool/ddr_test_rk3328.S
+++ /dev/null
@@ -1,9940 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
-/*
- * Copyright (C) 2019 Rockchip Electronics Co., Ltd.
- */
-
- .arch armv8-a+nosimd
- .file "ddr_test_code.c"
- .text
-.Ltext0:
- .cfi_sections .debug_frame
- .section .text.crosstalk,"ax",@progbits
- .align 2
- .global crosstalk
- .type crosstalk, %function
-crosstalk:
-.LFB200:
- .file 1 "cmd/ddr_tool/crosstalk.c"
- .loc 1 46 0
- .cfi_startproc
-.LVL0:
- stp x29, x30, [sp, -144]!
- .cfi_def_cfa_offset 144
- .cfi_offset 29, -144
- .cfi_offset 30, -136
- add x29, sp, 0
- .cfi_def_cfa_register 29
- stp x21, x22, [sp, 32]
- .cfi_offset 21, -112
- .cfi_offset 22, -104
- .loc 1 66 0
- adrp x22, .LC2
- .loc 1 46 0
- stp x23, x24, [sp, 48]
- .cfi_offset 23, -96
- .cfi_offset 24, -88
- mov x23, x0
- stp x19, x20, [sp, 16]
- mov x24, x1
- stp x25, x26, [sp, 64]
- .loc 1 63 0
- adrp x0, .LC1
-.LVL1:
- .loc 1 46 0
- stp x27, x28, [sp, 80]
- .cfi_offset 19, -128
- .cfi_offset 20, -120
- .cfi_offset 25, -80
- .cfi_offset 26, -72
- .cfi_offset 27, -64
- .cfi_offset 28, -56
- .loc 1 63 0
- add x0, x0, :lo12:.LC1
- bl printf
-.LVL2:
- .loc 1 71 0
- add x21, x29, 112
- .loc 1 66 0
- add x0, x22, :lo12:.LC2
- .loc 1 68 0
- adrp x25, .LC3
- .loc 1 66 0
- str x0, [x29, 104]
- .loc 1 64 0
- mov w20, 0
- .loc 1 68 0
- add x0, x25, :lo12:.LC3
- str x0, [x29, 96]
-.LVL3:
-.L6:
- .loc 1 66 0
- ldr x0, [x29, 104]
- .loc 1 71 0
- mov w26, 1
- .loc 1 66 0
- mov w1, w20
- .loc 1 71 0
- lsl w26, w26, w20
- .loc 1 65 0
- mov w28, -1
- .loc 1 67 0
- mov w27, 0
- .loc 1 66 0
- bl printf
-.LVL4:
-.L5:
- .loc 1 68 0
- ldr x0, [x29, 96]
- mov w1, w27
- .loc 1 69 0
- mvn w28, w28
-.LVL5:
- mov x19, 0
- .loc 1 68 0
- bl printf
-.LVL6:
-.L2:
- .loc 1 71 0 discriminator 3
- eor w0, w26, w28
- str w0, [x19, x21]
- add x19, x19, 4
- .loc 1 72 0 discriminator 3
- mvn w28, w28
-.LVL7:
- .loc 1 70 0 discriminator 3
- cmp x19, 32
- bne .L2
- .loc 1 74 0
- mov w1, w19
- mov x0, x21
- bl data_cpu_2_io
-.LVL8:
- .loc 1 75 0
- mov x3, x24
- mov x2, x23
- mov w1, w19
- mov x0, x21
- bl write_buf_to_ddr
-.LVL9:
- .loc 1 76 0
- mov w4, 1
- mov x3, x24
- mov x2, x23
- mov w1, w19
- mov x0, x21
- bl cmp_buf_data
-.LVL10:
- cbz x0, .L3
-.LVL11:
-.L11:
- .loc 1 78 0
- mov w0, -1
-.L1:
- .loc 1 111 0
- ldp x19, x20, [sp, 16]
- ldp x21, x22, [sp, 32]
- ldp x23, x24, [sp, 48]
-.LVL12:
- ldp x25, x26, [sp, 64]
- ldp x27, x28, [sp, 80]
- ldp x29, x30, [sp], 144
- .cfi_remember_state
- .cfi_restore 30
- .cfi_restore 29
- .cfi_restore 27
- .cfi_restore 28
- .cfi_restore 25
- .cfi_restore 26
- .cfi_restore 23
- .cfi_restore 24
- .cfi_restore 21
- .cfi_restore 22
- .cfi_restore 19
- .cfi_restore 20
- .cfi_def_cfa 31, 0
- ret
-.LVL13:
-.L3:
- .cfi_restore_state
- .loc 1 67 0 discriminator 2
- add w27, w27, 1
-.LVL14:
- cmp w27, 2
- bne .L5
- .loc 1 64 0 discriminator 2
- add w20, w20, 1
-.LVL15:
- cmp w20, 32
- bne .L6
- .loc 1 85 0
- adrp x0, .LC4
- add x0, x0, :lo12:.LC4
- bl printf
-.LVL16:
- .loc 1 86 0
- mov x0, 128
- bl malloc
-.LVL17:
- mov x21, x0
-.LVL18:
- .loc 1 87 0
- cbnz x0, .L7
- .loc 1 88 0
- adrp x0, .LC5
-.LVL19:
- mov x1, 128
- add x0, x0, :lo12:.LC5
- bl printf
-.LVL20:
-.L7:
- adrp x26, .LANCHOR0
- .loc 1 91 0
- add x27, x22, :lo12:.LC2
-.LVL21:
- .loc 1 93 0
- add x25, x25, :lo12:.LC3
- .loc 1 98 0
- add x26, x26, :lo12:.LANCHOR0
- .loc 1 69 0
- mov w20, 0
-.LVL22:
-.L14:
- .loc 1 92 0
- mov w22, 0
- .loc 1 96 0
- mov w28, 1
- .loc 1 91 0
- mov w1, w20
- mov x0, x27
- bl printf
-.LVL23:
-.L13:
- .loc 1 93 0
- mov w1, w22
- mov x0, x25
- bl printf
-.LVL24:
- .loc 1 96 0
- mov x19, 0
- lsl w1, w28, w22
-.LVL25:
-.L10:
- ldr w0, [x19, x26]
- .loc 1 95 0
- cbz w20, .L8
- .loc 1 96 0
- eor w0, w0, w1
-.L8:
- .loc 1 98 0
- str w0, [x21, x19]
- add x19, x19, 4
- .loc 1 94 0
- cmp x19, 128
- bne .L10
- .loc 1 100 0
- mov w1, w19
- mov x0, x21
- bl data_cpu_2_io
-.LVL26:
- .loc 1 101 0
- mov x3, x24
- mov x2, x23
- mov w1, w19
- mov x0, x21
- bl write_buf_to_ddr
-.LVL27:
- .loc 1 103 0
- mov w4, 1
- mov x3, x24
- mov x2, x23
- mov w1, w19
- mov x0, x21
- bl cmp_buf_data
-.LVL28:
- cbnz x0, .L11
- .loc 1 106 0
- cbz w20, .L12
- .loc 1 92 0 discriminator 2
- add w22, w22, 1
-.LVL29:
- cmp w22, 32
- bne .L13
-.L12:
- .loc 1 90 0 discriminator 2
- add w20, w20, 1
-.LVL30:
- cmp w20, 2
- bne .L14
- .loc 1 110 0
- mov w0, 0
- b .L1
- .cfi_endproc
-.LFE200:
- .size crosstalk, .-crosstalk
- .section .text.set_ddr_freq,"ax",@progbits
- .align 2
- .weak set_ddr_freq
- .type set_ddr_freq, %function
-set_ddr_freq:
-.LFB253:
- .file 2 "cmd/ddr_tool/ddr_tool.c"
- .loc 2 45 0
- .cfi_startproc
-.LVL31:
- .loc 2 47 0
- mov w0, 0
-.LVL32:
- ret
- .cfi_endproc
-.LFE253:
- .size set_ddr_freq, .-set_ddr_freq
- .section .text.set_vdd_logic,"ax",@progbits
- .align 2
- .weak set_vdd_logic
- .type set_vdd_logic, %function
-set_vdd_logic:
-.LFB254:
- .loc 2 50 0
- .cfi_startproc
-.LVL33:
- .loc 2 52 0
- mov w0, -1
-.LVL34:
- ret
- .cfi_endproc
-.LFE254:
- .size set_vdd_logic, .-set_vdd_logic
- .section .text.diagonalscan,"ax",@progbits
- .align 2
- .global diagonalscan
- .type diagonalscan, %function
-diagonalscan:
-.LFB268:
- .file 3 "cmd/ddr_tool/diagonalscan.c"
- .loc 3 16 0
- .cfi_startproc
-.LVL35:
- stp x29, x30, [sp, -112]!
- .cfi_def_cfa_offset 112
- .cfi_offset 29, -112
- .cfi_offset 30, -104
- .loc 3 19 0
- mov x2, 32
- .loc 3 16 0
- add x29, sp, 0
- .cfi_def_cfa_register 29
- stp x21, x22, [sp, 32]
- .cfi_offset 21, -80
- .cfi_offset 22, -72
- mov x22, x1
- stp x23, x24, [sp, 48]
- .cfi_offset 23, -64
- .cfi_offset 24, -56
- sub x23, x1, #32
- .loc 3 19 0
- adrp x1, .LANCHOR1
-.LVL36:
- add x1, x1, :lo12:.LANCHOR1
- .loc 3 16 0
- stp x19, x20, [sp, 16]
- stp x25, x26, [sp, 64]
- .cfi_offset 19, -96
- .cfi_offset 20, -88
- .cfi_offset 25, -48
- .cfi_offset 26, -40
- .loc 3 16 0
- mov x25, x0
- .loc 3 19 0
- add x0, x29, 80
-.LVL37:
- bl memcpy
-.LVL38:
- .loc 3 24 0
- adrp x0, .LC6
- add x0, x0, :lo12:.LC6
- bl printf
-.LVL39:
- .loc 3 25 0
- bl get_page_size
-.LVL40:
- sxtw x19, w0
-.LVL41:
- .loc 3 27 0
- tbz w19, #31, .L28
- .loc 3 28 0
- mov w1, w19
- adrp x0, .LC7
- add x0, x0, :lo12:.LC7
- bl printf
-.LVL42:
- .loc 3 29 0
- mov w0, -1
-.L31:
-.LVL43:
-.L27:
- .loc 3 64 0
- ldp x19, x20, [sp, 16]
-.LVL44:
- ldp x21, x22, [sp, 32]
- ldp x23, x24, [sp, 48]
- ldp x25, x26, [sp, 64]
-.LVL45:
- ldp x29, x30, [sp], 112
- .cfi_remember_state
- .cfi_restore 30
- .cfi_restore 29
- .cfi_restore 25
- .cfi_restore 26
- .cfi_restore 23
- .cfi_restore 24
- .cfi_restore 21
- .cfi_restore 22
- .cfi_restore 19
- .cfi_restore 20
- .cfi_def_cfa 31, 0
- ret
-.LVL46:
-.L28:
- .cfi_restore_state
- .loc 3 40 0
- lsr x22, x22, 1
-.LVL47:
- add x23, x25, x23
-.LVL48:
- mov w21, 0
- mov x20, 0
- .loc 3 37 0
- mov w1, 32
- add x0, x29, 80
- bl data_cpu_2_io
-.LVL49:
- .loc 3 39 0
- mov x2, 32
- add x1, x29, 80
- mov x0, x25
- bl memcpy
-.LVL50:
-.L30:
- .loc 3 40 0 discriminator 1
- cmp x20, x22
- bcc .L34
- mov x0, 0
-.LVL51:
- .loc 3 63 0
- b .L27
-.LVL52:
-.L34:
- .loc 3 41 0
- uxtw x24, w21
- mov x2, 32
- sub x26, x23, x24
- add x1, x29, 80
- mov x0, x26
- bl memcpy
-.LVL53:
- .loc 3 44 0
- add x2, x20, x25
- .loc 3 43 0
- mov x3, 32
- mov w4, 1
- add x2, x2, x24
- mov w1, w3
- add x0, x29, 80
- bl cmp_buf_data
-.LVL54:
- .loc 3 45 0
- cbnz x0, .L27
- .loc 3 48 0
- add x24, x24, 40
- add x20, x20, x19
-.LVL55:
- cmp x19, x24
- add w21, w21, 8
-.LVL56:
- csel w21, w21, wzr, cs
-.LVL57:
- .loc 3 50 0
- cmp x22, x20
- bls .L33
- .loc 3 51 0
- add x0, x25, x20
-.LVL58:
- mov x2, 32
- add x1, x29, 80
- add x0, x0, x21, uxtw
- bl memcpy
-.LVL59:
-.L33:
- .loc 3 53 0
- mov x3, 32
- mov w4, 1
- mov x2, x26
- mov w1, w3
- add x0, x29, 80
- sub x23, x23, x19
- bl cmp_buf_data
-.LVL60:
- .loc 3 56 0
- cbz x0, .L30
- b .L27
- .cfi_endproc
-.LFE268:
- .size diagonalscan, .-diagonalscan
- .section .text.random_test,"ax",@progbits
- .align 2
- .global random_test
- .type random_test, %function
-random_test:
-.LFB271:
- .file 4 "cmd/ddr_tool/random_test.c"
- .loc 4 97 0
- .cfi_startproc
-.LVL61:
- stp x29, x30, [sp, -112]!
- .cfi_def_cfa_offset 112
- .cfi_offset 29, -112
- .cfi_offset 30, -104
-.LBB6:
-.LBB7:
- .loc 4 19 0
- mov x2, x1
-.LBE7:
-.LBE6:
- .loc 4 97 0
- add x29, sp, 0
- .cfi_def_cfa_register 29
- stp x19, x20, [sp, 16]
- .cfi_offset 19, -96
- .cfi_offset 20, -88
- mov x20, x1
- stp x21, x22, [sp, 32]
- mov x19, x0
-.LVL62:
- stp x23, x24, [sp, 48]
-.LBB12:
-.LBB8:
- .loc 4 19 0
- mov w1, -2139062144
-.LVL63:
-.LBE8:
-.LBE12:
- .loc 4 97 0
- stp x27, x28, [sp, 80]
- .cfi_offset 21, -80
- .cfi_offset 22, -72
- .cfi_offset 23, -64
- .cfi_offset 24, -56
- .cfi_offset 27, -32
- .cfi_offset 28, -24
-.LBB13:
-.LBB9:
- .loc 4 24 0
- adrp x24, .LC8
-.LBE9:
-.LBE13:
- .loc 4 97 0
- stp x25, x26, [sp, 64]
- .cfi_offset 25, -48
- .cfi_offset 26, -40
-.LBB14:
-.LBB10:
- .loc 4 19 0
- bl memset
-.LVL64:
- .loc 4 25 0
- lsr x0, x20, 2
- .loc 4 24 0
- add x24, x24, :lo12:.LC8
- .loc 4 25 0
- str x0, [x29, 104]
- .loc 4 15 0
- mov w27, 0
- .loc 4 41 0
- adrp x0, .LC9
- .loc 4 21 0
- mov w23, 1077952576
- .loc 4 41 0
- add x0, x0, :lo12:.LC9
- .loc 4 20 0
- mov w21, -2139062144
- .loc 4 23 0
- mov w22, 0
- .loc 4 41 0
- str x0, [x29, 96]
-.LVL65:
-.L43:
- .loc 4 24 0
- mov w1, w22
- mov x0, x24
- bl printf
-.LVL66:
- .loc 4 25 0
- mov w1, 0
-.LVL67:
-.L38:
- ldr x2, [x29, 104]
- uxtw x0, w1
- cmp x0, x2
- bcc .L42
-.LVL68:
-.L41:
- .loc 4 41 0
- ldr x0, [x29, 96]
- .loc 4 23 0
- add w22, w22, 1
-.LVL69:
- .loc 4 39 0
- lsr w23, w23, 1
-.LVL70:
- .loc 4 40 0
- lsr w21, w21, 1
-.LVL71:
- .loc 4 41 0
- bl printf
-.LVL72:
- .loc 4 23 0
- cmp w22, 8
- bne .L43
- mov x28, -1
- b .L40
-.LVL73:
-.L42:
- .loc 4 26 0
- lsl x0, x0, 2
- add x5, x19, x0
- ldr w26, [x19, x0]
- .loc 4 27 0
- cmp w26, w21
- beq .L39
- .loc 4 28 0
- mov x28, x5
-.LVL74:
- .loc 4 29 0
- add x1, x5, 4
-.LVL75:
- mov x0, x5
- bl flush_dcache_range
-.LVL76:
- .loc 4 37 0
- cmn x28, #1
- .loc 4 32 0
- ldr w27, [x28]
- .loc 4 37 0
- beq .L41
-.LVL77:
-.L40:
- .loc 4 43 0
- adrp x0, .LC10
- add x0, x0, :lo12:.LC10
- bl printf
-.LVL78:
- .loc 4 44 0
- cmn x28, #1
- beq .L44
- .loc 4 45 0
- adrp x0, .LC11
- mov w4, w21
- mov w3, w27
- mov w2, w26
- mov x1, x28
- add x0, x0, :lo12:.LC11
- bl printf
-.LVL79:
-.L57:
-.LBE10:
-.LBE14:
-.LBB15:
-.LBB16:
- .loc 4 91 0
- mov w0, -1
-.L37:
-.LBE16:
-.LBE15:
- .loc 4 105 0
- ldp x19, x20, [sp, 16]
-.LVL80:
- ldp x21, x22, [sp, 32]
- ldp x23, x24, [sp, 48]
- ldp x25, x26, [sp, 64]
- ldp x27, x28, [sp, 80]
- ldp x29, x30, [sp], 112
- .cfi_remember_state
- .cfi_restore 30
- .cfi_restore 29
- .cfi_restore 27
- .cfi_restore 28
- .cfi_restore 25
- .cfi_restore 26
- .cfi_restore 23
- .cfi_restore 24
- .cfi_restore 21
- .cfi_restore 22
- .cfi_restore 19
- .cfi_restore 20
- .cfi_def_cfa 31, 0
- ret
-.LVL81:
-.L39:
- .cfi_restore_state
-.LBB18:
-.LBB11:
- .loc 4 35 0
- str w23, [x19, x0]
- .loc 4 25 0
- add w1, w1, 1
-.LVL82:
- b .L38
-.LVL83:
-.L44:
-.LBE11:
-.LBE18:
-.LBB19:
-.LBB17:
- .loc 4 64 0
- adrp x26, .LC12
- .loc 4 84 0
- adrp x24, .LC13
- .loc 4 72 0
- lsr x28, x20, 3
- .loc 4 64 0
- add x26, x26, :lo12:.LC12
- .loc 4 84 0
- add x24, x24, :lo12:.LC13
- .loc 4 72 0
- mov x27, 0
- mov x21, 0
-.LVL84:
-.L51:
- .loc 4 64 0
- mov x1, x21
- mov x0, x26
- bl printf
-.LVL85:
- .loc 4 66 0
- lsl x22, x21, 24
- lsl x0, x21, 8
- orr x22, x22, x21, lsl 32
- orr x0, x0, x21, lsl 16
- .loc 4 70 0
- mov x2, x20
- .loc 4 66 0
- orr x22, x22, x0
- lsl x0, x21, 40
- orr x0, x0, x21, lsl 48
- orr x22, x22, x0
- orr x0, x21, x21, lsl 56
- orr x22, x22, x0
-.LVL86:
- .loc 4 70 0
- mov x0, x19
- mov w1, w22
- bl memset
-.LVL87:
- .loc 4 72 0
- mov x0, 0
-.LVL88:
-.L46:
- cmp x0, x28
- bne .L50
-.LVL89:
-.L49:
- .loc 4 84 0
- mov x0, x24
- .loc 4 63 0
- add x21, x21, 1
-.LVL90:
- .loc 4 84 0
- bl printf
-.LVL91:
- .loc 4 63 0
- cmp x21, 256
- bne .L51
- mov x23, -1
- b .L48
-.LVL92:
-.L50:
- lsl x1, x0, 3
- add x23, x1, x19
- .loc 4 73 0
- ldr x25, [x1, x19]
-.LVL93:
- .loc 4 74 0
- cmp x22, x25
- beq .L47
-.LVL94:
- .loc 4 76 0
- add x1, x23, 4
- mov x0, x23
-.LVL95:
- bl flush_dcache_range
-.LVL96:
- .loc 4 78 0
- ldr x27, [x23]
-.LVL97:
- .loc 4 82 0
- cmn x23, #1
- beq .L49
-.LVL98:
-.L48:
- .loc 4 86 0
- adrp x0, .LC14
- add x0, x0, :lo12:.LC14
- bl printf
-.LVL99:
- .loc 4 93 0
- mov w0, 0
- .loc 4 87 0
- cmn x23, #1
- beq .L37
- .loc 4 88 0
- mov x4, x22
- mov x3, x27
- mov x2, x25
- mov x1, x23
- adrp x0, .LC15
- add x0, x0, :lo12:.LC15
- bl printf
-.LVL100:
- b .L57
-.LVL101:
-.L47:
- .loc 4 72 0
- add x0, x0, 1
-.LVL102:
- b .L46
-.LBE17:
-.LBE19:
- .cfi_endproc
-.LFE271:
- .size random_test, .-random_test
- .section .text.scan_freq,"ax",@progbits
- .align 2
- .type scan_freq, %function
-scan_freq:
-.LFB255:
- .loc 2 55 0
- .cfi_startproc
-.LVL103:
- stp x29, x30, [sp, -80]!
- .cfi_def_cfa_offset 80
- .cfi_offset 29, -80
- .cfi_offset 30, -72
- add x29, sp, 0
- .cfi_def_cfa_register 29
- stp x19, x20, [sp, 16]
- .cfi_offset 19, -64
- .cfi_offset 20, -56
- mov w19, w0
- stp x21, x22, [sp, 32]
- .loc 2 61 0
- mov w0, 16960
-.LVL104:
- .loc 2 55 0
- stp x23, x24, [sp, 48]
- .loc 2 61 0
- movk w0, 0xf, lsl 16
- .loc 2 55 0
- stp x25, x26, [sp, 64]
- .cfi_offset 21, -48
- .cfi_offset 22, -40
- .cfi_offset 23, -32
- .cfi_offset 24, -24
- .cfi_offset 25, -16
- .cfi_offset 26, -8
- .loc 2 55 0
- mov x22, x2
- .loc 2 61 0
- cmp w19, w0
- bls .L59
- .loc 2 62 0
- udiv w19, w19, w0
-.LVL105:
-.L59:
- .loc 2 63 0
- cmp w1, w0
- bls .L60
- .loc 2 64 0
- udiv w1, w1, w0
-.LVL106:
-.L60:
- .loc 2 66 0
- cmp w19, w1
- bls .L61
- mov w0, w19
- mov w19, w1
-.LVL107:
- mov w1, w0
-.LVL108:
-.L61:
- .loc 2 75 0
- mov w25, 16960
- adrp x24, .LC16
- .loc 2 71 0
- sub w21, w1, w19
-.LVL109:
- .loc 2 75 0
- add x24, x24, :lo12:.LC16
- .loc 2 73 0
- mov w23, 0
- .loc 2 75 0
- movk w25, 0xf, lsl 16
-.LVL110:
-.L62:
- .loc 2 73 0 discriminator 1
- cmp x22, x23, uxtw
- bhi .L66
- .loc 2 73 0 is_stmt 0 discriminator 3
- cbnz x22, .L67
-.L66:
- .loc 2 74 0 is_stmt 1
- bl rand
-.LVL111:
- udiv w20, w0, w21
- .loc 2 75 0
- mov w1, w23
- .loc 2 74 0
- msub w20, w20, w21, w0
- .loc 2 75 0
- mov x0, x24
-.LVL112:
- .loc 2 74 0
- add w20, w20, w19
- .loc 2 75 0
- mul w20, w20, w25
- mov w2, w20
- bl printf
-.LVL113:
- .loc 2 76 0
- and x0, x20, 4294967232
- bl set_ddr_freq
-.LVL114:
- mov w26, w0
-.LVL115:
- .loc 2 79 0
- ldr x0, [x18]
-.LVL116:
- mov x1, 1048576
- ldr x0, [x0, 136]
- bl random_test
-.LVL117:
- mov w20, w0
-.LVL118:
- .loc 2 80 0
- cbz w0, .L63
- .loc 2 81 0
- adrp x0, .LC17
-.LVL119:
- mov w1, w26
- add x0, x0, :lo12:.LC17
- bl printf
-.LVL120:
-.L58:
- .loc 2 91 0
- mov w0, w20
- ldp x19, x20, [sp, 16]
-.LVL121:
- ldp x21, x22, [sp, 32]
-.LVL122:
- ldp x23, x24, [sp, 48]
-.LVL123:
- ldp x25, x26, [sp, 64]
- ldp x29, x30, [sp], 80
- .cfi_remember_state
- .cfi_restore 30
- .cfi_restore 29
- .cfi_restore 25
- .cfi_restore 26
- .cfi_restore 23
- .cfi_restore 24
- .cfi_restore 21
- .cfi_restore 22
- .cfi_restore 19
- .cfi_restore 20
- .cfi_def_cfa 31, 0
- ret
-.LVL124:
-.L63:
- .cfi_restore_state
- .loc 2 84 0
- bl ctrlc
-.LVL125:
- cbz w0, .L65
-.LVL126:
-.L67:
- .loc 2 73 0
- mov w20, 0
- b .L58
-.LVL127:
-.L65:
- .loc 2 73 0 is_stmt 0 discriminator 2
- add w23, w23, 1
-.LVL128:
- b .L62
- .cfi_endproc
-.LFE255:
- .size scan_freq, .-scan_freq
- .section .text.do_ddr_test,"ax",@progbits
- .align 2
- .type do_ddr_test, %function
-do_ddr_test:
-.LFB256:
- .loc 2 100 0 is_stmt 1
- .cfi_startproc
-.LVL129:
- stp x29, x30, [sp, -224]!
- .cfi_def_cfa_offset 224
- .cfi_offset 29, -224
- .cfi_offset 30, -216
- .loc 2 113 0
- adrp x0, .LC18
-.LVL130:
- add x0, x0, :lo12:.LC18
- .loc 2 100 0
- add x29, sp, 0
- .cfi_def_cfa_register 29
- stp x19, x20, [sp, 16]
- .cfi_offset 19, -208
- .cfi_offset 20, -200
- .loc 2 115 0
- add x20, x29, 152
- .loc 2 100 0
- stp x21, x22, [sp, 32]
- .cfi_offset 21, -192
- .cfi_offset 22, -184
- .loc 2 115 0
- add x21, x29, 120
- .loc 2 100 0
- stp x23, x24, [sp, 48]
- .cfi_offset 23, -176
- .cfi_offset 24, -168
- mov w23, w2
- stp x25, x26, [sp, 64]
- .cfi_offset 25, -160
- .cfi_offset 26, -152
- mov x26, x3
- stp x27, x28, [sp, 80]
- .cfi_offset 27, -144
- .cfi_offset 28, -136
- .loc 2 103 0
- stp xzr, xzr, [x29, 184]
- stp xzr, xzr, [x29, 200]
- str xzr, [x29, 216]
-.LVL131:
- .loc 2 113 0
- bl printf
-.LVL132:
- .loc 2 115 0
- mov w2, 1
- mov x1, x20
- mov x0, x21
- bl get_print_available_addr
-.LVL133:
- .loc 2 117 0
- cmp w23, 1
- ble .L160
- .loc 2 121 0
- adrp x24, .LANCHOR2
- add x27, x24, :lo12:.LANCHOR2
- mov x25, 0
- str x24, [x29, 104]
-.L75:
- ldr x1, [x27, x25, lsl 3]
- mov w19, w25
-.LVL134:
- ldr x0, [x26, 8]
- bl strcasecmp
-.LVL135:
- cbz w0, .L74
-.LVL136:
- add x25, x25, 1
- .loc 2 120 0 discriminator 2
- cmp x25, 7
- bne .L75
- .loc 2 128 0
- adrp x0, .LC27
- add x0, x0, :lo12:.LC27
- b .L161
-.LVL137:
-.L112:
- .loc 2 133 0
- adrp x0, .LC19
- add x0, x0, :lo12:.LC19
-.LVL138:
-.L161:
- .loc 2 128 0
- bl printf
-.LVL139:
-.L160:
- .loc 2 129 0
- mov w23, -1
- b .L72
-.LVL140:
-.L78:
- .loc 2 138 0
- add x0, x26, x27
- add x1, x29, 184
- add x2, x1, x27
- mov w1, 0
- add x27, x27, 8
- ldr x0, [x0, 16]
- bl strict_strtoul
-.LVL141:
- tbz w0, #31, .L77
- .loc 2 139 0
- adrp x0, .LC20
- add x0, x0, :lo12:.LC20
- b .L161
-.LVL142:
-.L79:
- .loc 2 157 0
- bl data_cpu_2_io_init
-.LVL143:
- .loc 2 159 0
- cbnz w19, .L80
- .loc 2 161 0
- ldr x0, [x29, 192]
- cbz x0, .L81
- .loc 2 162 0
- bl set_vdd_logic
-.LVL144:
-.L81:
- .loc 2 163 0
- ldr x0, [x29, 184]
- bl set_ddr_freq
-.LVL145:
-.L82:
- .loc 2 305 0
- adrp x0, .LC26
- add x0, x0, :lo12:.LC26
- bl printf
-.LVL146:
- b .L72
-.LVL147:
-.L80:
- .loc 2 164 0
- cmp w19, 1
- bne .L83
- .loc 2 166 0
- ldr x0, [x29, 208]
- cbz x0, .L84
- .loc 2 167 0
- bl set_vdd_logic
-.LVL148:
-.L84:
- .loc 2 168 0
- ldr w0, [x29, 184]
- ldr w1, [x29, 192]
- ldr x2, [x29, 200]
- bl scan_freq
-.LVL149:
- b .L82
-.L83:
- .loc 2 169 0
- sub w25, w25, #5
- cmp w25, 1
- bhi .L85
- .loc 2 171 0
- ldr x0, [x29, 208]
- cbz x0, .L86
- .loc 2 172 0
- bl set_vdd_logic
-.LVL150:
-.L86:
- .loc 2 173 0
- cmp w19, 5
- bne .L114
- .loc 2 175 0
- mov x1, 65535
- mov x0, 0
- movk x1, 0x9f, lsl 16
-.L90:
-.LVL151:
- ldr x2, [x20, x0, lsl 3]
- cmp x2, x1
- bls .L88
- .loc 2 176 0
- mov w1, w0
-.LVL152:
- .loc 2 185 0
- mov x2, 10485760
- str x2, [x20, w0, uxtw 3]
-.LVL153:
-.L89:
- .loc 2 108 0 discriminator 1
- mov x0, 0
-.LVL154:
-.L93:
- .loc 2 188 0
- cmp w1, w0
- beq .L92
- .loc 2 190 0
- str xzr, [x21, x0, lsl 3]
- .loc 2 191 0
- str xzr, [x20, x0, lsl 3]
-.L92:
-.LVL155:
- add x0, x0, 1
-.LVL156:
- .loc 2 187 0 discriminator 2
- cmp x0, 4
- bne .L93
- .loc 2 193 0
- mov w28, 60
-.L87:
-.LVL157:
- .loc 2 201 0
- adrp x26, .LC22
-.LVL158:
- .loc 2 205 0
- adrp x27, .LC23
- .loc 2 201 0
- add x26, x26, :lo12:.LC22
- .loc 2 205 0
- add x27, x27, :lo12:.LC23
- .loc 2 198 0
- mov w25, 0
-.LVL159:
-.L94:
- .loc 2 199 0
- ldr x0, [x29, 200]
- cbz x0, .L100
- .loc 2 199 0 is_stmt 0 discriminator 1
- cmp x0, x25, uxtw
- bls .L82
-.L100:
- .loc 2 201 0 is_stmt 1
- mov x19, 0
- .loc 2 200 0
- add w25, w25, 1
-.LVL160:
- .loc 2 201 0
- mov w1, w25
- mov x0, x26
- bl printf
-.LVL161:
-.L98:
- .loc 2 203 0
- ldr x3, [x20, x19, lsl 3]
- cbz x3, .L95
- .loc 2 205 0
- ldr x2, [x21, x19, lsl 3]
- mov w1, w19
- mov x0, x27
- bl printf
-.LVL162:
- .loc 2 207 0
- ldr x0, [x29, 192]
- bl set_ddr_freq
-.LVL163:
- .loc 2 208 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
- bl random_test
-.LVL164:
- mov w24, w0
-.LVL165:
- .loc 2 210 0
- cbnz w0, .L115
- .loc 2 211 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
-.LVL166:
- bl crosstalk
-.LVL167:
- mov w24, w0
-.LVL168:
- .loc 2 215 0
- cbnz w0, .L116
- .loc 2 216 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
-.LVL169:
- bl diagonalscan
-.LVL170:
- mov w24, w0
-.LVL171:
- .loc 2 220 0
- cbnz w0, .L117
- .loc 2 221 0
- ldr w0, [x29, 184]
-.LVL172:
- and x2, x28, 1020
- ldr w1, [x29, 192]
- .loc 2 224 0
- mov w22, 1
- .loc 2 221 0
- bl scan_freq
-.LVL173:
- mov w24, w0
-.LVL174:
-.L96:
- .loc 2 226 0
- ldr x0, [x29, 184]
-.LVL175:
- bl set_ddr_freq
-.LVL176:
- .loc 2 227 0
- cbnz w24, .L118
- .loc 2 228 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
- bl random_test
-.LVL177:
- mov w2, w0
-.LVL178:
- .loc 2 232 0
- cbnz w0, .L119
- .loc 2 233 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
-.LVL179:
- str w2, [x29, 100]
- bl crosstalk
-.LVL180:
- mov w22, w0
-.LVL181:
- .loc 2 237 0
- ldr w2, [x29, 100]
- cbnz w0, .L120
- .loc 2 238 0
- ldr x1, [x20, x19, lsl 3]
- ldr x0, [x21, x19, lsl 3]
-.LVL182:
- bl diagonalscan
-.LVL183:
- mov w24, w0
-.LVL184:
- .loc 2 243 0
- cbnz w0, .L121
- .loc 2 245 0
- bl ctrlc
-.LVL185:
- cbnz w0, .L122
- .loc 2 240 0
- mov w22, 4
-.LVL186:
-.L95:
- add x19, x19, 1
-.LVL187:
- .loc 2 202 0 discriminator 2
- cmp x19, 4
- bne .L98
- mov w2, 0
- mov w24, 0
-.LVL188:
-.L97:
- .loc 2 250 0
- orr w2, w24, w2
-.LVL189:
- cbz w2, .L94
-.LVL190:
-.L99:
- .loc 2 302 0
- cbz w24, .L82
- .loc 2 303 0
- ldr x0, [x29, 104]
- add x24, x0, :lo12:.LANCHOR2
-.LVL191:
- adrp x0, .LC25
- add x0, x0, :lo12:.LC25
- ldr x1, [x24, w22, sxtw 3]
- bl printf
-.LVL192:
- b .L72
-.LVL193:
-.L88:
- add x0, x0, 1
-.LVL194:
- .loc 2 174 0 discriminator 2
- cmp x0, 4
- bne .L90
- .loc 2 181 0
- ldr x2, [x29, 152]
- mov w1, 10
- adrp x0, .LC28
- add x0, x0, :lo12:.LC28
- lsr x2, x2, 20
- bl printf
-.LVL195:
- .loc 2 108 0
- mov w1, 0
- b .L89
-.L114:
- .loc 2 195 0
- mov w28, 1000
- b .L87
-.LVL196:
-.L115:
- .loc 2 209 0
- mov w22, 2
- b .L96
-.LVL197:
-.L116:
- .loc 2 213 0
- mov w22, 3
- b .L96
-.LVL198:
-.L117:
- .loc 2 218 0
- mov w22, 4
- b .L96
-.LVL199:
-.L118:
- mov w2, 0
- b .L97
-.LVL200:
-.L119:
- .loc 2 228 0
- mov w24, w0
- mov w2, 0
- .loc 2 230 0
- mov w22, 2
- b .L97
-.LVL201:
-.L120:
- .loc 2 233 0
- mov w24, w0
- .loc 2 235 0
- mov w22, 3
- b .L97
-.LVL202:
-.L121:
- mov w2, w22
-.LVL203:
-.L158:
- .loc 2 240 0
- mov w22, 4
- b .L97
-.L122:
- .loc 2 246 0
- mov w2, -1
- b .L158
-.LVL204:
-.L85:
- .loc 2 259 0
- mov x2, x20
- mov x1, x21
- add x0, x29, 200
- bl judge_test_addr
-.LVL205:
- mov w27, w0
-.LVL206:
- .loc 2 260 0
- cbz w0, .L123
- .loc 2 263 0
- ldr x0, [x29, 184]
-.LVL207:
- bl set_ddr_freq
-.LVL208:
- .loc 2 265 0
- ldr x0, [x29, 216]
- cbz x0, .L102
- .loc 2 266 0
- bl set_vdd_logic
-.LVL209:
-.L102:
- .loc 2 270 0
- adrp x26, .LC24
-.LVL210:
- mov w25, 0
- add x26, x26, :lo12:.LC24
- b .L110
-.LVL211:
-.L111:
- .loc 2 271 0
- mov x28, 0
- .loc 2 269 0
- add w25, w25, 1
-.LVL212:
- .loc 2 270 0
- mov w1, w25
- mov x0, x26
- bl printf
-.LVL213:
-.L103:
- .loc 2 271 0 discriminator 1
- cmp w27, w28
- bhi .L109
- mov w0, 0
- mov w24, 0
-.LVL214:
-.L108:
- .loc 2 297 0
- orr w0, w24, w0
-.LVL215:
- cbnz w0, .L99
-.LVL216:
-.L110:
- .loc 2 268 0
- ldr x0, [x29, 192]
- cbz x0, .L111
- .loc 2 268 0 is_stmt 0 discriminator 1
- cmp x0, x25, uxtw
- bhi .L111
- b .L82
-.LVL217:
-.L109:
- .loc 2 278 0 is_stmt 1
- ldr x1, [x20, x28, lsl 3]
- .loc 2 272 0
- cmp w19, 3
- .loc 2 278 0
- ldr x0, [x21, x28, lsl 3]
- .loc 2 272 0
- beq .L105
- cmp w19, 4
- beq .L106
- .loc 2 274 0
- bl random_test
-.LVL218:
-.L159:
- .loc 2 282 0
- mov w24, w0
-.LVL219:
- .loc 2 290 0
- bl ctrlc
-.LVL220:
- cbnz w0, .L124
- add x28, x28, 1
-.LVL221:
- mov w22, w19
- .loc 2 294 0
- cbz w24, .L103
- mov w22, w19
- b .L108
-.LVL222:
-.L105:
- .loc 2 278 0
- bl crosstalk
-.LVL223:
- b .L159
-.L106:
- .loc 2 282 0
- bl diagonalscan
-.LVL224:
- b .L159
-.LVL225:
-.L124:
- mov w22, w19
- .loc 2 291 0
- mov w0, -1
- b .L108
-.LVL226:
-.L123:
- .loc 2 261 0
- mov w23, 1
-.LVL227:
- b .L72
-.LVL228:
-.L74:
- .loc 2 132 0
- adrp x0, .LANCHOR3
- add x0, x0, :lo12:.LANCHOR3
- ldrb w0, [x0, w25, sxtw]
- cmp w23, w0
- blt .L112
- sub w23, w23, #2
-.LVL229:
- .loc 2 132 0 is_stmt 0 discriminator 1
- mov x27, 0
- lsl x23, x23, 3
-.LVL230:
-.L77:
- .loc 2 137 0 is_stmt 1 discriminator 1
- cmp x27, x23
- bne .L78
- .loc 2 147 0
- add x2, x29, 112
- mov w1, 0
- mov w0, 53
- bl uclass_get_device
-.LVL231:
- mov w23, w0
-.LVL232:
- .loc 2 148 0
- cbz w0, .L79
- .loc 2 149 0
- mov w1, w0
- adrp x0, .LC21
-.LVL233:
- add x0, x0, :lo12:.LC21
- bl printf
-.LVL234:
-.L72:
- .loc 2 308 0
- mov w0, w23
- ldp x19, x20, [sp, 16]
- ldp x21, x22, [sp, 32]
- ldp x23, x24, [sp, 48]
- ldp x25, x26, [sp, 64]
- ldp x27, x28, [sp, 80]
- ldp x29, x30, [sp], 224
- .cfi_restore 30
- .cfi_restore 29
- .cfi_restore 27
- .cfi_restore 28
- .cfi_restore 25
- .cfi_restore 26
- .cfi_restore 23
- .cfi_restore 24
- .cfi_restore 21
- .cfi_restore 22
- .cfi_restore 19
- .cfi_restore 20
- .cfi_def_cfa 31, 0
- ret
- .cfi_endproc
-.LFE256:
- .size do_ddr_test, .-do_ddr_test
- .global _u_boot_list_2_cmd_2_ddr_test
- .section .rodata
- .align 3
- .set .LANCHOR1,. + 0
-.LC0:
- .word 1437226410
- .word -1437226411
- .word 1515890085
- .word -1515890086
- .word -267448336
- .word 267448335
- .word 0
- .word -1
- .section .rodata.crosstalk.str1.1,"aMS",@progbits,1
-.LC1:
- .string "\nbitflip: \n"
-.LC2:
- .string "\b\b\b%3u"
-.LC3:
- .string "%3u\b\b\b"
-.LC4:
- .string "\nISI:\n"
-.LC5:
- .string "malloc %lu byte fail\n"
- .section .rodata.diagonalscan.str1.1,"aMS",@progbits,1
-.LC6:
- .string "\nDiagonalScan\n"
-.LC7:
- .string "get page size fail:0x%x\n"
- .section .rodata.do_ddr_test.str1.1,"aMS",@progbits,1
-.LC18:
- .string "ddr tester version 1.0.1\n"
-.LC19:
- .string "test parameters error\n"
-.LC20:
- .string "test pattern error\n"
-.LC21:
- .string "rockchip dmc probe fail: %d\n"
-.LC22:
- .string "\rtimes:%08u:\n"
-.LC23:
- .string "loop:%d, start:0x%lx, len:0x%lx\n"
-.LC24:
- .string "\rtimes:%08u, "
-.LC25:
- .string "\n%s test fail\n"
-.LC26:
- .string "\ntest pass\n"
-.LC27:
- .string "test pattern unsupported\n"
-.LC28:
- .string "fasttest need %uMB, but actually only %luMB\n"
- .section .rodata.g_isi_pattern,"a",@progbits
- .align 3
- .set .LANCHOR0,. + 0
- .type g_isi_pattern, %object
- .size g_isi_pattern, 128
-g_isi_pattern:
- .word -1
- .word 0
- .word -1
- .word 0
- .word -1
- .word 0
- .word -1
- .word -1
- .word -1
- .word -1
- .word 0
- .word -1
- .word -1
- .word -1
- .word -1
- .word 0
- .word -1
- .word 0
- .word -1
- .word 0
- .word -1
- .word 0
- .word 0
- .word 0
- .word 0
- .word -1
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .section .rodata.random_test.str1.1,"aMS",@progbits,1
-.LC8:
- .string "%u"
-.LC9:
- .string "\b"
-.LC10:
- .string " "
-.LC11:
- .string "\nrandom test1 fail:address:0x%lx,read:0x%x,reread:0x%x,expect:0x%x\n"
-.LC12:
- .string "%4lu"
-.LC13:
- .string "\b\b\b\b"
-.LC14:
- .string " "
-.LC15:
- .string "\nrandom test2 fail:address:0x%lx,read:0x%lx,reread:0x%lx,expect:0x%lx\n"
- .section .rodata.scan_freq.str1.1,"aMS",@progbits,1
-.LC16:
- .string "% d:change freq to %d Hz\n"
-.LC17:
- .string "check data fail at %d Hz\n"
- .section .rodata.str1.1,"aMS",@progbits,1
-.LC29:
- .string "ddr_test"
-.LC30:
- .string "for dram simple test\n"
-.LC31:
- .ascii "arg1: test pattern include:\n\tchangefreq\n\tscanfreq\n\tran"
- .ascii "dom\n\tcrosstalk\n\tdiagonalscan\n\tfast_test\n\tfull_test\n"
- .ascii "for changereq: arg2:freq(Hz),arg3[option]:volt\nfor scanfreq"
- .ascii ": arg2:minfreq(Hz),arg3:maxfreq(Hz),\n\targ4:scanfreq times,"
- .ascii " arg5[option]:volt\nfor random, crosstalk and diagonalscan:a"
- .ascii "rg2:freq(Hz), arg3:test times,\n\targ4: start addr, arg5:len"
- .ascii "gth, arg6[option]:volt\nfor fast_test and full_test:arg2: mi"
- .ascii "n_freq(Hz), arg3: max_freq(Hz)\n\targ4: test times, arg5[opt"
- .ascii "ion]:volt\n\nfreq: means dram's target frequency,unit:Hz, if"
- .ascii " 0:keep current freq\nminfreq, maxfreq: means min and max fr"
- .ascii "equency for dram test,unit:Hz\ntest times: test loop, if 0: "
- .ascii "endless loop\nstart_adr: start address of memory space for t"
- .ascii "esting,unit:physical address\nlength: length of memory space"
- .ascii " for testing,unit:Byte, if 0: full memory space test\nvolt: "
- .ascii "means target voltage of vdd_logic\n\nexample:\nddr freq chan"
- .ascii "ge to:786MHz, vdd_logic:1.05v:\n\t 'ddr_test changefreq 7860"
- .ascii "00000 1050000'\nddr freq change to:786MHz, with default vdd_"
- .ascii "logic:\n\t 'ddr_test changefreq 786000000'\nscanning ddr fre"
- .ascii "quency between 200 and 786MHz for 10 times:\n\t 'ddr_test sc"
- .ascii "anfreq 200000000 786000000 100'\ndoing random test 10 times "
- .ascii "start from"
- .string " physical address 0x200000 and\nlength is 128MB, freq:786MHz, if freq=0 may keep current freq:\n\t 'ddr_test random 786000000 10 0x200000 0x8000000'\ndoing fast test for dram between 200MHz to 786MHz with 10 times:\n\t 'ddr_test fast_test 200000000 786000000 10'"
-.LC32:
- .string "changefreq"
-.LC33:
- .string "scanfreq"
-.LC34:
- .string "random"
-.LC35:
- .string "crosstalk"
-.LC36:
- .string "diagonalscan"
-.LC37:
- .string "fast_test"
-.LC38:
- .string "full_test"
- .section .rodata.test_pat_param,"a",@progbits
- .align 3
- .set .LANCHOR3,. + 0
- .type test_pat_param, %object
- .size test_pat_param, 7
-test_pat_param:
- .byte 3
- .byte 5
- .byte 6
- .byte 6
- .byte 6
- .byte 5
- .byte 5
- .section .rodata.test_pattern,"a",@progbits
- .align 3
- .set .LANCHOR2,. + 0
- .type test_pattern, %object
- .size test_pattern, 56
-test_pattern:
- .xword .LC32
- .xword .LC33
- .xword .LC34
- .xword .LC35
- .xword .LC36
- .xword .LC37
- .xword .LC38
- .section .u_boot_list_2_cmd_2_ddr_test,"aw",@progbits
- .align 2
- .type _u_boot_list_2_cmd_2_ddr_test, %object
- .size _u_boot_list_2_cmd_2_ddr_test, 48
-_u_boot_list_2_cmd_2_ddr_test:
- .8byte .LC29
- .word 7
- .word 1
- .8byte do_ddr_test
- .8byte .LC30
- .8byte .LC31
- .8byte 0
- .text
-.Letext0:
- .file 5 "include/common.h"
- .file 6 "./arch/arm/include/asm/types.h"
- .file 7 "include/linux/types.h"
- .file 8 "include/errno.h"
- .file 9 "include/linux/string.h"
- .file 10 "include/efi.h"
- .file 11 "include/dm/device.h"
- .file 12 "include/ide.h"
- .file 13 "include/linux/list.h"
- .file 14 "include/part.h"
- .file 15 "include/flash.h"
- .file 16 "include/lmb.h"
- .file 17 "include/asm-generic/u-boot.h"
- .file 18 "./arch/arm/include/asm/u-boot-arm.h"
- .file 19 "include/command.h"
- .file 20 "include/linux/libfdt_env.h"
- .file 21 "include/linux/../../scripts/dtc/libfdt/fdt.h"
- .file 22 "include/linux/libfdt.h"
- .file 23 "include/image.h"
- .file 24 "include/dm/uclass-id.h"
- .file 25 "./arch/arm/include/asm/global_data.h"
- .file 26 "include/asm-generic/global_data.h"
- .file 27 "include/dm/of.h"
- .file 28 "include/net.h"
- .file 29 "include/malloc.h"
- .file 30 "include/dm/ofnode.h"
- .file 31 "include/linux/compat.h"
- .file 32 "include/dm/uclass.h"
- .file 33 "include/console.h"
- .file 34 "include/stdio_dev.h"
- .file 35 "include/iomux.h"
- .file 36 "include/log.h"
- .file 37 "include/stdio.h"
- .file 38 "./arch/arm/include/asm/arch/sdram.h"
- .file 39 "cmd/ddr_tool/../memtester/io_map.h"
- .file 40 "cmd/ddr_tool/../memtester/ddr_tester_common.h"
- .file 41 "include/vsprintf.h"
- .section .debug_info,"",@progbits
-.Ldebug_info0:
- .4byte 0x27ad
- .2byte 0x4
- .4byte .Ldebug_abbrev0
- .byte 0x8
- .uleb128 0x1
- .4byte .LASF478
- .byte 0xc
- .4byte .LASF479
- .4byte .LASF480
- .4byte .Ldebug_ranges0+0x90
- .8byte 0
- .4byte .Ldebug_line0
- .uleb128 0x2
- .4byte .LASF4
- .byte 0x5
- .byte 0xd
- .4byte 0x34
- .uleb128 0x3
- .byte 0x1
- .byte 0x8
- .4byte .LASF0
- .uleb128 0x3
- .byte 0x8
- .byte 0x7
- .4byte .LASF1
- .uleb128 0x4
- .4byte 0x3b
- .uleb128 0x3
- .byte 0x2
- .byte 0x7
- .4byte .LASF2
- .uleb128 0x5
- .4byte .LASF21
- .byte 0x8
- .byte 0xc
- .4byte 0x59
- .uleb128 0x6
- .byte 0x4
- .byte 0x5
- .string "int"
- .uleb128 0x3
- .byte 0x1
- .byte 0x6
- .4byte .LASF3
- .uleb128 0x2
- .4byte .LASF5
- .byte 0x6
- .byte 0xc
- .4byte 0x34
- .uleb128 0x3
- .byte 0x2
- .byte 0x5
- .4byte .LASF6
- .uleb128 0x2
- .4byte .LASF7
- .byte 0x6
- .byte 0x12
- .4byte 0x84
- .uleb128 0x3
- .byte 0x4
- .byte 0x7
- .4byte .LASF8
- .uleb128 0x3
- .byte 0x8
- .byte 0x5
- .4byte .LASF9
- .uleb128 0x3
- .byte 0x8
- .byte 0x7
- .4byte .LASF10
- .uleb128 0x7
- .string "u8"
- .byte 0x6
- .byte 0x1f
- .4byte 0x34
- .uleb128 0x8
- .4byte 0x99
- .uleb128 0x7
- .string "u32"
- .byte 0x6
- .byte 0x25
- .4byte 0x84
- .uleb128 0x4
- .4byte 0xa8
- .uleb128 0x2
- .4byte .LASF11
- .byte 0x6
- .byte 0x31
- .4byte 0x92
- .uleb128 0x2
- .4byte .LASF12
- .byte 0x6
- .byte 0x32
- .4byte 0x92
- .uleb128 0x3
- .byte 0x8
- .byte 0x7
- .4byte .LASF13
- .uleb128 0x9
- .byte 0x8
- .4byte 0xe7
- .uleb128 0x8
- .4byte 0xd5
- .uleb128 0x3
- .byte 0x1
- .byte 0x8
- .4byte .LASF14
- .uleb128 0x8
- .4byte 0xe0
- .uleb128 0x3
- .byte 0x8
- .byte 0x5
- .4byte .LASF15
- .uleb128 0x9
- .byte 0x8
- .4byte 0xe0
- .uleb128 0x8
- .4byte 0xf3
- .uleb128 0x2
- .4byte .LASF16
- .byte 0x7
- .byte 0x59
- .4byte 0x47
- .uleb128 0x2
- .4byte .LASF17
- .byte 0x7
- .byte 0x5b
- .4byte 0x3b
- .uleb128 0x2
- .4byte .LASF18
- .byte 0x7
- .byte 0x69
- .4byte 0x67
- .uleb128 0x2
- .4byte .LASF19
- .byte 0x7
- .byte 0x6b
- .4byte 0x79
- .uleb128 0x2
- .4byte .LASF20
- .byte 0x7
- .byte 0x97
- .4byte 0x79
- .uleb128 0xa
- .byte 0x8
- .uleb128 0x5
- .4byte .LASF22
- .byte 0x9
- .byte 0xb
- .4byte 0xf3
- .uleb128 0x3
- .byte 0x1
- .byte 0x2
- .4byte .LASF23
- .uleb128 0xb
- .4byte 0xe0
- .4byte 0x154
- .uleb128 0xc
- .byte 0
- .uleb128 0xd
- .4byte .LASF24
- .byte 0xa
- .2byte 0x140
- .4byte 0x149
- .uleb128 0xd
- .4byte .LASF25
- .byte 0xa
- .2byte 0x143
- .4byte 0x149
- .uleb128 0xd
- .4byte .LASF26
- .byte 0xa
- .2byte 0x143
- .4byte 0x149
- .uleb128 0xe
- .4byte .LASF45
- .byte 0xa0
- .byte 0xb
- .byte 0x80
- .4byte 0x25d
- .uleb128 0xf
- .4byte .LASF27
- .byte 0xb
- .byte 0x81
- .4byte 0x1517
- .byte 0
- .uleb128 0xf
- .4byte .LASF28
- .byte 0xb
- .byte 0x82
- .4byte 0xd5
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF29
- .byte 0xb
- .byte 0x83
- .4byte 0x135
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF30
- .byte 0xb
- .byte 0x84
- .4byte 0x135
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF31
- .byte 0xb
- .byte 0x85
- .4byte 0x135
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF32
- .byte 0xb
- .byte 0x86
- .4byte 0x14e2
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF33
- .byte 0xb
- .byte 0x87
- .4byte 0x109
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF34
- .byte 0xb
- .byte 0x88
- .4byte 0x25d
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF35
- .byte 0xb
- .byte 0x89
- .4byte 0x135
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF36
- .byte 0xb
- .byte 0x8a
- .4byte 0x155a
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF37
- .byte 0xb
- .byte 0x8b
- .4byte 0x135
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF38
- .byte 0xb
- .byte 0x8c
- .4byte 0x135
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF39
- .byte 0xb
- .byte 0x8d
- .4byte 0x290
- .byte 0x60
- .uleb128 0xf
- .4byte .LASF40
- .byte 0xb
- .byte 0x8e
- .4byte 0x290
- .byte 0x70
- .uleb128 0xf
- .4byte .LASF41
- .byte 0xb
- .byte 0x8f
- .4byte 0x290
- .byte 0x80
- .uleb128 0xf
- .4byte .LASF42
- .byte 0xb
- .byte 0x90
- .4byte 0x11f
- .byte 0x90
- .uleb128 0xf
- .4byte .LASF43
- .byte 0xb
- .byte 0x91
- .4byte 0x59
- .byte 0x94
- .uleb128 0x10
- .string "seq"
- .byte 0xb
- .byte 0x92
- .4byte 0x59
- .byte 0x98
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x178
- .uleb128 0x9
- .byte 0x8
- .4byte 0x269
- .uleb128 0x11
- .uleb128 0xb
- .4byte 0x109
- .4byte 0x275
- .uleb128 0xc
- .byte 0
- .uleb128 0x5
- .4byte .LASF44
- .byte 0xc
- .byte 0x10
- .4byte 0x26a
- .uleb128 0xb
- .4byte 0x34
- .4byte 0x290
- .uleb128 0x12
- .4byte 0xce
- .byte 0x5
- .byte 0
- .uleb128 0xe
- .4byte .LASF46
- .byte 0x10
- .byte 0xd
- .byte 0x16
- .4byte 0x2b5
- .uleb128 0xf
- .4byte .LASF47
- .byte 0xd
- .byte 0x17
- .4byte 0x2b5
- .byte 0
- .uleb128 0xf
- .4byte .LASF48
- .byte 0xd
- .byte 0x17
- .4byte 0x2b5
- .byte 0x8
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x290
- .uleb128 0xe
- .4byte .LASF49
- .byte 0x10
- .byte 0xe
- .byte 0xf
- .4byte 0x2e0
- .uleb128 0xf
- .4byte .LASF28
- .byte 0xe
- .byte 0x10
- .4byte 0xf3
- .byte 0
- .uleb128 0xf
- .4byte .LASF50
- .byte 0xe
- .byte 0x11
- .4byte 0x2f9
- .byte 0x8
- .byte 0
- .uleb128 0x8
- .4byte 0x2bb
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x2f9
- .uleb128 0x14
- .4byte 0x59
- .uleb128 0x14
- .4byte 0x59
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x2e5
- .uleb128 0xb
- .4byte 0x2e0
- .4byte 0x30a
- .uleb128 0xc
- .byte 0
- .uleb128 0x8
- .4byte 0x2ff
- .uleb128 0x5
- .4byte .LASF49
- .byte 0xe
- .byte 0xce
- .4byte 0x30a
- .uleb128 0x15
- .2byte 0x1218
- .byte 0xf
- .byte 0x13
- .4byte 0x361
- .uleb128 0xf
- .4byte .LASF51
- .byte 0xf
- .byte 0x14
- .4byte 0x109
- .byte 0
- .uleb128 0xf
- .4byte .LASF52
- .byte 0xf
- .byte 0x15
- .4byte 0xfe
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF53
- .byte 0xf
- .byte 0x16
- .4byte 0x109
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF54
- .byte 0xf
- .byte 0x17
- .4byte 0x361
- .byte 0x18
- .uleb128 0x16
- .4byte .LASF55
- .byte 0xf
- .byte 0x18
- .4byte 0x372
- .2byte 0x1018
- .byte 0
- .uleb128 0xb
- .4byte 0x109
- .4byte 0x372
- .uleb128 0x17
- .4byte 0xce
- .2byte 0x1ff
- .byte 0
- .uleb128 0xb
- .4byte 0x29
- .4byte 0x383
- .uleb128 0x17
- .4byte 0xce
- .2byte 0x1ff
- .byte 0
- .uleb128 0x2
- .4byte .LASF56
- .byte 0xf
- .byte 0x32
- .4byte 0x31a
- .uleb128 0xb
- .4byte 0x383
- .4byte 0x399
- .uleb128 0xc
- .byte 0
- .uleb128 0x5
- .4byte .LASF57
- .byte 0xf
- .byte 0x34
- .4byte 0x38e
- .uleb128 0x3
- .byte 0x10
- .byte 0x4
- .4byte .LASF58
- .uleb128 0xe
- .4byte .LASF59
- .byte 0x10
- .byte 0x10
- .byte 0x10
- .4byte 0x3d0
- .uleb128 0xf
- .4byte .LASF60
- .byte 0x10
- .byte 0x11
- .4byte 0xb8
- .byte 0
- .uleb128 0xf
- .4byte .LASF51
- .byte 0x10
- .byte 0x12
- .4byte 0xc3
- .byte 0x8
- .byte 0
- .uleb128 0xe
- .4byte .LASF61
- .byte 0xa0
- .byte 0x10
- .byte 0x15
- .4byte 0x401
- .uleb128 0x10
- .string "cnt"
- .byte 0x10
- .byte 0x16
- .4byte 0x3b
- .byte 0
- .uleb128 0xf
- .4byte .LASF51
- .byte 0x10
- .byte 0x17
- .4byte 0xc3
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF62
- .byte 0x10
- .byte 0x18
- .4byte 0x401
- .byte 0x10
- .byte 0
- .uleb128 0xb
- .4byte 0x3ab
- .4byte 0x411
- .uleb128 0x12
- .4byte 0xce
- .byte 0x8
- .byte 0
- .uleb128 0x18
- .string "lmb"
- .2byte 0x140
- .byte 0x10
- .byte 0x1b
- .4byte 0x437
- .uleb128 0xf
- .4byte .LASF63
- .byte 0x10
- .byte 0x1c
- .4byte 0x3d0
- .byte 0
- .uleb128 0xf
- .4byte .LASF64
- .byte 0x10
- .byte 0x1d
- .4byte 0x3d0
- .byte 0xa0
- .byte 0
- .uleb128 0x19
- .string "lmb"
- .byte 0x10
- .byte 0x20
- .4byte 0x411
- .uleb128 0x1a
- .byte 0x10
- .byte 0x11
- .byte 0x5a
- .4byte 0x463
- .uleb128 0xf
- .4byte .LASF54
- .byte 0x11
- .byte 0x5b
- .4byte 0xb8
- .byte 0
- .uleb128 0xf
- .4byte .LASF51
- .byte 0x11
- .byte 0x5c
- .4byte 0xc3
- .byte 0x8
- .byte 0
- .uleb128 0xe
- .4byte .LASF65
- .byte 0xc8
- .byte 0x11
- .byte 0x1b
- .4byte 0x554
- .uleb128 0xf
- .4byte .LASF66
- .byte 0x11
- .byte 0x1c
- .4byte 0x3b
- .byte 0
- .uleb128 0xf
- .4byte .LASF67
- .byte 0x11
- .byte 0x1d
- .4byte 0xc3
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF68
- .byte 0x11
- .byte 0x1e
- .4byte 0x3b
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF69
- .byte 0x11
- .byte 0x1f
- .4byte 0x3b
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF70
- .byte 0x11
- .byte 0x20
- .4byte 0x3b
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF71
- .byte 0x11
- .byte 0x21
- .4byte 0x3b
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF72
- .byte 0x11
- .byte 0x22
- .4byte 0x3b
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF73
- .byte 0x11
- .byte 0x24
- .4byte 0x3b
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF74
- .byte 0x11
- .byte 0x25
- .4byte 0x3b
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF75
- .byte 0x11
- .byte 0x26
- .4byte 0x3b
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF76
- .byte 0x11
- .byte 0x31
- .4byte 0x3b
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF77
- .byte 0x11
- .byte 0x32
- .4byte 0x3b
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF78
- .byte 0x11
- .byte 0x33
- .4byte 0x280
- .byte 0x60
- .uleb128 0xf
- .4byte .LASF79
- .byte 0x11
- .byte 0x34
- .4byte 0x47
- .byte 0x66
- .uleb128 0xf
- .4byte .LASF80
- .byte 0x11
- .byte 0x35
- .4byte 0x3b
- .byte 0x68
- .uleb128 0xf
- .4byte .LASF81
- .byte 0x11
- .byte 0x36
- .4byte 0x3b
- .byte 0x70
- .uleb128 0xf
- .4byte .LASF82
- .byte 0x11
- .byte 0x57
- .4byte 0x109
- .byte 0x78
- .uleb128 0xf
- .4byte .LASF83
- .byte 0x11
- .byte 0x58
- .4byte 0x109
- .byte 0x80
- .uleb128 0xf
- .4byte .LASF84
- .byte 0x11
- .byte 0x5d
- .4byte 0x554
- .byte 0x88
- .byte 0
- .uleb128 0xb
- .4byte 0x442
- .4byte 0x564
- .uleb128 0x12
- .4byte 0xce
- .byte 0x3
- .byte 0
- .uleb128 0x2
- .4byte .LASF85
- .byte 0x11
- .byte 0x5f
- .4byte 0x463
- .uleb128 0x5
- .4byte .LASF86
- .byte 0x12
- .byte 0x13
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF87
- .byte 0x12
- .byte 0x14
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF88
- .byte 0x12
- .byte 0x15
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF89
- .byte 0x12
- .byte 0x16
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF90
- .byte 0x12
- .byte 0x17
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF91
- .byte 0x12
- .byte 0x18
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF92
- .byte 0x12
- .byte 0x19
- .4byte 0x109
- .uleb128 0xe
- .4byte .LASF93
- .byte 0x30
- .byte 0x13
- .byte 0x1e
- .4byte 0x61d
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x13
- .byte 0x1f
- .4byte 0xf3
- .byte 0
- .uleb128 0xf
- .4byte .LASF94
- .byte 0x13
- .byte 0x20
- .4byte 0x59
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF95
- .byte 0x13
- .byte 0x21
- .4byte 0x59
- .byte 0xc
- .uleb128 0x10
- .string "cmd"
- .byte 0x13
- .byte 0x23
- .4byte 0x647
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF96
- .byte 0x13
- .byte 0x24
- .4byte 0xf3
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF97
- .byte 0x13
- .byte 0x26
- .4byte 0xf3
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF98
- .byte 0x13
- .byte 0x2a
- .4byte 0x676
- .byte 0x28
- .byte 0
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x63b
- .uleb128 0x14
- .4byte 0x63b
- .uleb128 0x14
- .4byte 0x59
- .uleb128 0x14
- .4byte 0x59
- .uleb128 0x14
- .4byte 0x641
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x5bc
- .uleb128 0x9
- .byte 0x8
- .4byte 0xf9
- .uleb128 0x9
- .byte 0x8
- .4byte 0x61d
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x670
- .uleb128 0x14
- .4byte 0x59
- .uleb128 0x14
- .4byte 0x641
- .uleb128 0x14
- .4byte 0xe0
- .uleb128 0x14
- .4byte 0x59
- .uleb128 0x14
- .4byte 0x670
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0xf3
- .uleb128 0x9
- .byte 0x8
- .4byte 0x64d
- .uleb128 0x2
- .4byte .LASF99
- .byte 0x13
- .byte 0x2e
- .4byte 0x5bc
- .uleb128 0x1b
- .4byte .LASF167
- .byte 0x4
- .4byte 0x59
- .byte 0x13
- .byte 0x7a
- .4byte 0x6aa
- .uleb128 0x1c
- .4byte .LASF100
- .byte 0
- .uleb128 0x1c
- .4byte .LASF101
- .byte 0x1
- .uleb128 0x1d
- .4byte .LASF102
- .sleb128 -1
- .byte 0
- .uleb128 0x2
- .4byte .LASF103
- .byte 0x14
- .byte 0x11
- .4byte 0x12a
- .uleb128 0xe
- .4byte .LASF104
- .byte 0x28
- .byte 0x15
- .byte 0x39
- .4byte 0x73a
- .uleb128 0xf
- .4byte .LASF105
- .byte 0x15
- .byte 0x3a
- .4byte 0x6aa
- .byte 0
- .uleb128 0xf
- .4byte .LASF106
- .byte 0x15
- .byte 0x3b
- .4byte 0x6aa
- .byte 0x4
- .uleb128 0xf
- .4byte .LASF107
- .byte 0x15
- .byte 0x3c
- .4byte 0x6aa
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF108
- .byte 0x15
- .byte 0x3d
- .4byte 0x6aa
- .byte 0xc
- .uleb128 0xf
- .4byte .LASF109
- .byte 0x15
- .byte 0x3e
- .4byte 0x6aa
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF110
- .byte 0x15
- .byte 0x3f
- .4byte 0x6aa
- .byte 0x14
- .uleb128 0xf
- .4byte .LASF111
- .byte 0x15
- .byte 0x40
- .4byte 0x6aa
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF112
- .byte 0x15
- .byte 0x43
- .4byte 0x6aa
- .byte 0x1c
- .uleb128 0xf
- .4byte .LASF113
- .byte 0x15
- .byte 0x46
- .4byte 0x6aa
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF114
- .byte 0x15
- .byte 0x49
- .4byte 0x6aa
- .byte 0x24
- .byte 0
- .uleb128 0xd
- .4byte .LASF115
- .byte 0x16
- .2byte 0x136
- .4byte 0x746
- .uleb128 0x9
- .byte 0x8
- .4byte 0x6b5
- .uleb128 0x1e
- .4byte .LASF116
- .byte 0x40
- .byte 0x17
- .2byte 0x134
- .4byte 0x7f6
- .uleb128 0x1f
- .4byte .LASF117
- .byte 0x17
- .2byte 0x135
- .4byte 0x12a
- .byte 0
- .uleb128 0x1f
- .4byte .LASF118
- .byte 0x17
- .2byte 0x136
- .4byte 0x12a
- .byte 0x4
- .uleb128 0x1f
- .4byte .LASF119
- .byte 0x17
- .2byte 0x137
- .4byte 0x12a
- .byte 0x8
- .uleb128 0x1f
- .4byte .LASF120
- .byte 0x17
- .2byte 0x138
- .4byte 0x12a
- .byte 0xc
- .uleb128 0x1f
- .4byte .LASF121
- .byte 0x17
- .2byte 0x139
- .4byte 0x12a
- .byte 0x10
- .uleb128 0x1f
- .4byte .LASF122
- .byte 0x17
- .2byte 0x13a
- .4byte 0x12a
- .byte 0x14
- .uleb128 0x1f
- .4byte .LASF123
- .byte 0x17
- .2byte 0x13b
- .4byte 0x12a
- .byte 0x18
- .uleb128 0x1f
- .4byte .LASF124
- .byte 0x17
- .2byte 0x13c
- .4byte 0x114
- .byte 0x1c
- .uleb128 0x1f
- .4byte .LASF125
- .byte 0x17
- .2byte 0x13d
- .4byte 0x114
- .byte 0x1d
- .uleb128 0x1f
- .4byte .LASF126
- .byte 0x17
- .2byte 0x13e
- .4byte 0x114
- .byte 0x1e
- .uleb128 0x1f
- .4byte .LASF127
- .byte 0x17
- .2byte 0x13f
- .4byte 0x114
- .byte 0x1f
- .uleb128 0x1f
- .4byte .LASF128
- .byte 0x17
- .2byte 0x140
- .4byte 0x7f6
- .byte 0x20
- .byte 0
- .uleb128 0xb
- .4byte 0x114
- .4byte 0x806
- .uleb128 0x12
- .4byte 0xce
- .byte 0x1f
- .byte 0
- .uleb128 0x20
- .4byte .LASF129
- .byte 0x17
- .2byte 0x141
- .4byte 0x74c
- .uleb128 0x1e
- .4byte .LASF130
- .byte 0x30
- .byte 0x17
- .2byte 0x143
- .4byte 0x894
- .uleb128 0x1f
- .4byte .LASF54
- .byte 0x17
- .2byte 0x144
- .4byte 0x109
- .byte 0
- .uleb128 0x21
- .string "end"
- .byte 0x17
- .2byte 0x144
- .4byte 0x109
- .byte 0x8
- .uleb128 0x1f
- .4byte .LASF131
- .byte 0x17
- .2byte 0x145
- .4byte 0x109
- .byte 0x10
- .uleb128 0x1f
- .4byte .LASF132
- .byte 0x17
- .2byte 0x145
- .4byte 0x109
- .byte 0x18
- .uleb128 0x1f
- .4byte .LASF133
- .byte 0x17
- .2byte 0x146
- .4byte 0x109
- .byte 0x20
- .uleb128 0x1f
- .4byte .LASF134
- .byte 0x17
- .2byte 0x147
- .4byte 0x114
- .byte 0x28
- .uleb128 0x1f
- .4byte .LASF135
- .byte 0x17
- .2byte 0x147
- .4byte 0x114
- .byte 0x29
- .uleb128 0x21
- .string "os"
- .byte 0x17
- .2byte 0x147
- .4byte 0x114
- .byte 0x2a
- .uleb128 0x1f
- .4byte .LASF136
- .byte 0x17
- .2byte 0x148
- .4byte 0x114
- .byte 0x2b
- .byte 0
- .uleb128 0x20
- .4byte .LASF137
- .byte 0x17
- .2byte 0x149
- .4byte 0x812
- .uleb128 0x22
- .4byte .LASF138
- .2byte 0x280
- .byte 0x17
- .2byte 0x14f
- .4byte 0xa3d
- .uleb128 0x1f
- .4byte .LASF139
- .byte 0x17
- .2byte 0x155
- .4byte 0xa3d
- .byte 0
- .uleb128 0x1f
- .4byte .LASF140
- .byte 0x17
- .2byte 0x156
- .4byte 0x806
- .byte 0x8
- .uleb128 0x1f
- .4byte .LASF141
- .byte 0x17
- .2byte 0x157
- .4byte 0x109
- .byte 0x48
- .uleb128 0x1f
- .4byte .LASF142
- .byte 0x17
- .2byte 0x15a
- .4byte 0xd5
- .byte 0x50
- .uleb128 0x1f
- .4byte .LASF143
- .byte 0x17
- .2byte 0x15c
- .4byte 0x135
- .byte 0x58
- .uleb128 0x1f
- .4byte .LASF144
- .byte 0x17
- .2byte 0x15d
- .4byte 0xd5
- .byte 0x60
- .uleb128 0x1f
- .4byte .LASF145
- .byte 0x17
- .2byte 0x15e
- .4byte 0x59
- .byte 0x68
- .uleb128 0x1f
- .4byte .LASF146
- .byte 0x17
- .2byte 0x160
- .4byte 0x135
- .byte 0x70
- .uleb128 0x1f
- .4byte .LASF147
- .byte 0x17
- .2byte 0x161
- .4byte 0xd5
- .byte 0x78
- .uleb128 0x1f
- .4byte .LASF148
- .byte 0x17
- .2byte 0x162
- .4byte 0x59
- .byte 0x80
- .uleb128 0x1f
- .4byte .LASF149
- .byte 0x17
- .2byte 0x164
- .4byte 0x135
- .byte 0x88
- .uleb128 0x1f
- .4byte .LASF150
- .byte 0x17
- .2byte 0x165
- .4byte 0xd5
- .byte 0x90
- .uleb128 0x1f
- .4byte .LASF151
- .byte 0x17
- .2byte 0x166
- .4byte 0x59
- .byte 0x98
- .uleb128 0x1f
- .4byte .LASF152
- .byte 0x17
- .2byte 0x168
- .4byte 0x135
- .byte 0xa0
- .uleb128 0x1f
- .4byte .LASF153
- .byte 0x17
- .2byte 0x169
- .4byte 0xd5
- .byte 0xa8
- .uleb128 0x1f
- .4byte .LASF154
- .byte 0x17
- .2byte 0x16a
- .4byte 0x59
- .byte 0xb0
- .uleb128 0x21
- .string "os"
- .byte 0x17
- .2byte 0x16e
- .4byte 0x894
- .byte 0xb8
- .uleb128 0x21
- .string "ep"
- .byte 0x17
- .2byte 0x16f
- .4byte 0x109
- .byte 0xe8
- .uleb128 0x1f
- .4byte .LASF155
- .byte 0x17
- .2byte 0x171
- .4byte 0x109
- .byte 0xf0
- .uleb128 0x1f
- .4byte .LASF156
- .byte 0x17
- .2byte 0x171
- .4byte 0x109
- .byte 0xf8
- .uleb128 0x23
- .4byte .LASF157
- .byte 0x17
- .2byte 0x173
- .4byte 0xf3
- .2byte 0x100
- .uleb128 0x23
- .4byte .LASF158
- .byte 0x17
- .2byte 0x174
- .4byte 0x109
- .2byte 0x108
- .uleb128 0x23
- .4byte .LASF159
- .byte 0x17
- .2byte 0x176
- .4byte 0x109
- .2byte 0x110
- .uleb128 0x23
- .4byte .LASF160
- .byte 0x17
- .2byte 0x177
- .4byte 0x109
- .2byte 0x118
- .uleb128 0x23
- .4byte .LASF161
- .byte 0x17
- .2byte 0x178
- .4byte 0x109
- .2byte 0x120
- .uleb128 0x23
- .4byte .LASF162
- .byte 0x17
- .2byte 0x179
- .4byte 0x109
- .2byte 0x128
- .uleb128 0x24
- .string "kbd"
- .byte 0x17
- .2byte 0x17a
- .4byte 0xa43
- .2byte 0x130
- .uleb128 0x23
- .4byte .LASF163
- .byte 0x17
- .2byte 0x17d
- .4byte 0x59
- .2byte 0x138
- .uleb128 0x23
- .4byte .LASF164
- .byte 0x17
- .2byte 0x18a
- .4byte 0x59
- .2byte 0x13c
- .uleb128 0x24
- .string "lmb"
- .byte 0x17
- .2byte 0x18d
- .4byte 0x411
- .2byte 0x140
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x806
- .uleb128 0x9
- .byte 0x8
- .4byte 0x564
- .uleb128 0x20
- .4byte .LASF165
- .byte 0x17
- .2byte 0x18f
- .4byte 0x8a0
- .uleb128 0xd
- .4byte .LASF166
- .byte 0x17
- .2byte 0x191
- .4byte 0xa49
- .uleb128 0x1b
- .4byte .LASF168
- .byte 0x4
- .4byte 0x59
- .byte 0x18
- .byte 0xe
- .4byte 0xc7c
- .uleb128 0x1c
- .4byte .LASF169
- .byte 0
- .uleb128 0x1c
- .4byte .LASF170
- .byte 0x1
- .uleb128 0x1c
- .4byte .LASF171
- .byte 0x2
- .uleb128 0x1c
- .4byte .LASF172
- .byte 0x3
- .uleb128 0x1c
- .4byte .LASF173
- .byte 0x4
- .uleb128 0x1c
- .4byte .LASF174
- .byte 0x5
- .uleb128 0x1c
- .4byte .LASF175
- .byte 0x6
- .uleb128 0x1c
- .4byte .LASF176
- .byte 0x7
- .uleb128 0x1c
- .4byte .LASF177
- .byte 0x8
- .uleb128 0x1c
- .4byte .LASF178
- .byte 0x9
- .uleb128 0x1c
- .4byte .LASF179
- .byte 0xa
- .uleb128 0x1c
- .4byte .LASF180
- .byte 0xb
- .uleb128 0x1c
- .4byte .LASF181
- .byte 0xc
- .uleb128 0x1c
- .4byte .LASF182
- .byte 0xd
- .uleb128 0x1c
- .4byte .LASF183
- .byte 0xe
- .uleb128 0x1c
- .4byte .LASF184
- .byte 0xf
- .uleb128 0x1c
- .4byte .LASF185
- .byte 0x10
- .uleb128 0x1c
- .4byte .LASF186
- .byte 0x11
- .uleb128 0x1c
- .4byte .LASF187
- .byte 0x12
- .uleb128 0x1c
- .4byte .LASF188
- .byte 0x13
- .uleb128 0x1c
- .4byte .LASF189
- .byte 0x14
- .uleb128 0x1c
- .4byte .LASF190
- .byte 0x15
- .uleb128 0x1c
- .4byte .LASF191
- .byte 0x16
- .uleb128 0x1c
- .4byte .LASF192
- .byte 0x17
- .uleb128 0x1c
- .4byte .LASF193
- .byte 0x18
- .uleb128 0x1c
- .4byte .LASF194
- .byte 0x19
- .uleb128 0x1c
- .4byte .LASF195
- .byte 0x1a
- .uleb128 0x1c
- .4byte .LASF196
- .byte 0x1b
- .uleb128 0x1c
- .4byte .LASF197
- .byte 0x1c
- .uleb128 0x1c
- .4byte .LASF198
- .byte 0x1d
- .uleb128 0x1c
- .4byte .LASF199
- .byte 0x1e
- .uleb128 0x1c
- .4byte .LASF200
- .byte 0x1f
- .uleb128 0x1c
- .4byte .LASF201
- .byte 0x20
- .uleb128 0x1c
- .4byte .LASF202
- .byte 0x21
- .uleb128 0x1c
- .4byte .LASF203
- .byte 0x22
- .uleb128 0x1c
- .4byte .LASF204
- .byte 0x23
- .uleb128 0x1c
- .4byte .LASF205
- .byte 0x24
- .uleb128 0x1c
- .4byte .LASF206
- .byte 0x25
- .uleb128 0x1c
- .4byte .LASF207
- .byte 0x26
- .uleb128 0x1c
- .4byte .LASF208
- .byte 0x27
- .uleb128 0x1c
- .4byte .LASF209
- .byte 0x28
- .uleb128 0x1c
- .4byte .LASF210
- .byte 0x29
- .uleb128 0x1c
- .4byte .LASF211
- .byte 0x2a
- .uleb128 0x1c
- .4byte .LASF212
- .byte 0x2b
- .uleb128 0x1c
- .4byte .LASF213
- .byte 0x2c
- .uleb128 0x1c
- .4byte .LASF214
- .byte 0x2d
- .uleb128 0x1c
- .4byte .LASF215
- .byte 0x2e
- .uleb128 0x1c
- .4byte .LASF216
- .byte 0x2f
- .uleb128 0x1c
- .4byte .LASF217
- .byte 0x30
- .uleb128 0x1c
- .4byte .LASF218
- .byte 0x31
- .uleb128 0x1c
- .4byte .LASF219
- .byte 0x32
- .uleb128 0x1c
- .4byte .LASF220
- .byte 0x33
- .uleb128 0x1c
- .4byte .LASF221
- .byte 0x34
- .uleb128 0x1c
- .4byte .LASF222
- .byte 0x35
- .uleb128 0x1c
- .4byte .LASF223
- .byte 0x36
- .uleb128 0x1c
- .4byte .LASF224
- .byte 0x37
- .uleb128 0x1c
- .4byte .LASF225
- .byte 0x38
- .uleb128 0x1c
- .4byte .LASF226
- .byte 0x39
- .uleb128 0x1c
- .4byte .LASF227
- .byte 0x3a
- .uleb128 0x1c
- .4byte .LASF228
- .byte 0x3b
- .uleb128 0x1c
- .4byte .LASF229
- .byte 0x3c
- .uleb128 0x1c
- .4byte .LASF230
- .byte 0x3d
- .uleb128 0x1c
- .4byte .LASF231
- .byte 0x3e
- .uleb128 0x1c
- .4byte .LASF232
- .byte 0x3f
- .uleb128 0x1c
- .4byte .LASF233
- .byte 0x40
- .uleb128 0x1c
- .4byte .LASF234
- .byte 0x41
- .uleb128 0x1c
- .4byte .LASF235
- .byte 0x42
- .uleb128 0x1c
- .4byte .LASF236
- .byte 0x43
- .uleb128 0x1c
- .4byte .LASF237
- .byte 0x44
- .uleb128 0x1c
- .4byte .LASF238
- .byte 0x45
- .uleb128 0x1c
- .4byte .LASF239
- .byte 0x46
- .uleb128 0x1c
- .4byte .LASF240
- .byte 0x47
- .uleb128 0x1c
- .4byte .LASF241
- .byte 0x48
- .uleb128 0x1c
- .4byte .LASF242
- .byte 0x49
- .uleb128 0x1c
- .4byte .LASF243
- .byte 0x4a
- .uleb128 0x1c
- .4byte .LASF244
- .byte 0x4b
- .uleb128 0x1c
- .4byte .LASF245
- .byte 0x4c
- .uleb128 0x1c
- .4byte .LASF246
- .byte 0x4d
- .uleb128 0x1c
- .4byte .LASF247
- .byte 0x4e
- .uleb128 0x1c
- .4byte .LASF248
- .byte 0x4f
- .uleb128 0x1c
- .4byte .LASF249
- .byte 0x50
- .uleb128 0x1c
- .4byte .LASF250
- .byte 0x51
- .uleb128 0x1c
- .4byte .LASF251
- .byte 0x52
- .uleb128 0x1c
- .4byte .LASF252
- .byte 0x53
- .uleb128 0x1c
- .4byte .LASF253
- .byte 0x54
- .uleb128 0x1c
- .4byte .LASF254
- .byte 0x55
- .uleb128 0x1d
- .4byte .LASF255
- .sleb128 -1
- .byte 0
- .uleb128 0x25
- .byte 0x4
- .4byte 0x84
- .byte 0x24
- .byte 0xe0
- .4byte 0xc8f
- .uleb128 0x1c
- .4byte .LASF256
- .byte 0x5
- .byte 0
- .uleb128 0xe
- .4byte .LASF257
- .byte 0x40
- .byte 0x19
- .byte 0xc
- .4byte 0xd08
- .uleb128 0xf
- .4byte .LASF258
- .byte 0x19
- .byte 0x22
- .4byte 0x3b
- .byte 0
- .uleb128 0x10
- .string "tbu"
- .byte 0x19
- .byte 0x23
- .4byte 0x84
- .byte 0x8
- .uleb128 0x10
- .string "tbl"
- .byte 0x19
- .byte 0x24
- .4byte 0x84
- .byte 0xc
- .uleb128 0xf
- .4byte .LASF259
- .byte 0x19
- .byte 0x25
- .4byte 0x3b
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF260
- .byte 0x19
- .byte 0x26
- .4byte 0x92
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF261
- .byte 0x19
- .byte 0x28
- .4byte 0x3b
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF262
- .byte 0x19
- .byte 0x29
- .4byte 0x3b
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF263
- .byte 0x19
- .byte 0x2b
- .4byte 0x3b
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF264
- .byte 0x19
- .byte 0x2c
- .4byte 0x3b
- .byte 0x38
- .byte 0
- .uleb128 0xe
- .4byte .LASF265
- .byte 0x18
- .byte 0x1a
- .byte 0x22
- .4byte 0xd44
- .uleb128 0xf
- .4byte .LASF266
- .byte 0x1a
- .byte 0x23
- .4byte 0xa8
- .byte 0
- .uleb128 0x10
- .string "id"
- .byte 0x1a
- .byte 0x24
- .4byte 0xa8
- .byte 0x4
- .uleb128 0xf
- .4byte .LASF267
- .byte 0x1a
- .byte 0x25
- .4byte 0xa8
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF268
- .byte 0x1a
- .byte 0x26
- .4byte 0x109
- .byte 0x10
- .byte 0
- .uleb128 0x26
- .4byte .LASF269
- .2byte 0x1a0
- .byte 0x1a
- .byte 0x29
- .4byte 0xf3c
- .uleb128 0x10
- .string "bd"
- .byte 0x1a
- .byte 0x2a
- .4byte 0xa43
- .byte 0
- .uleb128 0xf
- .4byte .LASF42
- .byte 0x1a
- .byte 0x2b
- .4byte 0x3b
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF267
- .byte 0x1a
- .byte 0x2c
- .4byte 0x84
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF270
- .byte 0x1a
- .byte 0x2d
- .4byte 0x3b
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF271
- .byte 0x1a
- .byte 0x2e
- .4byte 0x3b
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF272
- .byte 0x1a
- .byte 0x30
- .4byte 0x3b
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF273
- .byte 0x1a
- .byte 0x31
- .4byte 0x3b
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF274
- .byte 0x1a
- .byte 0x33
- .4byte 0x3b
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF275
- .byte 0x1a
- .byte 0x3d
- .4byte 0x3b
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF276
- .byte 0x1a
- .byte 0x41
- .4byte 0x3b
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF277
- .byte 0x1a
- .byte 0x42
- .4byte 0x3b
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF278
- .byte 0x1a
- .byte 0x44
- .4byte 0x3b
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF279
- .byte 0x1a
- .byte 0x45
- .4byte 0x3b
- .byte 0x60
- .uleb128 0xf
- .4byte .LASF280
- .byte 0x1a
- .byte 0x46
- .4byte 0xc3
- .byte 0x68
- .uleb128 0xf
- .4byte .LASF281
- .byte 0x1a
- .byte 0x47
- .4byte 0x3b
- .byte 0x70
- .uleb128 0xf
- .4byte .LASF282
- .byte 0x1a
- .byte 0x48
- .4byte 0x3b
- .byte 0x78
- .uleb128 0xf
- .4byte .LASF283
- .byte 0x1a
- .byte 0x49
- .4byte 0x3b
- .byte 0x80
- .uleb128 0xf
- .4byte .LASF284
- .byte 0x1a
- .byte 0x4a
- .4byte 0x3b
- .byte 0x88
- .uleb128 0xf
- .4byte .LASF285
- .byte 0x1a
- .byte 0x4b
- .4byte 0xf3c
- .byte 0x90
- .uleb128 0xf
- .4byte .LASF286
- .byte 0x1a
- .byte 0x4e
- .4byte 0x25d
- .byte 0x98
- .uleb128 0xf
- .4byte .LASF287
- .byte 0x1a
- .byte 0x4f
- .4byte 0x25d
- .byte 0xa0
- .uleb128 0xf
- .4byte .LASF288
- .byte 0x1a
- .byte 0x50
- .4byte 0x290
- .byte 0xa8
- .uleb128 0xf
- .4byte .LASF289
- .byte 0x1a
- .byte 0x56
- .4byte 0x263
- .byte 0xb8
- .uleb128 0xf
- .4byte .LASF290
- .byte 0x1a
- .byte 0x57
- .4byte 0x135
- .byte 0xc0
- .uleb128 0xf
- .4byte .LASF291
- .byte 0x1a
- .byte 0x58
- .4byte 0x3b
- .byte 0xc8
- .uleb128 0xf
- .4byte .LASF292
- .byte 0x1a
- .byte 0x5a
- .4byte 0xfb4
- .byte 0xd0
- .uleb128 0x10
- .string "jt"
- .byte 0x1a
- .byte 0x5c
- .4byte 0xfbf
- .byte 0xd8
- .uleb128 0xf
- .4byte .LASF293
- .byte 0x1a
- .byte 0x5d
- .4byte 0xfc5
- .byte 0xe0
- .uleb128 0x16
- .4byte .LASF294
- .byte 0x1a
- .byte 0x67
- .4byte 0x84
- .2byte 0x100
- .uleb128 0x16
- .4byte .LASF295
- .byte 0x1a
- .byte 0x68
- .4byte 0x84
- .2byte 0x104
- .uleb128 0x16
- .4byte .LASF296
- .byte 0x1a
- .byte 0x6a
- .4byte 0x3b
- .2byte 0x108
- .uleb128 0x16
- .4byte .LASF297
- .byte 0x1a
- .byte 0x6b
- .4byte 0x3b
- .2byte 0x110
- .uleb128 0x16
- .4byte .LASF298
- .byte 0x1a
- .byte 0x6c
- .4byte 0x3b
- .2byte 0x118
- .uleb128 0x16
- .4byte .LASF299
- .byte 0x1a
- .byte 0x75
- .4byte 0x25d
- .2byte 0x120
- .uleb128 0x16
- .4byte .LASF136
- .byte 0x1a
- .byte 0x76
- .4byte 0xc8f
- .2byte 0x128
- .uleb128 0x16
- .4byte .LASF300
- .byte 0x1a
- .byte 0x7c
- .4byte 0x109
- .2byte 0x168
- .uleb128 0x16
- .4byte .LASF301
- .byte 0x1a
- .byte 0x7d
- .4byte 0x109
- .2byte 0x170
- .uleb128 0x16
- .4byte .LASF302
- .byte 0x1a
- .byte 0x83
- .4byte 0xb8
- .2byte 0x178
- .uleb128 0x16
- .4byte .LASF303
- .byte 0x1a
- .byte 0x88
- .4byte 0xd08
- .2byte 0x180
- .uleb128 0x16
- .4byte .LASF304
- .byte 0x1a
- .byte 0x89
- .4byte 0x109
- .2byte 0x198
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0xd44
- .uleb128 0xe
- .4byte .LASF305
- .byte 0x40
- .byte 0x1b
- .byte 0x2c
- .4byte 0xfaf
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x1b
- .byte 0x2d
- .4byte 0xd5
- .byte 0
- .uleb128 0xf
- .4byte .LASF135
- .byte 0x1b
- .byte 0x2e
- .4byte 0xd5
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF306
- .byte 0x1b
- .byte 0x2f
- .4byte 0x145c
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF307
- .byte 0x1b
- .byte 0x30
- .4byte 0xd5
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF308
- .byte 0x1b
- .byte 0x32
- .4byte 0x14a4
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF34
- .byte 0x1b
- .byte 0x33
- .4byte 0xfb4
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF309
- .byte 0x1b
- .byte 0x34
- .4byte 0xfb4
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF310
- .byte 0x1b
- .byte 0x35
- .4byte 0xfb4
- .byte 0x38
- .byte 0
- .uleb128 0x8
- .4byte 0xf42
- .uleb128 0x9
- .byte 0x8
- .4byte 0xf42
- .uleb128 0x27
- .4byte .LASF481
- .uleb128 0x9
- .byte 0x8
- .4byte 0xfba
- .uleb128 0xb
- .4byte 0xe0
- .4byte 0xfd5
- .uleb128 0x12
- .4byte 0xce
- .byte 0x1f
- .byte 0
- .uleb128 0x2
- .4byte .LASF311
- .byte 0x1a
- .byte 0x8f
- .4byte 0xd44
- .uleb128 0x4
- .4byte 0xfd5
- .uleb128 0x5
- .4byte .LASF312
- .byte 0x5
- .byte 0xab
- .4byte 0x109
- .uleb128 0xb
- .4byte 0x99
- .4byte 0xffb
- .uleb128 0xc
- .byte 0
- .uleb128 0x5
- .4byte .LASF313
- .byte 0x5
- .byte 0xad
- .4byte 0xff0
- .uleb128 0x5
- .4byte .LASF314
- .byte 0x5
- .byte 0xae
- .4byte 0xff0
- .uleb128 0x5
- .4byte .LASF315
- .byte 0x5
- .byte 0xfc
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF316
- .byte 0x5
- .byte 0xfd
- .4byte 0x109
- .uleb128 0x5
- .4byte .LASF317
- .byte 0x5
- .byte 0xfe
- .4byte 0x109
- .uleb128 0xe
- .4byte .LASF318
- .byte 0x4
- .byte 0x1c
- .byte 0x2e
- .4byte 0x104b
- .uleb128 0xf
- .4byte .LASF319
- .byte 0x1c
- .byte 0x2f
- .4byte 0x12a
- .byte 0
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x29
- .uleb128 0xe
- .4byte .LASF320
- .byte 0x68
- .byte 0x1c
- .byte 0xa6
- .4byte 0x10ee
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x1c
- .byte 0xa8
- .4byte 0x10ee
- .byte 0
- .uleb128 0xf
- .4byte .LASF321
- .byte 0x1c
- .byte 0xa9
- .4byte 0x280
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF322
- .byte 0x1c
- .byte 0xaa
- .4byte 0xb8
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF164
- .byte 0x1c
- .byte 0xab
- .4byte 0x59
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF323
- .byte 0x1c
- .byte 0xad
- .4byte 0x1118
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF324
- .byte 0x1c
- .byte 0xae
- .4byte 0x1137
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF325
- .byte 0x1c
- .byte 0xaf
- .4byte 0x114c
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF326
- .byte 0x1c
- .byte 0xb0
- .4byte 0x115d
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF327
- .byte 0x1c
- .byte 0xb4
- .4byte 0x114c
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF47
- .byte 0x1c
- .byte 0xb5
- .4byte 0x1112
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF328
- .byte 0x1c
- .byte 0xb6
- .4byte 0x59
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF35
- .byte 0x1c
- .byte 0xb7
- .4byte 0x135
- .byte 0x60
- .byte 0
- .uleb128 0xb
- .4byte 0xe0
- .4byte 0x10fe
- .uleb128 0x12
- .4byte 0xce
- .byte 0xf
- .byte 0
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x1112
- .uleb128 0x14
- .4byte 0x1112
- .uleb128 0x14
- .4byte 0xa43
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1051
- .uleb128 0x9
- .byte 0x8
- .4byte 0x10fe
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x1137
- .uleb128 0x14
- .4byte 0x1112
- .uleb128 0x14
- .4byte 0x135
- .uleb128 0x14
- .4byte 0x59
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x111e
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x114c
- .uleb128 0x14
- .4byte 0x1112
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x113d
- .uleb128 0x28
- .4byte 0x115d
- .uleb128 0x14
- .4byte 0x1112
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1152
- .uleb128 0x5
- .4byte .LASF329
- .byte 0x1c
- .byte 0xbd
- .4byte 0x1112
- .uleb128 0x28
- .4byte 0x117e
- .uleb128 0x14
- .4byte 0x135
- .uleb128 0x14
- .4byte 0x59
- .byte 0
- .uleb128 0xd
- .4byte .LASF330
- .byte 0x1c
- .2byte 0x11e
- .4byte 0x118a
- .uleb128 0x9
- .byte 0x8
- .4byte 0x116e
- .uleb128 0xb
- .4byte 0x99
- .4byte 0x11a0
- .uleb128 0x12
- .4byte 0xce
- .byte 0x5
- .byte 0
- .uleb128 0xd
- .4byte .LASF331
- .byte 0x1c
- .2byte 0x1fd
- .4byte 0x1032
- .uleb128 0xd
- .4byte .LASF332
- .byte 0x1c
- .2byte 0x1fe
- .4byte 0x1032
- .uleb128 0xd
- .4byte .LASF333
- .byte 0x1c
- .2byte 0x200
- .4byte 0x1032
- .uleb128 0xd
- .4byte .LASF334
- .byte 0x1c
- .2byte 0x205
- .4byte 0xfc5
- .uleb128 0xd
- .4byte .LASF335
- .byte 0x1c
- .2byte 0x206
- .4byte 0xfc5
- .uleb128 0xb
- .4byte 0xe0
- .4byte 0x11ec
- .uleb128 0x12
- .4byte 0xce
- .byte 0x3f
- .byte 0
- .uleb128 0xd
- .4byte .LASF336
- .byte 0x1c
- .2byte 0x207
- .4byte 0x11dc
- .uleb128 0xd
- .4byte .LASF337
- .byte 0x1c
- .2byte 0x209
- .4byte 0x1190
- .uleb128 0xd
- .4byte .LASF338
- .byte 0x1c
- .2byte 0x20a
- .4byte 0x1190
- .uleb128 0xd
- .4byte .LASF339
- .byte 0x1c
- .2byte 0x20b
- .4byte 0x1032
- .uleb128 0xd
- .4byte .LASF340
- .byte 0x1c
- .2byte 0x20c
- .4byte 0x1032
- .uleb128 0xd
- .4byte .LASF341
- .byte 0x1c
- .2byte 0x20d
- .4byte 0x104b
- .uleb128 0xb
- .4byte 0x104b
- .4byte 0x1244
- .uleb128 0x12
- .4byte 0xce
- .byte 0x3
- .byte 0
- .uleb128 0xd
- .4byte .LASF342
- .byte 0x1c
- .2byte 0x20e
- .4byte 0x1234
- .uleb128 0xd
- .4byte .LASF343
- .byte 0x1c
- .2byte 0x20f
- .4byte 0x104b
- .uleb128 0xd
- .4byte .LASF344
- .byte 0x1c
- .2byte 0x210
- .4byte 0x59
- .uleb128 0xb
- .4byte 0xa3
- .4byte 0x1278
- .uleb128 0x12
- .4byte 0xce
- .byte 0x5
- .byte 0
- .uleb128 0x8
- .4byte 0x1268
- .uleb128 0xd
- .4byte .LASF345
- .byte 0x1c
- .2byte 0x211
- .4byte 0x1278
- .uleb128 0xd
- .4byte .LASF346
- .byte 0x1c
- .2byte 0x212
- .4byte 0x1278
- .uleb128 0xd
- .4byte .LASF347
- .byte 0x1c
- .2byte 0x216
- .4byte 0xfe
- .uleb128 0xd
- .4byte .LASF348
- .byte 0x1c
- .2byte 0x217
- .4byte 0xfe
- .uleb128 0xd
- .4byte .LASF349
- .byte 0x1c
- .2byte 0x219
- .4byte 0x59
- .uleb128 0xb
- .4byte 0xe0
- .4byte 0x12ca
- .uleb128 0x17
- .4byte 0xce
- .2byte 0x3ff
- .byte 0
- .uleb128 0xd
- .4byte .LASF350
- .byte 0x1c
- .2byte 0x220
- .4byte 0x12b9
- .uleb128 0xd
- .4byte .LASF351
- .byte 0x1c
- .2byte 0x222
- .4byte 0xa8
- .uleb128 0xd
- .4byte .LASF352
- .byte 0x1c
- .2byte 0x224
- .4byte 0xa8
- .uleb128 0xd
- .4byte .LASF353
- .byte 0x1c
- .2byte 0x230
- .4byte 0x1032
- .uleb128 0x29
- .4byte .LASF354
- .byte 0x4
- .4byte 0x84
- .byte 0x1c
- .2byte 0x286
- .4byte 0x1324
- .uleb128 0x1c
- .4byte .LASF355
- .byte 0
- .uleb128 0x1c
- .4byte .LASF356
- .byte 0x1
- .uleb128 0x1c
- .4byte .LASF357
- .byte 0x2
- .uleb128 0x1c
- .4byte .LASF358
- .byte 0x3
- .byte 0
- .uleb128 0xd
- .4byte .LASF359
- .byte 0x1c
- .2byte 0x28c
- .4byte 0x12fa
- .uleb128 0xd
- .4byte .LASF360
- .byte 0x1d
- .2byte 0x3ba
- .4byte 0x109
- .uleb128 0xd
- .4byte .LASF361
- .byte 0x1d
- .2byte 0x3bb
- .4byte 0x109
- .uleb128 0xd
- .4byte .LASF362
- .byte 0x1d
- .2byte 0x3bc
- .4byte 0x109
- .uleb128 0xb
- .4byte 0xa8
- .4byte 0x1364
- .uleb128 0x12
- .4byte 0xce
- .byte 0x1f
- .byte 0
- .uleb128 0x2a
- .4byte .LASF379
- .byte 0x1
- .byte 0xa
- .4byte 0x1354
- .uleb128 0x9
- .byte 0x3
- .8byte g_isi_pattern
- .uleb128 0x9
- .byte 0x8
- .4byte 0xa8
- .uleb128 0xe
- .4byte .LASF27
- .byte 0x78
- .byte 0xb
- .byte 0xee
- .4byte 0x1457
- .uleb128 0xf
- .4byte .LASF28
- .byte 0xb
- .byte 0xef
- .4byte 0xf3
- .byte 0
- .uleb128 0x10
- .string "id"
- .byte 0xb
- .byte 0xf0
- .4byte 0xa61
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF363
- .byte 0xb
- .byte 0xf1
- .4byte 0x158a
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF364
- .byte 0xb
- .byte 0xf2
- .4byte 0x159f
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF365
- .byte 0xb
- .byte 0xf3
- .4byte 0x159f
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF366
- .byte 0xb
- .byte 0xf4
- .4byte 0x159f
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF367
- .byte 0xb
- .byte 0xf5
- .4byte 0x159f
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF368
- .byte 0xb
- .byte 0xf6
- .4byte 0x159f
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF369
- .byte 0xb
- .byte 0xf7
- .4byte 0x159f
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF370
- .byte 0xb
- .byte 0xf8
- .4byte 0x159f
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF371
- .byte 0xb
- .byte 0xf9
- .4byte 0x159f
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF372
- .byte 0xb
- .byte 0xfa
- .4byte 0x59
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF373
- .byte 0xb
- .byte 0xfb
- .4byte 0x59
- .byte 0x5c
- .uleb128 0xf
- .4byte .LASF374
- .byte 0xb
- .byte 0xfc
- .4byte 0x59
- .byte 0x60
- .uleb128 0xf
- .4byte .LASF375
- .byte 0xb
- .byte 0xfd
- .4byte 0x59
- .byte 0x64
- .uleb128 0x10
- .string "ops"
- .byte 0xb
- .byte 0xfe
- .4byte 0x263
- .byte 0x68
- .uleb128 0xf
- .4byte .LASF42
- .byte 0xb
- .byte 0xff
- .4byte 0x11f
- .byte 0x70
- .byte 0
- .uleb128 0x8
- .4byte 0x137f
- .uleb128 0x2
- .4byte .LASF306
- .byte 0x1b
- .byte 0xf
- .4byte 0xa8
- .uleb128 0xe
- .4byte .LASF376
- .byte 0x20
- .byte 0x1b
- .byte 0x19
- .4byte 0x14a4
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x1b
- .byte 0x1a
- .4byte 0xf3
- .byte 0
- .uleb128 0xf
- .4byte .LASF377
- .byte 0x1b
- .byte 0x1b
- .4byte 0x59
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF378
- .byte 0x1b
- .byte 0x1c
- .4byte 0x135
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF47
- .byte 0x1b
- .byte 0x1d
- .4byte 0x14a4
- .byte 0x18
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1467
- .uleb128 0x2b
- .string "gd"
- .byte 0x1b
- .byte 0x57
- .4byte 0x14b4
- .uleb128 0x9
- .byte 0x8
- .4byte 0xfe0
- .uleb128 0x2c
- .4byte .LASF482
- .byte 0x8
- .byte 0x1e
- .byte 0x33
- .4byte 0x14dc
- .uleb128 0x2d
- .string "np"
- .byte 0x1e
- .byte 0x34
- .4byte 0x14dc
- .uleb128 0x2e
- .4byte .LASF380
- .byte 0x1e
- .byte 0x35
- .4byte 0xec
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0xfaf
- .uleb128 0x2
- .4byte .LASF381
- .byte 0x1e
- .byte 0x36
- .4byte 0x14ba
- .uleb128 0xe
- .4byte .LASF382
- .byte 0x4
- .byte 0x1f
- .byte 0xc
- .4byte 0x1506
- .uleb128 0x10
- .string "pid"
- .byte 0x1f
- .byte 0xd
- .4byte 0x59
- .byte 0
- .byte 0
- .uleb128 0x5
- .4byte .LASF383
- .byte 0x1f
- .byte 0x10
- .4byte 0x1511
- .uleb128 0x9
- .byte 0x8
- .4byte 0x14ed
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1457
- .uleb128 0xe
- .4byte .LASF36
- .byte 0x30
- .byte 0x20
- .byte 0x23
- .4byte 0x155a
- .uleb128 0xf
- .4byte .LASF35
- .byte 0x20
- .byte 0x24
- .4byte 0x135
- .byte 0
- .uleb128 0xf
- .4byte .LASF384
- .byte 0x20
- .byte 0x25
- .4byte 0x1689
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF385
- .byte 0x20
- .byte 0x26
- .4byte 0x290
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF41
- .byte 0x20
- .byte 0x27
- .4byte 0x290
- .byte 0x20
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x151d
- .uleb128 0xe
- .4byte .LASF386
- .byte 0x10
- .byte 0xb
- .byte 0xb5
- .4byte 0x1585
- .uleb128 0xf
- .4byte .LASF387
- .byte 0xb
- .byte 0xb6
- .4byte 0xd5
- .byte 0
- .uleb128 0xf
- .4byte .LASF388
- .byte 0xb
- .byte 0xb7
- .4byte 0x109
- .byte 0x8
- .byte 0
- .uleb128 0x8
- .4byte 0x1560
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1585
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x159f
- .uleb128 0x14
- .4byte 0x25d
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1590
- .uleb128 0xe
- .4byte .LASF389
- .byte 0x80
- .byte 0x20
- .byte 0x54
- .4byte 0x1689
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x20
- .byte 0x55
- .4byte 0xd5
- .byte 0
- .uleb128 0x10
- .string "id"
- .byte 0x20
- .byte 0x56
- .4byte 0xa61
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF390
- .byte 0x20
- .byte 0x57
- .4byte 0x159f
- .byte 0x10
- .uleb128 0xf
- .4byte .LASF391
- .byte 0x20
- .byte 0x58
- .4byte 0x159f
- .byte 0x18
- .uleb128 0xf
- .4byte .LASF392
- .byte 0x20
- .byte 0x59
- .4byte 0x159f
- .byte 0x20
- .uleb128 0xf
- .4byte .LASF393
- .byte 0x20
- .byte 0x5a
- .4byte 0x159f
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF394
- .byte 0x20
- .byte 0x5b
- .4byte 0x159f
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF369
- .byte 0x20
- .byte 0x5c
- .4byte 0x159f
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF370
- .byte 0x20
- .byte 0x5d
- .4byte 0x159f
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF323
- .byte 0x20
- .byte 0x5e
- .4byte 0x169e
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF395
- .byte 0x20
- .byte 0x5f
- .4byte 0x169e
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF372
- .byte 0x20
- .byte 0x60
- .4byte 0x59
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF396
- .byte 0x20
- .byte 0x61
- .4byte 0x59
- .byte 0x5c
- .uleb128 0xf
- .4byte .LASF397
- .byte 0x20
- .byte 0x62
- .4byte 0x59
- .byte 0x60
- .uleb128 0xf
- .4byte .LASF374
- .byte 0x20
- .byte 0x63
- .4byte 0x59
- .byte 0x64
- .uleb128 0xf
- .4byte .LASF375
- .byte 0x20
- .byte 0x64
- .4byte 0x59
- .byte 0x68
- .uleb128 0x10
- .string "ops"
- .byte 0x20
- .byte 0x65
- .4byte 0x263
- .byte 0x70
- .uleb128 0xf
- .4byte .LASF42
- .byte 0x20
- .byte 0x66
- .4byte 0x11f
- .byte 0x78
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x15a5
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x169e
- .uleb128 0x14
- .4byte 0x155a
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x168f
- .uleb128 0x5
- .4byte .LASF398
- .byte 0x21
- .byte 0xb
- .4byte 0x149
- .uleb128 0xe
- .4byte .LASF399
- .byte 0x70
- .byte 0x22
- .byte 0x16
- .4byte 0x1740
- .uleb128 0xf
- .4byte .LASF42
- .byte 0x22
- .byte 0x17
- .4byte 0x59
- .byte 0
- .uleb128 0x10
- .string "ext"
- .byte 0x22
- .byte 0x18
- .4byte 0x59
- .byte 0x4
- .uleb128 0xf
- .4byte .LASF28
- .byte 0x22
- .byte 0x19
- .4byte 0xfc5
- .byte 0x8
- .uleb128 0xf
- .4byte .LASF54
- .byte 0x22
- .byte 0x1d
- .4byte 0x1755
- .byte 0x28
- .uleb128 0xf
- .4byte .LASF400
- .byte 0x22
- .byte 0x1e
- .4byte 0x1755
- .byte 0x30
- .uleb128 0xf
- .4byte .LASF401
- .byte 0x22
- .byte 0x23
- .4byte 0x176b
- .byte 0x38
- .uleb128 0xf
- .4byte .LASF402
- .byte 0x22
- .byte 0x25
- .4byte 0x1781
- .byte 0x40
- .uleb128 0xf
- .4byte .LASF403
- .byte 0x22
- .byte 0x2a
- .4byte 0x1755
- .byte 0x48
- .uleb128 0xf
- .4byte .LASF404
- .byte 0x22
- .byte 0x2b
- .4byte 0x1755
- .byte 0x50
- .uleb128 0xf
- .4byte .LASF35
- .byte 0x22
- .byte 0x2f
- .4byte 0x135
- .byte 0x58
- .uleb128 0xf
- .4byte .LASF405
- .byte 0x22
- .byte 0x30
- .4byte 0x290
- .byte 0x60
- .byte 0
- .uleb128 0x13
- .4byte 0x59
- .4byte 0x174f
- .uleb128 0x14
- .4byte 0x174f
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x16af
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1740
- .uleb128 0x28
- .4byte 0x176b
- .uleb128 0x14
- .4byte 0x174f
- .uleb128 0x14
- .4byte 0xe7
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x175b
- .uleb128 0x28
- .4byte 0x1781
- .uleb128 0x14
- .4byte 0x174f
- .uleb128 0x14
- .4byte 0xd5
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x1771
- .uleb128 0xb
- .4byte 0x174f
- .4byte 0x1792
- .uleb128 0xc
- .byte 0
- .uleb128 0x5
- .4byte .LASF406
- .byte 0x22
- .byte 0x48
- .4byte 0x1787
- .uleb128 0xb
- .4byte 0xf3
- .4byte 0x17ad
- .uleb128 0x12
- .4byte 0xce
- .byte 0x2
- .byte 0
- .uleb128 0x5
- .4byte .LASF407
- .byte 0x22
- .byte 0x49
- .4byte 0x179d
- .uleb128 0xb
- .4byte 0x17c8
- .4byte 0x17c8
- .uleb128 0x12
- .4byte 0xce
- .byte 0x2
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x174f
- .uleb128 0x5
- .4byte .LASF408
- .byte 0x23
- .byte 0x15
- .4byte 0x17b8
- .uleb128 0xb
- .4byte 0x59
- .4byte 0x17e9
- .uleb128 0x12
- .4byte 0xce
- .byte 0x2
- .byte 0
- .uleb128 0x5
- .4byte .LASF409
- .byte 0x23
- .byte 0x1a
- .4byte 0x17d9
- .uleb128 0x25
- .byte 0x4
- .4byte 0x84
- .byte 0x2
- .byte 0x13
- .4byte 0x1831
- .uleb128 0x1c
- .4byte .LASF410
- .byte 0
- .uleb128 0x1c
- .4byte .LASF411
- .byte 0x1
- .uleb128 0x1c
- .4byte .LASF412
- .byte 0x2
- .uleb128 0x1c
- .4byte .LASF413
- .byte 0x3
- .uleb128 0x1c
- .4byte .LASF414
- .byte 0x4
- .uleb128 0x1c
- .4byte .LASF415
- .byte 0x5
- .uleb128 0x1c
- .4byte .LASF416
- .byte 0x6
- .uleb128 0x1c
- .4byte .LASF417
- .byte 0x7
- .byte 0
- .uleb128 0xb
- .4byte 0xdb
- .4byte 0x1841
- .uleb128 0x12
- .4byte 0xce
- .byte 0x6
- .byte 0
- .uleb128 0x8
- .4byte 0x1831
- .uleb128 0x2a
- .4byte .LASF418
- .byte 0x2
- .byte 0x1e
- .4byte 0x1841
- .uleb128 0x9
- .byte 0x3
- .8byte test_pattern
- .uleb128 0xb
- .4byte 0xa3
- .4byte 0x186b
- .uleb128 0x12
- .4byte 0xce
- .byte 0x6
- .byte 0
- .uleb128 0x8
- .4byte 0x185b
- .uleb128 0x2a
- .4byte .LASF419
- .byte 0x2
- .byte 0x28
- .4byte 0x186b
- .uleb128 0x9
- .byte 0x3
- .8byte test_pat_param
- .uleb128 0x2f
- .4byte .LASF420
- .byte 0x2
- .2byte 0x136
- .4byte 0x67c
- .uleb128 0x9
- .byte 0x3
- .8byte _u_boot_list_2_cmd_2_ddr_test
- .uleb128 0x30
- .4byte .LASF429
- .byte 0x4
- .byte 0x60
- .4byte 0x59
- .8byte .LFB271
- .8byte .LFE271-.LFB271
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x1b4f
- .uleb128 0x31
- .4byte .LASF421
- .byte 0x4
- .byte 0x60
- .4byte 0x109
- .4byte .LLST15
- .uleb128 0x31
- .4byte .LASF422
- .byte 0x4
- .byte 0x60
- .4byte 0x109
- .4byte .LLST16
- .uleb128 0x32
- .string "ret"
- .byte 0x4
- .byte 0x62
- .4byte 0x59
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x33
- .4byte 0x1bc3
- .8byte .LBB6
- .4byte .Ldebug_ranges0+0
- .byte 0x4
- .byte 0x64
- .4byte 0x1a2b
- .uleb128 0x34
- .4byte 0x1bde
- .4byte .LLST17
- .uleb128 0x34
- .4byte 0x1bd3
- .4byte .LLST18
- .uleb128 0x35
- .4byte .Ldebug_ranges0+0
- .uleb128 0x36
- .4byte 0x1be9
- .4byte .LLST19
- .uleb128 0x36
- .4byte 0x1bf2
- .4byte .LLST20
- .uleb128 0x36
- .4byte 0x1bfb
- .4byte .LLST21
- .uleb128 0x36
- .4byte 0x1c06
- .4byte .LLST22
- .uleb128 0x37
- .4byte 0x1c11
- .uleb128 0x36
- .4byte 0x1c1c
- .4byte .LLST23
- .uleb128 0x36
- .4byte 0x1c27
- .4byte .LLST24
- .uleb128 0x36
- .4byte 0x1c32
- .4byte .LLST25
- .uleb128 0x38
- .8byte .LVL64
- .4byte 0x26e7
- .4byte 0x1981
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x6
- .byte 0x11
- .sleb128 -2139062144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL66
- .4byte 0x26f3
- .4byte 0x199f
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x86
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL72
- .4byte 0x26f3
- .4byte 0x19b9
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x4
- .byte 0x8f
- .sleb128 192
- .byte 0x6
- .byte 0
- .uleb128 0x38
- .8byte .LVL76
- .4byte 0x26fe
- .4byte 0x19d7
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8c
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8c
- .sleb128 4
- .byte 0
- .uleb128 0x38
- .8byte .LVL78
- .4byte 0x26f3
- .4byte 0x19f6
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC10
- .byte 0
- .uleb128 0x3a
- .8byte .LVL79
- .4byte 0x26f3
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC11
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8c
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x8b
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .byte 0
- .byte 0
- .byte 0
- .uleb128 0x3b
- .4byte 0x1b4f
- .8byte .LBB15
- .4byte .Ldebug_ranges0+0x60
- .byte 0x4
- .byte 0x66
- .uleb128 0x3c
- .4byte 0x1b6a
- .uleb128 0x3c
- .4byte 0x1b5f
- .uleb128 0x35
- .4byte .Ldebug_ranges0+0x60
- .uleb128 0x36
- .4byte 0x1b75
- .4byte .LLST26
- .uleb128 0x36
- .4byte 0x1b7e
- .4byte .LLST27
- .uleb128 0x3d
- .4byte 0x1b87
- .uleb128 0x1
- .byte 0x66
- .uleb128 0x3d
- .4byte 0x1b92
- .uleb128 0x1
- .byte 0x69
- .uleb128 0x3d
- .4byte 0x1b9d
- .uleb128 0x1
- .byte 0x6b
- .uleb128 0x37
- .4byte 0x1ba8
- .uleb128 0x36
- .4byte 0x1bb1
- .4byte .LLST28
- .uleb128 0x38
- .8byte .LVL85
- .4byte 0x26f3
- .4byte 0x1aa0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL87
- .4byte 0x26e7
- .4byte 0x1ac4
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x86
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL91
- .4byte 0x26f3
- .4byte 0x1adc
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL96
- .4byte 0x26fe
- .4byte 0x1afa
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x87
- .sleb128 4
- .byte 0
- .uleb128 0x38
- .8byte .LVL99
- .4byte 0x26f3
- .4byte 0x1b19
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC14
- .byte 0
- .uleb128 0x3a
- .8byte .LVL100
- .4byte 0x26f3
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC15
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x89
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x8b
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x2
- .byte 0x86
- .sleb128 0
- .byte 0
- .byte 0
- .byte 0
- .byte 0
- .uleb128 0x3e
- .4byte .LASF426
- .byte 0x4
- .byte 0x36
- .4byte 0x59
- .byte 0x1
- .4byte 0x1bbd
- .uleb128 0x3f
- .4byte .LASF421
- .byte 0x4
- .byte 0x36
- .4byte 0x109
- .uleb128 0x3f
- .4byte .LASF422
- .byte 0x4
- .byte 0x36
- .4byte 0x109
- .uleb128 0x40
- .string "i"
- .byte 0x4
- .byte 0x38
- .4byte 0x109
- .uleb128 0x40
- .string "j"
- .byte 0x4
- .byte 0x38
- .4byte 0x109
- .uleb128 0x41
- .4byte .LASF423
- .byte 0x4
- .byte 0x39
- .4byte 0x109
- .uleb128 0x41
- .4byte .LASF378
- .byte 0x4
- .byte 0x39
- .4byte 0x109
- .uleb128 0x41
- .4byte .LASF424
- .byte 0x4
- .byte 0x3a
- .4byte 0x109
- .uleb128 0x40
- .string "p"
- .byte 0x4
- .byte 0x3b
- .4byte 0x1bbd
- .uleb128 0x41
- .4byte .LASF425
- .byte 0x4
- .byte 0x3c
- .4byte 0x109
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x42
- .uleb128 0x3e
- .4byte .LASF427
- .byte 0x4
- .byte 0xb
- .4byte 0x59
- .byte 0x1
- .4byte 0x1c3e
- .uleb128 0x3f
- .4byte .LASF421
- .byte 0x4
- .byte 0xb
- .4byte 0x109
- .uleb128 0x3f
- .4byte .LASF422
- .byte 0x4
- .byte 0xb
- .4byte 0x109
- .uleb128 0x40
- .string "i"
- .byte 0x4
- .byte 0xd
- .4byte 0xa8
- .uleb128 0x40
- .string "j"
- .byte 0x4
- .byte 0xd
- .4byte 0xa8
- .uleb128 0x41
- .4byte .LASF428
- .byte 0x4
- .byte 0xe
- .4byte 0xa8
- .uleb128 0x41
- .4byte .LASF423
- .byte 0x4
- .byte 0xe
- .4byte 0xa8
- .uleb128 0x41
- .4byte .LASF378
- .byte 0x4
- .byte 0xe
- .4byte 0xa8
- .uleb128 0x41
- .4byte .LASF424
- .byte 0x4
- .byte 0xf
- .4byte 0xa8
- .uleb128 0x40
- .string "p32"
- .byte 0x4
- .byte 0x10
- .4byte 0x1c3e
- .uleb128 0x41
- .4byte .LASF425
- .byte 0x4
- .byte 0x11
- .4byte 0x109
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0xb3
- .uleb128 0x30
- .4byte .LASF430
- .byte 0x3
- .byte 0xf
- .4byte 0x59
- .8byte .LFB268
- .8byte .LFE268-.LFB268
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x1e70
- .uleb128 0x31
- .4byte .LASF431
- .byte 0x3
- .byte 0xf
- .4byte 0x109
- .4byte .LLST9
- .uleb128 0x31
- .4byte .LASF377
- .byte 0x3
- .byte 0xf
- .4byte 0x109
- .4byte .LLST10
- .uleb128 0x42
- .4byte .LASF268
- .byte 0x3
- .byte 0x11
- .4byte 0x109
- .4byte .LLST11
- .uleb128 0x2a
- .4byte .LASF432
- .byte 0x3
- .byte 0x11
- .4byte 0x109
- .uleb128 0x1
- .byte 0x64
- .uleb128 0x42
- .4byte .LASF433
- .byte 0x3
- .byte 0x12
- .4byte 0x59
- .4byte .LLST12
- .uleb128 0x2a
- .4byte .LASF434
- .byte 0x3
- .byte 0x13
- .4byte 0x1e70
- .uleb128 0x2
- .byte 0x91
- .sleb128 -32
- .uleb128 0x43
- .string "col"
- .byte 0x3
- .byte 0x15
- .4byte 0xa8
- .4byte .LLST13
- .uleb128 0x2a
- .4byte .LASF435
- .byte 0x3
- .byte 0x15
- .4byte 0xa8
- .uleb128 0x1
- .byte 0x65
- .uleb128 0x42
- .4byte .LASF436
- .byte 0x3
- .byte 0x16
- .4byte 0x109
- .4byte .LLST14
- .uleb128 0x44
- .4byte .LASF483
- .byte 0x3
- .byte 0x3e
- .8byte .L31
- .uleb128 0x38
- .8byte .LVL38
- .4byte 0x270a
- .4byte 0x1d22
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x9
- .byte 0x3
- .8byte .LANCHOR1
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .byte 0
- .uleb128 0x38
- .8byte .LVL39
- .4byte 0x26f3
- .4byte 0x1d41
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC6
- .byte 0
- .uleb128 0x45
- .8byte .LVL40
- .4byte 0x2713
- .uleb128 0x38
- .8byte .LVL42
- .4byte 0x26f3
- .4byte 0x1d73
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC7
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL49
- .4byte 0x271e
- .4byte 0x1d92
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .byte 0
- .uleb128 0x38
- .8byte .LVL50
- .4byte 0x2729
- .4byte 0x1db7
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x89
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .byte 0
- .uleb128 0x38
- .8byte .LVL53
- .4byte 0x2729
- .4byte 0x1ddc
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .byte 0
- .uleb128 0x38
- .8byte .LVL54
- .4byte 0x2735
- .4byte 0x1e12
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x8
- .byte 0x84
- .sleb128 0
- .byte 0x88
- .sleb128 0
- .byte 0x22
- .byte 0x89
- .sleb128 0
- .byte 0x22
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x1
- .byte 0x31
- .byte 0
- .uleb128 0x38
- .8byte .LVL59
- .4byte 0x2729
- .4byte 0x1e43
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0xe
- .byte 0x85
- .sleb128 0
- .byte 0xc
- .4byte 0xffffffff
- .byte 0x1a
- .byte 0x84
- .sleb128 0
- .byte 0x22
- .byte 0x89
- .sleb128 0
- .byte 0x22
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .byte 0
- .uleb128 0x3a
- .8byte .LVL60
- .4byte 0x2735
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x3
- .byte 0x8f
- .sleb128 144
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x8
- .byte 0x20
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x1
- .byte 0x31
- .byte 0
- .byte 0
- .uleb128 0xb
- .4byte 0xa8
- .4byte 0x1e80
- .uleb128 0x12
- .4byte 0xce
- .byte 0x7
- .byte 0
- .uleb128 0x46
- .4byte .LASF448
- .byte 0x2
- .byte 0x62
- .4byte 0x59
- .8byte .LFB256
- .8byte .LFE256-.LFB256
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x2293
- .uleb128 0x31
- .4byte .LASF437
- .byte 0x2
- .byte 0x62
- .4byte 0x2293
- .4byte .LLST37
- .uleb128 0x31
- .4byte .LASF438
- .byte 0x2
- .byte 0x62
- .4byte 0x59
- .4byte .LLST38
- .uleb128 0x31
- .4byte .LASF439
- .byte 0x2
- .byte 0x62
- .4byte 0x59
- .4byte .LLST39
- .uleb128 0x31
- .4byte .LASF440
- .byte 0x2
- .byte 0x63
- .4byte 0x641
- .4byte .LLST40
- .uleb128 0x43
- .string "i"
- .byte 0x2
- .byte 0x65
- .4byte 0x59
- .4byte .LLST41
- .uleb128 0x42
- .4byte .LASF441
- .byte 0x2
- .byte 0x66
- .4byte 0x59
- .4byte .LLST42
- .uleb128 0x42
- .4byte .LASF442
- .byte 0x2
- .byte 0x66
- .4byte 0x59
- .4byte .LLST43
- .uleb128 0x32
- .string "arg"
- .byte 0x2
- .byte 0x67
- .4byte 0x2299
- .uleb128 0x2
- .byte 0x91
- .sleb128 -40
- .uleb128 0x2a
- .4byte .LASF431
- .byte 0x2
- .byte 0x68
- .4byte 0x22a9
- .uleb128 0x3
- .byte 0x91
- .sleb128 -104
- .uleb128 0x2a
- .4byte .LASF377
- .byte 0x2
- .byte 0x69
- .4byte 0x22a9
- .uleb128 0x3
- .byte 0x91
- .sleb128 -72
- .uleb128 0x42
- .4byte .LASF443
- .byte 0x2
- .byte 0x6a
- .4byte 0xa8
- .4byte .LLST44
- .uleb128 0x42
- .4byte .LASF444
- .byte 0x2
- .byte 0x6b
- .4byte 0xa8
- .4byte .LLST45
- .uleb128 0x42
- .4byte .LASF445
- .byte 0x2
- .byte 0x6c
- .4byte 0xa8
- .4byte .LLST46
- .uleb128 0x43
- .string "ret"
- .byte 0x2
- .byte 0x6d
- .4byte 0x59
- .4byte .LLST47
- .uleb128 0x42
- .4byte .LASF446
- .byte 0x2
- .byte 0x6e
- .4byte 0x59
- .4byte .LLST48
- .uleb128 0x42
- .4byte .LASF447
- .byte 0x2
- .byte 0x6f
- .4byte 0xa8
- .4byte .LLST49
- .uleb128 0x32
- .string "dev"
- .byte 0x2
- .byte 0x91
- .4byte 0x25d
- .uleb128 0x3
- .byte 0x91
- .sleb128 -112
- .uleb128 0x38
- .8byte .LVL132
- .4byte 0x26f3
- .4byte 0x1fbc
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC18
- .byte 0
- .uleb128 0x38
- .8byte .LVL133
- .4byte 0x2740
- .4byte 0x1fdf
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x1
- .byte 0x31
- .byte 0
- .uleb128 0x38
- .8byte .LVL135
- .4byte 0x274b
- .4byte 0x1ffd
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x8
- .byte 0x89
- .sleb128 0
- .byte 0x33
- .byte 0x24
- .byte 0x8b
- .sleb128 0
- .byte 0x22
- .byte 0x6
- .byte 0
- .uleb128 0x45
- .8byte .LVL139
- .4byte 0x26f3
- .uleb128 0x38
- .8byte .LVL141
- .4byte 0x2756
- .4byte 0x202d
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x1
- .byte 0x30
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x8
- .byte 0x8f
- .sleb128 0
- .byte 0x8b
- .sleb128 0
- .byte 0x22
- .byte 0x23
- .uleb128 0x110
- .byte 0
- .uleb128 0x45
- .8byte .LVL143
- .4byte 0x2761
- .uleb128 0x45
- .8byte .LVL144
- .4byte 0x23eb
- .uleb128 0x45
- .8byte .LVL145
- .4byte 0x241b
- .uleb128 0x38
- .8byte .LVL146
- .4byte 0x26f3
- .4byte 0x2073
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC26
- .byte 0
- .uleb128 0x45
- .8byte .LVL148
- .4byte 0x23eb
- .uleb128 0x45
- .8byte .LVL149
- .4byte 0x22b9
- .uleb128 0x45
- .8byte .LVL150
- .4byte 0x23eb
- .uleb128 0x38
- .8byte .LVL161
- .4byte 0x26f3
- .4byte 0x20b8
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x89
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL162
- .4byte 0x26f3
- .4byte 0x20d6
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8b
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .byte 0
- .uleb128 0x45
- .8byte .LVL163
- .4byte 0x241b
- .uleb128 0x45
- .8byte .LVL164
- .4byte 0x189b
- .uleb128 0x45
- .8byte .LVL167
- .4byte 0x244c
- .uleb128 0x45
- .8byte .LVL170
- .4byte 0x1c44
- .uleb128 0x38
- .8byte .LVL173
- .4byte 0x22b9
- .4byte 0x2126
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x6
- .byte 0x8c
- .sleb128 0
- .byte 0xa
- .2byte 0x3fc
- .byte 0x1a
- .byte 0
- .uleb128 0x45
- .8byte .LVL176
- .4byte 0x241b
- .uleb128 0x45
- .8byte .LVL177
- .4byte 0x189b
- .uleb128 0x45
- .8byte .LVL180
- .4byte 0x244c
- .uleb128 0x45
- .8byte .LVL183
- .4byte 0x1c44
- .uleb128 0x45
- .8byte .LVL185
- .4byte 0x276c
- .uleb128 0x38
- .8byte .LVL192
- .4byte 0x26f3
- .4byte 0x2198
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC25
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0xe
- .byte 0x86
- .sleb128 0
- .byte 0x33
- .byte 0x24
- .byte 0x9
- .byte 0xe5
- .byte 0x24
- .byte 0x9
- .byte 0xe5
- .byte 0x26
- .byte 0x88
- .sleb128 0
- .byte 0x22
- .byte 0x6
- .byte 0
- .uleb128 0x38
- .8byte .LVL195
- .4byte 0x26f3
- .4byte 0x21bc
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC28
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x1
- .byte 0x3a
- .byte 0
- .uleb128 0x38
- .8byte .LVL205
- .4byte 0x2777
- .4byte 0x21e1
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x3
- .byte 0x8f
- .sleb128 296
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x45
- .8byte .LVL208
- .4byte 0x241b
- .uleb128 0x45
- .8byte .LVL209
- .4byte 0x23eb
- .uleb128 0x38
- .8byte .LVL213
- .4byte 0x26f3
- .4byte 0x2219
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x89
- .sleb128 0
- .byte 0
- .uleb128 0x45
- .8byte .LVL218
- .4byte 0x189b
- .uleb128 0x45
- .8byte .LVL220
- .4byte 0x276c
- .uleb128 0x45
- .8byte .LVL223
- .4byte 0x244c
- .uleb128 0x45
- .8byte .LVL224
- .4byte 0x1c44
- .uleb128 0x38
- .8byte .LVL231
- .4byte 0x2782
- .4byte 0x2271
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8
- .byte 0x35
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x1
- .byte 0x30
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x3
- .byte 0x8f
- .sleb128 208
- .byte 0
- .uleb128 0x3a
- .8byte .LVL234
- .4byte 0x26f3
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC21
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .byte 0
- .byte 0
- .uleb128 0x9
- .byte 0x8
- .4byte 0x67c
- .uleb128 0xb
- .4byte 0x109
- .4byte 0x22a9
- .uleb128 0x12
- .4byte 0xce
- .byte 0x4
- .byte 0
- .uleb128 0xb
- .4byte 0x109
- .4byte 0x22b9
- .uleb128 0x12
- .4byte 0xce
- .byte 0x3
- .byte 0
- .uleb128 0x46
- .4byte .LASF449
- .byte 0x2
- .byte 0x36
- .4byte 0x59
- .8byte .LFB255
- .8byte .LFE255-.LFB255
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x23eb
- .uleb128 0x31
- .4byte .LASF450
- .byte 0x2
- .byte 0x36
- .4byte 0xa8
- .4byte .LLST29
- .uleb128 0x31
- .4byte .LASF451
- .byte 0x2
- .byte 0x36
- .4byte 0xa8
- .4byte .LLST30
- .uleb128 0x31
- .4byte .LASF452
- .byte 0x2
- .byte 0x36
- .4byte 0x109
- .4byte .LLST31
- .uleb128 0x43
- .string "i"
- .byte 0x2
- .byte 0x39
- .4byte 0xa8
- .4byte .LLST32
- .uleb128 0x42
- .4byte .LASF453
- .byte 0x2
- .byte 0x3a
- .4byte 0xa8
- .4byte .LLST33
- .uleb128 0x42
- .4byte .LASF454
- .byte 0x2
- .byte 0x3a
- .4byte 0xa8
- .4byte .LLST34
- .uleb128 0x42
- .4byte .LASF455
- .byte 0x2
- .byte 0x3a
- .4byte 0xa8
- .4byte .LLST35
- .uleb128 0x43
- .string "ret"
- .byte 0x2
- .byte 0x3b
- .4byte 0x59
- .4byte .LLST36
- .uleb128 0x45
- .8byte .LVL111
- .4byte 0x278d
- .uleb128 0x38
- .8byte .LVL113
- .4byte 0x26f3
- .4byte 0x2381
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL114
- .4byte 0x241b
- .4byte 0x239f
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x8
- .byte 0x84
- .sleb128 0
- .byte 0xc
- .4byte 0xffffffc0
- .byte 0x1a
- .byte 0
- .uleb128 0x38
- .8byte .LVL117
- .4byte 0x189b
- .4byte 0x23b8
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x3
- .byte 0x40
- .byte 0x40
- .byte 0x24
- .byte 0
- .uleb128 0x38
- .8byte .LVL120
- .4byte 0x26f3
- .4byte 0x23dd
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC17
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8a
- .sleb128 0
- .byte 0
- .uleb128 0x45
- .8byte .LVL125
- .4byte 0x276c
- .byte 0
- .uleb128 0x30
- .4byte .LASF456
- .byte 0x2
- .byte 0x31
- .4byte 0x59
- .8byte .LFB254
- .8byte .LFE254-.LFB254
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x241b
- .uleb128 0x47
- .string "uv"
- .byte 0x2
- .byte 0x31
- .4byte 0xa8
- .4byte .LLST8
- .byte 0
- .uleb128 0x30
- .4byte .LASF457
- .byte 0x2
- .byte 0x2c
- .4byte 0x59
- .8byte .LFB253
- .8byte .LFE253-.LFB253
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x244c
- .uleb128 0x31
- .4byte .LASF455
- .byte 0x2
- .byte 0x2c
- .4byte 0x109
- .4byte .LLST7
- .byte 0
- .uleb128 0x30
- .4byte .LASF458
- .byte 0x1
- .byte 0x2d
- .4byte 0x59
- .8byte .LFB200
- .8byte .LFE200-.LFB200
- .uleb128 0x1
- .byte 0x9c
- .4byte 0x26d2
- .uleb128 0x31
- .4byte .LASF431
- .byte 0x1
- .byte 0x2d
- .4byte 0x109
- .4byte .LLST0
- .uleb128 0x31
- .4byte .LASF377
- .byte 0x1
- .byte 0x2d
- .4byte 0x109
- .4byte .LLST1
- .uleb128 0x42
- .4byte .LASF459
- .byte 0x1
- .byte 0x2f
- .4byte 0xa8
- .4byte .LLST2
- .uleb128 0x43
- .string "i"
- .byte 0x1
- .byte 0x2f
- .4byte 0xa8
- .4byte .LLST3
- .uleb128 0x43
- .string "j"
- .byte 0x1
- .byte 0x2f
- .4byte 0xa8
- .4byte .LLST4
- .uleb128 0x43
- .string "q"
- .byte 0x1
- .byte 0x2f
- .4byte 0xa8
- .4byte .LLST5
- .uleb128 0x32
- .string "buf"
- .byte 0x1
- .byte 0x30
- .4byte 0x1e70
- .uleb128 0x2
- .byte 0x91
- .sleb128 -32
- .uleb128 0x43
- .string "p"
- .byte 0x1
- .byte 0x31
- .4byte 0x1379
- .4byte .LLST6
- .uleb128 0x48
- .4byte .LASF460
- .4byte 0x26e2
- .uleb128 0x9
- .byte 0x3
- .8byte .LC35
- .uleb128 0x38
- .8byte .LVL2
- .4byte 0x26f3
- .4byte 0x250e
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC1
- .byte 0
- .uleb128 0x38
- .8byte .LVL4
- .4byte 0x26f3
- .4byte 0x252e
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x4
- .byte 0x8f
- .sleb128 200
- .byte 0x6
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL6
- .4byte 0x26f3
- .4byte 0x254e
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x4
- .byte 0x8f
- .sleb128 192
- .byte 0x6
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8b
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL8
- .4byte 0x271e
- .4byte 0x256c
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL9
- .4byte 0x2799
- .4byte 0x2596
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL10
- .4byte 0x2735
- .4byte 0x25c5
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x1
- .byte 0x31
- .byte 0
- .uleb128 0x38
- .8byte .LVL16
- .4byte 0x26f3
- .4byte 0x25e4
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC4
- .byte 0
- .uleb128 0x38
- .8byte .LVL17
- .4byte 0x27a4
- .4byte 0x25fc
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8
- .byte 0x80
- .byte 0
- .uleb128 0x38
- .8byte .LVL20
- .4byte 0x26f3
- .4byte 0x2621
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x9
- .byte 0x3
- .8byte .LC5
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x8
- .byte 0x80
- .byte 0
- .uleb128 0x38
- .8byte .LVL23
- .4byte 0x26f3
- .4byte 0x263f
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x8b
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x84
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL24
- .4byte 0x26f3
- .4byte 0x265d
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x89
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x86
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL26
- .4byte 0x271e
- .4byte 0x267b
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .byte 0
- .uleb128 0x38
- .8byte .LVL27
- .4byte 0x2799
- .4byte 0x26a5
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .byte 0
- .uleb128 0x3a
- .8byte .LVL28
- .4byte 0x2735
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x50
- .uleb128 0x2
- .byte 0x85
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x51
- .uleb128 0x2
- .byte 0x83
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x52
- .uleb128 0x2
- .byte 0x87
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x53
- .uleb128 0x2
- .byte 0x88
- .sleb128 0
- .uleb128 0x39
- .uleb128 0x1
- .byte 0x54
- .uleb128 0x2
- .byte 0x8c
- .sleb128 0
- .byte 0
- .byte 0
- .uleb128 0xb
- .4byte 0xe7
- .4byte 0x26e2
- .uleb128 0x12
- .4byte 0xce
- .byte 0x9
- .byte 0
- .uleb128 0x8
- .4byte 0x26d2
- .uleb128 0x49
- .4byte .LASF461
- .4byte .LASF461
- .byte 0x1d
- .2byte 0x16c
- .uleb128 0x4a
- .4byte .LASF462
- .4byte .LASF462
- .byte 0x25
- .byte 0x12
- .uleb128 0x49
- .4byte .LASF463
- .4byte .LASF463
- .byte 0x5
- .2byte 0x258
- .uleb128 0x4b
- .4byte .LASF466
- .4byte .LASF466
- .uleb128 0x4a
- .4byte .LASF464
- .4byte .LASF464
- .byte 0x26
- .byte 0x5f
- .uleb128 0x4a
- .4byte .LASF465
- .4byte .LASF465
- .byte 0x27
- .byte 0xb
- .uleb128 0x49
- .4byte .LASF466
- .4byte .LASF466
- .byte 0x1d
- .2byte 0x16d
- .uleb128 0x4a
- .4byte .LASF467
- .4byte .LASF467
- .byte 0x28
- .byte 0xe
- .uleb128 0x4a
- .4byte .LASF468
- .4byte .LASF468
- .byte 0x28
- .byte 0x11
- .uleb128 0x4a
- .4byte .LASF469
- .4byte .LASF469
- .byte 0x9
- .byte 0x2d
- .uleb128 0x4a
- .4byte .LASF470
- .4byte .LASF470
- .byte 0x29
- .byte 0x29
- .uleb128 0x4a
- .4byte .LASF471
- .4byte .LASF471
- .byte 0x27
- .byte 0xc
- .uleb128 0x4a
- .4byte .LASF472
- .4byte .LASF472
- .byte 0x21
- .byte 0x11
- .uleb128 0x4a
- .4byte .LASF473
- .4byte .LASF473
- .byte 0x28
- .byte 0x12
- .uleb128 0x4a
- .4byte .LASF474
- .4byte .LASF474
- .byte 0x20
- .byte 0x94
- .uleb128 0x49
- .4byte .LASF475
- .4byte .LASF475
- .byte 0x5
- .2byte 0x2b9
- .uleb128 0x4a
- .4byte .LASF476
- .4byte .LASF476
- .byte 0x28
- .byte 0xd
- .uleb128 0x49
- .4byte .LASF477
- .4byte .LASF477
- .byte 0x1d
- .2byte 0x398
- .byte 0
- .section .debug_abbrev,"",@progbits
-.Ldebug_abbrev0:
- .uleb128 0x1
- .uleb128 0x11
- .byte 0x1
- .uleb128 0x25
- .uleb128 0xe
- .uleb128 0x13
- .uleb128 0xb
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x1b
- .uleb128 0xe
- .uleb128 0x55
- .uleb128 0x17
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x10
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x2
- .uleb128 0x16
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x3
- .uleb128 0x24
- .byte 0
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3e
- .uleb128 0xb
- .uleb128 0x3
- .uleb128 0xe
- .byte 0
- .byte 0
- .uleb128 0x4
- .uleb128 0x35
- .byte 0
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x5
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .byte 0
- .byte 0
- .uleb128 0x6
- .uleb128 0x24
- .byte 0
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3e
- .uleb128 0xb
- .uleb128 0x3
- .uleb128 0x8
- .byte 0
- .byte 0
- .uleb128 0x7
- .uleb128 0x16
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x8
- .uleb128 0x26
- .byte 0
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x9
- .uleb128 0xf
- .byte 0
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0xa
- .uleb128 0xf
- .byte 0
- .uleb128 0xb
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0xb
- .uleb128 0x1
- .byte 0x1
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0xc
- .uleb128 0x21
- .byte 0
- .byte 0
- .byte 0
- .uleb128 0xd
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .byte 0
- .byte 0
- .uleb128 0xe
- .uleb128 0x13
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0xf
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x10
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x11
- .uleb128 0x26
- .byte 0
- .byte 0
- .byte 0
- .uleb128 0x12
- .uleb128 0x21
- .byte 0
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2f
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x13
- .uleb128 0x15
- .byte 0x1
- .uleb128 0x27
- .uleb128 0x19
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x14
- .uleb128 0x5
- .byte 0
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x15
- .uleb128 0x13
- .byte 0x1
- .uleb128 0xb
- .uleb128 0x5
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x16
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0x5
- .byte 0
- .byte 0
- .uleb128 0x17
- .uleb128 0x21
- .byte 0
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2f
- .uleb128 0x5
- .byte 0
- .byte 0
- .uleb128 0x18
- .uleb128 0x13
- .byte 0x1
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0xb
- .uleb128 0x5
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x19
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .byte 0
- .byte 0
- .uleb128 0x1a
- .uleb128 0x13
- .byte 0x1
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x1b
- .uleb128 0x4
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x1c
- .uleb128 0x28
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x1c
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x1d
- .uleb128 0x28
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x1c
- .uleb128 0xd
- .byte 0
- .byte 0
- .uleb128 0x1e
- .uleb128 0x13
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x1f
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x20
- .uleb128 0x16
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x21
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x22
- .uleb128 0x13
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0x5
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x23
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0x5
- .byte 0
- .byte 0
- .uleb128 0x24
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x38
- .uleb128 0x5
- .byte 0
- .byte 0
- .uleb128 0x25
- .uleb128 0x4
- .byte 0x1
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x26
- .uleb128 0x13
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0x5
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x27
- .uleb128 0x13
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3c
- .uleb128 0x19
- .byte 0
- .byte 0
- .uleb128 0x28
- .uleb128 0x15
- .byte 0x1
- .uleb128 0x27
- .uleb128 0x19
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x29
- .uleb128 0x4
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x2a
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x2b
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3f
- .uleb128 0x19
- .byte 0
- .byte 0
- .uleb128 0x2c
- .uleb128 0x17
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0xb
- .uleb128 0xb
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x2d
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x2e
- .uleb128 0xd
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x2f
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x2
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x30
- .uleb128 0x2e
- .byte 0x1
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x27
- .uleb128 0x19
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x12
- .uleb128 0x7
- .uleb128 0x40
- .uleb128 0x18
- .uleb128 0x2117
- .uleb128 0x19
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x31
- .uleb128 0x5
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x32
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x33
- .uleb128 0x1d
- .byte 0x1
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x52
- .uleb128 0x1
- .uleb128 0x55
- .uleb128 0x17
- .uleb128 0x58
- .uleb128 0xb
- .uleb128 0x59
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x34
- .uleb128 0x5
- .byte 0
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x35
- .uleb128 0xb
- .byte 0x1
- .uleb128 0x55
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x36
- .uleb128 0x34
- .byte 0
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x37
- .uleb128 0x34
- .byte 0
- .uleb128 0x31
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x38
- .uleb128 0x4109
- .byte 0x1
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x39
- .uleb128 0x410a
- .byte 0
- .uleb128 0x2
- .uleb128 0x18
- .uleb128 0x2111
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x3a
- .uleb128 0x4109
- .byte 0x1
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x31
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x3b
- .uleb128 0x1d
- .byte 0x1
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x52
- .uleb128 0x1
- .uleb128 0x55
- .uleb128 0x17
- .uleb128 0x58
- .uleb128 0xb
- .uleb128 0x59
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x3c
- .uleb128 0x5
- .byte 0
- .uleb128 0x31
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x3d
- .uleb128 0x34
- .byte 0
- .uleb128 0x31
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x3e
- .uleb128 0x2e
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x27
- .uleb128 0x19
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x20
- .uleb128 0xb
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x3f
- .uleb128 0x5
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x40
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x41
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x42
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x43
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x44
- .uleb128 0xa
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x11
- .uleb128 0x1
- .byte 0
- .byte 0
- .uleb128 0x45
- .uleb128 0x4109
- .byte 0
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x31
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x46
- .uleb128 0x2e
- .byte 0x1
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x27
- .uleb128 0x19
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x11
- .uleb128 0x1
- .uleb128 0x12
- .uleb128 0x7
- .uleb128 0x40
- .uleb128 0x18
- .uleb128 0x2117
- .uleb128 0x19
- .uleb128 0x1
- .uleb128 0x13
- .byte 0
- .byte 0
- .uleb128 0x47
- .uleb128 0x5
- .byte 0
- .uleb128 0x3
- .uleb128 0x8
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x2
- .uleb128 0x17
- .byte 0
- .byte 0
- .uleb128 0x48
- .uleb128 0x34
- .byte 0
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x49
- .uleb128 0x13
- .uleb128 0x34
- .uleb128 0x19
- .uleb128 0x2
- .uleb128 0x18
- .byte 0
- .byte 0
- .uleb128 0x49
- .uleb128 0x2e
- .byte 0
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .uleb128 0x6e
- .uleb128 0xe
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0x5
- .byte 0
- .byte 0
- .uleb128 0x4a
- .uleb128 0x2e
- .byte 0
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .uleb128 0x6e
- .uleb128 0xe
- .uleb128 0x3
- .uleb128 0xe
- .uleb128 0x3a
- .uleb128 0xb
- .uleb128 0x3b
- .uleb128 0xb
- .byte 0
- .byte 0
- .uleb128 0x4b
- .uleb128 0x2e
- .byte 0
- .uleb128 0x3f
- .uleb128 0x19
- .uleb128 0x3c
- .uleb128 0x19
- .uleb128 0x6e
- .uleb128 0xe
- .uleb128 0x3
- .uleb128 0xe
- .byte 0
- .byte 0
- .byte 0
- .section .debug_loc,"",@progbits
-.Ldebug_loc0:
-.LLST15:
- .8byte .LVL61
- .8byte .LVL64-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL64-1
- .8byte .LVL80
- .2byte 0x1
- .byte 0x63
- .8byte .LVL80
- .8byte .LVL81
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST16:
- .8byte .LVL61
- .8byte .LVL63
- .2byte 0x1
- .byte 0x51
- .8byte .LVL63
- .8byte .LVL64-1
- .2byte 0x1
- .byte 0x52
- .8byte .LVL64-1
- .8byte .LVL80
- .2byte 0x1
- .byte 0x64
- .8byte .LVL80
- .8byte .LVL81
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x51
- .byte 0x9f
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x1
- .byte 0x64
- .8byte 0
- .8byte 0
-.LLST17:
- .8byte .LVL62
- .8byte .LVL63
- .2byte 0x1
- .byte 0x51
- .8byte .LVL63
- .8byte .LVL64-1
- .2byte 0x1
- .byte 0x52
- .8byte .LVL64-1
- .8byte .LVL79
- .2byte 0x1
- .byte 0x64
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x1
- .byte 0x64
- .8byte 0
- .8byte 0
-.LLST18:
- .8byte .LVL62
- .8byte .LVL64-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL64-1
- .8byte .LVL79
- .2byte 0x1
- .byte 0x63
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST19:
- .8byte .LVL66
- .8byte .LVL67
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL67
- .8byte .LVL68
- .2byte 0x1
- .byte 0x51
- .8byte .LVL73
- .8byte .LVL75
- .2byte 0x1
- .byte 0x51
- .8byte .LVL81
- .8byte .LVL83
- .2byte 0x1
- .byte 0x51
- .8byte 0
- .8byte 0
-.LLST20:
- .8byte .LVL64
- .8byte .LVL65
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL65
- .8byte .LVL69
- .2byte 0x1
- .byte 0x66
- .8byte .LVL69
- .8byte .LVL72
- .2byte 0x3
- .byte 0x86
- .sleb128 -1
- .byte 0x9f
- .8byte .LVL72
- .8byte .LVL79
- .2byte 0x1
- .byte 0x66
- .8byte .LVL81
- .8byte .LVL84
- .2byte 0x1
- .byte 0x66
- .8byte 0
- .8byte 0
-.LLST21:
- .8byte .LVL64
- .8byte .LVL65
- .2byte 0x6
- .byte 0x9e
- .uleb128 0x4
- .4byte 0x80808080
- .8byte .LVL65
- .8byte .LVL79
- .2byte 0x1
- .byte 0x65
- .8byte .LVL81
- .8byte .LVL84
- .2byte 0x1
- .byte 0x65
- .8byte 0
- .8byte 0
-.LLST22:
- .8byte .LVL64
- .8byte .LVL65
- .2byte 0x6
- .byte 0xc
- .4byte 0x40404040
- .byte 0x9f
- .8byte .LVL65
- .8byte .LVL79
- .2byte 0x1
- .byte 0x67
- .8byte .LVL81
- .8byte .LVL84
- .2byte 0x1
- .byte 0x67
- .8byte 0
- .8byte 0
-.LLST23:
- .8byte .LVL62
- .8byte .LVL65
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST24:
- .8byte .LVL64
- .8byte .LVL80
- .2byte 0x1
- .byte 0x63
- .8byte .LVL80
- .8byte .LVL81
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST25:
- .8byte .LVL62
- .8byte .LVL68
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte .LVL72
- .8byte .LVL74
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte .LVL74
- .8byte .LVL76-1
- .2byte 0x1
- .byte 0x55
- .8byte .LVL76-1
- .8byte .LVL79
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL81
- .8byte .LFE271
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST26:
- .8byte .LVL87
- .8byte .LVL88
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL88
- .8byte .LVL89
- .2byte 0x1
- .byte 0x50
- .8byte .LVL92
- .8byte .LVL95
- .2byte 0x1
- .byte 0x50
- .8byte .LVL101
- .8byte .LFE271
- .2byte 0x1
- .byte 0x50
- .8byte 0
- .8byte 0
-.LLST27:
- .8byte .LVL84
- .8byte .LVL90
- .2byte 0x1
- .byte 0x65
- .8byte .LVL90
- .8byte .LVL91
- .2byte 0x3
- .byte 0x85
- .sleb128 -1
- .byte 0x9f
- .8byte .LVL91
- .8byte .LFE271
- .2byte 0x1
- .byte 0x65
- .8byte 0
- .8byte 0
-.LLST28:
- .8byte .LVL84
- .8byte .LVL89
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte .LVL91
- .8byte .LVL94
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte .LVL94
- .8byte .LVL101
- .2byte 0x1
- .byte 0x67
- .8byte .LVL101
- .8byte .LFE271
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST9:
- .8byte .LVL35
- .8byte .LVL37
- .2byte 0x1
- .byte 0x50
- .8byte .LVL37
- .8byte .LVL45
- .2byte 0x1
- .byte 0x69
- .8byte .LVL45
- .8byte .LVL46
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte .LVL46
- .8byte .LFE268
- .2byte 0x1
- .byte 0x69
- .8byte 0
- .8byte 0
-.LLST10:
- .8byte .LVL35
- .8byte .LVL36
- .2byte 0x1
- .byte 0x51
- .8byte .LVL36
- .8byte .LVL43
- .2byte 0x1
- .byte 0x66
- .8byte .LVL43
- .8byte .LVL46
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x51
- .byte 0x9f
- .8byte .LVL46
- .8byte .LVL47
- .2byte 0x1
- .byte 0x66
- .8byte .LVL47
- .8byte .LVL48
- .2byte 0x3
- .byte 0x87
- .sleb128 32
- .byte 0x9f
- .8byte .LVL48
- .8byte .LFE268
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x51
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST11:
- .8byte .LVL50
- .8byte .LVL55
- .2byte 0x1
- .byte 0x64
- .8byte 0
- .8byte 0
-.LLST12:
- .8byte .LVL41
- .8byte .LVL44
- .2byte 0x1
- .byte 0x63
- .8byte .LVL46
- .8byte .LFE268
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST13:
- .8byte .LVL50
- .8byte .LVL56
- .2byte 0x1
- .byte 0x65
- .8byte .LVL56
- .8byte .LVL57
- .2byte 0x3
- .byte 0x85
- .sleb128 -8
- .byte 0x9f
- .8byte .LVL57
- .8byte .LFE268
- .2byte 0x3
- .byte 0x88
- .sleb128 -40
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST14:
- .8byte .LVL38
- .8byte .LVL43
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL46
- .8byte .LVL51
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL51
- .8byte .LVL52
- .2byte 0x1
- .byte 0x50
- .8byte .LVL52
- .8byte .LVL54
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL54
- .8byte .LVL58
- .2byte 0x1
- .byte 0x50
- .8byte .LVL60
- .8byte .LFE268
- .2byte 0x1
- .byte 0x50
- .8byte 0
- .8byte 0
-.LLST37:
- .8byte .LVL129
- .8byte .LVL130
- .2byte 0x1
- .byte 0x50
- .8byte .LVL130
- .8byte .LFE256
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST38:
- .8byte .LVL129
- .8byte .LVL132-1
- .2byte 0x1
- .byte 0x51
- .8byte .LVL132-1
- .8byte .LFE256
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x51
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST39:
- .8byte .LVL129
- .8byte .LVL132-1
- .2byte 0x1
- .byte 0x52
- .8byte .LVL132-1
- .8byte .LVL138
- .2byte 0x1
- .byte 0x67
- .8byte .LVL138
- .8byte .LVL228
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x52
- .byte 0x9f
- .8byte .LVL228
- .8byte .LVL229
- .2byte 0x1
- .byte 0x67
- .8byte .LVL229
- .8byte .LFE256
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x52
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST40:
- .8byte .LVL129
- .8byte .LVL132-1
- .2byte 0x1
- .byte 0x53
- .8byte .LVL132-1
- .8byte .LVL145
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL145
- .8byte .LVL147
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x53
- .byte 0x9f
- .8byte .LVL147
- .8byte .LVL158
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL158
- .8byte .LVL193
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x53
- .byte 0x9f
- .8byte .LVL193
- .8byte .LVL196
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL196
- .8byte .LVL204
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x53
- .byte 0x9f
- .8byte .LVL204
- .8byte .LVL210
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL210
- .8byte .LVL226
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x53
- .byte 0x9f
- .8byte .LVL226
- .8byte .LVL234
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL234
- .8byte .LFE256
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x53
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST41:
- .8byte .LVL134
- .8byte .LVL136
- .2byte 0x1
- .byte 0x63
- .8byte .LVL136
- .8byte .LVL137
- .2byte 0x3
- .byte 0x83
- .sleb128 1
- .byte 0x9f
- .8byte .LVL137
- .8byte .LVL138
- .2byte 0x1
- .byte 0x63
- .8byte .LVL151
- .8byte .LVL153
- .2byte 0x1
- .byte 0x50
- .8byte .LVL153
- .8byte .LVL154
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL154
- .8byte .LVL155
- .2byte 0x1
- .byte 0x50
- .8byte .LVL155
- .8byte .LVL156
- .2byte 0x3
- .byte 0x70
- .sleb128 1
- .byte 0x9f
- .8byte .LVL161
- .8byte .LVL186
- .2byte 0x1
- .byte 0x63
- .8byte .LVL186
- .8byte .LVL187
- .2byte 0x3
- .byte 0x83
- .sleb128 1
- .byte 0x9f
- .8byte .LVL193
- .8byte .LVL194
- .2byte 0x3
- .byte 0x70
- .sleb128 1
- .byte 0x9f
- .8byte .LVL196
- .8byte .LVL204
- .2byte 0x1
- .byte 0x63
- .8byte .LVL213
- .8byte .LVL214
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL217
- .8byte .LVL221
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL222
- .8byte .LVL226
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL228
- .8byte .LVL230
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST42:
- .8byte .LVL137
- .8byte .LVL138
- .2byte 0x1
- .byte 0x63
- .8byte .LVL140
- .8byte .LVL145
- .2byte 0x1
- .byte 0x63
- .8byte .LVL147
- .8byte .LVL159
- .2byte 0x1
- .byte 0x63
- .8byte .LVL193
- .8byte .LVL196
- .2byte 0x1
- .byte 0x63
- .8byte .LVL204
- .8byte .LVL234
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST43:
- .8byte .LVL165
- .8byte .LVL168
- .2byte 0x2
- .byte 0x32
- .byte 0x9f
- .8byte .LVL168
- .8byte .LVL171
- .2byte 0x2
- .byte 0x33
- .byte 0x9f
- .8byte .LVL171
- .8byte .LVL174
- .2byte 0x2
- .byte 0x34
- .byte 0x9f
- .8byte .LVL178
- .8byte .LVL181
- .2byte 0x2
- .byte 0x32
- .byte 0x9f
- .8byte .LVL181
- .8byte .LVL184
- .2byte 0x2
- .byte 0x33
- .byte 0x9f
- .8byte .LVL184
- .8byte .LVL186
- .2byte 0x2
- .byte 0x34
- .byte 0x9f
- .8byte .LVL196
- .8byte .LVL197
- .2byte 0x2
- .byte 0x32
- .byte 0x9f
- .8byte .LVL197
- .8byte .LVL198
- .2byte 0x2
- .byte 0x33
- .byte 0x9f
- .8byte .LVL198
- .8byte .LVL199
- .2byte 0x2
- .byte 0x34
- .byte 0x9f
- .8byte .LVL200
- .8byte .LVL201
- .2byte 0x2
- .byte 0x32
- .byte 0x9f
- .8byte .LVL201
- .8byte .LVL202
- .2byte 0x2
- .byte 0x33
- .byte 0x9f
- .8byte .LVL202
- .8byte .LVL204
- .2byte 0x2
- .byte 0x34
- .byte 0x9f
- .8byte .LVL219
- .8byte .LVL222
- .2byte 0x1
- .byte 0x63
- .8byte .LVL225
- .8byte .LVL226
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST44:
- .8byte .LVL157
- .8byte .LVL159
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL159
- .8byte .LVL193
- .2byte 0x1
- .byte 0x69
- .8byte .LVL196
- .8byte .LVL204
- .2byte 0x1
- .byte 0x69
- .8byte .LVL211
- .8byte .LVL226
- .2byte 0x1
- .byte 0x69
- .8byte 0
- .8byte 0
-.LLST45:
- .8byte .LVL131
- .8byte .LVL145
- .2byte 0x2
- .byte 0x31
- .byte 0x9f
- .8byte .LVL147
- .8byte .LVL190
- .2byte 0x2
- .byte 0x31
- .byte 0x9f
- .8byte .LVL193
- .8byte .LVL206
- .2byte 0x2
- .byte 0x31
- .byte 0x9f
- .8byte .LVL206
- .8byte .LVL207
- .2byte 0x1
- .byte 0x50
- .8byte .LVL207
- .8byte .LVL226
- .2byte 0x1
- .byte 0x6b
- .8byte .LVL226
- .8byte .LVL228
- .2byte 0x1
- .byte 0x50
- .8byte .LVL228
- .8byte .LVL234
- .2byte 0x2
- .byte 0x31
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST46:
- .8byte .LVL131
- .8byte .LVL145
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL147
- .8byte .LVL152
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL152
- .8byte .LVL153
- .2byte 0x1
- .byte 0x50
- .8byte .LVL193
- .8byte .LVL196
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL204
- .8byte .LVL234
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST47:
- .8byte .LVL131
- .8byte .LVL142
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL142
- .8byte .LVL143-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL143-1
- .8byte .LVL145
- .2byte 0x1
- .byte 0x67
- .8byte .LVL147
- .8byte .LVL159
- .2byte 0x1
- .byte 0x67
- .8byte .LVL159
- .8byte .LVL165
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL165
- .8byte .LVL166
- .2byte 0x1
- .byte 0x50
- .8byte .LVL166
- .8byte .LVL168
- .2byte 0x1
- .byte 0x68
- .8byte .LVL168
- .8byte .LVL169
- .2byte 0x1
- .byte 0x50
- .8byte .LVL169
- .8byte .LVL171
- .2byte 0x1
- .byte 0x68
- .8byte .LVL171
- .8byte .LVL172
- .2byte 0x1
- .byte 0x50
- .8byte .LVL172
- .8byte .LVL174
- .2byte 0x1
- .byte 0x68
- .8byte .LVL174
- .8byte .LVL175
- .2byte 0x1
- .byte 0x50
- .8byte .LVL175
- .8byte .LVL178
- .2byte 0x1
- .byte 0x68
- .8byte .LVL178
- .8byte .LVL179
- .2byte 0x1
- .byte 0x50
- .8byte .LVL179
- .8byte .LVL180-1
- .2byte 0x1
- .byte 0x52
- .8byte .LVL180-1
- .8byte .LVL181
- .2byte 0x3
- .byte 0x8f
- .sleb128 196
- .8byte .LVL181
- .8byte .LVL182
- .2byte 0x1
- .byte 0x50
- .8byte .LVL182
- .8byte .LVL184
- .2byte 0x1
- .byte 0x66
- .8byte .LVL184
- .8byte .LVL185-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL185-1
- .8byte .LVL186
- .2byte 0x1
- .byte 0x68
- .8byte .LVL186
- .8byte .LVL188
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL188
- .8byte .LVL191
- .2byte 0x1
- .byte 0x68
- .8byte .LVL193
- .8byte .LVL196
- .2byte 0x1
- .byte 0x67
- .8byte .LVL196
- .8byte .LVL199
- .2byte 0x1
- .byte 0x50
- .8byte .LVL199
- .8byte .LVL200
- .2byte 0x1
- .byte 0x68
- .8byte .LVL200
- .8byte .LVL203
- .2byte 0x1
- .byte 0x50
- .8byte .LVL203
- .8byte .LVL204
- .2byte 0x1
- .byte 0x68
- .8byte .LVL204
- .8byte .LVL211
- .2byte 0x1
- .byte 0x67
- .8byte .LVL211
- .8byte .LVL214
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL214
- .8byte .LVL216
- .2byte 0x1
- .byte 0x68
- .8byte .LVL216
- .8byte .LVL219
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL219
- .8byte .LVL220-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL220-1
- .8byte .LVL222
- .2byte 0x1
- .byte 0x68
- .8byte .LVL222
- .8byte .LVL225
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL225
- .8byte .LVL226
- .2byte 0x1
- .byte 0x68
- .8byte .LVL226
- .8byte .LVL227
- .2byte 0x1
- .byte 0x67
- .8byte .LVL228
- .8byte .LVL232
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL232
- .8byte .LVL233
- .2byte 0x1
- .byte 0x50
- .8byte .LVL233
- .8byte .LVL234-1
- .2byte 0x1
- .byte 0x51
- .8byte .LVL234-1
- .8byte .LVL234
- .2byte 0x1
- .byte 0x67
- .8byte 0
- .8byte 0
-.LLST48:
- .8byte .LVL131
- .8byte .LVL145
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL147
- .8byte .LVL188
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL188
- .8byte .LVL189
- .2byte 0x1
- .byte 0x52
- .8byte .LVL193
- .8byte .LVL214
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL214
- .8byte .LVL215
- .2byte 0x1
- .byte 0x50
- .8byte .LVL216
- .8byte .LVL234
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST49:
- .8byte .LVL157
- .8byte .LVL190
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL196
- .8byte .LVL204
- .2byte 0x1
- .byte 0x6c
- .8byte 0
- .8byte 0
-.LLST29:
- .8byte .LVL103
- .8byte .LVL104
- .2byte 0x1
- .byte 0x50
- .8byte .LVL104
- .8byte .LVL107
- .2byte 0x1
- .byte 0x63
- .8byte .LVL107
- .8byte .LVL108
- .2byte 0x1
- .byte 0x50
- .8byte .LVL108
- .8byte .LVL121
- .2byte 0x1
- .byte 0x63
- .8byte .LVL124
- .8byte .LFE255
- .2byte 0x1
- .byte 0x63
- .8byte 0
- .8byte 0
-.LLST30:
- .8byte .LVL103
- .8byte .LVL106
- .2byte 0x1
- .byte 0x51
- .8byte .LVL106
- .8byte .LVL110
- .2byte 0x1
- .byte 0x51
- .8byte 0
- .8byte 0
-.LLST31:
- .8byte .LVL103
- .8byte .LVL110
- .2byte 0x1
- .byte 0x52
- .8byte .LVL110
- .8byte .LVL122
- .2byte 0x1
- .byte 0x66
- .8byte .LVL122
- .8byte .LVL124
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x52
- .byte 0x9f
- .8byte .LVL124
- .8byte .LFE255
- .2byte 0x1
- .byte 0x66
- .8byte 0
- .8byte 0
-.LLST32:
- .8byte .LVL109
- .8byte .LVL110
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL110
- .8byte .LVL123
- .2byte 0x1
- .byte 0x67
- .8byte .LVL124
- .8byte .LFE255
- .2byte 0x1
- .byte 0x67
- .8byte 0
- .8byte 0
-.LLST33:
- .8byte .LVL109
- .8byte .LVL122
- .2byte 0x1
- .byte 0x65
- .8byte .LVL124
- .8byte .LFE255
- .2byte 0x1
- .byte 0x65
- .8byte 0
- .8byte 0
-.LLST34:
- .8byte .LVL111
- .8byte .LVL112
- .2byte 0x9
- .byte 0x70
- .sleb128 0
- .byte 0x85
- .sleb128 0
- .byte 0x1d
- .byte 0x83
- .sleb128 0
- .byte 0x22
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST35:
- .8byte .LVL115
- .8byte .LVL116
- .2byte 0x1
- .byte 0x50
- .8byte .LVL116
- .8byte .LVL120
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL124
- .8byte .LVL126
- .2byte 0x1
- .byte 0x6a
- .8byte .LVL127
- .8byte .LFE255
- .2byte 0x1
- .byte 0x6a
- .8byte 0
- .8byte 0
-.LLST36:
- .8byte .LVL103
- .8byte .LVL118
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL118
- .8byte .LVL119
- .2byte 0x1
- .byte 0x50
- .8byte .LVL119
- .8byte .LVL120
- .2byte 0x1
- .byte 0x64
- .8byte .LVL124
- .8byte .LVL125-1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL125-1
- .8byte .LVL126
- .2byte 0x1
- .byte 0x64
- .8byte .LVL127
- .8byte .LFE255
- .2byte 0x1
- .byte 0x64
- .8byte 0
- .8byte 0
-.LLST8:
- .8byte .LVL33
- .8byte .LVL34
- .2byte 0x1
- .byte 0x50
- .8byte .LVL34
- .8byte .LFE254
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST7:
- .8byte .LVL31
- .8byte .LVL32
- .2byte 0x1
- .byte 0x50
- .8byte .LVL32
- .8byte .LFE253
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST0:
- .8byte .LVL0
- .8byte .LVL1
- .2byte 0x1
- .byte 0x50
- .8byte .LVL1
- .8byte .LVL12
- .2byte 0x1
- .byte 0x67
- .8byte .LVL12
- .8byte .LVL13
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x50
- .byte 0x9f
- .8byte .LVL13
- .8byte .LFE200
- .2byte 0x1
- .byte 0x67
- .8byte 0
- .8byte 0
-.LLST1:
- .8byte .LVL0
- .8byte .LVL2-1
- .2byte 0x1
- .byte 0x51
- .8byte .LVL2-1
- .8byte .LVL12
- .2byte 0x1
- .byte 0x68
- .8byte .LVL12
- .8byte .LVL13
- .2byte 0x4
- .byte 0xf3
- .uleb128 0x1
- .byte 0x51
- .byte 0x9f
- .8byte .LVL13
- .8byte .LFE200
- .2byte 0x1
- .byte 0x68
- .8byte 0
- .8byte 0
-.LLST2:
- .8byte .LVL2
- .8byte .LVL3
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte .LVL3
- .8byte .LVL11
- .2byte 0x1
- .byte 0x64
- .8byte .LVL13
- .8byte .LVL22
- .2byte 0x1
- .byte 0x64
- .8byte .LVL23
- .8byte .LFE200
- .2byte 0x1
- .byte 0x66
- .8byte 0
- .8byte 0
-.LLST3:
- .8byte .LVL24
- .8byte .LVL25
- .2byte 0x2
- .byte 0x30
- .byte 0x9f
- .8byte 0
- .8byte 0
-.LLST4:
- .8byte .LVL4
- .8byte .LVL11
- .2byte 0x1
- .byte 0x6b
- .8byte .LVL13
- .8byte .LVL21
- .2byte 0x1
- .byte 0x6b
- .8byte .LVL22
- .8byte .LFE200
- .2byte 0x1
- .byte 0x64
- .8byte 0
- .8byte 0
-.LLST5:
- .8byte .LVL3
- .8byte .LVL4
- .2byte 0x3
- .byte 0x9
- .byte 0xff
- .byte 0x9f
- .8byte .LVL4
- .8byte .LVL5
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL5
- .8byte .LVL6
- .2byte 0x4
- .byte 0x8c
- .sleb128 0
- .byte 0x20
- .byte 0x9f
- .8byte .LVL6
- .8byte .LVL11
- .2byte 0x1
- .byte 0x6c
- .8byte .LVL13
- .8byte .LVL22
- .2byte 0x1
- .byte 0x6c
- .8byte 0
- .8byte 0
-.LLST6:
- .8byte .LVL18
- .8byte .LVL19
- .2byte 0x1
- .byte 0x50
- .8byte .LVL19
- .8byte .LFE200
- .2byte 0x1
- .byte 0x65
- .8byte 0
- .8byte 0
- .section .debug_aranges,"",@progbits
- .4byte 0x8c
- .2byte 0x2
- .4byte .Ldebug_info0
- .byte 0x8
- .byte 0
- .2byte 0
- .2byte 0
- .8byte .LFB200
- .8byte .LFE200-.LFB200
- .8byte .LFB253
- .8byte .LFE253-.LFB253
- .8byte .LFB254
- .8byte .LFE254-.LFB254
- .8byte .LFB268
- .8byte .LFE268-.LFB268
- .8byte .LFB271
- .8byte .LFE271-.LFB271
- .8byte .LFB255
- .8byte .LFE255-.LFB255
- .8byte .LFB256
- .8byte .LFE256-.LFB256
- .8byte 0
- .8byte 0
- .section .debug_ranges,"",@progbits
-.Ldebug_ranges0:
- .8byte .LBB6
- .8byte .LBE6
- .8byte .LBB12
- .8byte .LBE12
- .8byte .LBB13
- .8byte .LBE13
- .8byte .LBB14
- .8byte .LBE14
- .8byte .LBB18
- .8byte .LBE18
- .8byte 0
- .8byte 0
- .8byte .LBB15
- .8byte .LBE15
- .8byte .LBB19
- .8byte .LBE19
- .8byte 0
- .8byte 0
- .8byte .LFB200
- .8byte .LFE200
- .8byte .LFB253
- .8byte .LFE253
- .8byte .LFB254
- .8byte .LFE254
- .8byte .LFB268
- .8byte .LFE268
- .8byte .LFB271
- .8byte .LFE271
- .8byte .LFB255
- .8byte .LFE255
- .8byte .LFB256
- .8byte .LFE256
- .8byte 0
- .8byte 0
- .section .debug_line,"",@progbits
-.Ldebug_line0:
- .section .debug_str,"MS",@progbits,1
-.LASF30:
- .string "parent_platdata"
-.LASF109:
- .string "off_mem_rsvmap"
-.LASF193:
- .string "UCLASS_I2C_EEPROM"
-.LASF481:
- .string "jt_funcs"
-.LASF198:
- .string "UCLASS_IRQ"
-.LASF159:
- .string "initrd_start"
-.LASF192:
- .string "UCLASS_I2C"
-.LASF13:
- .string "sizetype"
-.LASF335:
- .string "net_hostname"
-.LASF330:
- .string "push_packet"
-.LASF54:
- .string "start"
-.LASF231:
- .string "UCLASS_SPI"
-.LASF309:
- .string "child"
-.LASF196:
- .string "UCLASS_I2S"
-.LASF356:
- .string "NETLOOP_RESTART"
-.LASF194:
- .string "UCLASS_I2C_GENERIC"
-.LASF206:
- .string "UCLASS_MOD_EXP"
-.LASF253:
- .string "UCLASS_IO_DOMAIN"
-.LASF266:
- .string "using_pre_serial"
-.LASF37:
- .string "uclass_priv"
-.LASF226:
- .string "UCLASS_RKNAND"
-.LASF170:
- .string "UCLASS_DEMO"
-.LASF379:
- .string "g_isi_pattern"
-.LASF117:
- .string "ih_magic"
-.LASF46:
- .string "list_head"
-.LASF425:
- .string "err_addr"
-.LASF370:
- .string "child_pre_probe"
-.LASF302:
- .string "pm_ctx_phys"
-.LASF174:
- .string "UCLASS_TEST_PROBE"
-.LASF307:
- .string "full_name"
-.LASF249:
- .string "UCLASS_KEY"
-.LASF80:
- .string "bi_intfreq"
-.LASF460:
- .string "__func__"
-.LASF11:
- .string "phys_addr_t"
-.LASF244:
- .string "UCLASS_VIDEO_BRIDGE"
-.LASF301:
- .string "video_bottom"
-.LASF457:
- .string "set_ddr_freq"
-.LASF5:
- .string "__u8"
-.LASF355:
- .string "NETLOOP_CONTINUE"
-.LASF234:
- .string "UCLASS_SPI_GENERIC"
-.LASF296:
- .string "malloc_base"
-.LASF464:
- .string "get_page_size"
-.LASF56:
- .string "flash_info_t"
-.LASF210:
- .string "UCLASS_PANEL"
-.LASF134:
- .string "comp"
-.LASF129:
- .string "image_header_t"
-.LASF164:
- .string "state"
-.LASF186:
- .string "UCLASS_CROS_EC"
-.LASF74:
- .string "bi_dsp_freq"
-.LASF131:
- .string "image_start"
-.LASF445:
- .string "fast_test_bank"
-.LASF172:
- .string "UCLASS_TEST_FDT"
-.LASF430:
- .string "diagonalscan"
-.LASF65:
- .string "bd_info"
-.LASF168:
- .string "uclass_id"
-.LASF121:
- .string "ih_load"
-.LASF314:
- .string "__dtb_dt_spl_begin"
-.LASF394:
- .string "pre_remove"
-.LASF427:
- .string "random_test1"
-.LASF426:
- .string "random_test2"
-.LASF7:
- .string "__u32"
-.LASF35:
- .string "priv"
-.LASF299:
- .string "cur_serial_dev"
-.LASF469:
- .string "strcasecmp"
-.LASF143:
- .string "fit_hdr_os"
-.LASF341:
- .string "net_tx_packet"
-.LASF248:
- .string "UCLASS_FG"
-.LASF340:
- .string "net_server_ip"
-.LASF482:
- .string "ofnode_union"
-.LASF348:
- .string "net_native_vlan"
-.LASF246:
- .string "UCLASS_VIDEO_CRTC"
-.LASF185:
- .string "UCLASS_CODEC"
-.LASF478:
- .ascii "GNU C11 6.3.1 20170404 -ms"
- .string "trict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -fno-pic -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
-.LASF293:
- .string "env_buf"
-.LASF21:
- .string "errno"
-.LASF15:
- .string "long int"
-.LASF69:
- .string "bi_flashsize"
-.LASF401:
- .string "putc"
-.LASF29:
- .string "platdata"
-.LASF215:
- .string "UCLASS_PHY"
-.LASF92:
- .string "IRQ_STACK_START_IN"
-.LASF113:
- .string "size_dt_strings"
-.LASF243:
- .string "UCLASS_VIDEO"
-.LASF402:
- .string "puts"
-.LASF475:
- .string "rand"
-.LASF279:
- .string "relocaddr"
-.LASF385:
- .string "dev_head"
-.LASF351:
- .string "net_boot_file_size"
-.LASF407:
- .string "stdio_names"
-.LASF123:
- .string "ih_dcrc"
-.LASF79:
- .string "bi_ethspeed"
-.LASF169:
- .string "UCLASS_ROOT"
-.LASF44:
- .string "ide_bus_offset"
-.LASF419:
- .string "test_pat_param"
-.LASF338:
- .string "net_server_ethaddr"
-.LASF82:
- .string "bi_arch_number"
-.LASF3:
- .string "signed char"
-.LASF199:
- .string "UCLASS_KEYBOARD"
-.LASF18:
- .string "uint8_t"
-.LASF375:
- .string "per_child_platdata_auto_alloc_size"
-.LASF45:
- .string "udevice"
-.LASF467:
- .string "cmp_buf_data"
-.LASF125:
- .string "ih_arch"
-.LASF106:
- .string "totalsize"
-.LASF446:
- .string "abort"
-.LASF118:
- .string "ih_hcrc"
-.LASF281:
- .string "mon_len"
-.LASF133:
- .string "load"
-.LASF239:
- .string "UCLASS_TPM"
-.LASF428:
- .string "cmp_value"
-.LASF59:
- .string "lmb_property"
-.LASF111:
- .string "last_comp_version"
-.LASF0:
- .string "unsigned char"
-.LASF392:
- .string "pre_probe"
-.LASF453:
- .string "delta_freq"
-.LASF412:
- .string "RANDOM"
-.LASF166:
- .string "images"
-.LASF252:
- .string "UCLASS_DVFS"
-.LASF75:
- .string "bi_ddr_freq"
-.LASF200:
- .string "UCLASS_LED"
-.LASF120:
- .string "ih_size"
-.LASF39:
- .string "uclass_node"
-.LASF23:
- .string "_Bool"
-.LASF376:
- .string "property"
-.LASF359:
- .string "net_state"
-.LASF378:
- .string "value"
-.LASF195:
- .string "UCLASS_I2C_MUX"
-.LASF14:
- .string "char"
-.LASF25:
- .string "_binary_u_boot_bin_start"
-.LASF418:
- .string "test_pattern"
-.LASF357:
- .string "NETLOOP_SUCCESS"
-.LASF36:
- .string "uclass"
-.LASF382:
- .string "p_current"
-.LASF384:
- .string "uc_drv"
-.LASF354:
- .string "net_loop_state"
-.LASF43:
- .string "req_seq"
-.LASF310:
- .string "sibling"
-.LASF287:
- .string "dm_root_f"
-.LASF321:
- .string "enetaddr"
-.LASF221:
- .string "UCLASS_PWRSEQ"
-.LASF452:
- .string "times"
-.LASF454:
- .string "target_freq"
-.LASF380:
- .string "of_offset"
-.LASF149:
- .string "fit_hdr_fdt"
-.LASF349:
- .string "net_restart_wrap"
-.LASF404:
- .string "getc"
-.LASF337:
- .string "net_ethaddr"
-.LASF42:
- .string "flags"
-.LASF437:
- .string "cmdtp"
-.LASF126:
- .string "ih_type"
-.LASF107:
- .string "off_dt_struct"
-.LASF458:
- .string "crosstalk"
-.LASF70:
- .string "bi_flashoffset"
-.LASF350:
- .string "net_boot_file_name"
-.LASF387:
- .string "compatible"
-.LASF171:
- .string "UCLASS_TEST"
-.LASF119:
- .string "ih_time"
-.LASF274:
- .string "fb_base"
-.LASF271:
- .string "bus_clk"
-.LASF222:
- .string "UCLASS_RAM"
-.LASF189:
- .string "UCLASS_ETH"
-.LASF32:
- .string "node"
-.LASF130:
- .string "image_info"
-.LASF408:
- .string "console_devices"
-.LASF136:
- .string "arch"
-.LASF273:
- .string "mem_clk"
-.LASF476:
- .string "write_buf_to_ddr"
-.LASF270:
- .string "cpu_clk"
-.LASF50:
- .string "select_hwpart"
-.LASF342:
- .string "net_rx_packets"
-.LASF360:
- .string "mem_malloc_start"
-.LASF91:
- .string "_datarelro_start_ofs"
-.LASF17:
- .string "ulong"
-.LASF122:
- .string "ih_ep"
-.LASF61:
- .string "lmb_region"
-.LASF448:
- .string "do_ddr_test"
-.LASF462:
- .string "printf"
-.LASF144:
- .string "fit_uname_os"
-.LASF76:
- .string "bi_bootflags"
-.LASF339:
- .string "net_ip"
-.LASF291:
- .string "fdt_size"
-.LASF333:
- .string "net_dns_server"
-.LASF353:
- .string "net_ping_ip"
-.LASF63:
- .string "memory"
-.LASF104:
- .string "fdt_header"
-.LASF361:
- .string "mem_malloc_end"
-.LASF202:
- .string "UCLASS_MAILBOX"
-.LASF156:
- .string "rd_end"
-.LASF364:
- .string "bind"
-.LASF282:
- .string "irq_sp"
-.LASF161:
- .string "cmdline_start"
-.LASF328:
- .string "index"
-.LASF269:
- .string "global_data"
-.LASF400:
- .string "stop"
-.LASF396:
- .string "per_device_auto_alloc_size"
-.LASF472:
- .string "ctrlc"
-.LASF95:
- .string "repeatable"
-.LASF229:
- .string "UCLASS_SCSI"
-.LASF241:
- .string "UCLASS_USB_DEV_GENERIC"
-.LASF203:
- .string "UCLASS_MASS_STORAGE"
-.LASF1:
- .string "long unsigned int"
-.LASF179:
- .string "UCLASS_SIMPLE_BUS"
-.LASF455:
- .string "freq"
-.LASF311:
- .string "gd_t"
-.LASF334:
- .string "net_nis_domain"
-.LASF398:
- .string "console_buffer"
-.LASF151:
- .string "fit_noffset_fdt"
-.LASF432:
- .string "next_adr"
-.LASF423:
- .string "wr_value"
-.LASF459:
- .string "shift"
-.LASF358:
- .string "NETLOOP_FAIL"
-.LASF247:
- .string "UCLASS_WDT"
-.LASF260:
- .string "timer_reset_value"
-.LASF283:
- .string "start_addr_sp"
-.LASF71:
- .string "bi_sramstart"
-.LASF26:
- .string "_binary_u_boot_bin_end"
-.LASF284:
- .string "reloc_off"
-.LASF473:
- .string "judge_test_addr"
-.LASF112:
- .string "boot_cpuid_phys"
-.LASF259:
- .string "lastinc"
-.LASF263:
- .string "tlb_fillptr"
-.LASF456:
- .string "set_vdd_logic"
-.LASF147:
- .string "fit_uname_rd"
-.LASF235:
- .string "UCLASS_SYSCON"
-.LASF184:
- .string "UCLASS_CPU"
-.LASF142:
- .string "fit_uname_cfg"
-.LASF230:
- .string "UCLASS_SERIAL"
-.LASF347:
- .string "net_our_vlan"
-.LASF303:
- .string "serial"
-.LASF365:
- .string "probe"
-.LASF182:
- .string "UCLASS_BLK"
-.LASF137:
- .string "image_info_t"
-.LASF178:
- .string "UCLASS_USB_EMUL"
-.LASF439:
- .string "argc"
-.LASF261:
- .string "tlb_addr"
-.LASF214:
- .string "UCLASS_PCI_GENERIC"
-.LASF440:
- .string "argv"
-.LASF132:
- .string "image_len"
-.LASF77:
- .string "bi_ip_addr"
-.LASF216:
- .string "UCLASS_PINCONFIG"
-.LASF324:
- .string "send"
-.LASF237:
- .string "UCLASS_THERMAL"
-.LASF140:
- .string "legacy_hdr_os_copy"
-.LASF9:
- .string "long long int"
-.LASF417:
- .string "TESTCASSMAX"
-.LASF443:
- .string "test_times"
-.LASF167:
- .string "command_ret_t"
-.LASF290:
- .string "new_fdt"
-.LASF22:
- .string "___strtok"
-.LASF352:
- .string "net_boot_file_expected_size_in_blocks"
-.LASF451:
- .string "max_freq"
-.LASF363:
- .string "of_match"
-.LASF209:
- .string "UCLASS_NVME"
-.LASF264:
- .string "tlb_emerg"
-.LASF138:
- .string "bootm_headers"
-.LASF470:
- .string "strict_strtoul"
-.LASF55:
- .string "protect"
-.LASF240:
- .string "UCLASS_USB"
-.LASF447:
- .string "scan_freq_loop"
-.LASF389:
- .string "uclass_driver"
-.LASF250:
- .string "UCLASS_RC"
-.LASF294:
- .string "timebase_h"
-.LASF295:
- .string "timebase_l"
-.LASF187:
- .string "UCLASS_DISPLAY"
-.LASF346:
- .string "net_null_ethaddr"
-.LASF277:
- .string "env_valid"
-.LASF416:
- .string "FULLTEST"
-.LASF34:
- .string "parent"
-.LASF177:
- .string "UCLASS_PCI_EMUL"
-.LASF38:
- .string "parent_priv"
-.LASF251:
- .string "UCLASS_CHARGE_DISPLAY"
-.LASF315:
- .string "load_addr"
-.LASF98:
- .string "complete"
-.LASF89:
- .string "_datarelrolocal_start_ofs"
-.LASF97:
- .string "help"
-.LASF268:
- .string "addr"
-.LASF101:
- .string "CMD_RET_FAILURE"
-.LASF8:
- .string "unsigned int"
-.LASF16:
- .string "ushort"
-.LASF320:
- .string "eth_device"
-.LASF372:
- .string "priv_auto_alloc_size"
-.LASF297:
- .string "malloc_limit"
-.LASF218:
- .string "UCLASS_PMIC"
-.LASF422:
- .string "capacity"
-.LASF139:
- .string "legacy_hdr_os"
-.LASF108:
- .string "off_dt_strings"
-.LASF312:
- .string "monitor_flash_len"
-.LASF204:
- .string "UCLASS_MISC"
-.LASF67:
- .string "bi_memsize"
-.LASF438:
- .string "flag"
-.LASF24:
- .string "image_base"
-.LASF236:
- .string "UCLASS_SYSRESET"
-.LASF383:
- .string "current"
-.LASF191:
- .string "UCLASS_FIRMWARE"
-.LASF450:
- .string "min_freq"
-.LASF201:
- .string "UCLASS_LPC"
-.LASF197:
- .string "UCLASS_IDE"
-.LASF405:
- .string "list"
-.LASF306:
- .string "phandle"
-.LASF300:
- .string "video_top"
-.LASF397:
- .string "per_device_platdata_auto_alloc_size"
-.LASF165:
- .string "bootm_headers_t"
-.LASF73:
- .string "bi_arm_freq"
-.LASF224:
- .string "UCLASS_REMOTEPROC"
-.LASF465:
- .string "data_cpu_2_io"
-.LASF325:
- .string "recv"
-.LASF135:
- .string "type"
-.LASF146:
- .string "fit_hdr_rd"
-.LASF276:
- .string "env_addr"
-.LASF72:
- .string "bi_sramsize"
-.LASF449:
- .string "scan_freq"
-.LASF431:
- .string "start_adr"
-.LASF288:
- .string "uclass_root"
-.LASF190:
- .string "UCLASS_GPIO"
-.LASF219:
- .string "UCLASS_PWM"
-.LASF444:
- .string "test_banks"
-.LASF58:
- .string "long double"
-.LASF278:
- .string "ram_top"
-.LASF421:
- .string "baseaddr"
-.LASF480:
- .string "/home/typ/src/u-boot_gerrit/u-boot-ddr"
-.LASF155:
- .string "rd_start"
-.LASF220:
- .string "UCLASS_POWER_DOMAIN"
-.LASF223:
- .string "UCLASS_REGULATOR"
-.LASF317:
- .string "save_size"
-.LASF183:
- .string "UCLASS_CLK"
-.LASF31:
- .string "uclass_platdata"
-.LASF322:
- .string "iobase"
-.LASF429:
- .string "random_test"
-.LASF88:
- .string "_datarel_start_ofs"
-.LASF265:
- .string "pre_serial"
-.LASF128:
- .string "ih_name"
-.LASF435:
- .string "next_col"
-.LASF124:
- .string "ih_os"
-.LASF162:
- .string "cmdline_end"
-.LASF343:
- .string "net_rx_packet"
-.LASF256:
- .string "LOGF_MAX_CATEGORIES"
-.LASF289:
- .string "fdt_blob"
-.LASF386:
- .string "udevice_id"
-.LASF51:
- .string "size"
-.LASF10:
- .string "long long unsigned int"
-.LASF395:
- .string "destroy"
-.LASF116:
- .string "image_header"
-.LASF377:
- .string "length"
-.LASF20:
- .string "__be32"
-.LASF68:
- .string "bi_flashstart"
-.LASF145:
- .string "fit_noffset_os"
-.LASF205:
- .string "UCLASS_MMC"
-.LASF327:
- .string "write_hwaddr"
-.LASF479:
- .string "cmd/ddr_tool/ddr_test_code.c"
-.LASF255:
- .string "UCLASS_INVALID"
-.LASF471:
- .string "data_cpu_2_io_init"
-.LASF94:
- .string "maxargs"
-.LASF242:
- .string "UCLASS_USB_HUB"
-.LASF414:
- .string "DIAGONALSCAN"
-.LASF371:
- .string "child_post_remove"
-.LASF93:
- .string "cmd_tbl_s"
-.LASF99:
- .string "cmd_tbl_t"
-.LASF41:
- .string "sibling_node"
-.LASF292:
- .string "of_root"
-.LASF461:
- .string "memset"
-.LASF57:
- .string "flash_info"
-.LASF110:
- .string "version"
-.LASF326:
- .string "halt"
-.LASF62:
- .string "region"
-.LASF114:
- .string "size_dt_struct"
-.LASF286:
- .string "dm_root"
-.LASF304:
- .string "sys_start_tick"
-.LASF308:
- .string "properties"
-.LASF207:
- .string "UCLASS_MTD"
-.LASF103:
- .string "fdt32_t"
-.LASF285:
- .string "new_gd"
-.LASF468:
- .string "get_print_available_addr"
-.LASF208:
- .string "UCLASS_NORTHBRIDGE"
-.LASF78:
- .string "bi_enetaddr"
-.LASF477:
- .string "malloc"
-.LASF369:
- .string "child_post_bind"
-.LASF483:
- .string "exit"
-.LASF318:
- .string "in_addr"
-.LASF344:
- .string "net_rx_packet_len"
-.LASF323:
- .string "init"
-.LASF102:
- .string "CMD_RET_USAGE"
-.LASF313:
- .string "__dtb_dt_begin"
-.LASF225:
- .string "UCLASS_RESET"
-.LASF148:
- .string "fit_noffset_rd"
-.LASF436:
- .string "err_adr"
-.LASF181:
- .string "UCLASS_AHCI"
-.LASF12:
- .string "phys_size_t"
-.LASF27:
- .string "driver"
-.LASF87:
- .string "FIQ_STACK_START"
-.LASF163:
- .string "verify"
-.LASF381:
- .string "ofnode"
-.LASF28:
- .string "name"
-.LASF441:
- .string "test_case"
-.LASF211:
- .string "UCLASS_PANEL_BACKLIGHT"
-.LASF238:
- .string "UCLASS_TIMER"
-.LASF233:
- .string "UCLASS_SPI_FLASH"
-.LASF424:
- .string "reread_val"
-.LASF275:
- .string "have_console"
-.LASF81:
- .string "bi_busfreq"
-.LASF6:
- .string "short int"
-.LASF217:
- .string "UCLASS_PINCTRL"
-.LASF227:
- .string "UCLASS_RAMDISK"
-.LASF434:
- .string "pattern"
-.LASF176:
- .string "UCLASS_I2C_EMUL"
-.LASF232:
- .string "UCLASS_SPMI"
-.LASF96:
- .string "usage"
-.LASF366:
- .string "remove"
-.LASF173:
- .string "UCLASS_TEST_BUS"
-.LASF316:
- .string "save_addr"
-.LASF374:
- .string "per_child_auto_alloc_size"
-.LASF463:
- .string "flush_dcache_range"
-.LASF413:
- .string "CROSSTALK"
-.LASF298:
- .string "malloc_ptr"
-.LASF160:
- .string "initrd_end"
-.LASF391:
- .string "pre_unbind"
-.LASF267:
- .string "baudrate"
-.LASF90:
- .string "_datarellocal_start_ofs"
-.LASF40:
- .string "child_head"
-.LASF257:
- .string "arch_global_data"
-.LASF254:
- .string "UCLASS_COUNT"
-.LASF399:
- .string "stdio_dev"
-.LASF272:
- .string "pci_clk"
-.LASF49:
- .string "block_drvr"
-.LASF466:
- .string "memcpy"
-.LASF53:
- .string "flash_id"
-.LASF305:
- .string "device_node"
-.LASF280:
- .string "ram_size"
-.LASF154:
- .string "fit_noffset_setup"
-.LASF115:
- .string "working_fdt"
-.LASF336:
- .string "net_root_path"
-.LASF188:
- .string "UCLASS_DMA"
-.LASF85:
- .string "bd_t"
-.LASF319:
- .string "s_addr"
-.LASF393:
- .string "post_probe"
-.LASF345:
- .string "net_bcast_ethaddr"
-.LASF83:
- .string "bi_boot_params"
-.LASF19:
- .string "uint32_t"
-.LASF362:
- .string "mem_malloc_brk"
-.LASF331:
- .string "net_gateway"
-.LASF373:
- .string "platdata_auto_alloc_size"
-.LASF403:
- .string "tstc"
-.LASF66:
- .string "bi_memstart"
-.LASF245:
- .string "UCLASS_VIDEO_CONSOLE"
-.LASF406:
- .string "stdio_devices"
-.LASF329:
- .string "eth_current"
-.LASF420:
- .string "_u_boot_list_2_cmd_2_ddr_test"
-.LASF368:
- .string "ofdata_to_platdata"
-.LASF64:
- .string "reserved"
-.LASF410:
- .string "CHANGEFREQ"
-.LASF433:
- .string "page_size"
-.LASF415:
- .string "FASTTEST"
-.LASF409:
- .string "cd_count"
-.LASF84:
- .string "bi_dram"
-.LASF2:
- .string "short unsigned int"
-.LASF105:
- .string "magic"
-.LASF152:
- .string "fit_hdr_setup"
-.LASF141:
- .string "legacy_hdr_valid"
-.LASF411:
- .string "SCANFREQ"
-.LASF60:
- .string "base"
-.LASF442:
- .string "err_case"
-.LASF228:
- .string "UCLASS_RTC"
-.LASF258:
- .string "timer_rate_hz"
-.LASF52:
- .string "sector_count"
-.LASF127:
- .string "ih_comp"
-.LASF390:
- .string "post_bind"
-.LASF367:
- .string "unbind"
-.LASF157:
- .string "ft_addr"
-.LASF474:
- .string "uclass_get_device"
-.LASF4:
- .string "uchar"
-.LASF158:
- .string "ft_len"
-.LASF47:
- .string "next"
-.LASF388:
- .string "data"
-.LASF100:
- .string "CMD_RET_SUCCESS"
-.LASF153:
- .string "fit_uname_setup"
-.LASF48:
- .string "prev"
-.LASF212:
- .string "UCLASS_PCH"
-.LASF213:
- .string "UCLASS_PCI"
-.LASF332:
- .string "net_netmask"
-.LASF33:
- .string "driver_data"
-.LASF86:
- .string "IRQ_STACK_START"
-.LASF180:
- .string "UCLASS_ADC"
-.LASF175:
- .string "UCLASS_SPI_EMUL"
-.LASF262:
- .string "tlb_size"
-.LASF150:
- .string "fit_uname_fdt"
- .hidden malloc
- .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
- .section .note.GNU-stack,"",@progbits
diff --git a/u-boot/cmd/memtester/ddr_tester_common.c b/u-boot/cmd/ddr_tool/ddr_tool_common.c
similarity index 92%
rename from u-boot/cmd/memtester/ddr_tester_common.c
rename to u-boot/cmd/ddr_tool/ddr_tool_common.c
index 713d1a9..e2faf6a 100644
--- a/u-boot/cmd/memtester/ddr_tester_common.c
+++ b/u-boot/cmd/ddr_tool/ddr_tool_common.c
@@ -5,7 +5,7 @@
#include <common.h>
#include <power/regulator.h>
-#include "ddr_tester_common.h"
+#include "ddr_tool_common.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -84,6 +84,13 @@
for (i = 0; i < max_bank; i++) {
start_adr[i] = gd->bd->bi_dram[i].start;
length[i] = gd->bd->bi_dram[i].size;
+#if defined(CONFIG_ROCKCHIP_RV1126)
+ /* On RV1126, writing data to 0x00600000 will cause a crash. */
+ if (start_adr[i] == 0 && length[i] > 0x00700000) {
+ start_adr[i] = 0x00700000;
+ length[i] -= 0x00700000;
+ }
+#endif
}
length[max_bank - 1] = (gd->start_addr_sp - RESERVED_SP_SIZE -
diff --git a/u-boot/cmd/memtester/ddr_tester_common.h b/u-boot/cmd/ddr_tool/ddr_tool_common.h
similarity index 81%
rename from u-boot/cmd/memtester/ddr_tester_common.h
rename to u-boot/cmd/ddr_tool/ddr_tool_common.h
index 2ff3fd7..59422b2 100644
--- a/u-boot/cmd/memtester/ddr_tester_common.h
+++ b/u-boot/cmd/ddr_tool/ddr_tool_common.h
@@ -4,8 +4,8 @@
*/
/* Function declaration. */
-#ifndef _CMD_MEMTESTER_DDR_TOOL_COMMON_H
-#define _CMD_MEMTESTER_DDR_TOOL_COMMON_H
+#ifndef __CMD_DDR_TOOL_DDR_TOOL_COMMON_H
+#define __CMD_DDR_TOOL_DDR_TOOL_COMMON_H
/* reserved 1MB for stack */
#define RESERVED_SP_SIZE 0x100000
@@ -17,4 +17,4 @@
void get_print_available_addr(ulong *start_adr, ulong *length, int print_en);
int judge_test_addr(ulong *arg, ulong *start_adr, ulong *length);
int set_vdd_logic(u32 uv);
-#endif /* _CMD_MEMTESTER_DDR_TOOL_COMMON_H */
+#endif /* __CMD_DDR_TOOL_DDR_TOOL_COMMON_H */
diff --git a/u-boot/cmd/ddr_tool/ddr_tool_mp.S b/u-boot/cmd/ddr_tool/ddr_tool_mp.S
new file mode 100644
index 0000000..ca53486
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/ddr_tool_mp.S
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2023 Rockchip Electronics Co., Ltd.
+ */
+
+ .global __sp
+
+ .global secondary_main
+ .global secondary_init
+ .global get_cpu_id
+ .global lock_byte_mutex
+ .global unlock_byte_mutex
+
+#ifndef CONFIG_ARM64
+ .align 7
+vectors_2:
+ ldr pc, =die_loop /* reset */
+ ldr pc, =die_loop /* undefine */
+ ldr pc, =die_loop /* swi */
+ ldr pc, =die_loop /* iabort */
+ ldr pc, =die_loop /* dabort */
+ ldr pc, =die_loop /* reserved */
+ ldr pc, =die_loop /* irq */
+ ldr pc, =die_loop /* fiq */
+
+ .align 7
+die_loop:
+ b die_loop
+
+ .align 7
+ .type secondary_init, %function
+secondary_init:
+ bl irq_disable
+ bl icache_invalid
+
+ /* set sp */
+ ldr r2, =__sp
+ ldr r1, [r2]
+ bic r1, r1, #0xf
+ mov sp, r1
+ bl icache_invalid
+
+ mrc p15, 0, r0, c1, c0, 0 /* CP15 C1 System Control Register */
+ bic r0, r0, #0x2000 /* clear V (bit[13], VBAR) */
+ mcr p15, 0, r0, c1, c0, 0 /* for remap VBAR */
+ ldr r0, =vectors_2
+ mcr p15, 0, r0, c12, c0, 0
+ bl icache_invalid
+
+ b secondary_main
+
+irq_disable:
+ mrs r0, cpsr
+ orr r0, r0, #0xc0
+ msr cpsr, r0
+ bx lr
+
+icache_invalid:
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 0
+ bx lr
+
+ .type get_cpu_id, %function
+get_cpu_id:
+ mrc p15, 0, r0, c0, c0, 5
+ and r0, r0, #0x3
+ bx lr
+
+ .align 7
+ .type lock_byte_mutex, %function
+lock_byte_mutex:
+ mov r2, #0x1
+try:
+ ldrex r1, [r0]
+ cmp r1, #0
+ strexeq r1, r2, [r0]
+ cmpeq r1, #0
+ bne try
+ dmb
+ bx lr
+
+ .align 7
+ .type unlock_byte_mutex, %function
+unlock_byte_mutex:
+ dmb
+ mov r1, #0
+ str r1, [r0]
+ dsb
+ bx lr
+#else /* CONFIG_ARM64 */
+ .align 7
+el2_vectors:
+synchronous_sp0:
+ b secondary_init
+ .align 7
+irq_sp0:
+ b irq_sp0
+ .align 7
+fiq_sp0:
+ b fiq_sp0
+ .align 7
+serror_sp0:
+ b serror_sp0
+ .align 7
+synchronous_spx:
+ b synchronous_spx
+ .align 7
+irq_spx:
+ b irq_spx
+ .align 7
+fiq_spx:
+ b fiq_spx
+ .align 7
+serror_spx:
+ b serror_spx
+
+ .align 7
+ .type secondary_init, %function
+secondary_init:
+ bl irq_disable
+
+ /* set sp */
+ ldr x2, =__sp
+ ldr x1, [x2]
+ bic x1, x1, #0xf
+ mov sp, x1
+ bl icache_invalid
+
+ ldr w0, =el2_vectors
+ msr vbar_el2, x0
+ bl icache_invalid
+
+ bl secondary_main
+
+ .type irq_disable, %function
+irq_disable:
+ msr daifset, #0x3
+ ic iallu
+ ret
+
+ .type icache_invalid, %function
+icache_invalid:
+ ic iallu
+ ret
+
+ .align 7
+ .type lock_byte_mutex, %function
+lock_byte_mutex:
+ ldxrb w1, [x0]
+ cmp w1, #1
+ bne 1f
+ wfe
+ b lock_byte_mutex
+1:
+ mov x1, #1
+ stxrb w2, w1, [x0]
+ cmp w2, #0
+ bne lock_byte_mutex
+ dmb sy
+ ret
+
+ .align 7
+ .type unlock_byte_mutex, %function
+unlock_byte_mutex:
+ dmb sy
+ mov x1, #0
+ strb w1, [x0]
+ dsb sy
+ sev
+ ret
+#endif /* #ifdef CONFIG_ARM */
diff --git a/u-boot/cmd/memtester/io_map.c b/u-boot/cmd/ddr_tool/io_map.c
similarity index 100%
rename from u-boot/cmd/memtester/io_map.c
rename to u-boot/cmd/ddr_tool/io_map.c
diff --git a/u-boot/cmd/memtester/io_map.h b/u-boot/cmd/ddr_tool/io_map.h
similarity index 64%
rename from u-boot/cmd/memtester/io_map.h
rename to u-boot/cmd/ddr_tool/io_map.h
index 3b17440..5ec4994 100644
--- a/u-boot/cmd/memtester/io_map.h
+++ b/u-boot/cmd/ddr_tool/io_map.h
@@ -3,12 +3,12 @@
* Copyright (C) 2019 Rockchip Electronics Co., Ltd.
*/
-#ifndef _CMD_MEMTESTER_IO_MAP_H
-#define _CMD_MEMTESTER_IO_MAP_H
+#ifndef __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H
+#define __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H
#define CPU_2_IO_ALIGN_LEN (16) /* 16 byte */
int data_cpu_2_io(void *p, u32 len);
void data_cpu_2_io_init(void);
-#endif /* _CMD_MEMTESTER_IO_MAP_H */
+#endif /* __CMD_DDR_TOOL_MEMTESTER_IO_MAP_H */
diff --git a/u-boot/cmd/ddr_tool/memtester/Makefile b/u-boot/cmd/ddr_tool/memtester/Makefile
new file mode 100644
index 0000000..7e26994
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/memtester/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_MEMTESTER) += memtester.o
+obj-$(CONFIG_CMD_MEMTESTER) += tests.o
diff --git a/u-boot/cmd/memtester/memtester.c b/u-boot/cmd/ddr_tool/memtester/memtester.c
similarity index 98%
rename from u-boot/cmd/memtester/memtester.c
rename to u-boot/cmd/ddr_tool/memtester/memtester.c
index 7936c03..37aaa5c 100644
--- a/u-boot/cmd/memtester/memtester.c
+++ b/u-boot/cmd/ddr_tool/memtester/memtester.c
@@ -20,8 +20,8 @@
#include "sizes.h"
#include "types.h"
#include "tests.h"
-#include "io_map.h"
-#include "ddr_tester_common.h"
+#include "../ddr_tool_common.h"
+#include "../io_map.h"
#define EXIT_FAIL_NONSTARTER 0x01
#define EXIT_FAIL_ADDRESSLINES 0x02
diff --git a/u-boot/cmd/memtester/memtester.h b/u-boot/cmd/ddr_tool/memtester/memtester.h
similarity index 86%
rename from u-boot/cmd/memtester/memtester.h
rename to u-boot/cmd/ddr_tool/memtester/memtester.h
index 5275a8c..8e5d91f 100644
--- a/u-boot/cmd/memtester/memtester.h
+++ b/u-boot/cmd/ddr_tool/memtester/memtester.h
@@ -13,8 +13,8 @@
* See other comments in that file.
*
*/
-#ifndef _CMD_MEMTESTER_H
-#define _CMD_MEMTESTER_H
+#ifndef __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H
+#define __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H
#include <linux/types.h>
/* extern declarations. */
@@ -25,4 +25,4 @@
int doing_memtester(unsigned long *arg, unsigned long testenable,
unsigned long loops, unsigned long err_exit,
unsigned long fix_bit, unsigned long fix_level);
-#endif /* _CMD_MEMTESTER_H */
+#endif /* __CMD_DDR_TOOL_MEMTESTER_MEMTESTER_H */
diff --git a/u-boot/cmd/memtester/sizes.h b/u-boot/cmd/ddr_tool/memtester/sizes.h
similarity index 86%
rename from u-boot/cmd/memtester/sizes.h
rename to u-boot/cmd/ddr_tool/memtester/sizes.h
index 8c86e11..71d1988 100644
--- a/u-boot/cmd/memtester/sizes.h
+++ b/u-boot/cmd/ddr_tool/memtester/sizes.h
@@ -12,8 +12,8 @@
* This file contains some macro definitions for handling 32/64 bit platforms.
*
*/
-#ifndef __MEMTESTER_SIZES_H
-#define __MEMTESTER_SIZES_H
+#ifndef __CMD_DDR_TOOL_MEMTESTER_SIZES_H
+#define __CMD_DDR_TOOL_MEMTESTER_SIZES_H
#include <common.h>
@@ -26,4 +26,4 @@
#define CHECKERBOARD2 0xaaaaaaaa
#define UL_BYTE(x) ((x | x << 8 | x << 16 | x << 24))
-#endif /* __MEMTESTER_SIZES_H */
+#endif /* __CMD_DDR_TOOL_MEMTESTER_SIZES_H */
diff --git a/u-boot/cmd/memtester/tests.c b/u-boot/cmd/ddr_tool/memtester/tests.c
similarity index 99%
rename from u-boot/cmd/memtester/tests.c
rename to u-boot/cmd/ddr_tool/memtester/tests.c
index 4f27c1c..b4aa288 100644
--- a/u-boot/cmd/memtester/tests.c
+++ b/u-boot/cmd/ddr_tool/memtester/tests.c
@@ -17,7 +17,7 @@
#include "memtester.h"
#include "sizes.h"
#include "types.h"
-#include "io_map.h"
+#include "../io_map.h"
union {
unsigned char bytes[UL_LEN / 8];
diff --git a/u-boot/cmd/memtester/tests.h b/u-boot/cmd/ddr_tool/memtester/tests.h
similarity index 94%
rename from u-boot/cmd/memtester/tests.h
rename to u-boot/cmd/ddr_tool/memtester/tests.h
index b3ddcae..5082dbc 100644
--- a/u-boot/cmd/memtester/tests.h
+++ b/u-boot/cmd/ddr_tool/memtester/tests.h
@@ -15,6 +15,9 @@
*
*/
+#ifndef __CMD_DDR_TOOL_MEMTESTER_TESTS_H
+#define __CMD_DDR_TOOL_MEMTESTER_TESTS_H
+
/* Function declaration. */
int test_stuck_address(u32v *bufa, size_t count);
@@ -54,3 +57,5 @@
int test_16bit_wide_random(u32v *bufa, u32v *bufb, size_t count,
ul fix_bit, ul fix_level);
#endif
+
+#endif /* __CMD_DDR_TOOL_MEMTESTER_TESTS_H */
diff --git a/u-boot/cmd/memtester/types.h b/u-boot/cmd/ddr_tool/memtester/types.h
similarity index 100%
rename from u-boot/cmd/memtester/types.h
rename to u-boot/cmd/ddr_tool/memtester/types.h
diff --git a/u-boot/cmd/ddr_tool/stressapptest/Makefile b/u-boot/cmd/ddr_tool/stressapptest/Makefile
new file mode 100644
index 0000000..94e332f
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/stressapptest/Makefile
@@ -0,0 +1,7 @@
+#
+# (C) Copyright 2023 Rockchip Electronics Co., Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_CMD_STRESSAPPTEST) += stressapptest.o
diff --git a/u-boot/cmd/ddr_tool/stressapptest/stressapptest.c b/u-boot/cmd/ddr_tool/stressapptest/stressapptest.c
new file mode 100644
index 0000000..35b493c
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/stressapptest/stressapptest.c
@@ -0,0 +1,1207 @@
+// Copyright 2006 Google Inc. All Rights Reserved.
+/* Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is stressapptest for Rockchip platform in U-Boot, the design idea and
+ * the patterns are from code.google.com/p/stressapptest.
+ */
+
+#include <common.h>
+#include <amp.h>
+#include <div64.h>
+#include <malloc.h>
+#include <asm/arch/rockchip_smccc.h>
+#include "stressapptest.h"
+#include "../ddr_tool_common.h"
+
+#define __version__ "v1.2.0 20230619"
+
+#if defined(CONFIG_ARM64)
+/* Float operation in TOOLCHAIN_ARM32 will cause the compile error */
+#define WARM_CPU
+#endif
+
+#define PAT_NUM 26
+#define PATTERN_LIST_SIZE (PAT_NUM * 2 * 4)
+
+#define CPU_NUM_MAX 16
+
+static u32 walking_1_data[] = {
+ 0x00000001, 0x00000002, 0x00000004, 0x00000008,
+ 0x00000010, 0x00000020, 0x00000040, 0x00000080,
+ 0x00000100, 0x00000200, 0x00000400, 0x00000800,
+ 0x00001000, 0x00002000, 0x00004000, 0x00008000,
+ 0x00010000, 0x00020000, 0x00040000, 0x00080000,
+ 0x00100000, 0x00200000, 0x00400000, 0x00800000,
+ 0x01000000, 0x02000000, 0x04000000, 0x08000000,
+ 0x10000000, 0x20000000, 0x40000000, 0x80000000,
+ 0x40000000, 0x20000000, 0x10000000, 0x08000000,
+ 0x04000000, 0x02000000, 0x01000000, 0x00800000,
+ 0x00400000, 0x00200000, 0x00100000, 0x00080000,
+ 0x00040000, 0x00020000, 0x00010000, 0x00008000,
+ 0x00004000, 0x00002000, 0x00001000, 0x00000800,
+ 0x00000400, 0x00000200, 0x00000100, 0x00000080,
+ 0x00000040, 0x00000020, 0x00000010, 0x00000008,
+ 0x00000004, 0x00000002, 0x00000001, 0x00000000
+};
+
+static struct pat walking_1 = {
+ "walking_1",
+ walking_1_data,
+ ARRAY_SIZE(walking_1_data) - 1, /* mask */
+ {1, 1, 2, 1} /* weight */
+};
+
+static u32 walking_1_x16_data[] = {
+ 0x00020001, 0x00080004, 0x00200010, 0x00800040,
+ 0x02000100, 0x08000400, 0x20001000, 0x80004000,
+ 0x20004000, 0x08001000, 0x02000400, 0x00800100,
+ 0x00200040, 0x00080010, 0x00020004, 0x00000001
+};
+
+static struct pat walking_1_x16 = {
+ "walking_1_x16",
+ walking_1_x16_data,
+ ARRAY_SIZE(walking_1_x16_data) - 1, /* mask */
+ {2, 0, 0, 0} /* Weight for choosing 32/64/128/256 bit wide of this pattern */
+ /* Reuse for walking_0_x16, because of invert */
+};
+
+static u32 walking_1_x16_repeat_data[] = {
+ 0x00010001, 0x00020002, 0x00040004, 0x00080008,
+ 0x00100010, 0x00200020, 0x00400040, 0x00800080,
+ 0x01000100, 0x02000200, 0x04000400, 0x08000800,
+ 0x10001000, 0x20002000, 0x40004000, 0x80008000,
+ 0x40004000, 0x20002000, 0x10001000, 0x08000800,
+ 0x04000400, 0x02000200, 0x01000100, 0x00800080,
+ 0x00400040, 0x00200020, 0x00100010, 0x00080008,
+ 0x00040004, 0x00020002, 0x00010001, 0x00000000
+};
+
+static struct pat walking_1_x16_repeat = {
+ "walking_1_x16_repeat",
+ walking_1_x16_repeat_data,
+ ARRAY_SIZE(walking_1_x16_repeat_data) - 1, /* mask */
+ {2, 4, 2, 0} /* Weight for choosing 32/64/128/256 bit wide of this pattern */
+ /* Reuse for walking_0_x16_repeat, because of invert */
+};
+
+static u32 walking_inv_1_data[] = {
+ 0x00000001, 0xfffffffe, 0x00000002, 0xfffffffd,
+ 0x00000004, 0xfffffffb, 0x00000008, 0xfffffff7,
+ 0x00000010, 0xffffffef, 0x00000020, 0xffffffdf,
+ 0x00000040, 0xffffffbf, 0x00000080, 0xffffff7f,
+ 0x00000100, 0xfffffeff, 0x00000200, 0xfffffdff,
+ 0x00000400, 0xfffffbff, 0x00000800, 0xfffff7ff,
+ 0x00001000, 0xffffefff, 0x00002000, 0xffffdfff,
+ 0x00004000, 0xffffbfff, 0x00008000, 0xffff7fff,
+ 0x00010000, 0xfffeffff, 0x00020000, 0xfffdffff,
+ 0x00040000, 0xfffbffff, 0x00080000, 0xfff7ffff,
+ 0x00100000, 0xffefffff, 0x00200000, 0xffdfffff,
+ 0x00400000, 0xffbfffff, 0x00800000, 0xff7fffff,
+ 0x01000000, 0xfeffffff, 0x02000000, 0xfdffffff,
+ 0x04000000, 0xfbffffff, 0x08000000, 0xf7ffffff,
+ 0x10000000, 0xefffffff, 0x20000000, 0xdfffffff,
+ 0x40000000, 0xbfffffff, 0x80000000, 0x7fffffff,
+ 0x40000000, 0xbfffffff, 0x20000000, 0xdfffffff,
+ 0x10000000, 0xefffffff, 0x08000000, 0xf7ffffff,
+ 0x04000000, 0xfbffffff, 0x02000000, 0xfdffffff,
+ 0x01000000, 0xfeffffff, 0x00800000, 0xff7fffff,
+ 0x00400000, 0xffbfffff, 0x00200000, 0xffdfffff,
+ 0x00100000, 0xffefffff, 0x00080000, 0xfff7ffff,
+ 0x00040000, 0xfffbffff, 0x00020000, 0xfffdffff,
+ 0x00010000, 0xfffeffff, 0x00008000, 0xffff7fff,
+ 0x00004000, 0xffffbfff, 0x00002000, 0xffffdfff,
+ 0x00001000, 0xffffefff, 0x00000800, 0xfffff7ff,
+ 0x00000400, 0xfffffbff, 0x00000200, 0xfffffdff,
+ 0x00000100, 0xfffffeff, 0x00000080, 0xffffff7f,
+ 0x00000040, 0xffffffbf, 0x00000020, 0xffffffdf,
+ 0x00000010, 0xffffffef, 0x00000008, 0xfffffff7,
+ 0x00000004, 0xfffffffb, 0x00000002, 0xfffffffd,
+ 0x00000001, 0xfffffffe, 0x00000000, 0xffffffff
+};
+
+static struct pat walking_inv_1 = {
+ "walking_inv_1",
+ walking_inv_1_data,
+ ARRAY_SIZE(walking_inv_1_data) - 1, /* mask */
+ {2, 2, 5, 5} /* weight */
+};
+
+static u32 walking_inv_1_x16_data[] = {
+ 0xfffe0001, 0xfffd0002, 0xfffb0004, 0xfff70008,
+ 0xffef0010, 0xffdf0020, 0xffbf0040, 0xff7f0080,
+ 0xfeff0100, 0xfdff0200, 0xfbff0400, 0xf7ff0800,
+ 0xefff1000, 0xdfff2000, 0xbfff4000, 0x7fff8000,
+ 0xbfff4000, 0xdfff2000, 0xefff1000, 0xf7ff0800,
+ 0xfbff0400, 0xfdff0200, 0xfeff0100, 0xff7f0080,
+ 0xffbf0040, 0xffdf0020, 0xffef0010, 0xfff70008,
+ 0xfffb0004, 0xfffd0002, 0xfffe0001, 0xffff0000
+};
+
+static struct pat walking_inv_1_x16 = {
+ "walking_inv_1_x16",
+ walking_inv_1_x16_data,
+ ARRAY_SIZE(walking_inv_1_x16_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 walking_inv_1_x16_repeat_data[] = {
+ 0x00010001, 0xfffefffe, 0x00020002, 0xfffdfffd,
+ 0x00040004, 0xfffbfffb, 0x00080008, 0xfff7fff7,
+ 0x00100010, 0xffefffef, 0x00200020, 0xffdfffdf,
+ 0x00400040, 0xffbfffbf, 0x00800080, 0xff7fff7f,
+ 0x01000100, 0xfefffeff, 0x02000200, 0xfdfffdff,
+ 0x04000400, 0xfbfffbff, 0x08000800, 0xf7fff7ff,
+ 0x10001000, 0xefffefff, 0x20002000, 0xdfffdfff,
+ 0x40004000, 0xbfffbfff, 0x80008000, 0x7fff7fff,
+ 0x40004000, 0xbfffbfff, 0x20002000, 0xdfffdfff,
+ 0x10001000, 0xefffefff, 0x08000800, 0xf7fff7ff,
+ 0x04000400, 0xfbfffbff, 0x02000200, 0xfdfffdff,
+ 0x01000100, 0xfefffeff, 0x00800080, 0xff7fff7f,
+ 0x00400040, 0xffbfffbf, 0x00200020, 0xffdfffdf,
+ 0x00100010, 0xffefffef, 0x00080008, 0xfff7fff7,
+ 0x00040004, 0xfffbfffb, 0x00020002, 0xfffdfffd,
+ 0x00010001, 0xfffefffe, 0x00000000, 0xffffffff
+};
+
+static struct pat walking_inv_1_x16_repeat = {
+ "walking_inv_1_x16_repeat",
+ walking_inv_1_x16_repeat_data,
+ ARRAY_SIZE(walking_inv_1_x16_repeat_data) - 1, /* mask */
+ {2, 5, 5, 0} /* weight */
+};
+
+static u32 walking_0_data[] = {
+ 0xfffffffe, 0xfffffffd, 0xfffffffb, 0xfffffff7,
+ 0xffffffef, 0xffffffdf, 0xffffffbf, 0xffffff7f,
+ 0xfffffeff, 0xfffffdff, 0xfffffbff, 0xfffff7ff,
+ 0xffffefff, 0xffffdfff, 0xffffbfff, 0xffff7fff,
+ 0xfffeffff, 0xfffdffff, 0xfffbffff, 0xfff7ffff,
+ 0xffefffff, 0xffdfffff, 0xffbfffff, 0xff7fffff,
+ 0xfeffffff, 0xfdffffff, 0xfbffffff, 0xf7ffffff,
+ 0xefffffff, 0xdfffffff, 0xbfffffff, 0x7fffffff,
+ 0xbfffffff, 0xdfffffff, 0xefffffff, 0xf7ffffff,
+ 0xfbffffff, 0xfdffffff, 0xfeffffff, 0xff7fffff,
+ 0xffbfffff, 0xffdfffff, 0xffefffff, 0xfff7ffff,
+ 0xfffbffff, 0xfffdffff, 0xfffeffff, 0xffff7fff,
+ 0xffffbfff, 0xffffdfff, 0xffffefff, 0xfffff7ff,
+ 0xfffffbff, 0xfffffdff, 0xfffffeff, 0xffffff7f,
+ 0xffffffbf, 0xffffffdf, 0xffffffef, 0xfffffff7,
+ 0xfffffffb, 0xfffffffd, 0xfffffffe, 0xffffffff
+};
+
+static struct pat walking_0 = {
+ "walking_0",
+ walking_0_data,
+ ARRAY_SIZE(walking_0_data) - 1, /* mask */
+ {1, 1, 2, 1} /* weight */
+};
+
+static u32 one_zero_data[] = {0x00000000, 0xffffffff};
+
+static struct pat one_zero = {
+ "one_zero",
+ one_zero_data,
+ ARRAY_SIZE(one_zero_data) - 1, /* mask */
+ {5, 5, 15, 5} /* weight */
+};
+
+static unsigned int one_zero_x16_data[] = {0x0000ffff, 0x0000ffff};
+
+static struct pat one_zero_x16 = {
+ "one_zero_x16",
+ one_zero_x16_data,
+ ARRAY_SIZE(one_zero_x16_data) - 1, /* mask */
+ {5, 0, 0, 0} /* weight */
+};
+
+static u32 just_0_data[] = {0x00000000, 0x00000000};
+
+static struct pat just_0 = {
+ "just_0",
+ just_0_data,
+ ARRAY_SIZE(just_0_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 just_1_data[] = {0xffffffff, 0xffffffff};
+
+static struct pat just_1 = {
+ "just_1",
+ just_1_data,
+ ARRAY_SIZE(just_1_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 just_5_data[] = {0x55555555, 0x55555555};
+
+static struct pat just_5 = {
+ "just_5",
+ just_5_data,
+ ARRAY_SIZE(just_5_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 just_a_data[] = {0xaaaaaaaa, 0xaaaaaaaa};
+
+static struct pat just_a = {
+ "just_a",
+ just_a_data,
+ ARRAY_SIZE(just_a_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 five_a_data[] = {0x55555555, 0xaaaaaaaa};
+
+static struct pat five_a = {
+ "five_a",
+ five_a_data,
+ ARRAY_SIZE(five_a_data) - 1, /* mask */
+ {1, 1, 1, 1} /* weight */
+};
+
+static unsigned int five_a_x16_data[] = {0x5555aaaa, 0x5555aaaa};
+
+static struct pat five_a_x16 = {
+ "five_a_x16",
+ five_a_x16_data,
+ ARRAY_SIZE(five_a_x16_data) - 1, /* mask */
+ {1, 0, 0, 0} /* weight */
+};
+
+static u32 five_a8_data[] = {
+ 0x5aa5a55a, 0xa55a5aa5, 0xa55a5aa5, 0x5aa5a55a
+};
+
+static struct pat five_a8 = {
+ "five_a8",
+ five_a8_data,
+ ARRAY_SIZE(five_a8_data) - 1, /* mask */
+ {1, 1, 1, 1} /* weight */
+};
+
+static u32 five_a8_x16_data[] = {0x5aa5a55a, 0xa55a5aa5};
+
+static struct pat five_a8_x16 = {
+ "five_a8_x16",
+ five_a8_x16_data,
+ ARRAY_SIZE(five_a8_x16_data) - 1, /* mask */
+ {1, 0, 0, 0} /* weight */
+};
+
+static unsigned int five_a8_x16_repeat_data[] = {
+ 0x5aa55aa5, 0xa55aa55a, 0xa55aa55a, 0x5aa55aa5
+};
+
+static struct pat five_a8_x16_repeat = {
+ "five_a8_x16_repeat",
+ five_a8_x16_repeat_data,
+ ARRAY_SIZE(five_a8_x16_repeat_data) - 1, /* mask */
+ {1, 1, 1, 0} /* weight */
+};
+
+static u32 long_8b10b_data[] = {0x16161616, 0x16161616};
+
+static struct pat long_8b10b = {
+ "long_8b10b",
+ long_8b10b_data,
+ ARRAY_SIZE(long_8b10b_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 short_8b10b_data[] = {0xb5b5b5b5, 0xb5b5b5b5};
+
+static struct pat short_8b10b = {
+ "short_8b10b",
+ short_8b10b_data,
+ ARRAY_SIZE(short_8b10b_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 checker_8b10b_data[] = {0xb5b5b5b5, 0x4a4a4a4a};
+
+static struct pat checker_8b10b = {
+ "checker_8b10b",
+ checker_8b10b_data,
+ ARRAY_SIZE(checker_8b10b_data) - 1, /* mask */
+ {1, 0, 1, 1} /* weight */
+};
+
+static u32 checker_8b10b_x16_data[] = {0xb5b54a4a, 0xb5b54a4a};
+
+static struct pat checker_8b10b_x16 = {
+ "checker_8b10b_x16",
+ checker_8b10b_x16_data,
+ ARRAY_SIZE(checker_8b10b_x16_data) - 1, /* mask */
+ {1, 0, 0, 0} /* weight */
+};
+
+static u32 five_7_data[] = {0x55555557, 0x55575555};
+
+static struct pat five_7 = {
+ "five_7",
+ five_7_data,
+ ARRAY_SIZE(five_7_data) - 1, /* mask */
+ {0, 2, 0, 0} /* weight */
+};
+
+static u32 five_7_x16_data[] = {0x55575557, 0x57555755};
+
+static struct pat five_7_x16 = {
+ "five_7_x16",
+ five_7_x16_data,
+ ARRAY_SIZE(five_7_x16_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static u32 zero2_fd_data[] = {0x00020002, 0xfffdfffd};
+
+static struct pat zero2_fd = {
+ "zero2_fd",
+ zero2_fd_data,
+ ARRAY_SIZE(zero2_fd_data) - 1, /* mask */
+ {0, 2, 0, 0} /* weight */
+};
+
+static u32 zero2_fd_x16_data[] = {0x02020202, 0xfdfdfdfd};
+
+static struct pat zero2_fd_x16 = {
+ "zero2_fd_x16",
+ zero2_fd_x16_data,
+ ARRAY_SIZE(zero2_fd_x16_data) - 1, /* mask */
+ {2, 0, 0, 0} /* weight */
+};
+
+static struct pat *pat_array[] = {
+ &walking_1,
+ &walking_1_x16,
+ &walking_1_x16_repeat,
+ &walking_inv_1,
+ &walking_inv_1_x16,
+ &walking_inv_1_x16_repeat,
+ &walking_0,
+ &one_zero,
+ &one_zero_x16,
+ &just_0,
+ &just_1,
+ &just_5,
+ &just_a,
+ &five_a,
+ &five_a_x16,
+ &five_a8,
+ &five_a8_x16,
+ &five_a8_x16_repeat,
+ &long_8b10b,
+ &short_8b10b,
+ &checker_8b10b,
+ &checker_8b10b_x16,
+ &five_7,
+ &five_7_x16,
+ &zero2_fd,
+ &zero2_fd_x16
+};
+
+static u32 cpu_copy_err[CPU_NUM_MAX];
+static u32 cpu_inv_err[CPU_NUM_MAX];
+
+static u64 start_time_us;
+static u64 test_time_us;
+
+static bool cpu_init_finish[CPU_NUM_MAX];
+static bool cpu_test_finish[CPU_NUM_MAX];
+static bool pattern_page_init_finish;
+
+#if (CPU_NUM_MAX > 1)
+static ulong test_count = 0;
+static ulong __gd; /* set r9/x18 of secondary cpu to gd addr */
+#endif
+ulong __sp; /* set sp of secondary cpu */
+
+u32 print_mutex; /* 0: unlock, 1: lock */
+
+static u64 get_time_us(void)
+{
+ return lldiv(get_ticks(), CONFIG_SYS_HZ_CLOCK / (CONFIG_SYS_HZ * 1000));
+}
+
+static u64 run_time_us(void)
+{
+ return get_time_us() - start_time_us;
+}
+
+static void print_time_stamp(void)
+{
+ u64 time_us;
+
+ time_us = run_time_us();
+
+ printf("[%5d.%06d] ", (u32)(time_us / 1000000), (u32)(time_us % 1000000));
+}
+
+static u32 pattern_get(struct pattern *pattern, u32 offset)
+{
+ u32 ret;
+
+ ret = pattern->pat->data_array[(offset >> pattern->repeat) &
+ pattern->pat->mask];
+
+ return pattern->inv ? ~ret : ret;
+}
+
+static void pattern_adler_sum_calc(struct pattern *pattern,
+ struct stressapptest_params *sat)
+{
+ int i = 0;
+ u64 a1 = 1;
+ u64 b1 = 0;
+ u64 a2 = 1;
+ u64 b2 = 0;
+
+ while (i < sat->block_size_byte / sizeof(u32)) {
+ a1 += (u64)pattern_get(pattern, i++);
+ b1 += a1;
+ a1 += pattern_get(pattern, i++);
+ b1 += a1;
+
+ a2 += (u64)pattern_get(pattern, i++);
+ b2 += a2;
+ a2 += pattern_get(pattern, i++);
+ b2 += a2;
+ }
+
+ pattern->adler_sum.a1 = a1;
+ pattern->adler_sum.b1 = b1;
+ pattern->adler_sum.a2 = a2;
+ pattern->adler_sum.b2 = b2;
+}
+
+static void pattern_list_init(struct pattern *pattern_list,
+ struct stressapptest_params *sat)
+{
+ u32 weight_count = 0;
+ int k = 0;
+
+ for (int i = 0; i < PAT_NUM; i++) {
+ for (int j = 0; j < 8; j++) {
+ pattern_list[k].pat = pat_array[i];
+ pattern_list[k].inv = j % 2;
+ pattern_list[k].repeat = j / 2;
+ pattern_list[k].weight = pattern_list[k].pat->weight[j / 2];
+ pattern_adler_sum_calc(&pattern_list[k], sat);
+ weight_count += pattern_list[k].weight;
+ k++;
+ }
+ }
+
+ sat->weight_count = weight_count;
+}
+
+static u32 get_max_page_num(ulong page_size_byte)
+{
+ ulong start_adr[CONFIG_NR_DRAM_BANKS], length[CONFIG_NR_DRAM_BANKS];
+ u32 page_num = 0;
+
+ get_print_available_addr(start_adr, length, 0);
+
+ page_num = 0;
+ for (int i = 0; i < ARRAY_SIZE(start_adr) || i < ARRAY_SIZE(length); i++) {
+ if ((start_adr[i] == 0 && length[i] == 0))
+ break;
+ page_num += (u32)(length[i] / page_size_byte);
+ }
+
+ return page_num;
+}
+
+static int get_page_addr(struct page *page_list,
+ struct stressapptest_params *sat)
+{
+ ulong start_adr[CONFIG_NR_DRAM_BANKS], length[CONFIG_NR_DRAM_BANKS];
+ ulong used_length;
+ u32 page = 0;
+
+ get_print_available_addr(start_adr, length, 0);
+
+ printf("Address for test:\n Start End Length\n");
+ for (int i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ if ((start_adr[i] == 0 && length[i] == 0) || page >= sat->page_num)
+ break;
+ if (start_adr[i] + length[i] < sat->total_start_addr)
+ continue;
+ if (start_adr[i] < sat->total_start_addr) {
+ length[i] -= sat->total_start_addr - start_adr[i];
+ start_adr[i] = sat->total_start_addr;
+ }
+
+ used_length = 0;
+ while (page < sat->page_num &&
+ length[i] >= used_length + sat->page_size_byte) {
+ page_list[page].base_addr = (void *)(start_adr[i] + used_length);
+ used_length += sat->page_size_byte;
+ page++;
+ }
+ printf(" 0x%09lx - 0x%09lx 0x%09lx\n",
+ start_adr[i], start_adr[i] + used_length, used_length);
+ }
+
+ printf("page_num = %d, page_size = 0x%lx, total_test_size = 0x%lx\n",
+ page, sat->page_size_byte, sat->page_size_byte * page);
+
+ if (sat->total_test_size_mb == 0) {
+ /* No arg for total_test_size_mb, test all available space by default. */
+ sat->page_num = page;
+ } else if (page < sat->page_num || page < sat->cpu_num * 4) {
+ printf("ERROR: Cannot get enough pages to test.\n");
+ printf("Please decrease page_size or test_size\n");
+
+ return -1;
+ }
+
+ return 0;
+}
+
+static void page_init_valid(struct page *page, struct pattern *pattern_list,
+ struct stressapptest_params *sat)
+{
+ int target;
+ int i = 0;
+ u64 *mem;
+
+ target = (rand() % sat->weight_count) + 1;
+ do {
+ target -= pattern_list[i++].weight;
+ if (target <= 0)
+ break;
+ } while (i < PATTERN_LIST_SIZE);
+ page->pattern = &pattern_list[--i];
+ page->valid = 1;
+
+ mem = (u64 *)page->base_addr;
+ for (i = 0; i < sat->page_size_byte / sizeof(u64); i++)
+ mem[i] = (u64)pattern_get(page->pattern, i * 2) |
+ (u64)pattern_get(page->pattern, i * 2 + 1) << 32;
+}
+
+static void page_init_empty(struct page *page)
+{
+ page->valid = 0;
+}
+
+static void page_init(struct pattern *pattern_list,
+ struct stressapptest_params *sat)
+{
+ int i, cpu;
+ u32 empty_page_num;
+
+ for (cpu = 0; cpu < sat->cpu_num; cpu++) {
+ empty_page_num = 0;
+ for (i = cpu; i < sat->page_num; i += sat->cpu_num) {
+ if (rand() % 5 < 3) {
+ page_list[i].valid = 1;
+ } else {
+ page_list[i].valid = 0;
+ empty_page_num++;
+ }
+ }
+ while (empty_page_num >= sat->page_num / sat->cpu_num / 2 && i > 0) {
+ i -= sat->cpu_num;
+ if (page_list[i].valid == 0) {
+ page_list[i].valid = 1;
+ empty_page_num--;
+ }
+ }
+ i = cpu;
+ while (empty_page_num < 2 && i < sat->page_num) {
+ if (page_list[i].valid == 1) {
+ page_list[i].valid = 0;
+ empty_page_num++;
+ }
+ i += sat->cpu_num;
+ }
+ }
+
+ for (i = 0; i < sat->page_num; i++) {
+ if (page_list[i].valid == 1)
+ page_init_valid(&page_list[i], pattern_list, sat);
+ else
+ page_init_empty(&page_list[i]);
+ }
+ flush_dcache_all();
+}
+
+static u32 page_rand_pick(struct page *page_list, bool valid,
+ struct stressapptest_params *sat, u8 cpu_id)
+{
+ u32 pick;
+
+ pick = rand() % sat->page_num;
+ pick = pick / sat->cpu_num * sat->cpu_num + cpu_id;
+ if (pick >= sat->page_num)
+ pick = cpu_id;
+
+ while (page_list[pick].valid != valid) {
+ pick += sat->cpu_num;
+ if (pick >= sat->page_num)
+ pick = cpu_id;
+ }
+
+ return pick;
+}
+
+static u32 block_mis_search(void *dst_addr, struct pattern *src_pattern, char *item,
+ struct stressapptest_params *sat, u8 cpu_id)
+{
+ u32 *dst_mem;
+ u32 read, reread, expected;
+ u32 err = 0;
+ u32 *print_addr;
+ int i, j;
+
+ dst_mem = (u32 *)dst_addr;
+
+ for (i = 0; i < sat->block_size_byte / sizeof(u32); i++) {
+ read = dst_mem[i];
+ expected = pattern_get(src_pattern, i);
+
+ if (read != expected) {
+ flush_dcache_range((ulong)&dst_mem[i], (ulong)&dst_mem[i + 1]);
+ reread = dst_mem[i];
+
+ lock_byte_mutex(&print_mutex);
+
+ print_time_stamp();
+ printf("%s Hardware Error: miscompare on CPU %d at 0x%lx:\n",
+ item, cpu_id, (ulong)&dst_mem[i]);
+ printf(" read: 0x%08x\n", read);
+ printf(" reread: 0x%08x(reread^read:0x%08x)\n",
+ reread, reread ^ read);
+ printf(" expected:0x%08x(expected^read:0x%08x)\n",
+ expected, expected ^ read);
+ printf(" \'%s%s%d\'", src_pattern->pat->name,
+ src_pattern->inv ? "~" : "",
+ 32 << src_pattern->repeat);
+ if (reread == expected)
+ printf(" read error");
+ printf("\n");
+
+ /* Dump data around the error address */
+ print_addr = &dst_mem[i] - 64;
+ for (j = 0; j < 128; j += 8)
+ printf(" [0x%010lx] 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
+ (ulong)(print_addr + j),
+ *(print_addr + j), *(print_addr + j + 1),
+ *(print_addr + j + 2), *(print_addr + j + 3),
+ *(print_addr + j + 4), *(print_addr + j + 5),
+ *(print_addr + j + 6), *(print_addr + j + 7));
+
+ unlock_byte_mutex(&print_mutex);
+
+ /* fix the error */
+ dst_mem[i] = expected;
+ err++;
+ }
+ }
+ flush_dcache_all();
+
+ if (err == 0) {
+ lock_byte_mutex(&print_mutex);
+ printf("%s ERROR detected but cannot find mismatch data (maybe read error).\n", item);
+ unlock_byte_mutex(&print_mutex);
+ }
+
+ return err;
+}
+
+static u32 block_inv_check(void *dst_addr, struct pattern *src_pattern,
+ struct stressapptest_params *sat, u8 cpu_id)
+{
+ u32 *dst_mem;
+ u32 err = 0;
+ int i = 0;
+#if defined(WARM_CPU)
+ double a, b, c, d;
+#endif
+
+ struct adler_sum adler_sum = {
+ 1, 0, 1, 0
+ };
+
+ dst_mem = (u32 *)dst_addr;
+
+#if defined(WARM_CPU)
+ a = 2.0 * dst_mem[0];
+ b = 5.0 * dst_mem[0];
+ c = 7.0 * dst_mem[0];
+ d = 9.0 * dst_mem[0];
+#endif
+
+ while (i < sat->block_size_byte / sizeof(u32)) {
+ adler_sum.a1 += dst_mem[i++];
+ adler_sum.b1 += adler_sum.a1;
+ adler_sum.a1 += dst_mem[i++];
+ adler_sum.b1 += adler_sum.a1;
+
+#if defined(WARM_CPU)
+ a = a * b;
+ b = b + c;
+#endif
+
+ adler_sum.a2 += dst_mem[i++];
+ adler_sum.b2 += adler_sum.a2;
+ adler_sum.a2 += dst_mem[i++];
+ adler_sum.b2 += adler_sum.a2;
+#if defined(WARM_CPU)
+ c = c * d;
+ d = d + d;
+#endif
+ }
+
+#if defined(WARM_CPU)
+ d = a + b + c + d;
+ if (d == 1.0)
+ /* Reference the result so that it can't be discarded by the compiler. */
+ printf("This will probably never happen.\n");
+#endif
+
+ if (adler_sum.a1 != src_pattern->adler_sum.a1 ||
+ adler_sum.b1 != src_pattern->adler_sum.b1 ||
+ adler_sum.a2 != src_pattern->adler_sum.a2 ||
+ adler_sum.b2 != src_pattern->adler_sum.b2)
+ err = block_mis_search(dst_addr, src_pattern, "Inv", sat, cpu_id);
+
+ return err;
+}
+
+static void page_inv_up(void *src_addr, struct stressapptest_params *sat)
+{
+ void *dst_addr = src_addr;
+ uint data;
+ uint *dst_mem;
+
+ for (int i = 0; i < sat->block_num; i++) {
+ dst_mem = (uint *)dst_addr;
+ for (int j = 0; j < sat->block_size_byte / sizeof(uint); j++) {
+ data = dst_mem[j];
+ dst_mem[j] = ~data;
+ }
+ dst_addr += sat->block_size_byte;
+ flush_dcache_all();
+ }
+}
+
+static void page_inv_down(void *src_addr, struct stressapptest_params *sat)
+{
+ void *dst_addr = src_addr;
+ uint data;
+ uint *dst_mem;
+
+ dst_addr += sat->block_size_byte * (sat->block_num - 1);
+
+ for (int i = sat->block_num - 1; i >= 0; i--) {
+ dst_mem = (uint *)dst_addr;
+ for (int j = sat->block_size_byte / sizeof(uint) - 1; j >= 0; j--) {
+ data = dst_mem[j];
+ dst_mem[j] = ~data;
+ }
+ dst_addr -= sat->block_size_byte;
+ flush_dcache_all();
+ }
+}
+
+static u32 page_inv(struct stressapptest_params *sat, u8 cpu_id)
+{
+ u32 src;
+ void *dst_block_addr;
+ u32 err = 0;
+
+ src = page_rand_pick(page_list, 1, sat, cpu_id); /* pick a valid page */
+ dst_block_addr = page_list[src].base_addr;
+
+ for (int i = 0; i < 4; i++) {
+ if (rand() % 2 == 0)
+ page_inv_up(page_list[src].base_addr, sat);
+ else
+ page_inv_down(page_list[src].base_addr, sat);
+ }
+
+ for (int i = 0; i < sat->block_num; i++) {
+ err += block_inv_check(dst_block_addr, page_list[src].pattern, sat, cpu_id);
+ dst_block_addr += sat->block_size_byte;
+ }
+
+ flush_dcache_all();
+
+ return err;
+}
+
+static u32 block_copy_check(void *dst_addr, struct adler_sum *adler_sum,
+ struct pattern *src_pattern, struct stressapptest_params *sat,
+ u8 cpu_id)
+{
+ u32 err = 0;
+
+ if (adler_sum->a1 != src_pattern->adler_sum.a1 ||
+ adler_sum->b1 != src_pattern->adler_sum.b1 ||
+ adler_sum->a2 != src_pattern->adler_sum.a2 ||
+ adler_sum->b2 != src_pattern->adler_sum.b2)
+ err = block_mis_search(dst_addr, src_pattern, "Copy", sat, cpu_id);
+
+ return err;
+}
+
+static u32 block_copy(void *dst_addr, void *src_addr,
+ struct pattern *src_pattern,
+ struct stressapptest_params *sat, u8 cpu_id)
+{
+ u64 *dst_mem;
+ u64 *src_mem;
+ u64 data;
+ int i = 0;
+#if defined(WARM_CPU)
+ double a, b, c, d;
+#endif
+
+ struct adler_sum adler_sum = {
+ 1, 0, 1, 0
+ };
+
+ dst_mem = (u64 *)dst_addr;
+ src_mem = (u64 *)src_addr;
+
+#if defined(WARM_CPU)
+ a = 2.0 * src_mem[0];
+ b = 5.0 * src_mem[0];
+ c = 7.0 * src_mem[0];
+ d = 9.0 * src_mem[0];
+#endif
+
+ while (i < sat->block_size_byte / sizeof(u64)) {
+ data = src_mem[i];
+ adler_sum.a1 += data & 0xffffffff;
+ adler_sum.b1 += adler_sum.a1;
+ adler_sum.a1 += data >> 32;
+ adler_sum.b1 += adler_sum.a1;
+ dst_mem[i] = data;
+ i++;
+
+#if defined(WARM_CPU)
+ a = a * b;
+ b = b + c;
+#endif
+
+ data = src_mem[i];
+ adler_sum.a2 += data & 0xffffffff;
+ adler_sum.b2 += adler_sum.a2;
+ adler_sum.a2 += data >> 32;
+ adler_sum.b2 += adler_sum.a2;
+ dst_mem[i] = data;
+ i++;
+
+#if defined(WARM_CPU)
+ c = c * d;
+ d = d + d;
+#endif
+ }
+
+ flush_dcache_all();
+
+#if defined(WARM_CPU)
+ d = a + b + c + d;
+ if (d == 1.0)
+ /* Reference the result so that it can't be discarded by the compiler. */
+ printf("This will probably never happen.\n");
+#endif
+
+ return block_copy_check(dst_addr, &adler_sum, src_pattern, sat, cpu_id);
+}
+
+static u32 page_copy(struct stressapptest_params *sat, u8 cpu_id)
+{
+ u32 dst;
+ u32 src;
+ void *dst_block_addr;
+ void *src_block_addr;
+ u32 err = 0;
+
+ dst = page_rand_pick(page_list, 0, sat, cpu_id); /* pick a empty page */
+ dst_block_addr = page_list[dst].base_addr;
+ src = page_rand_pick(page_list, 1, sat, cpu_id); /* pick a valid page */
+ src_block_addr = page_list[src].base_addr;
+ flush_dcache_all();
+
+ for (int i = 0; i < sat->block_num; i++) {
+ err += block_copy(dst_block_addr, src_block_addr,
+ page_list[src].pattern, sat, cpu_id);
+ dst_block_addr += sat->block_size_byte;
+ src_block_addr += sat->block_size_byte;
+ }
+
+ page_list[dst].pattern = page_list[src].pattern;
+ page_list[dst].valid = 1;
+ page_list[src].valid = 0;
+ flush_dcache_all();
+
+ return err;
+}
+
+void secondary_main(void)
+{
+#if (CPU_NUM_MAX > 1)
+ u8 cpu_id;
+ ulong test = 0;
+
+#ifndef CONFIG_ARM64
+ asm volatile("mov r9, %0" : : "r" (__gd)); /* set r9 to gd addr */
+#else
+ asm volatile("mov x18, %0" : : "r" (__gd)); /* set x18 to gd addr */
+#endif
+ dcache_enable();
+ icache_enable();
+
+ udelay(100);
+
+ flush_dcache_all();
+
+ cpu_id = sat.cpu_num;
+ cpu_init_finish[cpu_id] = 1;
+ printf("CPU%d start OK.\n", cpu_id);
+
+ while (pattern_page_init_finish == 0) {
+ udelay(100);
+ flush_dcache_all();
+ }
+
+ while (1) {
+ udelay(100);
+ flush_dcache_all();
+ while (test < test_count) {
+ cpu_test_finish[cpu_id] = 0;
+ flush_dcache_all();
+ while (run_time_us() < test_time_us) {
+ if (rand() % 2 == 0)
+ cpu_copy_err[cpu_id] += page_copy(&sat, cpu_id);
+ else
+ cpu_inv_err[cpu_id] += page_inv(&sat, cpu_id);
+ }
+ test++;
+ cpu_test_finish[cpu_id] = 1;
+ flush_dcache_all();
+ }
+ }
+#else
+ return;
+#endif
+}
+
+static int doing_stressapptest(void)
+{
+ int i;
+ u32 pre_10s;
+ u32 now_10s;
+
+ struct pattern pattern_list[PATTERN_LIST_SIZE];
+ void *page_info;
+
+ u32 all_copy_err = 0;
+ u32 all_inv_err = 0;
+ u32 cpu_no_response_err = 0;
+
+ int ret = CMD_RET_SUCCESS;
+
+ for (i = 0; i < CPU_NUM_MAX; i++) {
+ cpu_copy_err[i] = 0;
+ cpu_inv_err[i] = 0;
+ cpu_init_finish[i] = 0;
+ cpu_test_finish[i] = 0;
+ }
+ pattern_page_init_finish = 0;
+ print_mutex = 0;
+ asm volatile("clrex");
+
+#if (CPU_NUM_MAX > 1)
+ if (test_count == 0) {
+ __gd = (ulong)gd;
+ asm volatile("mov %0, sp" : "=r" (__sp));
+ printf("CPU0 sp is at 0x%lx now.\n", __sp);
+ __sp &= ~(ulong)0xffff;
+ for (sat.cpu_num = 1; sat.cpu_num < CPU_NUM_MAX; sat.cpu_num++) {
+ __sp -= 0x10000;
+ flush_dcache_all();
+ if (psci_cpu_on(sat.cpu_num, (ulong)secondary_init) == 0) {
+ mdelay(10);
+ printf("Calling CPU%d, sp = 0x%lx\n", sat.cpu_num, __sp);
+ } else {
+ break;
+ }
+ while (cpu_init_finish[sat.cpu_num] == 0) {
+ udelay(1000);
+ flush_dcache_all();
+ }
+ }
+ }
+#else
+ sat.cpu_num = 1;
+#endif
+
+ if (sat.total_test_size_mb == 0)
+ sat.page_num = get_max_page_num(sat.page_size_byte);
+ else
+ sat.page_num = (sat.total_test_size_mb << 20) / sat.page_size_byte;
+ sat.block_num = sat.page_size_byte / sat.block_size_byte;
+
+ udelay(100);
+
+ page_info = malloc(sizeof(struct page) * sat.page_num);
+ if (page_info == 0) {
+ printf("ERROR: StressAppTest fail to malloc.\n");
+ printf("Please try increasing CONFIG_SYS_MALLOC_LEN in include/configs/rxxxxx_common.h.\n");
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+ page_list = (struct page *)page_info;
+
+ if (get_page_addr(page_list, &sat) < 0) {
+ ret = CMD_RET_FAILURE;
+ goto out;
+ }
+
+ pattern_list_init(pattern_list, &sat);
+ page_init(pattern_list, &sat);
+
+#if (CPU_NUM_MAX > 1)
+ if (sat.cpu_num > 1) {
+ pattern_page_init_finish = 1;
+ test_count++;
+ flush_dcache_all();
+ }
+#endif
+
+ pre_10s = (u32)(run_time_us() / 1000000 / 10);
+ lock_byte_mutex(&print_mutex);
+ print_time_stamp();
+ printf("Start StressAppTest in U-Boot:\n");
+ unlock_byte_mutex(&print_mutex);
+
+ while (run_time_us() < test_time_us) {
+ if (rand() % 2 == 0)
+ cpu_copy_err[0] += page_copy(&sat, 0);
+ else
+ cpu_inv_err[0] += page_inv(&sat, 0);
+
+ /* Print every 10 seconds */
+ now_10s = (u32)(run_time_us() / 1000000 / 10);
+ if (now_10s > pre_10s) {
+ pre_10s = now_10s;
+ lock_byte_mutex(&print_mutex);
+ print_time_stamp();
+ printf("Seconds remaining: %d\n", (u32)(test_time_us / 1000000 - now_10s * 10));
+ unlock_byte_mutex(&print_mutex);
+ }
+ }
+
+#if (CPU_NUM_MAX > 1)
+ for (i = 1; i < sat.cpu_num; i++) {
+ while (cpu_test_finish[i] == 0) {
+ if ((u32)(run_time_us() / 1000000 / 10) > pre_10s + 6) {
+ /* wait for secondary CPU in 60s */
+ lock_byte_mutex(&print_mutex);
+ print_time_stamp();
+ printf("ERROR: Cannot wait for CPU%d to finish!\n", i);
+ unlock_byte_mutex(&print_mutex);
+ cpu_no_response_err++;
+ break;
+ }
+ mdelay(1);
+ flush_dcache_all();
+ }
+ }
+#endif
+
+ for (i = 0; i < sat.cpu_num; i++) {
+ all_copy_err += cpu_copy_err[i];
+ all_inv_err += cpu_inv_err[i];
+ }
+ print_time_stamp();
+ printf("StressAppTest Result: ");
+ if (all_copy_err == 0 && all_inv_err == 0 && cpu_no_response_err == 0)
+ printf("Pass.\n");
+ else
+ printf("FAIL!\nStressAppTest detects %d copy errors, %d inv errors.\n",
+ all_copy_err, all_inv_err);
+
+out:
+ free(page_info);
+
+ return ret;
+}
+
+static int do_stressapptest(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ ulong test_time_sec = 20;
+ ulong page_size_kb = 1024;
+
+ sat.total_test_size_mb = 0;
+ sat.block_size_byte = 4096;
+ sat.total_start_addr = 0x0;
+
+ printf("StressAppTest in U-Boot, " __version__ "\n");
+
+ if (argc > 1) {
+ if (strict_strtoul(argv[1], 0, &test_time_sec) < 0)
+ return CMD_RET_USAGE;
+ if (test_time_sec < 1)
+ test_time_sec = 20;
+ }
+ if (argc > 2) {
+ if (strict_strtoul(argv[2], 0, &sat.total_test_size_mb) < 0)
+ return CMD_RET_USAGE;
+ if (sat.total_test_size_mb < 1)
+ sat.total_test_size_mb = 0;
+ }
+ if (argc > 3) {
+ if (strict_strtoul(argv[3], 0, &sat.total_start_addr) < 0)
+ return CMD_RET_USAGE;
+ if (sat.total_start_addr < 0x1)
+ sat.total_start_addr = 0x0;
+ }
+ if (argc > 4) {
+ if (strict_strtoul(argv[4], 0, &page_size_kb) < 0)
+ return CMD_RET_USAGE;
+ if (page_size_kb < 1)
+ page_size_kb = 1024;
+ }
+
+ sat.page_size_byte = page_size_kb << 10;
+
+ start_time_us = get_time_us();
+ test_time_us = (u64)test_time_sec * 1000000;
+
+ /* Change rand seed. If not do this, rand() would be same after boot.*/
+ srand((unsigned int)(start_time_us & 0xffffffff));
+
+ return doing_stressapptest();
+}
+
+U_BOOT_CMD(stressapptest, 5, 1, do_stressapptest,
+ "StressAppTest for Rockchip\n",
+ "\narg1: test time in second, default value is 20s.\n"
+ "arg2: test size in MB, default value is all available space.\n"
+ "arg3: start addr for test.\n"
+ "arg4: test page size in kB, default value is 1024kB(1MB).\n"
+ "example:\n"
+ " stressapptest: test for 20s, test size is all available space, each page size is 1MB.\n"
+ " stressapptest 43200 64: test for 12h, test size is 64MB, each page size is 1MB (64 pages).\n"
+ " stressapptest 86400 1024 0x80000000: test for 24h, test size is 1024MB, start addr for test is 0x80000000, each page size is 1MB (1024 pages).\n"
+ " stressapptest 43200 16 0x40000000 512: test for 12h, test size is 16MB, start addr for test is 0x40000000, each page size is 512kB (32 pages).\n"
+);
diff --git a/u-boot/cmd/ddr_tool/stressapptest/stressapptest.h b/u-boot/cmd/ddr_tool/stressapptest/stressapptest.h
new file mode 100644
index 0000000..e1e8fb7
--- /dev/null
+++ b/u-boot/cmd/ddr_tool/stressapptest/stressapptest.h
@@ -0,0 +1,70 @@
+/* Copyright 2006 Google Inc. All Rights Reserved. */
+/* Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* This is stressapptest for Rockchip platform in U-Boot, the design idea and
+ * the patterns are from code.google.com/p/stressapptest.
+ */
+
+#ifndef __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H
+#define __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H
+
+struct stressapptest_params {
+ ulong total_start_addr;
+ ulong total_test_size_mb;
+ /* total_test_size = page_size * page_num */
+ ulong page_size_byte;
+ u32 page_num;
+ /* page_size = block_size * block_num */
+ u32 block_size_byte;
+ u32 block_num;
+
+ u32 weight_count;
+
+ u8 cpu_num;
+} sat;
+
+struct pat {
+ const char *name;
+ const unsigned int *data_array;
+ /* mask = size - 1, So data_array[index & mask] is always valid. */
+ const unsigned int mask;
+ const unsigned int weight[4]; /* Weighted frequency of this pattern. */
+};
+
+struct adler_sum {
+ u64 a1;
+ u64 b1;
+ u64 a2;
+ u64 b2;
+};
+
+struct pattern {
+ struct pat *pat;
+ bool inv;
+ u32 repeat;
+ u32 weight;
+ struct adler_sum adler_sum;
+};
+
+struct page {
+ void *base_addr;
+ struct pattern *pattern;
+ bool valid; /* 1: valid, 0: empty */
+} *page_list;
+
+extern void secondary_init(void);
+extern void lock_byte_mutex(u32 *flag);
+extern u32 unlock_byte_mutex(u32 *flag);
+
+#endif /* __CMD_DDR_TOOL_STRESSAPPTEST_STRESSAPPTEST_H */
diff --git a/u-boot/cmd/memtester/Makefile b/u-boot/cmd/memtester/Makefile
deleted file mode 100644
index 6a4347a..0000000
--- a/u-boot/cmd/memtester/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-$(CONFIG_CMD_MEMTESTER) += tests.o
-obj-$(CONFIG_CMD_MEMTESTER) += memtester.o
-obj-$(CONFIG_CMD_MEMTESTER) += io_map.o
-obj-$(CONFIG_CMD_MEMTESTER) += ddr_tester_common.o
diff --git a/u-boot/cmd/mmc.c b/u-boot/cmd/mmc.c
index 0813330..ef6321f 100644
--- a/u-boot/cmd/mmc.c
+++ b/u-boot/cmd/mmc.c
@@ -129,6 +129,7 @@
static int do_mmc_test_secure_storage(cmd_tbl_t *cmdtp,
int flag, int argc, char * const argv[])
{
+#ifdef CONFIG_MMC
struct mmc *mmc;
if (curr_device < 0) {
@@ -143,7 +144,8 @@
mmc = init_mmc_device(curr_device, false);
if (!mmc)
- return CMD_RET_FAILURE;
+ printf("No mmc device\n");
+#endif
int i, count = 100;
diff --git a/u-boot/cmd/mtd.c b/u-boot/cmd/mtd.c
index 31ef7be..1f7542e 100644
--- a/u-boot/cmd/mtd.c
+++ b/u-boot/cmd/mtd.c
@@ -13,6 +13,10 @@
#include <mapmem.h>
#include <mtd.h>
+#define DEV_NAME_MAX_LENGTH 0x40
+static char g_devname[DEV_NAME_MAX_LENGTH];
+static struct mtd_info *g_mtd;
+
static uint mtd_len_to_pages(struct mtd_info *mtd, u64 len)
{
do_div(len, mtd->writesize);
@@ -244,14 +248,20 @@
return CMD_RET_USAGE;
mtd_name = argv[2];
- mtd_probe_devices();
- mtd = get_mtd_device_nm(mtd_name);
- if (IS_ERR_OR_NULL(mtd)) {
- printf("MTD device %s not found, ret %ld\n",
- mtd_name, PTR_ERR(mtd));
- return CMD_RET_FAILURE;
+ if (!strncmp(mtd_name, g_devname, strlen(mtd_name)) && g_mtd) {
+ mtd = g_mtd;
+ } else {
+ mtd_probe_devices();
+ mtd = get_mtd_device_nm(mtd_name);
+ if (IS_ERR_OR_NULL(mtd)) {
+ printf("MTD device %s not found, ret %ld\n",
+ mtd_name, PTR_ERR(mtd));
+ return CMD_RET_FAILURE;
+ }
+ put_mtd_device(mtd);
+ g_mtd = mtd;
+ strncpy(g_devname, mtd_name, strlen(mtd_name));
}
- put_mtd_device(mtd);
argc -= 3;
argv += 3;
diff --git a/u-boot/cmd/pci.c b/u-boot/cmd/pci.c
index b8c799f..6eecd69 100644
--- a/u-boot/cmd/pci.c
+++ b/u-boot/cmd/pci.c
@@ -47,7 +47,6 @@
return pci_byte_size(size) * 2;
}
-#ifdef CONFIG_DM_PCI
static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
{
for (; regs->name; regs++) {
@@ -59,41 +58,8 @@
pci_field_width(regs->size), val);
}
}
-#else
-static unsigned long pci_read_config(pci_dev_t dev, int offset,
- enum pci_size_t size)
-{
- u32 val32;
- u16 val16;
- u8 val8;
- switch (size) {
- case PCI_SIZE_8:
- pci_read_config_byte(dev, offset, &val8);
- return val8;
- case PCI_SIZE_16:
- pci_read_config_word(dev, offset, &val16);
- return val16;
- case PCI_SIZE_32:
- default:
- pci_read_config_dword(dev, offset, &val32);
- return val32;
- }
-}
-
-static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
-{
- for (; regs->name; regs++) {
- printf(" %s =%*s%#.*lx\n", regs->name,
- (int)(28 - strlen(regs->name)), "",
- pci_field_width(regs->size),
- pci_read_config(dev, regs->offset, regs->size));
- }
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
-int pci_bar_show(struct udevice *dev)
+static int pci_bar_show(struct udevice *dev)
{
u8 header_type;
int bar_cnt, bar_id, mem_type;
@@ -105,9 +71,14 @@
int prefetchable;
dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
+ header_type &= 0x7f;
if (header_type == PCI_HEADER_TYPE_CARDBUS) {
printf("CardBus doesn't support BARs\n");
+ return -ENOSYS;
+ } else if (header_type != PCI_HEADER_TYPE_NORMAL &&
+ header_type != PCI_HEADER_TYPE_BRIDGE) {
+ printf("unknown header type\n");
return -ENOSYS;
}
@@ -149,7 +120,7 @@
if ((!is_64 && size_low) || (is_64 && size)) {
size = ~size + 1;
- printf(" %d %#016llx %#016llx %d %s %s\n",
+ printf(" %d %#018llx %#018llx %d %s %s\n",
bar_id, (unsigned long long)base,
(unsigned long long)size, is_64 ? 64 : 32,
is_io ? "I/O" : "MEM",
@@ -162,7 +133,6 @@
return 0;
}
-#endif
static struct pci_reg_info regs_start[] = {
{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
@@ -258,29 +228,18 @@
*
* @dev: Bus+Device+Function number
*/
-#ifdef CONFIG_DM_PCI
-void pci_header_show(struct udevice *dev)
-#else
-void pci_header_show(pci_dev_t dev)
-#endif
+static void pci_header_show(struct udevice *dev)
{
-#ifdef CONFIG_DM_PCI
unsigned long class, header_type;
dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
-#else
- u8 class, header_type;
-
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
- pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
-#endif
pci_show_regs(dev, regs_start);
printf(" class code = 0x%.2x (%s)\n", (int)class,
pci_class_str(class));
pci_show_regs(dev, regs_rest);
- switch (header_type & 0x03) {
+ switch (header_type & 0x7f) {
case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
pci_show_regs(dev, regs_normal);
break;
@@ -297,17 +256,14 @@
}
}
-void pciinfo_header(int busnum, bool short_listing)
+static void pciinfo_header(bool short_listing)
{
- printf("Scanning PCI devices on bus %d\n", busnum);
-
if (short_listing) {
printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
printf("_____________________________________________________________\n");
}
}
-#ifdef CONFIG_DM_PCI
/**
* pci_header_show_brief() - Show the short-form PCI device header
*
@@ -330,11 +286,15 @@
pci_class_str(class), subclass);
}
-static void pciinfo(struct udevice *bus, bool short_listing)
+static void pciinfo(struct udevice *bus, bool short_listing, bool multi)
{
struct udevice *dev;
- pciinfo_header(bus->seq, short_listing);
+ if (!multi)
+ printf("Scanning PCI devices on bus %d\n", bus->seq);
+
+ if (!multi || bus->seq == 0)
+ pciinfo_header(short_listing);
for (device_find_first_child(bus, &dev);
dev;
@@ -353,102 +313,6 @@
}
}
}
-
-#else
-
-/**
- * pci_header_show_brief() - Show the short-form PCI device header
- *
- * Reads and prints the header of the specified PCI device in short form.
- *
- * @dev: Bus+Device+Function number
- */
-void pci_header_show_brief(pci_dev_t dev)
-{
- u16 vendor, device;
- u8 class, subclass;
-
- pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID, &device);
- pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
- pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
-
- printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
- vendor, device,
- pci_class_str(class), subclass);
-}
-
-/**
- * pciinfo() - Show a list of devices on the PCI bus
- *
- * Show information about devices on PCI bus. Depending on @short_pci_listing
- * the output will be more or less exhaustive.
- *
- * @bus_num: The number of the bus to be scanned
- * @short_pci_listing: true to use short form, showing only a brief header
- * for each device
- */
-void pciinfo(int bus_num, int short_pci_listing)
-{
- struct pci_controller *hose = pci_bus_to_hose(bus_num);
- int device;
- int function;
- unsigned char header_type;
- unsigned short vendor_id;
- pci_dev_t dev;
- int ret;
-
- if (!hose)
- return;
-
- pciinfo_header(bus_num, short_pci_listing);
-
- for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
- header_type = 0;
- vendor_id = 0;
- for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
- function++) {
- /*
- * If this is not a multi-function device, we skip
- * the rest.
- */
- if (function && !(header_type & 0x80))
- break;
-
- dev = PCI_BDF(bus_num, device, function);
-
- if (pci_skip_dev(hose, dev))
- continue;
-
- ret = pci_read_config_word(dev, PCI_VENDOR_ID,
- &vendor_id);
- if (ret)
- goto error;
- if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
- continue;
-
- if (!function) {
- pci_read_config_byte(dev, PCI_HEADER_TYPE,
- &header_type);
- }
-
- if (short_pci_listing) {
- printf("%02x.%02x.%02x ", bus_num, device,
- function);
- pci_header_show_brief(dev);
- } else {
- printf("\nFound PCI device %02x.%02x.%02x:\n",
- bus_num, device, function);
- pci_header_show(dev);
- }
- }
- }
-
- return;
-error:
- printf("Cannot read bus configuration: %d\n", ret);
-}
-#endif
/**
* get_pci_dev() - Convert the "bus.device.function" identifier into a number
@@ -481,13 +345,8 @@
return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
}
-#ifdef CONFIG_DM_PCI
static int pci_cfg_display(struct udevice *dev, ulong addr,
enum pci_size_t size, ulong length)
-#else
-static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
- ulong length)
-#endif
{
#define DISP_LINE_LEN 16
ulong i, nbytes, linebytes;
@@ -508,11 +367,7 @@
for (i = 0; i < linebytes; i += byte_size) {
unsigned long val;
-#ifdef CONFIG_DM_PCI
dm_pci_read_config(dev, addr, &val, size);
-#else
- val = pci_read_config(bdf, addr, size);
-#endif
printf(" %0*lx", pci_field_width(size), val);
addr += byte_size;
}
@@ -527,31 +382,8 @@
return (rc);
}
-#ifndef CONFIG_DM_PCI
-static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
-{
- if (size == 4) {
- pci_write_config_dword(bdf, addr, value);
- }
- else if (size == 2) {
- ushort val = value & 0xffff;
- pci_write_config_word(bdf, addr, val);
- }
- else {
- u_char val = value & 0xff;
- pci_write_config_byte(bdf, addr, val);
- }
- return 0;
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
ulong value, int incrflag)
-#else
-static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
- int incrflag)
-#endif
{
ulong i;
int nbytes;
@@ -562,11 +394,7 @@
*/
do {
printf("%08lx:", addr);
-#ifdef CONFIG_DM_PCI
dm_pci_read_config(dev, addr, &val, size);
-#else
- val = pci_read_config(bdf, addr, size);
-#endif
printf(" %0*lx", pci_field_width(size), val);
nbytes = cli_readline(" ? ");
@@ -593,11 +421,7 @@
/* good enough to not time out
*/
bootretry_reset_cmd_timeout();
-#ifdef CONFIG_DM_PCI
dm_pci_write_config(dev, addr, i, size);
-#else
- pci_cfg_write(bdf, addr, size, i);
-#endif
if (incrflag)
addr += size;
}
@@ -607,7 +431,6 @@
return 0;
}
-#ifdef CONFIG_DM_PCI
static const struct pci_flag_info {
uint flag;
const char *name;
@@ -621,7 +444,7 @@
static void pci_show_regions(struct udevice *bus)
{
- struct pci_controller *hose = dev_get_uclass_priv(bus);
+ struct pci_controller *hose = dev_get_uclass_priv(pci_get_controller(bus));
const struct pci_region *reg;
int i, j;
@@ -630,10 +453,11 @@
return;
}
- printf("# %-16s %-16s %-16s %s\n", "Bus start", "Phys start", "Size",
+ printf("Buses %02x-%02x\n", hose->first_busno, hose->last_busno);
+ printf("# %-18s %-18s %-18s %s\n", "Bus start", "Phys start", "Size",
"Flags");
for (i = 0, reg = hose->regions; i < hose->region_count; i++, reg++) {
- printf("%d %#016llx %#016llx %#016llx ", i,
+ printf("%d %#018llx %#018llx %#018llx ", i,
(unsigned long long)reg->bus_start,
(unsigned long long)reg->phys_start,
(unsigned long long)reg->size);
@@ -646,7 +470,6 @@
printf("\n");
}
}
-#endif
/* PCI Configuration Space access commands
*
@@ -660,15 +483,12 @@
{
ulong addr = 0, value = 0, cmd_size = 0;
enum pci_size_t size = PCI_SIZE_32;
-#ifdef CONFIG_DM_PCI
struct udevice *dev, *bus;
-#else
- pci_dev_t dev;
-#endif
- int busnum = 0;
+ int busnum = -1;
pci_dev_t bdf = 0;
char cmd = 's';
int ret = 0;
+ char *endp;
if (argc > 1)
cmd = argv[1][0];
@@ -686,19 +506,15 @@
if (argc > 4)
value = simple_strtoul(argv[4], NULL, 16);
case 'h': /* header */
-#ifdef CONFIG_DM_PCI
case 'b': /* bars */
-#endif
if (argc < 3)
goto usage;
if ((bdf = get_pci_dev(argv[2])) == -1)
return 1;
break;
-#if defined(CONFIG_DM_PCI)
case 'e':
pci_init();
return 0;
-#endif
case 'r': /* no break */
default: /* scan bus */
value = 1; /* short listing */
@@ -707,10 +523,37 @@
value = 0;
argc--;
}
- if (argc > 1)
- busnum = simple_strtoul(argv[1], NULL, 16);
+ if (argc > 2 || (argc > 1 && cmd != 'r' && argv[1][0] != 's')) {
+ if (argv[argc - 1][0] != '*') {
+ busnum = simple_strtoul(argv[argc - 1], &endp, 16);
+ if (*endp)
+ goto usage;
+ }
+ argc--;
+ }
+ if (cmd == 'r' && argc > 2)
+ goto usage;
+ else if (cmd != 'r' && (argc > 2 || (argc == 2 && argv[1][0] != 's')))
+ goto usage;
}
-#ifdef CONFIG_DM_PCI
+ if (busnum == -1) {
+ if (cmd != 'r') {
+ for (busnum = 0;
+ uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
+ busnum++)
+ pciinfo(bus, value, true);
+ } else {
+ for (busnum = 0;
+ uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus) == 0;
+ busnum++) {
+ /* Regions are controller specific so skip non-root buses */
+ if (device_is_on_pci_bus(bus))
+ continue;
+ pci_show_regions(bus);
+ }
+ }
+ return 0;
+ }
ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
if (ret) {
printf("No such bus\n");
@@ -719,22 +562,15 @@
if (cmd == 'r')
pci_show_regions(bus);
else
- pciinfo(bus, value);
-#else
- pciinfo(busnum, value);
-#endif
+ pciinfo(bus, value, false);
return 0;
}
-#ifdef CONFIG_DM_PCI
ret = dm_pci_bus_find_bdf(bdf, &dev);
if (ret) {
printf("No such device\n");
return CMD_RET_FAILURE;
}
-#else
- dev = bdf;
-#endif
switch (argv[1][0]) {
case 'h': /* header */
@@ -755,17 +591,10 @@
case 'w': /* write */
if (argc < 5)
goto usage;
-#ifdef CONFIG_DM_PCI
ret = dm_pci_write_config(dev, addr, value, size);
-#else
- ret = pci_cfg_write(dev, addr, size, value);
-#endif
break;
-#ifdef CONFIG_DM_PCI
-
case 'b': /* bars */
return pci_bar_show(dev);
-#endif
default:
ret = CMD_RET_USAGE;
break;
@@ -780,20 +609,16 @@
#ifdef CONFIG_SYS_LONGHELP
static char pci_help_text[] =
- "[bus] [long]\n"
+ "[bus|*] [long]\n"
" - short or long list of PCI devices on bus 'bus'\n"
-#if defined(CONFIG_DM_PCI)
"pci enum\n"
" - Enumerate PCI buses\n"
-#endif
"pci header b.d.f\n"
" - show header of PCI device 'bus.device.function'\n"
-#ifdef CONFIG_DM_PCI
"pci bar b.d.f\n"
" - show BARs base and size for device b.d.f'\n"
- "pci regions\n"
+ "pci regions [bus|*]\n"
" - show PCI regions\n"
-#endif
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
" - display PCI configuration space (CFG)\n"
"pci next[.b, .w, .l] b.d.f address\n"
diff --git a/u-boot/cmd/script_update.c b/u-boot/cmd/script_update.c
index 2d6e423..d4a7da7 100644
--- a/u-boot/cmd/script_update.c
+++ b/u-boot/cmd/script_update.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <malloc.h>
+#include <dm/device.h>
/*
* Script file example:
@@ -144,6 +145,8 @@
int argc, char * const argv[])
{
struct blk_desc *desc;
+ struct udevice *dev;
+ int devnum = -1;
int part_type;
char cmd[128];
char *buf;
@@ -151,9 +154,31 @@
printf("## retrieving usb_update.txt ...\n");
- desc = blk_get_devnum_by_type(IF_TYPE_USB, 0);
- if (!desc)
+ if (run_command("usb reset", 0))
return CMD_RET_FAILURE;
+
+ for (blk_first_device(IF_TYPE_USB, &dev);
+ dev;
+ blk_next_device(&dev)) {
+ desc = dev_get_uclass_platdata(dev);
+ if (desc->type == DEV_TYPE_UNKNOWN)
+ continue;
+
+ if (desc->lba > 0L && desc->blksz > 0L) {
+ devnum = desc->devnum;
+ break;
+ }
+ }
+ if (devnum < 0) {
+ printf("No available udisk\n");
+ return CMD_RET_FAILURE;
+ }
+
+ desc = blk_get_devnum_by_type(IF_TYPE_USB, devnum);
+ if (!desc) {
+ printf("No usb %d found\n", devnum);
+ return CMD_RET_FAILURE;
+ }
buf = memalign(ARCH_DMA_MINALIGN, SCRIPT_FILE_MAX_SIZE * 2);
if (!buf)
@@ -162,18 +187,15 @@
part_type = desc->part_type;
desc->part_type = PART_TYPE_DOS;
- snprintf(cmd, sizeof(cmd), "usb reset");
+ printf("## scanning usb %d\n", devnum);
+ snprintf(cmd, sizeof(cmd), "fatload usb %d 0x%08lx usb_update.txt",
+ devnum, (ulong)buf);
ret = run_command(cmd, 0);
- if (!ret) {
- snprintf(cmd, sizeof(cmd), "fatload usb 0 0x%08lx usb_update.txt", (ulong)buf);
- ret = run_command(cmd, 0);
- }
if (!ret) {
snprintf(cmd, sizeof(cmd), "script 0x%08lx", (ulong)buf);
ret = run_command(cmd, 0);
}
free(buf);
-
desc->part_type = part_type;
return ret;
diff --git a/u-boot/cmd/ufs.c b/u-boot/cmd/ufs.c
new file mode 100644
index 0000000..5b25788
--- /dev/null
+++ b/u-boot/cmd/ufs.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * ufs.c - UFS specific U-boot commands
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ *
+ */
+#include <common.h>
+#include <command.h>
+#include <ufs.h>
+
+static int do_ufs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int dev, ret;
+
+ if (argc >= 2) {
+ if (!strcmp(argv[1], "init")) {
+ if (argc == 3) {
+ dev = simple_strtoul(argv[2], NULL, 10);
+ ret = ufs_probe_dev(dev);
+ if (ret)
+ return CMD_RET_FAILURE;
+ } else {
+ ufs_probe();
+ }
+
+ return CMD_RET_SUCCESS;
+ }
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(ufs, 3, 1, do_ufs,
+ "UFS sub system",
+ "init [dev] - init UFS subsystem\n"
+);
diff --git a/u-boot/common/Kconfig b/u-boot/common/Kconfig
index 2de87b3..cc0753c 100644
--- a/u-boot/common/Kconfig
+++ b/u-boot/common/Kconfig
@@ -682,5 +682,17 @@
endmenu
+menu "MT support"
+
+config MP_BOOT
+ bool "Support MT boot"
+ default n
+
+config MP_BOOT_BOOTM
+ bool "MT simple bootm image"
+ depends on MP_BOOT
+
+endmenu
+
source "common/spl/Kconfig"
source "common/usbplug/Kconfig"
diff --git a/u-boot/common/Makefile b/u-boot/common/Makefile
index 1901154..e6f1c11 100644
--- a/u-boot/common/Makefile
+++ b/u-boot/common/Makefile
@@ -49,7 +49,6 @@
obj-$(CONFIG_CONSOLE_MUX) += iomux.o
obj-$(CONFIG_MTD_NOR_FLASH) += flash.o
obj-$(CONFIG_CMD_KGDB) += kgdb.o kgdb_stubs.o
-obj-$(CONFIG_I2C_EDID) += edid.o
obj-$(CONFIG_KALLSYMS) += kallsyms.o
obj-y += splash.o
obj-$(CONFIG_SPLASH_SOURCE) += splash_source.o
@@ -67,6 +66,7 @@
endif # !CONFIG_SPL_BUILD
+obj-$(CONFIG_$(SPL_TPL_)I2C_EDID) += edid.o
obj-$(CONFIG_$(SPL_TPL_)BOOTSTAGE) += bootstage.o
ifdef CONFIG_SPL_BUILD
@@ -166,3 +166,11 @@
obj-$(CONFIG_ANDROID_KEYMASTER_CA) += keymaster.o
obj-$(CONFIG_ANDROID_KEYMASTER_CA) += attestation_key.o
endif
+
+ifdef CONFIG_MP_BOOT
+ifndef CONFIG_SPL_BUILD
+obj-$(CONFIG_ROCKCHIP_RK3528) += mp_boot_rk3528.o
+else
+obj-$(CONFIG_ROCKCHIP_RK3528) += spl_mp_boot_rk3528.o
+endif
+endif
diff --git a/u-boot/common/android_ab.c b/u-boot/common/android_ab.c
index 2182d3d..5655274 100644
--- a/u-boot/common/android_ab.c
+++ b/u-boot/common/android_ab.c
@@ -406,7 +406,7 @@
return 0;
}
-void ab_update_root_uuid(void)
+static void ab_update_root_uuid(void)
{
/*
* In android a/b & avb process, the system.img is mandory and the
@@ -441,6 +441,60 @@
}
}
+void ab_update_root_partition(void)
+{
+ char *boot_args = env_get("bootargs");
+ char root_part_dev[64] = {0};
+ disk_partition_t part_info;
+ struct blk_desc *dev_desc;
+ const char *part_type;
+ int part_num;
+
+ dev_desc = rockchip_get_bootdev();
+ if (!dev_desc)
+ return;
+
+ if (ab_is_support_dynamic_partition(dev_desc))
+ return;
+
+ /* Get 'system' partition device number. */
+ part_num = part_get_info_by_name(dev_desc, ANDROID_PARTITION_SYSTEM, &part_info);
+ if (part_num < 0) {
+ printf("%s: Failed to get partition '%s'.\n", __func__, ANDROID_PARTITION_SYSTEM);
+ return;
+ }
+
+ /* Get partition type. */
+ part_type = part_get_type(dev_desc);
+ if (!part_type)
+ return;
+
+ /* Judge the partition device type. */
+ switch (dev_desc->if_type) {
+ case IF_TYPE_MMC:
+ if (strstr(part_type, "ENV"))
+ snprintf(root_part_dev, 64, "root=/dev/mmcblk0p%d", part_num);
+ else if (strstr(part_type, "EFI"))
+ ab_update_root_uuid();
+ break;
+ case IF_TYPE_MTD:
+ if (dev_desc->devnum == BLK_MTD_NAND || dev_desc->devnum == BLK_MTD_SPI_NAND) {
+ if (strstr(boot_args, "rootfstype=squashfs") || strstr(boot_args, "rootfstype=erofs"))
+ snprintf(root_part_dev, 64, "ubi.mtd=%d root=/dev/ubiblock0_0", part_num - 1);
+ else if (strstr(boot_args, "rootfstype=ubifs"))
+ snprintf(root_part_dev, 64, "ubi.mtd=%d root=ubi0:system", part_num - 1);
+ } else if (dev_desc->devnum == BLK_MTD_SPI_NOR) {
+ snprintf(root_part_dev, 64, "root=/dev/mtdblock%d", part_num - 1);
+ }
+ break;
+ default:
+ printf("%s: Not found part type, failed to set root part device.\n", __func__);
+ return;
+ }
+
+ env_update("bootargs", root_part_dev);
+}
+
int ab_get_slot_suffix(char *slot_suffix)
{
/* TODO: get from pre-loader or misc partition */
diff --git a/u-boot/common/android_bootloader.c b/u-boot/common/android_bootloader.c
index 772e6bf..ab080b8 100644
--- a/u-boot/common/android_bootloader.c
+++ b/u-boot/common/android_bootloader.c
@@ -18,6 +18,7 @@
#include <dt_table.h>
#include <image-android-dt.h>
#include <malloc.h>
+#include <mp_boot.h>
#include <fdt_support.h>
#include <fs.h>
#include <boot_rkimg.h>
@@ -462,15 +463,305 @@
slot->successful_boot = 0;
}
+static char *join_str(const char *a, const char *b)
+{
+ size_t len = strlen(a) + strlen(b) + 1 /* null term */;
+ char *ret = (char *)malloc(len);
+
+ if (!ret) {
+ debug("failed to alloc %zu\n", len);
+ return NULL;
+ }
+ strcpy(ret, a);
+ strcat(ret, b);
+
+ return ret;
+}
+
+static size_t get_partition_size(AvbOps *ops, char *name,
+ const char *slot_suffix)
+{
+ char *partition_name = join_str(name, slot_suffix);
+ uint64_t size = 0;
+ AvbIOResult res;
+
+ if (partition_name == NULL)
+ goto bail;
+
+ res = ops->get_size_of_partition(ops, partition_name, &size);
+ if (res != AVB_IO_RESULT_OK && res != AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION)
+ size = 0;
+bail:
+ if (partition_name)
+ free(partition_name);
+
+ return size;
+}
+
+static struct AvbOpsData preload_user_data;
+
+static int avb_image_distribute_prepare(AvbSlotVerifyData *slot_data,
+ AvbOps *ops, char *slot_suffix)
+{
+ struct AvbOpsData *data = (struct AvbOpsData *)(ops->user_data);
+ size_t vendor_boot_size;
+ size_t init_boot_size;
+ size_t resource_size;
+ size_t boot_size;
+ void *image_buf;
+
+ boot_size = max(get_partition_size(ops, ANDROID_PARTITION_BOOT, slot_suffix),
+ get_partition_size(ops, ANDROID_PARTITION_RECOVERY, slot_suffix));
+ init_boot_size = get_partition_size(ops,
+ ANDROID_PARTITION_INIT_BOOT, slot_suffix);
+ vendor_boot_size = get_partition_size(ops,
+ ANDROID_PARTITION_VENDOR_BOOT, slot_suffix);
+ resource_size = get_partition_size(ops,
+ ANDROID_PARTITION_RESOURCE, slot_suffix);
+ image_buf = sysmem_alloc(MEM_AVB_ANDROID,
+ boot_size + init_boot_size +
+ vendor_boot_size + resource_size);
+ if (!image_buf) {
+ printf("avb: sysmem alloc failed\n");
+ return -ENOMEM;
+ }
+
+ /* layout: | boot/recovery | vendor_boot | init_boot | resource | */
+ data->slot_suffix = slot_suffix;
+ data->boot.addr = image_buf;
+ data->boot.size = 0;
+ data->vendor_boot.addr = data->boot.addr + boot_size;
+ data->vendor_boot.size = 0;
+ data->init_boot.addr = data->vendor_boot.addr + vendor_boot_size;
+ data->init_boot.size = 0;
+ data->resource.addr = data->init_boot.addr + init_boot_size;
+ data->resource.size = 0;
+
+ return 0;
+}
+
+static int avb_image_distribute_finish(AvbSlotVerifyData *slot_data,
+ AvbSlotVerifyFlags flags,
+ ulong *load_address)
+{
+ struct andr_img_hdr *hdr;
+ ulong load_addr = *load_address;
+ void *vendor_boot_hdr = NULL;
+ void *init_boot_hdr = NULL;
+ void *boot_hdr = NULL;
+ char *part_name;
+ int i, ret;
+
+ for (i = 0; i < slot_data->num_loaded_partitions; i++) {
+ part_name = slot_data->loaded_partitions[i].partition_name;
+ if (!strncmp(ANDROID_PARTITION_BOOT, part_name, 4) ||
+ !strncmp(ANDROID_PARTITION_RECOVERY, part_name, 8)) {
+ boot_hdr = slot_data->loaded_partitions[i].data;
+ } else if (!strncmp(ANDROID_PARTITION_INIT_BOOT, part_name, 9)) {
+ init_boot_hdr = slot_data->loaded_partitions[i].data;
+ } else if (!strncmp(ANDROID_PARTITION_VENDOR_BOOT, part_name, 11)) {
+ vendor_boot_hdr = slot_data->loaded_partitions[i].data;
+ }
+ }
+
+ /*
+ * populate boot_img_hdr_v34
+ *
+ * If allow verification error: the images are loaded by
+ * ops->get_preloaded_partition() which auto populates
+ * boot_img_hdr_v34.
+ *
+ * If not allow verification error: the images are full loaded
+ * by ops->read_from_partition() which doesn't populate
+ * boot_img_hdr_v34, we need to fix it here for bootm and
+ */
+
+ hdr = boot_hdr;
+ if (hdr->header_version >= 3 &&
+ !(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR)) {
+ hdr = malloc(sizeof(struct andr_img_hdr));
+ if (!hdr)
+ return -ENOMEM;
+
+ ret = populate_boot_info(boot_hdr, vendor_boot_hdr,
+ init_boot_hdr, hdr, true);
+ if (ret < 0) {
+ printf("avb: populate boot info failed, ret=%d\n", ret);
+ return ret;
+ }
+ memcpy(boot_hdr, hdr, sizeof(*hdr));
+ }
+
+ /* distribute ! */
+ load_addr -= hdr->page_size;
+ if (android_image_memcpy_separate(boot_hdr, &load_addr)) {
+ printf("Failed to separate copy android image\n");
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ }
+
+ *load_address = load_addr;
+
+ return 0;
+}
+
+int android_image_verify_resource(const char *boot_part, ulong *resc_buf)
+{
+ const char *requested_partitions[] = {
+ NULL,
+ NULL,
+ };
+ struct AvbOpsData *data;
+ uint8_t unlocked = true;
+ AvbOps *ops;
+ AvbSlotVerifyFlags flags;
+ AvbSlotVerifyData *slot_data = {NULL};
+ AvbSlotVerifyResult verify_result;
+ char slot_suffix[3] = {0};
+ char *part_name;
+ void *image_buf = NULL;
+ int retry_no_vbmeta_partition = 1;
+ int i, ret;
+
+ ops = avb_ops_user_new();
+ if (ops == NULL) {
+ printf("avb_ops_user_new() failed!\n");
+ return -AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ }
+
+ if (ops->read_is_device_unlocked(ops, (bool *)&unlocked) != AVB_IO_RESULT_OK)
+ printf("Error determining whether device is unlocked.\n");
+
+ printf("Device is: %s\n", (unlocked & LOCK_MASK)? "UNLOCKED" : "LOCKED");
+
+ if (unlocked & LOCK_MASK) {
+ *resc_buf = 0;
+ return 0;
+ }
+
+ flags = AVB_SLOT_VERIFY_FLAGS_NONE;
+ if (strcmp(boot_part, ANDROID_PARTITION_RECOVERY) == 0)
+ flags |= AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
+
+#ifdef CONFIG_ANDROID_AB
+ part_name = strdup(boot_part);
+ *(part_name + strlen(boot_part) - 2) = '\0';
+ requested_partitions[0] = part_name;
+
+ ret = rk_avb_get_current_slot(slot_suffix);
+ if (ret) {
+ printf("Failed to get slot suffix, ret=%d\n", ret);
+ return ret;
+ }
+#else
+ requested_partitions[0] = boot_part;
+#endif
+ data = (struct AvbOpsData *)(ops->user_data);
+ ret = avb_image_distribute_prepare(slot_data, ops, slot_suffix);
+ if (ret) {
+ printf("avb image distribute prepare failed %d\n", ret);
+ return ret;
+ }
+
+retry_verify:
+ verify_result =
+ avb_slot_verify(ops,
+ requested_partitions,
+ slot_suffix,
+ flags,
+ AVB_HASHTREE_ERROR_MODE_RESTART,
+ &slot_data);
+ if (verify_result != AVB_SLOT_VERIFY_RESULT_OK &&
+ verify_result != AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED) {
+ if (retry_no_vbmeta_partition && strcmp(boot_part, ANDROID_PARTITION_RECOVERY) == 0) {
+ printf("Verify recovery with vbmeta.\n");
+ flags &= ~AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
+ retry_no_vbmeta_partition = 0;
+ goto retry_verify;
+ }
+ }
+
+ if (verify_result != AVB_SLOT_VERIFY_RESULT_OK || !slot_data) {
+ sysmem_free((ulong)data->boot.addr);
+ return verify_result;
+ }
+
+ for (i = 0; i < slot_data->num_loaded_partitions; i++) {
+ part_name = slot_data->loaded_partitions[i].partition_name;
+ if (!strncmp(ANDROID_PARTITION_RESOURCE, part_name, 8)) {
+ image_buf = slot_data->loaded_partitions[i].data;
+ break;
+ } else if (!strncmp(ANDROID_PARTITION_BOOT, part_name, 4) ||
+ !strncmp(ANDROID_PARTITION_RECOVERY, part_name, 8)) {
+ struct andr_img_hdr *hdr;
+
+ hdr = (void *)slot_data->loaded_partitions[i].data;
+ if (android_image_check_header(hdr))
+ continue;
+
+ if (hdr->header_version <= 2) {
+ image_buf = (void *)hdr + hdr->page_size +
+ ALIGN(hdr->kernel_size, hdr->page_size) +
+ ALIGN(hdr->ramdisk_size, hdr->page_size);
+ break;
+ }
+ }
+ }
+
+ if (image_buf) {
+ memcpy((char *)&preload_user_data, (char *)data, sizeof(*data));
+ *resc_buf = (ulong)image_buf;
+ }
+
+ return 0;
+}
+
+/*
+ * AVB Policy.
+ *
+ * == avb with unlock:
+ * Don't process hash verify.
+ * Go pre-loaded path: Loading vendor_boot and init_boot
+ * directly to where they should be, while loading the
+ * boot/recovery. The boot message tells like:
+ * ···
+ * preloaded: distribute image from 'boot_a'
+ * preloaded: distribute image from 'init_boot_a'
+ * preloaded: distribute image from 'vendor_boot_a'
+ * ···
+ *
+ * == avb with lock:
+ * Process hash verify.
+ * Go pre-loaded path: Loading full vendor_boot, init_boot and
+ * boot/recovery one by one to verify, and distributing them to
+ * where they should be by memcpy at last.
+ *
+ * The three images share a large memory buffer that allocated
+ * by sysmem_alloc(), it locate at high memory address that
+ * just lower than SP bottom. The boot message tells like:
+ * ···
+ * preloaded: full image from 'boot_a' at 0xe47f90c0 - 0xe7a4b0c0
+ * preloaded: full image from 'init_boot_a' at 0xeaff90c0 - 0xeb2950c0
+ * preloaded: full image from 'vendor_boot_a' at 0xe87f90c0 - 0xe9f6e0c0
+ * ···
+ */
static AvbSlotVerifyResult android_slot_verify(char *boot_partname,
unsigned long *android_load_address,
char *slot_suffix)
{
- const char *requested_partitions[1] = {NULL};
+ const char *requested_partitions[] = {
+ boot_partname,
+ NULL,
+ NULL,
+ NULL,
+ };
+ struct AvbOpsData *data;
+ struct blk_desc *dev_desc;
+ struct andr_img_hdr *hdr;
+ disk_partition_t part_info;
uint8_t unlocked = true;
AvbOps *ops;
AvbSlotVerifyFlags flags;
- AvbSlotVerifyData *slot_data[1] = {NULL};
+ AvbSlotVerifyData *slot_data = {NULL};
AvbSlotVerifyResult verify_result;
AvbABData ab_data, ab_data_orig;
size_t slot_index_to_boot = 0;
@@ -478,9 +769,29 @@
char can_boot = 1;
char retry_no_vbmeta_partition = 1;
unsigned long load_address = *android_load_address;
- struct andr_img_hdr *hdr;
+ int ret;
- requested_partitions[0] = boot_partname;
+ dev_desc = rockchip_get_bootdev();
+ if (!dev_desc)
+ return AVB_IO_RESULT_ERROR_IO;
+
+ if (part_get_info_by_name(dev_desc, boot_partname, &part_info) < 0) {
+ printf("Could not find \"%s\" partition\n", boot_partname);
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+ }
+
+ hdr = populate_andr_img_hdr(dev_desc, &part_info);
+ if (!hdr) {
+ printf("No valid android hdr\n");
+ return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
+ }
+
+ if (hdr->header_version >= 4) {
+ requested_partitions[1] = ANDROID_PARTITION_VENDOR_BOOT;
+ if (((hdr->os_version >> 25) & 0x7f) >= 13)
+ requested_partitions[2] = ANDROID_PARTITION_INIT_BOOT;
+ }
+
ops = avb_ops_user_new();
if (ops == NULL) {
printf("avb_ops_user_new() failed!\n");
@@ -497,7 +808,7 @@
if (unlocked & LOCK_MASK)
flags |= AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR;
- if(load_metadata(ops->ab_ops, &ab_data, &ab_data_orig)) {
+ if (load_metadata(ops->ab_ops, &ab_data, &ab_data_orig)) {
printf("Can not load metadata\n");
return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
}
@@ -509,8 +820,30 @@
else
slot_index_to_boot = 0;
- if (strcmp(boot_partname, "recovery") == 0)
+ if (strcmp(boot_partname, ANDROID_PARTITION_RECOVERY) == 0)
flags |= AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
+
+#ifdef CONFIG_MP_BOOT
+ preload_user_data.boot.addr = (void *)mpb_post(1);
+ preload_user_data.boot.size = (size_t)mpb_post(2);
+#endif
+
+ /* use preload one if available */
+ if (preload_user_data.boot.addr) {
+ data = (struct AvbOpsData *)(ops->user_data);
+
+ data->slot_suffix = slot_suffix;
+ data->boot = preload_user_data.boot;
+ data->vendor_boot = preload_user_data.vendor_boot;
+ data->init_boot = preload_user_data.init_boot;
+ data->resource = preload_user_data.resource;
+ } else {
+ ret = avb_image_distribute_prepare(slot_data, ops, slot_suffix);
+ if (ret < 0) {
+ printf("avb image distribute prepare failed %d\n", ret);
+ return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ }
+ }
retry_verify:
verify_result =
@@ -519,10 +852,10 @@
slot_suffix,
flags,
AVB_HASHTREE_ERROR_MODE_RESTART,
- &slot_data[0]);
+ &slot_data);
if (verify_result != AVB_SLOT_VERIFY_RESULT_OK &&
verify_result != AVB_SLOT_VERIFY_RESULT_ERROR_PUBLIC_KEY_REJECTED) {
- if (retry_no_vbmeta_partition && strcmp(boot_partname, "recovery") == 0) {
+ if (retry_no_vbmeta_partition && strcmp(boot_partname, ANDROID_PARTITION_RECOVERY) == 0) {
printf("Verify recovery with vbmeta.\n");
flags &= ~AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION;
retry_no_vbmeta_partition = 0;
@@ -558,7 +891,7 @@
break;
}
- if (!slot_data[0]) {
+ if (!slot_data) {
can_boot = 0;
goto out;
}
@@ -569,12 +902,12 @@
int len = 0;
char *bootargs, *newbootargs;
#ifdef CONFIG_ANDROID_AVB_ROLLBACK_INDEX
- if (rk_avb_update_stored_rollback_indexes_for_slot(ops, slot_data[0]))
+ if (rk_avb_update_stored_rollback_indexes_for_slot(ops, slot_data))
printf("Fail to update the rollback indexes.\n");
#endif
- if (*slot_data[0]->cmdline) {
- debug("Kernel command line: %s\n", slot_data[0]->cmdline);
- len += strlen(slot_data[0]->cmdline);
+ if (slot_data->cmdline) {
+ debug("Kernel command line: %s\n", slot_data->cmdline);
+ len += strlen(slot_data->cmdline);
}
bootargs = env_get("bootargs");
@@ -593,49 +926,15 @@
strcpy(newbootargs, bootargs);
strcat(newbootargs, " ");
}
- if (*slot_data[0]->cmdline)
- strcat(newbootargs, slot_data[0]->cmdline);
+ if (slot_data->cmdline)
+ strcat(newbootargs, slot_data->cmdline);
env_set("bootargs", newbootargs);
- hdr = (void *)slot_data[0]->loaded_partitions->data;
-
- /*
- * populate boot_img_hdr_v34
- *
- * If allow verification error: the image is loaded by
- * ops->get_preloaded_partition() which auto populates
- * boot_img_hdr_v34.
- *
- * If not allow verification error: the image is full loaded
- * by ops->read_from_partition() which doesn't populate
- * boot_img_hdr_v34, we need to fix it here.
- */
- if (hdr->header_version >= 3 &&
- !(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR)) {
- struct andr_img_hdr *v3hdr;
- struct blk_desc *dev_desc;
- disk_partition_t part;
-
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc)
- return -1;
-
- if (part_get_info_by_name(dev_desc,
- boot_partname, &part) < 0)
- return -1;
-
- v3hdr = populate_andr_img_hdr(dev_desc, &part);
- if (v3hdr) {
- memcpy(hdr, v3hdr, sizeof(*v3hdr));
- free(v3hdr);
- }
- }
-
- /* Reserve page_size */
- load_address -= hdr->page_size;
- if (android_image_memcpy_separate(hdr, &load_address)) {
- printf("Failed to separate copy android image\n");
- return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ /* if need, distribute full image to where they should be */
+ ret = avb_image_distribute_finish(slot_data, flags, &load_address);
+ if (ret) {
+ printf("avb image distribute finish failed %d\n", ret);
+ return ret;
}
*android_load_address = load_address;
} else {
@@ -649,8 +948,8 @@
verify_result = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
}
- if (slot_data[0] != NULL)
- avb_slot_verify_data_free(slot_data[0]);
+ if (slot_data != NULL)
+ avb_slot_verify_data_free(slot_data);
if ((unlocked & LOCK_MASK) && can_boot)
return 0;
@@ -1047,10 +1346,6 @@
printf("Android image load failed\n");
return -1;
}
-#endif
-
-#ifdef CONFIG_ANDROID_AB
- ab_update_root_uuid();
#endif
/* Set Android root variables. */
diff --git a/u-boot/common/board_f.c b/u-boot/common/board_f.c
index 190e5a4..dd76efc 100644
--- a/u-boot/common/board_f.c
+++ b/u-boot/common/board_f.c
@@ -21,6 +21,7 @@
#include <init_helpers.h>
#include <malloc.h>
#include <mapmem.h>
+#include <mp_boot.h>
#include <os.h>
#include <post.h>
#include <relocate.h>
@@ -254,6 +255,9 @@
/* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
#endif
+#ifdef CONFIG_MP_BOOT
+ mpb_init_x(3);
+#endif
return 0;
}
diff --git a/u-boot/common/board_info.c b/u-boot/common/board_info.c
index b48fd1e..1d0155e 100644
--- a/u-boot/common/board_info.c
+++ b/u-boot/common/board_info.c
@@ -26,6 +26,7 @@
if (model)
printf("Model: %s\n", model);
#endif
+ printf("MPIDR: 0x%lx\n", (ulong)read_mpidr());
#ifdef CONFIG_ARM64_BOOT_AARCH32
if (!(gd->flags & GD_FLG_RELOC))
diff --git a/u-boot/common/board_r.c b/u-boot/common/board_r.c
index 74fee37..c3d7d9c 100644
--- a/u-boot/common/board_r.c
+++ b/u-boot/common/board_r.c
@@ -481,21 +481,6 @@
}
#endif
-#ifdef CONFIG_MTD_BLK
-static int initr_mtd_blk(void)
-{
-#ifndef CONFIG_USING_KERNEL_DTB
- struct blk_desc *dev_desc;
-
- puts("mtd_blk: ");
- dev_desc = rockchip_get_bootdev();
- if (dev_desc)
- mtd_blk_map_partitions(dev_desc);
-#endif
- return 0;
-}
-#endif
-
#if !defined(CONFIG_USING_KERNEL_DTB) || !defined(CONFIG_ENV_IS_NOWHERE)
/*
* Tell if it's OK to load the environment early in boot.
@@ -966,9 +951,6 @@
#endif
#ifdef CONFIG_CMD_ONENAND
initr_onenand,
-#endif
-#ifdef CONFIG_MTD_BLK
- initr_mtd_blk,
#endif
#ifdef CONFIG_MMC
initr_mmc,
diff --git a/u-boot/common/bootm.c b/u-boot/common/bootm.c
index fcb561d..1bc426b 100644
--- a/u-boot/common/bootm.c
+++ b/u-boot/common/bootm.c
@@ -31,7 +31,7 @@
#include <image.h>
#ifdef USE_HOSTCC
-#define CONFIG_SYS_BOOTM_LEN 0x4000000
+#define CONFIG_SYS_BOOTM_LEN 0x10000000
#endif
#ifndef CONFIG_SYS_BOOTM_LEN
diff --git a/u-boot/common/fb_mmc.c b/u-boot/common/fb_mmc.c
index e083daa..f292d0d 100755
--- a/u-boot/common/fb_mmc.c
+++ b/u-boot/common/fb_mmc.c
@@ -31,6 +31,15 @@
#define CONFIG_FASTBOOT_MBR_NAME "mbr"
#endif
+#ifndef CONFIG_FASTBOOT_IDBLOCK_NAME
+#define CONFIG_FASTBOOT_IDBLOCK_NAME "idblock"
+#endif
+
+#define CONFIG_FASTBOOT_MMC_BLOCK_SIZE 512
+#define CONFIG_FASTBOOT_IDBLOCK_SECTOR 64
+/* idblock sector：64 ~ 64 + 5 * 1024(512K for each MiniloadAll.bin) */
+#define CONFIG_FASTBOOT_IDBLOCK_SECTOR_SIZE 5184
+
#define BOOT_PARTITION_NAME "boot"
#define FASTBOOT_MAX_BLK_WRITE 16384
static ulong timer;
@@ -363,6 +372,14 @@
}
#endif
+ if (strcmp(cmd, CONFIG_FASTBOOT_IDBLOCK_NAME) == 0) {
+ printf("%s: updating IDBLOCK\n", __func__);
+ info.blksz = CONFIG_FASTBOOT_MMC_BLOCK_SIZE;
+ info.start = CONFIG_FASTBOOT_IDBLOCK_SECTOR;
+ info.size = CONFIG_FASTBOOT_IDBLOCK_SECTOR_SIZE;
+ goto download;
+ }
+
#ifdef CONFIG_ANDROID_BOOT_IMAGE
if (strncasecmp(cmd, "zimage", 6) == 0) {
fb_mmc_update_zimage(dev_desc, download_buffer, download_bytes, response);
@@ -376,6 +393,7 @@
return;
}
+download:
if (is_sparse_image(download_buffer)) {
struct fb_mmc_sparse sparse_priv;
struct sparse_storage sparse;
diff --git a/u-boot/common/image-android.c b/u-boot/common/image-android.c
index fbd9bad..a77c0f3 100644
--- a/u-boot/common/image-android.c
+++ b/u-boot/common/image-android.c
@@ -6,14 +6,16 @@
#include <common.h>
#include <image.h>
-#include <android_image.h>
+#include <android_ab.h>
#include <android_bootloader.h>
+#include <android_image.h>
#include <malloc.h>
#include <mapmem.h>
#include <errno.h>
#include <boot_rkimg.h>
#include <crypto.h>
#include <sysmem.h>
+#include <mp_boot.h>
#include <u-boot/sha1.h>
#ifdef CONFIG_RKIMG_BOOTLOADER
#include <asm/arch/resource_img.h>
@@ -28,8 +30,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
-#define ANDROID_Q_VER 10
#define ANDROID_PARTITION_VENDOR_BOOT "vendor_boot"
+#define ANDROID_PARTITION_INIT_BOOT "init_boot"
#define BLK_CNT(_num_bytes, _block_size) \
((_num_bytes + _block_size - 1) / _block_size)
@@ -37,27 +39,110 @@
static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
static u32 android_kernel_comp_type = IH_COMP_NONE;
-u32 android_image_major_version(void)
+static int android_version_init(void)
{
- /* MSB 7-bits */
- return gd->bd->bi_andr_version >> 25;
+ struct andr_img_hdr *hdr = NULL;
+ struct blk_desc *desc;
+ const char *part_name = PART_BOOT;
+ disk_partition_t part;
+ int os_version;
+
+ desc = rockchip_get_bootdev();
+ if (!desc) {
+ printf("No bootdev\n");
+ return -1;
+ }
+
+#ifdef CONFIG_ANDROID_AB
+ part_name = ab_can_find_recovery_part() ? PART_RECOVERY : PART_BOOT;
+#endif
+ if (part_get_info_by_name(desc, part_name, &part) < 0)
+ return -1;
+
+ hdr = populate_andr_img_hdr(desc, &part);
+ if (!hdr)
+ return -1;
+
+ os_version = hdr->os_version;
+ if (os_version)
+ printf("Android %u.%u, Build %u.%u, v%d\n",
+ (os_version >> 25) & 0x7f, (os_version >> 18) & 0x7F,
+ ((os_version >> 4) & 0x7f) + 2000, os_version & 0x0F,
+ hdr->header_version);
+ free(hdr);
+
+ return (os_version >> 25) & 0x7f;
}
u32 android_bcb_msg_sector_offset(void)
{
+ static int android_version = -1; /* static */
+
/*
- * Rockchip platforms defines BCB message at the 16KB offset of
- * misc partition while the Google defines it at 0x00 offset.
+ * get android os version:
*
- * From Android-Q, the 0x00 offset is mandary on Google VTS, so that
- * this is a compatibility according to android image 'os_version'.
+ * There are two types of misc.img:
+ * Rockchip platforms defines BCB message at the 16KB offset of
+ * misc.img except for the Android version >= 10. Because Google
+ * defines it at 0x00 offset, and from Android-10 it becoms mandary
+ * on Google VTS.
+ *
+ * So we must get android 'os_version' to identify which type we
+ * are using, then we could able to use rockchip_get_boot_mode()
+ * which reads BCB from misc.img.
*/
#ifdef CONFIG_RKIMG_BOOTLOADER
- return (android_image_major_version() >= ANDROID_Q_VER) ? 0x00 : 0x20;
+ if (android_version < 0)
+ android_version = android_version_init();
+
+ return (android_version >= 10) ? 0x00 : 0x20;
#else
return 0x00;
#endif
}
+
+#ifdef CONFIG_ROCKCHIP_RESOURCE_IMAGE
+int android_image_init_resource(struct blk_desc *desc,
+ disk_partition_t *out_part,
+ ulong *out_blk_offset)
+{
+ struct andr_img_hdr *hdr = NULL;
+ const char *part_name = ANDROID_PARTITION_BOOT;
+ disk_partition_t part;
+ ulong offset;
+ int ret = 0;
+
+ if (!desc)
+ return -ENODEV;
+
+#ifndef CONFIG_ANDROID_AB
+ if (rockchip_get_boot_mode() == BOOT_MODE_RECOVERY)
+ part_name = ANDROID_PARTITION_RECOVERY;
+#endif
+ if (part_get_info_by_name(desc, part_name, &part) < 0)
+ return -ENOENT;
+
+ hdr = populate_andr_img_hdr(desc, &part);
+ if (!hdr)
+ return -EINVAL;
+
+ if (hdr->header_version >= 2 && hdr->dtb_size)
+ env_update("bootargs", "androidboot.dtb_idx=0");
+
+ if (hdr->header_version <= 2) {
+ offset = hdr->page_size +
+ ALIGN(hdr->kernel_size, hdr->page_size) +
+ ALIGN(hdr->ramdisk_size, hdr->page_size);
+ *out_part = part;
+ *out_blk_offset = DIV_ROUND_UP(offset, desc->blksz);
+ } else {
+ ret = -EINVAL;
+ }
+ free(hdr);
+
+ return ret;
+}
+#endif
static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
{
@@ -323,7 +408,7 @@
typedef enum {
IMG_KERNEL,
- IMG_RAMDISK,
+ IMG_RAMDISK, /* within boot.img or init_boot.img(Android-13 or later) */
IMG_SECOND,
IMG_RECOVERY_DTBO,
IMG_RK_DTB, /* within resource.img in second position */
@@ -343,7 +428,9 @@
{
struct blk_desc *desc = rockchip_get_bootdev();
disk_partition_t part_vendor_boot;
+ disk_partition_t part_init_boot;
__maybe_unused u32 typesz;
+ u32 andr_version = (hdr->os_version >> 25) & 0x7f;
ulong pgsz = hdr->page_size;
ulong blksz = desc->blksz;
ulong blkcnt, blkoff;
@@ -352,6 +439,7 @@
ulong extra = 0;
ulong length;
void *buffer;
+ void *tmp = NULL;
int ret = 0;
switch (img) {
@@ -366,17 +454,20 @@
return -ENOMEM;
break;
case IMG_VENDOR_RAMDISK:
- if (part_get_info_by_name(desc,
- ANDROID_PARTITION_VENDOR_BOOT,
- &part_vendor_boot) < 0) {
- printf("No vendor boot partition\n");
- return -ENOENT;
+ if (hdr->vendor_boot_buf) {
+ ram_base = hdr->vendor_boot_buf;
+ } else {
+ if (part_get_info_by_name(desc,
+ ANDROID_PARTITION_VENDOR_BOOT,
+ &part_vendor_boot) < 0) {
+ printf("No vendor boot partition\n");
+ return -ENOENT;
+ }
+ ram_base = 0;
}
- /* Always load vendor boot from storage: avb full load boot/recovery */
+
blkstart = part_vendor_boot.start;
pgsz = hdr->vendor_page_size;
- ram_base = 0;
-
bsoffs = ALIGN(VENDOR_BOOT_HDRv3_SIZE, pgsz);
length = hdr->vendor_ramdisk_size;
buffer = (void *)env_get_ulong("ramdisk_addr_r", 16, 0);
@@ -400,7 +491,25 @@
return -ENOMEM;
break;
case IMG_RAMDISK:
- bsoffs = pgsz + ALIGN(hdr->kernel_size, pgsz);
+ /* get ramdisk from init_boot.img ? */
+ if (hdr->header_version >= 4 && andr_version >= 13) {
+ if (hdr->init_boot_buf) {
+ ram_base = hdr->init_boot_buf;
+ } else {
+ if (part_get_info_by_name(desc,
+ ANDROID_PARTITION_INIT_BOOT, &part_init_boot) < 0) {
+ printf("No init boot partition\n");
+ return -ENOENT;
+ }
+ blkstart = part_init_boot.start;
+ ram_base = 0;
+ }
+ bsoffs = pgsz;
+ } else {
+ /* get ramdisk from generic boot.img */
+ bsoffs = pgsz + ALIGN(hdr->kernel_size, pgsz);
+ }
+
length = hdr->ramdisk_size;
buffer = (void *)env_get_ulong("ramdisk_addr_r", 16, 0);
blkcnt = DIV_ROUND_UP(hdr->ramdisk_size, blksz);
@@ -412,15 +521,20 @@
* | ramdisk |
* |----------------|
*
- * ramdisk_addr_r v3:
+ * ramdisk_addr_r v3 (Android-11 and later):
* |----------------|---------|
* | vendor-ramdisk | ramdisk |
* |----------------|---------|
*
- * ramdisk_addr_r v4:
+ * ramdisk_addr_r v4 (Android-12 and later):
* |----------------|---------|------------|------------|
* | vendor-ramdisk | ramdisk | bootconfig | bootparams |
* |----------------|---------|------------|------------|
+ *
+ * ramdisk_addr_r v4 + init_boot(Android-13 and later):
+ * |----------------|----------------|------------|------------|
+ * | vendor-ramdisk | (init_)ramdisk | bootconfig | bootparams |
+ * |----------------|----------------|------------|------------|
*/
if (hdr->header_version >= 3) {
buffer += hdr->vendor_ramdisk_size;
@@ -439,17 +553,20 @@
case IMG_BOOTCONFIG:
if (hdr->header_version < 4)
return 0;
- if (part_get_info_by_name(desc,
- ANDROID_PARTITION_VENDOR_BOOT,
- &part_vendor_boot) < 0) {
- printf("No vendor boot partition\n");
- return -ENOENT;
- }
+ if (hdr->vendor_boot_buf) {
+ ram_base = hdr->vendor_boot_buf;
+ } else {
+ if (part_get_info_by_name(desc,
+ ANDROID_PARTITION_VENDOR_BOOT,
+ &part_vendor_boot) < 0) {
+ printf("No vendor boot partition\n");
+ return -ENOENT;
+ }
+ ram_base = 0;
+ }
blkstart = part_vendor_boot.start;
pgsz = hdr->vendor_page_size;
- ram_base = 0;
-
bsoffs = ALIGN(VENDOR_BOOT_HDRv4_SIZE, pgsz) +
ALIGN(hdr->vendor_ramdisk_size, pgsz) +
ALIGN(hdr->dtb_size, pgsz) +
@@ -471,7 +588,7 @@
ALIGN(hdr->ramdisk_size, pgsz);
length = hdr->second_size;
blkcnt = DIV_ROUND_UP(hdr->second_size, blksz);
- buffer = malloc(blkcnt * blksz);
+ buffer = tmp = malloc(blkcnt * blksz);
typesz = sizeof(hdr->second_size);
break;
case IMG_RECOVERY_DTBO:
@@ -481,7 +598,7 @@
ALIGN(hdr->second_size, pgsz);
length = hdr->recovery_dtbo_size;
blkcnt = DIV_ROUND_UP(hdr->recovery_dtbo_size, blksz);
- buffer = malloc(blkcnt * blksz);
+ buffer = tmp = malloc(blkcnt * blksz);
typesz = sizeof(hdr->recovery_dtbo_size);
break;
case IMG_DTB:
@@ -492,7 +609,7 @@
ALIGN(hdr->recovery_dtbo_size, pgsz);
length = hdr->dtb_size;
blkcnt = DIV_ROUND_UP(hdr->dtb_size, blksz);
- buffer = malloc(blkcnt * blksz);
+ buffer = tmp = malloc(blkcnt * blksz);
typesz = sizeof(hdr->dtb_size);
break;
case IMG_RK_DTB:
@@ -540,14 +657,19 @@
if (hdr->header_version < 3) {
#ifdef CONFIG_ANDROID_BOOT_IMAGE_HASH
#ifdef CONFIG_DM_CRYPTO
- crypto_sha_update(crypto, (u32 *)buffer, length);
- crypto_sha_update(crypto, (u32 *)&length, typesz);
+ if (crypto) {
+ crypto_sha_update(crypto, (u32 *)buffer, length);
+ crypto_sha_update(crypto, (u32 *)&length, typesz);
+ }
#else
sha1_update(&sha1_ctx, (void *)buffer, length);
sha1_update(&sha1_ctx, (void *)&length, typesz);
#endif
#endif
}
+
+ if (tmp)
+ free(tmp);
return 0;
}
@@ -605,7 +727,12 @@
return -1;
#ifdef CONFIG_ANDROID_BOOT_IMAGE_HASH
- if (hdr->header_version < 3) {
+ int verify = 1;
+
+#ifdef CONFIG_MP_BOOT
+ verify = mpb_post(3);
+#endif
+ if (hdr->header_version < 3 && verify) {
struct udevice *dev = NULL;
uchar hash[20];
#ifdef CONFIG_DM_CRYPTO
@@ -936,6 +1063,7 @@
const disk_partition_t *boot_img)
{
struct boot_img_hdr_v34 *boot_hdr;
+ disk_partition_t part;
long blk_cnt, blks_read;
blk_cnt = BLK_CNT(sizeof(struct boot_img_hdr_v34), dev_desc->blksz);
@@ -960,6 +1088,13 @@
printf("boot header %d, is not >= v3.\n",
boot_hdr->header_version);
return NULL;
+ }
+
+ /* Start from android-13 GKI, it doesn't assign 'os_version' */
+ if (boot_hdr->header_version >= 4 && boot_hdr->os_version == 0) {
+ if (part_get_info_by_name(dev_desc,
+ ANDROID_PARTITION_INIT_BOOT, &part) > 0)
+ boot_hdr->os_version = 13 << 25;
}
return boot_hdr;
@@ -1003,19 +1138,26 @@
return vboot_hdr;
}
-static int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
- const struct vendor_boot_img_hdr_v34 *vendor_hdr,
- struct andr_img_hdr *hdr)
+int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
+ const struct vendor_boot_img_hdr_v34 *vendor_boot_hdr,
+ const struct boot_img_hdr_v34 *init_boot_hdr,
+ struct andr_img_hdr *hdr, bool save_hdr)
{
memset(hdr->magic, 0, ANDR_BOOT_MAGIC_SIZE);
memcpy(hdr->magic, boot_hdr->magic, ANDR_BOOT_MAGIC_SIZE);
hdr->kernel_size = boot_hdr->kernel_size;
- /* don't use vendor_hdr->kernel_addr, we prefer "hdr + hdr->page_size" */
+ /* don't use vendor_boot_hdr->kernel_addr, we prefer "hdr + hdr->page_size" */
hdr->kernel_addr = ANDROID_IMAGE_DEFAULT_KERNEL_ADDR;
- /* generic ramdisk: immediately following the vendor ramdisk */
- hdr->boot_ramdisk_size = boot_hdr->ramdisk_size;
- hdr->ramdisk_size = boot_hdr->ramdisk_size;
+
+ /*
+ * generic ramdisk: immediately following the vendor ramdisk.
+ * It can be from init_boot.img or boot.img.
+ */
+ if (init_boot_hdr)
+ hdr->ramdisk_size = init_boot_hdr->ramdisk_size;
+ else
+ hdr->ramdisk_size = boot_hdr->ramdisk_size;
/* actually, useless */
hdr->ramdisk_addr = env_get_ulong("ramdisk_addr_r", 16, 0);
@@ -1024,7 +1166,7 @@
hdr->second_size = 0;
hdr->second_addr = 0;
- hdr->tags_addr = vendor_hdr->tags_addr;
+ hdr->tags_addr = vendor_boot_hdr->tags_addr;
/* fixed in v3 */
hdr->page_size = 4096;
@@ -1032,7 +1174,7 @@
hdr->os_version = boot_hdr->os_version;
memset(hdr->name, 0, ANDR_BOOT_NAME_SIZE);
- strncpy(hdr->name, (const char *)vendor_hdr->name, ANDR_BOOT_NAME_SIZE);
+ strncpy(hdr->name, (const char *)vendor_boot_hdr->name, ANDR_BOOT_NAME_SIZE);
/* removed in v3 */
memset(hdr->cmdline, 0, ANDR_BOOT_ARGS_SIZE);
@@ -1042,14 +1184,14 @@
hdr->recovery_dtbo_offset = 0;
hdr->header_size = boot_hdr->header_size;
- hdr->dtb_size = vendor_hdr->dtb_size;
- hdr->dtb_addr = vendor_hdr->dtb_addr;
+ hdr->dtb_size = vendor_boot_hdr->dtb_size;
+ hdr->dtb_addr = vendor_boot_hdr->dtb_addr;
/* boot_img_hdr_v34 fields */
- hdr->vendor_ramdisk_size = vendor_hdr->vendor_ramdisk_size;
- hdr->vendor_page_size = vendor_hdr->page_size;
- hdr->vendor_header_version = vendor_hdr->header_version;
- hdr->vendor_header_size = vendor_hdr->header_size;
+ hdr->vendor_ramdisk_size = vendor_boot_hdr->vendor_ramdisk_size;
+ hdr->vendor_page_size = vendor_boot_hdr->page_size;
+ hdr->vendor_header_version = vendor_boot_hdr->header_version;
+ hdr->vendor_header_size = vendor_boot_hdr->header_size;
hdr->total_cmdline = calloc(1, TOTAL_BOOT_ARGS_SIZE);
if (!hdr->total_cmdline)
@@ -1057,30 +1199,33 @@
strncpy(hdr->total_cmdline, (const char *)boot_hdr->cmdline,
sizeof(boot_hdr->cmdline));
strncat(hdr->total_cmdline, " ", 1);
- strncat(hdr->total_cmdline, (const char *)vendor_hdr->cmdline,
- sizeof(vendor_hdr->cmdline));
+ strncat(hdr->total_cmdline, (const char *)vendor_boot_hdr->cmdline,
+ sizeof(vendor_boot_hdr->cmdline));
/* new for header v4 */
- if (vendor_hdr->header_version > 3) {
+ if (vendor_boot_hdr->header_version >= 4) {
hdr->vendor_ramdisk_table_size =
- vendor_hdr->vendor_ramdisk_table_size;
+ vendor_boot_hdr->vendor_ramdisk_table_size;
hdr->vendor_ramdisk_table_entry_num =
- vendor_hdr->vendor_ramdisk_table_entry_num;
+ vendor_boot_hdr->vendor_ramdisk_table_entry_num;
hdr->vendor_ramdisk_table_entry_size =
- vendor_hdr->vendor_ramdisk_table_entry_size;
+ vendor_boot_hdr->vendor_ramdisk_table_entry_size;
/*
* If we place additional "androidboot.xxx" parameters after
* bootconfig, this field value should be increased,
* but not over than ANDROID_ADDITION_BOOTCONFIG_PARAMS_MAX_SIZE.
*/
hdr->vendor_bootconfig_size =
- vendor_hdr->vendor_bootconfig_size;
+ vendor_boot_hdr->vendor_bootconfig_size;
} else {
hdr->vendor_ramdisk_table_size = 0;
hdr->vendor_ramdisk_table_entry_num = 0;
hdr->vendor_ramdisk_table_entry_size = 0;
hdr->vendor_bootconfig_size = 0;
}
+
+ hdr->init_boot_buf = save_hdr ? (void *)init_boot_hdr : 0;
+ hdr->vendor_boot_buf = save_hdr ? (void *)vendor_boot_hdr : 0;
if (hdr->page_size < sizeof(*hdr)) {
printf("android hdr is over size\n");
@@ -1110,10 +1255,13 @@
disk_partition_t *part_boot)
{
disk_partition_t part_vendor_boot;
- struct vendor_boot_img_hdr_v34 *vboot_hdr;
- struct boot_img_hdr_v34 *boot_hdr;
- struct andr_img_hdr *andr_hdr;
+ disk_partition_t part_init_boot;
+ struct vendor_boot_img_hdr_v34 *vboot_hdr = NULL;
+ struct boot_img_hdr_v34 *iboot_hdr = NULL;
+ struct boot_img_hdr_v34 *boot_hdr = NULL;
+ struct andr_img_hdr *andr_hdr = NULL;
int header_version;
+ int andr_version;
if (!dev_desc || !part_boot)
return NULL;
@@ -1134,6 +1282,7 @@
header_version = andr_hdr->header_version;
free(andr_hdr);
+ andr_hdr = NULL;
if (header_version < 3) {
return extract_boot_image_v012_header(dev_desc, part_boot);
@@ -1150,6 +1299,23 @@
if (!boot_hdr || !vboot_hdr)
goto image_load_exit;
+ andr_version = (boot_hdr->os_version >> 25) & 0x7f;
+ if (header_version >= 4 && andr_version >= 13) {
+ if (part_get_info_by_name(dev_desc,
+ ANDROID_PARTITION_INIT_BOOT,
+ &part_init_boot) < 0) {
+ printf("No init boot partition\n");
+ return NULL;
+ }
+ iboot_hdr = extract_boot_image_v34_header(dev_desc, &part_init_boot);
+ if (!iboot_hdr)
+ goto image_load_exit;
+ if (!iboot_hdr->ramdisk_size) {
+ printf("No ramdisk in init boot partition\n");
+ goto image_load_exit;
+ }
+ }
+
andr_hdr = (struct andr_img_hdr *)
malloc(sizeof(struct andr_img_hdr));
if (!andr_hdr) {
@@ -1157,21 +1323,21 @@
goto image_load_exit;
}
- if (populate_boot_info(boot_hdr, vboot_hdr, andr_hdr)) {
+ if (populate_boot_info(boot_hdr, vboot_hdr,
+ iboot_hdr, andr_hdr, false)) {
printf("populate boot info failed\n");
goto image_load_exit;
}
- free(boot_hdr);
- free(vboot_hdr);
+image_load_exit:
+ if (boot_hdr)
+ free(boot_hdr);
+ if (iboot_hdr)
+ free(iboot_hdr);
+ if (vboot_hdr)
+ free(vboot_hdr);
return andr_hdr;
-
-image_load_exit:
- free(boot_hdr);
- free(vboot_hdr);
-
- return NULL;
}
return NULL;
diff --git a/u-boot/common/image-fdt.c b/u-boot/common/image-fdt.c
index 2c79b96..2884880 100644
--- a/u-boot/common/image-fdt.c
+++ b/u-boot/common/image-fdt.c
@@ -78,39 +78,16 @@
}
#endif
-/**
- * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
- * @lmb: pointer to lmb handle, will be used for memory mgmt
- * @fdt_blob: pointer to fdt blob base address
- *
- * Adds the memreserve regions in the dtb to the lmb block. Adding the
- * memreserve regions prevents u-boot from using them to store the initrd
- * or the fdt blob.
- */
-void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
+void boot_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
{
- uint64_t addr, size;
- int i, total;
int rsv_offset, offset;
fdt_size_t rsv_size;
fdt_addr_t rsv_addr;
- /* we needn't repeat do reserve, do_bootm_linux would call this again */
- static int rsv_done;
const void *prop;
+ int i = 0;
- if (fdt_check_header(fdt_blob) != 0 || rsv_done)
+ if (fdt_check_header(fdt_blob) != 0)
return;
-
- rsv_done = 1;
-
- total = fdt_num_mem_rsv(fdt_blob);
- for (i = 0; i < total; i++) {
- if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
- continue;
- printf(" reserving fdt memory region: addr=%llx size=%llx\n",
- (unsigned long long)addr, (unsigned long long)size);
- lmb_reserve(lmb, addr, size);
- }
rsv_offset = fdt_subnode_offset(fdt_blob, 0, "reserved-memory");
if (rsv_offset == -FDT_ERR_NOTFOUND)
@@ -128,13 +105,56 @@
&rsv_size, false);
if (rsv_addr == FDT_ADDR_T_NONE || !rsv_size)
continue;
- printf(" 'reserved-memory' %s: addr=%llx size=%llx\n",
- fdt_get_name(fdt_blob, offset, NULL),
- (unsigned long long)rsv_addr, (unsigned long long)rsv_size);
- lmb_reserve(lmb, rsv_addr, rsv_size);
+
+ i++;
+ /* be quiet while reserve */
+ if (lmb) {
+ lmb_reserve(lmb, rsv_addr, rsv_size);
+ } else {
+ if (i == 1)
+ printf("## reserved-memory:\n");
+
+ printf(" %s: addr=%llx size=%llx\n",
+ fdt_get_name(fdt_blob, offset, NULL),
+ (unsigned long long)rsv_addr, (unsigned long long)rsv_size);
+ }
}
}
+/**
+ * boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
+ * @lmb: pointer to lmb handle, will be used for memory mgmt
+ * @fdt_blob: pointer to fdt blob base address
+ *
+ * Adds the memreserve regions in the dtb to the lmb block. Adding the
+ * memreserve regions prevents u-boot from using them to store the initrd
+ * or the fdt blob.
+ */
+void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob)
+{
+ uint64_t addr, size;
+ int i, total;
+ /* we needn't repeat do reserve, do_bootm_linux would call this again */
+ static int rsv_done;
+
+ if (fdt_check_header(fdt_blob) != 0 || rsv_done)
+ return;
+
+ rsv_done = 1;
+
+ total = fdt_num_mem_rsv(fdt_blob);
+ for (i = 0; i < total; i++) {
+ if (fdt_get_mem_rsv(fdt_blob, i, &addr, &size) != 0)
+ continue;
+ printf(" reserving fdt memory region: addr=%llx size=%llx\n",
+ (unsigned long long)addr, (unsigned long long)size);
+ lmb_reserve(lmb, addr, size);
+ }
+
+ /* lmb_reserve() for "reserved-memory" */
+ boot_mem_rsv_regions(lmb, fdt_blob);
+}
+
#ifdef CONFIG_SYSMEM
/**
* boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
diff --git a/u-boot/common/image-fit.c b/u-boot/common/image-fit.c
index d364788..0ee9eab 100644
--- a/u-boot/common/image-fit.c
+++ b/u-boot/common/image-fit.c
@@ -2175,6 +2175,7 @@
fit_image_check_os(fit, noffset, IH_OS_ARM_TRUSTED_FIRMWARE) ||
fit_image_check_os(fit, noffset, IH_OS_OP_TEE) ||
fit_image_check_os(fit, noffset, IH_OS_U_BOOT) ||
+ fit_image_check_os(fit, noffset, IH_OS_QNX) ||
fit_image_check_os(fit, noffset, IH_OS_OPENRTOS);
/*
diff --git a/u-boot/common/image-sparse.c b/u-boot/common/image-sparse.c
index f1382bd..505428e 100644
--- a/u-boot/common/image-sparse.c
+++ b/u-boot/common/image-sparse.c
@@ -56,10 +56,10 @@
lbaint_t blk;
lbaint_t blkcnt;
lbaint_t blks;
- uint32_t bytes_written = 0;
+ uint64_t bytes_written = 0;
unsigned int chunk;
unsigned int offset;
- unsigned int chunk_data_sz;
+ uint64_t chunk_data_sz;
uint32_t *fill_buf = NULL;
uint32_t fill_val;
sparse_header_t *sparse_header;
@@ -130,8 +130,8 @@
sizeof(chunk_header_t));
}
- chunk_data_sz = sparse_header->blk_sz * chunk_header->chunk_sz;
- blkcnt = chunk_data_sz / info->blksz;
+ chunk_data_sz = ((u64)sparse_header->blk_sz) * chunk_header->chunk_sz;
+ blkcnt = DIV_ROUND_UP_ULL(chunk_data_sz, info->blksz);
switch (chunk_header->chunk_type) {
case CHUNK_TYPE_RAW:
if (chunk_header->total_sz !=
@@ -161,7 +161,7 @@
return;
}
blk += blks;
- bytes_written += blkcnt * info->blksz;
+ bytes_written += ((u64)blkcnt) * info->blksz;
total_blocks += chunk_header->chunk_sz;
data += chunk_data_sz;
break;
@@ -222,8 +222,9 @@
blk += blks;
i += j;
}
- bytes_written += blkcnt * info->blksz;
- total_blocks += chunk_data_sz / sparse_header->blk_sz;
+ bytes_written += ((u64)blkcnt) * info->blksz;
+ total_blocks += DIV_ROUND_UP_ULL(chunk_data_sz,
+ sparse_header->blk_sz);
free(fill_buf);
break;
@@ -253,7 +254,7 @@
debug("Wrote %d blocks, expected to write %d blocks\n",
total_blocks, sparse_header->total_blks);
- printf("........ wrote %u bytes to '%s'\n", bytes_written, part_name);
+ printf("........ wrote %llu bytes to '%s'\n", bytes_written, part_name);
if (total_blocks != sparse_header->total_blks)
fastboot_fail("sparse image write failure", response);
diff --git a/u-boot/common/mp_boot_rk3528.S b/u-boot/common/mp_boot_rk3528.S
new file mode 100644
index 0000000..6d7c51a
--- /dev/null
+++ b/u-boot/common/mp_boot_rk3528.S
@@ -0,0 +1,9682 @@
+ .arch armv8-a+nosimd
+ .file "mp_boot.c"
+ .text
+.Ltext0:
+ .cfi_sections .debug_frame
+ .section .text.mpb_task_set_state,"ax",@progbits
+ .align 2
+ .type mpb_task_set_state, %function
+mpb_task_set_state:
+.LFB225:
+ .file 1 "common/mp_boot.c"
+ .loc 1 227 0
+ .cfi_startproc
+.LVL0:
+.LBB30:
+.LBB31:
+ .loc 1 146 0
+ mov x4, 136314880
+ mov w3, 1
+ lsl w3, w3, w1
+ ldr w5, [x4]
+.LBE31:
+.LBE30:
+ .loc 1 232 0
+ tst w3, w5
+ beq .L11
+.LBB32:
+.LBB33:
+ .loc 1 199 0
+ uxtw x5, w0
+ mov x3, 328
+ umull x0, w0, w3
+.LVL1:
+ madd x4, x5, x3, x4
+ mov w3, 0
+ ldrb w6, [x4, 328]
+ mov x4, 20
+ movk x4, 0x820, lsl 16
+ add x4, x0, x4
+.L3:
+.LVL2:
+ cmp w3, w6
+ blt .L5
+.LVL3:
+.L11:
+.LBE33:
+.LBE32:
+ .loc 1 252 0
+ mov w0, 0
+ ret
+.LVL4:
+.L5:
+.LBB35:
+.LBB34:
+ .loc 1 200 0
+ ldr w7, [x4], 40
+ cmp w1, w7
+ beq .L4
+ .loc 1 199 0
+ add w3, w3, 1
+.LVL5:
+ b .L3
+.L4:
+.LVL6:
+.LBE34:
+.LBE35:
+ .loc 1 239 0
+ mov x8, 328
+ sxtw x4, w3
+ mov x7, 40
+ .loc 1 240 0
+ add x0, x0, 16
+ .loc 1 239 0
+ mul x5, x5, x8
+ .loc 1 227 0
+ stp x29, x30, [sp, -16]!
+ .cfi_def_cfa_offset 16
+ .cfi_offset 29, -16
+ .cfi_offset 30, -8
+ .loc 1 239 0
+ nop // between mem op and mult-accumulate
+ madd x4, x4, x7, x5
+ mov x6, 136314880
+ .loc 1 240 0
+ smaddl x3, w3, w7, x0
+ .loc 1 227 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 239 0
+ add x4, x6, x4
+ .loc 1 227 0
+ .loc 1 239 0
+ add w1, w1, w2
+.LVL7:
+ .loc 1 240 0
+ add x0, x3, x6
+ .loc 1 239 0
+ str w1, [x4, 16]
+ .loc 1 241 0
+ add x1, x0, 4
+ bl flush_dcache_range
+.LVL8:
+ .loc 1 252 0
+ mov w0, 0
+ ldp x29, x30, [sp], 16
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE225:
+ .size mpb_task_set_state, .-mpb_task_set_state
+ .section .text.mpb_quit_load_image,"ax",@progbits
+ .align 2
+ .type mpb_quit_load_image, %function
+mpb_quit_load_image:
+.LFB238:
+ .loc 1 560 0
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ .loc 1 563 0
+ bl rockchip_get_boot_mode
+.LVL9:
+ cmp w0, 1
+ bne .L15
+ mov w19, w0
+.LBB38:
+.LBB39:
+ .loc 1 564 0
+ adrp x0, .LANCHOR0
+ ldr w1, [x0, #:lo12:.LANCHOR0]
+ cbnz w1, .L13
+ .loc 1 565 0
+ str w19, [x0, #:lo12:.LANCHOR0]
+ .loc 1 566 0
+ adrp x0, .LC1
+ add x0, x0, :lo12:.LC1
+ bl printf
+.LVL10:
+.L13:
+.LBE39:
+.LBE38:
+ .loc 1 573 0
+ mov w0, w19
+ ldr x19, [sp, 16]
+ ldp x29, x30, [sp], 32
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+ ret
+.L15:
+ .cfi_restore_state
+ .loc 1 572 0
+ mov w19, 0
+ b .L13
+ .cfi_endproc
+.LFE238:
+ .size mpb_quit_load_image, .-mpb_quit_load_image
+ .section .text.spl_init_display,"ax",@progbits
+ .align 2
+ .weak spl_init_display
+ .type spl_init_display, %function
+spl_init_display:
+.LFB252:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE252:
+ .size spl_init_display, .-spl_init_display
+ .section .text.spl_load_baseparamter,"ax",@progbits
+ .align 2
+ .weak spl_load_baseparamter
+ .type spl_load_baseparamter, %function
+spl_load_baseparamter:
+.LFB250:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE250:
+ .size spl_load_baseparamter, .-spl_load_baseparamter
+ .section .text.spl_load_fit,"ax",@progbits
+ .align 2
+ .weak spl_load_fit
+ .type spl_load_fit, %function
+spl_load_fit:
+.LFB248:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE248:
+ .size spl_load_fit, .-spl_load_fit
+ .section .text.spl_load_android,"ax",@progbits
+ .align 2
+ .weak spl_load_android
+ .type spl_load_android, %function
+spl_load_android:
+.LFB246:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE246:
+ .size spl_load_android, .-spl_load_android
+ .section .text.spl_hash_android,"ax",@progbits
+ .align 2
+ .weak spl_hash_android
+ .type spl_hash_android, %function
+spl_hash_android:
+.LFB244:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE244:
+ .size spl_hash_android, .-spl_hash_android
+ .section .text.spl_dummy,"ax",@progbits
+ .align 2
+ .weak spl_dummy
+ .type spl_dummy, %function
+spl_dummy:
+.LFB218:
+ .loc 1 52 0
+ .cfi_startproc
+.LVL11:
+ .loc 1 52 0
+ mov w0, 0
+.LVL12:
+ ret
+ .cfi_endproc
+.LFE218:
+ .size spl_dummy, .-spl_dummy
+ .section .text.mpb_task_is_done,"ax",@progbits
+ .align 2
+ .global mpb_task_is_done
+ .type mpb_task_is_done, %function
+mpb_task_is_done:
+.LFB226:
+ .loc 1 261 0
+ .cfi_startproc
+.LVL13:
+.LBB40:
+.LBB41:
+ .loc 1 146 0
+ mov x2, 136314880
+ mov w1, 1
+ lsl w1, w1, w0
+ ldr w2, [x2]
+.LBE41:
+.LBE40:
+ .loc 1 265 0
+ tst w1, w2
+ beq .L39
+ .loc 1 261 0
+ stp x29, x30, [sp, -96]!
+ .cfi_def_cfa_offset 96
+ .cfi_offset 29, -96
+ .cfi_offset 30, -88
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -80
+ .cfi_offset 20, -72
+ mov w19, w0
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -48
+ .cfi_offset 24, -40
+ .loc 1 275 0
+ mov w24, -559087616
+ .loc 1 261 0
+ str x27, [sp, 80]
+ .loc 1 275 0
+ add w24, w0, w24
+ .cfi_offset 27, -16
+ .loc 1 277 0
+ sub w27, w0, #65536
+ .loc 1 261 0
+ stp x21, x22, [sp, 32]
+ stp x25, x26, [sp, 64]
+ .cfi_offset 21, -64
+ .cfi_offset 22, -56
+ .cfi_offset 25, -32
+ .cfi_offset 26, -24
+ mov x21, 0
+.LVL14:
+.L31:
+ mov x22, 16
+ mov x20, 20
+ .loc 1 269 0
+ mov x26, 328
+ movk x22, 0x820, lsl 16
+ movk x20, 0x820, lsl 16
+ add x22, x21, x22
+ add x20, x21, x20
+ .loc 1 261 0
+ mov w23, 0
+ .loc 1 269 0
+ movk x26, 0x820, lsl 16
+ .loc 1 279 0
+ mov w25, 1431655765
+ b .L27
+.LVL15:
+.L30:
+ .loc 1 270 0
+ ldr w0, [x20]
+ cmp w19, w0
+ beq .L26
+.L29:
+ .loc 1 269 0
+ add w23, w23, 1
+.LVL16:
+ add x22, x22, 40
+ add x20, x20, 40
+.LVL17:
+.L27:
+ .loc 1 269 0 is_stmt 0 discriminator 1
+ ldrb w0, [x21, x26]
+ cmp w23, w0
+ blt .L30
+.LVL18:
+ add x21, x21, 328
+ .loc 1 268 0 is_stmt 1 discriminator 2
+ cmp x21, 1312
+ bne .L31
+ .loc 1 286 0
+ mov w0, 0
+.L23:
+ .loc 1 287 0
+ ldp x19, x20, [sp, 16]
+.LVL19:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL20:
+ ldp x25, x26, [sp, 64]
+ ldr x27, [sp, 80]
+.LVL21:
+ ldp x29, x30, [sp], 96
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL22:
+.L26:
+ .cfi_restore_state
+ .loc 1 272 0
+ mov x0, x22
+ mov x1, x20
+ bl invalidate_dcache_range
+.LVL23:
+ .loc 1 275 0
+ ldr w0, [x22]
+ cmp w0, w24
+ beq .L32
+ .loc 1 277 0
+ cmp w0, w27
+ beq .L24
+ .loc 1 279 0
+ add w1, w19, w25
+ cmp w0, w1
+ bne .L29
+ .loc 1 280 0
+ mov w0, -2
+ b .L23
+.L24:
+ .loc 1 266 0
+ mov w0, -1
+ b .L23
+.L32:
+ .loc 1 276 0
+ mov w0, 1
+ b .L23
+.LVL24:
+.L39:
+ .cfi_def_cfa 31, 0
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 27
+ .cfi_restore 29
+ .cfi_restore 30
+ .loc 1 266 0
+ mov w0, -1
+.LVL25:
+ .loc 1 287 0
+ ret
+ .cfi_endproc
+.LFE226:
+ .size mpb_task_is_done, .-mpb_task_is_done
+ .section .text.mpb_task_dump,"ax",@progbits
+ .align 2
+ .global mpb_task_dump
+ .type mpb_task_dump, %function
+mpb_task_dump:
+.LFB227:
+ .loc 1 290 0
+ .cfi_startproc
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ .loc 1 294 0
+ mov x0, 136314880
+ .loc 1 290 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 294 0
+ ldr x1, [x0, 1360]
+ ldr x2, [x0, 1368]
+ adrp x0, .LC2
+ .loc 1 290 0
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .loc 1 294 0
+ mov x20, 20
+ .loc 1 290 0
+ stp x23, x24, [sp, 48]
+ .loc 1 294 0
+ movk x20, 0x820, lsl 16
+ .loc 1 290 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .loc 1 299 0
+ adrp x23, .LANCHOR1
+ adrp x24, .LC3
+ .loc 1 296 0
+ mov w21, 0
+ .loc 1 299 0
+ add x23, x23, :lo12:.LANCHOR1
+ add x24, x24, :lo12:.LC3
+ .loc 1 294 0
+ add x0, x0, :lo12:.LC2
+ .loc 1 290 0
+ str x25, [sp, 64]
+ .cfi_offset 25, -16
+ .loc 1 294 0
+ bl printf
+.LVL26:
+.L43:
+ .loc 1 290 0
+ mov x19, x20
+ mov w22, 0
+ .loc 1 300 0
+ adrp x25, .LC4
+ b .L46
+.LVL27:
+.L44:
+ .loc 1 299 0 discriminator 3
+ ldr w2, [x19]
+ mov w1, w21
+ mov x0, x24
+ .loc 1 297 0 discriminator 3
+ add w22, w22, 1
+.LVL28:
+ add x19, x19, 40
+ .loc 1 299 0 discriminator 3
+ ldr x3, [x23, w2, uxtw 3]
+ bl printf
+.LVL29:
+ .loc 1 300 0 discriminator 3
+ ldr w1, [x19, -40]
+ add x0, x25, :lo12:.LC4
+ bl printf
+.LVL30:
+ .loc 1 301 0 discriminator 3
+ ldr x1, [x19, -52]
+ adrp x0, .LC5
+ add x0, x0, :lo12:.LC5
+ bl printf
+.LVL31:
+ .loc 1 302 0 discriminator 3
+ ldr w1, [x19, -44]
+ adrp x0, .LC6
+ add x0, x0, :lo12:.LC6
+ bl printf
+.LVL32:
+ .loc 1 303 0 discriminator 3
+ ldr w1, [x19, -28]
+ adrp x0, .LC7
+ add x0, x0, :lo12:.LC7
+ bl printf
+.LVL33:
+ .loc 1 304 0 discriminator 3
+ ldr x1, [x19, -20]
+ adrp x0, .LC8
+ add x0, x0, :lo12:.LC8
+ bl printf
+.LVL34:
+ .loc 1 305 0 discriminator 3
+ ldr w1, [x19, -36]
+ adrp x0, .LC9
+ add x0, x0, :lo12:.LC9
+ bl printf
+.LVL35:
+ .loc 1 306 0 discriminator 3
+ ldr w1, [x19, -32]
+ adrp x0, .LC10
+ add x0, x0, :lo12:.LC10
+ bl printf
+.LVL36:
+.L46:
+ .loc 1 297 0 discriminator 1
+ ldrb w0, [x20, 308]
+ cmp w22, w0
+ blt .L44
+ .loc 1 296 0 discriminator 2
+ add w21, w21, 1
+.LVL37:
+ add x20, x20, 328
+ cmp w21, 4
+ bne .L43
+ .loc 1 310 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+.LVL38:
+ ldp x23, x24, [sp, 48]
+ ldr x25, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE227:
+ .size mpb_task_dump, .-mpb_task_dump
+ .section .text.core_task_run.part.2,"ax",@progbits
+ .align 2
+ .type core_task_run.part.2, %function
+core_task_run.part.2:
+.LFB242:
+ .loc 1 370 0
+ .cfi_startproc
+.LVL39:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ mov w19, w0
+ stp x21, x22, [sp, 32]
+ mov w20, w2
+.LVL40:
+ stp x23, x24, [sp, 48]
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ and x22, x1, 255
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -16
+ .cfi_offset 26, -8
+.LBB52:
+.LBB53:
+ .loc 1 319 0
+ cbz w3, .L49
+ mov w25, w3
+ mov w23, 0
+ mov w21, 0
+ .loc 1 324 0
+ mov w26, 1
+.LVL41:
+.L54:
+ lsl w0, w26, w21
+ tst w0, w25
+ beq .L50
+.L51:
+ .loc 1 319 0
+ mov w24, 20000
+.L52:
+.LVL42:
+ .loc 1 329 0
+ mov w0, w21
+ bl mpb_task_is_done
+.LVL43:
+ cbz w0, .L53
+ .loc 1 344 0
+ mov w0, w21
+ bl mpb_task_is_done
+.LVL44:
+ .loc 1 345 0
+ cmp w0, 0
+ cinc w23, w23, lt
+.LVL45:
+.L50:
+ .loc 1 323 0
+ add w21, w21, 1
+.LVL46:
+ cmp w21, 8
+ bne .L54
+.LVL47:
+.LBE53:
+.LBE52:
+ .loc 1 387 0
+ cbz w23, .L49
+.LVL48:
+ .loc 1 389 0
+ uxtw x1, w19
+ mov x2, 328
+ sxtw x0, w22
+ mul x1, x1, x2
+ mov x2, 40
+ madd x0, x0, x2, x1
+ mov x1, 136314880
+ add x0, x1, x0
+ ldr w0, [x0, 28]
+ cbnz w0, .L55
+.LVL49:
+.L56:
+ .loc 1 410 0
+ mov w2, w20
+ mov w1, w19
+ adrp x0, .LC12
+ add x0, x0, :lo12:.LC12
+ bl printf
+.LVL50:
+ .loc 1 374 0
+ mov w21, 0
+ .loc 1 411 0
+ mov w2, 1431655765
+ mov w1, w20
+ mov w0, w19
+ bl mpb_task_set_state
+.LVL51:
+ b .L62
+.LVL52:
+.L53:
+.LBB55:
+.LBB54:
+ .loc 1 330 0
+ mov x0, 100
+ bl udelay
+.LVL53:
+ .loc 1 333 0
+ subs w24, w24, #1
+.LVL54:
+ bne .L52
+.LVL55:
+ .loc 1 337 0
+ bl mpb_task_dump
+.LVL56:
+ b .L51
+.LVL57:
+.L49:
+.LBE54:
+.LBE55:
+ .loc 1 392 0
+ uxtw x1, w19
+ mov x2, 328
+ sxtw x0, w22
+ mul x1, x1, x2
+ mov x2, 40
+ madd x0, x0, x2, x1
+ mov x1, 136314880
+ add x0, x1, x0
+ ldr w0, [x0, 28]
+ cbnz w0, .L56
+.L55:
+.LVL58:
+ .loc 1 397 0
+ mov w2, w20
+ mov w1, w19
+ adrp x0, .LC13
+ add x0, x0, :lo12:.LC13
+ bl printf
+.LVL59:
+ .loc 1 401 0
+ uxtw x24, w19
+ .loc 1 398 0
+ bl get_ticks
+.LVL60:
+ mov x23, x0
+.LVL61:
+ .loc 1 400 0
+ mov w2, 286331153
+ mov w1, w20
+ mov w0, w19
+.LVL62:
+ bl mpb_task_set_state
+.LVL63:
+ .loc 1 401 0
+ mov x1, 328
+ mov x0, 40
+ mul x1, x24, x1
+ madd x1, x22, x0, x1
+ mov x0, 8
+ movk x0, 0x820, lsl 16
+ ldr x1, [x0, x1]
+ mov x0, 1320
+ movk x0, 0x820, lsl 16
+ blr x1
+.LVL64:
+ mov w21, w0
+.LVL65:
+ .loc 1 402 0
+ cbnz w0, .L63
+ .loc 1 405 0
+ mov w2, -559087616
+ b .L81
+.L63:
+ .loc 1 403 0
+ mov w2, -65536
+.L81:
+ .loc 1 405 0
+ mov w1, w20
+ mov w0, w19
+.LVL66:
+ bl mpb_task_set_state
+.LVL67:
+ .loc 1 407 0
+ bl get_ticks
+.LVL68:
+ sub x0, x0, x23
+ mov x4, 24000
+ .loc 1 408 0
+ mov w3, w21
+ mov w2, w20
+ mov w1, w19
+ .loc 1 407 0
+ udiv x4, x0, x4
+ mov x0, 328
+ mul x0, x24, x0
+ mov x24, 40
+ madd x24, x22, x24, x0
+ mov x22, 40
+.LVL69:
+ movk x22, 0x820, lsl 16
+ .loc 1 408 0
+ adrp x0, .LC11
+ add x0, x0, :lo12:.LC11
+ .loc 1 407 0
+ str x4, [x22, x24]
+ .loc 1 408 0
+ bl printf
+.LVL70:
+.L62:
+.LBB56:
+.LBB57:
+.LBB58:
+.LBB59:
+ .loc 1 146 0
+ mov x0, 136314880
+ mov w1, 1
+ lsl w1, w1, w20
+ ldr w2, [x0]
+.LBE59:
+.LBE58:
+ .loc 1 212 0
+ tst w1, w2
+ beq .L48
+.LBB60:
+.LBB61:
+ .loc 1 199 0
+ uxtw x3, w19
+ mov x1, 328
+ umull x19, w19, w1
+.LVL71:
+ madd x0, x3, x1, x0
+ mov w1, 0
+ ldrb w2, [x0, 328]
+ mov x0, 20
+ movk x0, 0x820, lsl 16
+ add x0, x19, x0
+.L59:
+.LVL72:
+ cmp w1, w2
+ blt .L61
+.LVL73:
+.L48:
+.LBE61:
+.LBE60:
+.LBE57:
+.LBE56:
+ .loc 1 417 0
+ ldp x19, x20, [sp, 16]
+.LVL74:
+ ldp x21, x22, [sp, 32]
+.LVL75:
+ ldp x23, x24, [sp, 48]
+ ldp x25, x26, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL76:
+.L61:
+ .cfi_restore_state
+.LBB69:
+.LBB64:
+.LBB63:
+.LBB62:
+ .loc 1 200 0
+ ldr w4, [x0], 40
+ cmp w20, w4
+ beq .L60
+ .loc 1 199 0
+ add w1, w1, 1
+.LVL77:
+ b .L59
+.L60:
+.LVL78:
+.LBE62:
+.LBE63:
+ .loc 1 219 0
+ sxtw x2, w1
+ mov x5, 328
+ mov x4, 40
+ .loc 1 220 0
+ add x19, x19, 32
+ .loc 1 219 0
+ mul x3, x3, x5
+ mov x0, 136314880
+ madd x2, x2, x4, x3
+ .loc 1 220 0
+ smaddl x19, w1, w4, x19
+ .loc 1 219 0
+ add x2, x0, x2
+.LBE64:
+.LBE69:
+ .loc 1 417 0
+ ldp x23, x24, [sp, 48]
+.LBB70:
+.LBB65:
+ .loc 1 220 0
+ add x0, x19, x0
+.LBE65:
+.LBE70:
+ .loc 1 417 0
+ ldp x25, x26, [sp, 64]
+.LBB71:
+.LBB66:
+ .loc 1 221 0
+ add x1, x0, 4
+.LBE66:
+.LBE71:
+ .loc 1 417 0
+ ldp x19, x20, [sp, 16]
+.LVL79:
+.LBB72:
+.LBB67:
+ .loc 1 219 0
+ str w21, [x2, 32]
+.LBE67:
+.LBE72:
+ .loc 1 417 0
+ ldp x21, x22, [sp, 32]
+.LVL80:
+ ldp x29, x30, [sp], 80
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+.LBB73:
+.LBB68:
+ .loc 1 221 0
+ b flush_dcache_range
+.LVL81:
+.LBE68:
+.LBE73:
+ .cfi_endproc
+.LFE242:
+ .size core_task_run.part.2, .-core_task_run.part.2
+ .section .text.mpb_task_wait_done,"ax",@progbits
+ .align 2
+ .global mpb_task_wait_done
+ .type mpb_task_wait_done, %function
+mpb_task_wait_done:
+.LFB230:
+ .loc 1 366 0
+ .cfi_startproc
+.LVL82:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ mov w19, w0
+.LVL83:
+.L84:
+.LBB78:
+.LBB79:
+ .loc 1 355 0
+ mov w0, w19
+ bl mpb_task_is_done
+.LVL84:
+ cbnz w0, .L83
+.LVL85:
+.LBB80:
+.LBB81:
+ .file 2 "include/linux/delay.h"
+ .loc 2 16 0
+ mov x0, 1000
+ bl udelay
+.LVL86:
+ mov x0, 1000
+ bl udelay
+.LVL87:
+ b .L84
+.L83:
+.LBE81:
+.LBE80:
+ .loc 1 362 0
+ mov w0, w19
+.LBE79:
+.LBE78:
+ .loc 1 368 0
+ ldr x19, [sp, 16]
+.LVL88:
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+.LBB83:
+.LBB82:
+ .loc 1 362 0
+ b mpb_task_is_done
+.LVL89:
+.LBE82:
+.LBE83:
+ .cfi_endproc
+.LFE230:
+ .size mpb_task_wait_done, .-mpb_task_wait_done
+ .section .text.mpb_task_run,"ax",@progbits
+ .align 2
+ .global mpb_task_run
+ .type mpb_task_run, %function
+mpb_task_run:
+.LFB232:
+ .loc 1 420 0
+ .cfi_startproc
+.LVL90:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+.LBB90:
+.LBB91:
+ .loc 1 146 0
+ mov x3, 136314880
+.LBE91:
+.LBE90:
+ .loc 1 420 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+.LBB93:
+.LBB92:
+ .loc 1 146 0
+ mov w24, 1
+ ldr w2, [x3]
+ lsl w24, w24, w1
+.LVL91:
+.LBE92:
+.LBE93:
+ .loc 1 420 0
+ stp x19, x20, [sp, 16]
+ stp x21, x22, [sp, 32]
+ .loc 1 424 0
+ tst w24, w2
+ .loc 1 420 0
+ str x25, [sp, 64]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .cfi_offset 25, -16
+ .loc 1 424 0
+ beq .L86
+ .loc 1 424 0 is_stmt 0 discriminator 1
+ cbz w1, .L86
+ uxtw x25, w0
+.LVL92:
+ .loc 1 421 0 is_stmt 1
+ mov w19, 328
+ mov x0, 8
+.LVL93:
+ mov x22, x25
+ mov w21, w1
+ .loc 1 427 0
+ mov x20, x3
+ .loc 1 421 0
+ umaddl x19, w25, w19, x0
+ .loc 1 427 0
+ mov x0, 328
+ .loc 1 421 0
+ mov w23, 0
+ .loc 1 427 0
+ madd x25, x25, x0, x3
+.LVL94:
+ .loc 1 421 0
+ add x19, x19, x3
+.LVL95:
+.L89:
+ .loc 1 427 0 discriminator 1
+ ldrb w0, [x25, 328]
+ cmp w23, w0
+ blt .L91
+.LVL96:
+.L86:
+ .loc 1 431 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+ ldr x25, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL97:
+.L91:
+ .cfi_restore_state
+ .loc 1 428 0
+ ldr w0, [x19, 12]
+ cmp w21, w0
+ bne .L90
+ .loc 1 428 0 is_stmt 0 discriminator 1
+ ldr x0, [x19]
+ cbz x0, .L90
+.LVL98:
+.LBB94:
+.LBB95:
+.LBB96:
+.LBB97:
+ .loc 1 146 0 is_stmt 1
+ ldr w0, [x20]
+.LBE97:
+.LBE96:
+ .loc 1 377 0
+ tst w24, w0
+ beq .L90
+ ldr w3, [x19, 16]
+ mov w2, w21
+ mov w1, w23
+ mov w0, w22
+ bl core_task_run.part.2
+.LVL99:
+.L90:
+.LBE95:
+.LBE94:
+ .loc 1 427 0 discriminator 2
+ add w23, w23, 1
+.LVL100:
+ add x19, x19, 40
+ b .L89
+ .cfi_endproc
+.LFE232:
+ .size mpb_task_run, .-mpb_task_run
+ .section .text.core_main,"ax",@progbits
+ .align 2
+ .global core_main
+ .type core_main, %function
+core_main:
+.LFB233:
+ .loc 1 434 0
+ .cfi_startproc
+.LVL101:
+ stp x29, x30, [sp, -64]!
+ .cfi_def_cfa_offset 64
+ .cfi_offset 29, -64
+ .cfi_offset 30, -56
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -32
+ .cfi_offset 22, -24
+ uxtw x22, w0
+ stp x19, x20, [sp, 16]
+ .loc 1 435 0
+ mov x0, 8
+.LVL102:
+ .cfi_offset 19, -48
+ .cfi_offset 20, -40
+ mov w19, 328
+ mov x20, 136314880
+ .loc 1 434 0
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -16
+ .cfi_offset 24, -8
+ .loc 1 434 0
+ mov x23, x22
+.LVL103:
+ .loc 1 435 0
+ umaddl x19, w22, w19, x0
+ .loc 1 438 0
+ mov x0, 328
+ mov w21, 0
+.LBB102:
+.LBB103:
+.LBB104:
+.LBB105:
+ .loc 1 146 0
+ mov w24, 1
+.LBE105:
+.LBE104:
+.LBE103:
+.LBE102:
+ .loc 1 438 0
+ madd x22, x22, x0, x20
+.LVL104:
+ .loc 1 435 0
+ add x19, x19, x20
+.LVL105:
+.L103:
+ .loc 1 438 0 discriminator 1
+ ldrb w0, [x22, 328]
+ cmp w21, w0
+ blt .L105
+ .loc 1 442 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+.LVL106:
+ ldp x23, x24, [sp, 48]
+.LVL107:
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL108:
+.L105:
+ .cfi_restore_state
+ .loc 1 439 0
+ ldr x0, [x19]
+ cbz x0, .L104
+ .loc 1 440 0
+ ldr w2, [x19, 12]
+.LVL109:
+.LBB109:
+.LBB108:
+.LBB107:
+.LBB106:
+ .loc 1 146 0
+ ldr w0, [x20]
+ lsl w1, w24, w2
+.LBE106:
+.LBE107:
+ .loc 1 377 0
+ tst w1, w0
+ beq .L104
+ ldr w3, [x19, 16]
+ mov w1, w21
+ mov w0, w23
+ bl core_task_run.part.2
+.LVL110:
+.L104:
+.LBE108:
+.LBE109:
+ .loc 1 438 0 discriminator 2
+ add w21, w21, 1
+.LVL111:
+ add x19, x19, 40
+ b .L103
+ .cfi_endproc
+.LFE233:
+ .size core_main, .-core_main
+ .section .text.smp_entry,"ax",@progbits
+ .align 2
+ .global smp_entry
+ .type smp_entry, %function
+smp_entry:
+.LFB234:
+ .loc 1 448 0
+ .cfi_startproc
+.LVL112:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ .loc 1 448 0
+ mov w19, w0
+ .loc 1 450 0
+ adrp x0, .LANCHOR2
+.LVL113:
+ ldr x0, [x0, #:lo12:.LANCHOR2]
+.LVL114:
+.LBB110:
+.LBB111:
+ .loc 1 131 0
+#APP
+// 131 "common/mp_boot.c" 1
+ mov x18, x0
+
+// 0 "" 2
+.LVL115:
+#NO_APP
+.LBE111:
+.LBE110:
+ .loc 1 451 0
+ bl dcache_enable
+.LVL116:
+ .loc 1 455 0
+ cmp w19, 1
+ bne .L114
+.L118:
+ .loc 1 460 0
+ mov w0, w19
+ bl core_main
+.LVL117:
+ b .L115
+.L114:
+ .loc 1 459 0
+ cmp w19, 2
+ beq .L118
+.L115:
+ .loc 1 468 0
+ bl flush_dcache_all
+.LVL118:
+ .loc 1 469 0
+ bl disable_interrupts
+.LVL119:
+.LBB112:
+.LBB113:
+ .file 3 "./arch/arm/include/asm/system.h"
+ .loc 3 193 0
+#APP
+// 193 "./arch/arm/include/asm/system.h" 1
+ msr daifset, #0x04
+// 0 "" 2
+#NO_APP
+.LBE113:
+.LBE112:
+ .loc 1 471 0
+ bl icache_disable
+.LVL120:
+ .loc 1 472 0
+ bl invalidate_icache_all
+.LVL121:
+ .loc 1 473 0
+ bl dcache_disable
+.LVL122:
+.LBB114:
+.LBB115:
+ .loc 1 138 0
+#APP
+// 138 "common/mp_boot.c" 1
+ mrs x0, S3_1_c15_c2_1
+// 0 "" 2
+ .loc 1 139 0
+// 139 "common/mp_boot.c" 1
+ bic x0, x0, #0x40
+// 0 "" 2
+ .loc 1 140 0
+// 140 "common/mp_boot.c" 1
+ msr S3_1_c15_c2_1, x0
+// 0 "" 2
+#NO_APP
+.LBE115:
+.LBE114:
+ .loc 1 475 0
+ bl invalidate_dcache_all
+.LVL123:
+ .loc 1 478 0
+#APP
+// 478 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 479 0
+// 479 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+#NO_APP
+.L116:
+ .loc 1 481 0 discriminator 1
+#APP
+// 481 "common/mp_boot.c" 1
+ wfe
+// 0 "" 2
+#NO_APP
+ b .L116
+ .cfi_endproc
+.LFE234:
+ .size smp_entry, .-smp_entry
+ .section .text.mpb_init_1,"ax",@progbits
+ .align 2
+ .global mpb_init_1
+ .type mpb_init_1, %function
+mpb_init_1:
+.LFB236:
+ .loc 1 527 0
+ .cfi_startproc
+ stp x29, x30, [sp, -16]!
+ .cfi_def_cfa_offset 16
+ .cfi_offset 29, -16
+ .cfi_offset 30, -8
+ .loc 1 528 0
+ mov x2, 40
+ mov x1, x0
+ mov x0, 1320
+ .loc 1 527 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 528 0
+ movk x0, 0x820, lsl 16
+ .loc 1 527 0
+ .loc 1 528 0
+ bl memcpy
+.LVL124:
+ .loc 1 530 0
+ mov w1, 2
+ mov w0, 0
+ bl mpb_task_run
+.LVL125:
+ .loc 1 531 0
+ mov w2, 286331153
+ mov w1, 3
+ mov w0, 0
+ bl mpb_task_set_state
+.LVL126:
+ .loc 1 532 0
+ bl flush_dcache_all
+.LVL127:
+ .loc 1 533 0
+#APP
+// 533 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 534 0
+// 534 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+ .loc 1 535 0
+#NO_APP
+ ldp x29, x30, [sp], 16
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE236:
+ .size mpb_init_1, .-mpb_init_1
+ .section .text.mpb_init_x,"ax",@progbits
+ .align 2
+ .global mpb_init_x
+ .type mpb_init_x, %function
+mpb_init_x:
+.LFB237:
+ .loc 1 538 0
+ .cfi_startproc
+.LVL128:
+ stp x29, x30, [sp, -64]!
+ .cfi_def_cfa_offset 64
+ .cfi_offset 29, -64
+ .cfi_offset 30, -56
+ .loc 1 539 0
+ cmp w0, 2
+ .loc 1 538 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 539 0
+ beq .L123
+ cmp w0, 3
+ beq .L124
+ cbnz w0, .L121
+.LBB124:
+.LBB125:
+ .loc 1 494 0
+ adrp x1, .LANCHOR3
+ add x1, x1, :lo12:.LANCHOR3
+ mov x2, 48
+ add x0, x29, 16
+.LVL129:
+ bl memcpy
+.LVL130:
+ .loc 1 509 0
+ adrp x0, .LC14
+ add x0, x0, :lo12:.LC14
+ bl printf
+.LVL131:
+ .loc 1 511 0
+ mov x2, 1376
+ mov w1, 0
+ mov x0, 136314880
+ bl memset
+.LVL132:
+ .loc 1 512 0
+ adrp x0, .LANCHOR2
+ add x6, x29, 64
+.LBB126:
+.LBB127:
+ .loc 1 177 0
+ mov x4, 136314880
+ mov x7, 328
+.LBE127:
+.LBE126:
+ .loc 1 512 0
+ str x18, [x0, #:lo12:.LANCHOR2]
+.LVL133:
+ add x0, x29, 16
+.LBB130:
+.LBB128:
+ .loc 1 179 0
+ mov x8, 40
+ .loc 1 185 0
+ mov w10, 1
+.LVL134:
+.L126:
+.LBE128:
+.LBE130:
+ .loc 1 514 0
+ cmp x6, x0
+ bne .L128
+ .loc 1 517 0
+ bl flush_dcache_all
+.LVL135:
+.LBB131:
+ .loc 1 518 0
+#APP
+// 518 "common/mp_boot.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov x1, 8
+ adrp x0, save_boot_params_ret
+ movk x1, 0xfe48, lsl 16
+ add x0, x0, :lo12:save_boot_params_ret
+ str w0, [x1]
+.LVL136:
+.LBE131:
+.LBB132:
+ .loc 1 519 0
+#APP
+// 519 "common/mp_boot.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov x0, 4
+ mov w1, 48815
+ movk x0, 0xfe48, lsl 16
+ movk w1, 0xdead, lsl 16
+ str w1, [x0]
+.LBE132:
+ .loc 1 520 0
+#APP
+// 520 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 522 0
+// 522 "common/mp_boot.c" 1
+ sev
+// 0 "" 2
+ .loc 1 523 0
+// 523 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+.LVL137:
+#NO_APP
+.L121:
+.LBE125:
+.LBE124:
+ .loc 1 556 0
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+.L128:
+ .cfi_restore_state
+ ldp w1, w3, [x0]
+.LVL138:
+ ldp w12, w11, [x0, 16]
+.LBB135:
+.LBB134:
+.LBB133:
+.LBB129:
+ .loc 1 172 0
+ cmp w1, 3
+ ldr x13, [x0, 8]
+.LVL139:
+ beq .L127
+ .loc 1 176 0
+ sub w2, w3, #1
+ cmp w2, 6
+ bhi .L127
+.LVL140:
+ .loc 1 177 0
+ uxtw x1, w1
+ mul x2, x1, x7
+ add x5, x4, x2
+ .loc 1 179 0
+ ldrb w1, [x5, 328]
+.LVL141:
+ madd x1, x1, x8, x2
+ add x1, x4, x1
+ .loc 1 181 0
+ stp w3, w12, [x1, 20]
+.LVL142:
+ .loc 1 185 0
+ lsl w3, w10, w3
+.LVL143:
+ .loc 1 183 0
+ stp w11, wzr, [x1, 28]
+ .loc 1 179 0
+ str x13, [x1, 8]
+ .loc 1 184 0
+ str xzr, [x1, 40]
+ .loc 1 185 0
+ ldr w1, [x4]
+.LVL144:
+ orr w3, w1, w3
+ str w3, [x4]
+ .loc 1 186 0
+ ldrb w1, [x5, 328]
+ add w1, w1, 1
+ strb w1, [x5, 328]
+.L127:
+ add x0, x0, 24
+ b .L126
+.LVL145:
+.L123:
+.LBE129:
+.LBE133:
+.LBE134:
+.LBE135:
+ .loc 1 544 0
+ mov w2, -559087616
+ mov w1, 3
+ mov w0, 0
+.LVL146:
+ bl mpb_task_set_state
+.LVL147:
+ .loc 1 545 0
+ bl flush_dcache_all
+.LVL148:
+ .loc 1 546 0
+#APP
+// 546 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 547 0
+// 547 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+.LVL149:
+ .loc 1 556 0
+#NO_APP
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+.LBB136:
+.LBB137:
+ .loc 2 16 0
+ mov x0, 1000
+ b udelay
+.LVL150:
+.L124:
+ .cfi_restore_state
+.LBE137:
+.LBE136:
+ .loc 1 556 0
+ ldp x29, x30, [sp], 64
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ .loc 1 553 0
+ mov w2, -559087616
+ mov w1, 7
+ mov w0, 0
+.LVL151:
+ b mpb_task_set_state
+.LVL152:
+ .cfi_endproc
+.LFE237:
+ .size mpb_init_x, .-mpb_init_x
+ .section .text.mpb_post,"ax",@progbits
+ .align 2
+ .global mpb_post
+ .type mpb_post, %function
+mpb_post:
+.LFB239:
+ .loc 1 576 0
+ .cfi_startproc
+.LVL153:
+ .loc 1 580 0
+ cmp w0, 5
+ bhi .L147
+ .loc 1 576 0
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ .loc 1 580 0
+ adrp x1, .L136
+ add x1, x1, :lo12:.L136
+ .loc 1 576 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 580 0
+ ldrb w0, [x1,w0,uxtw]
+ adr x1, .Lrtx136
+ add x0, x1, w0, sxtb #2
+ br x0
+.Lrtx136:
+.LVL154:
+ .section .rodata.mpb_post,"a",@progbits
+ .align 0
+ .align 2
+.L136:
+ .byte (.L135 - .Lrtx136) / 4
+ .byte (.L137 - .Lrtx136) / 4
+ .byte (.L138 - .Lrtx136) / 4
+ .byte (.L139 - .Lrtx136) / 4
+ .byte (.L140 - .Lrtx136) / 4
+ .byte (.L141 - .Lrtx136) / 4
+ .section .text.mpb_post
+.L135:
+ .loc 1 582 0
+ mov w0, 5
+.L155:
+ .loc 1 602 0
+ bl mpb_task_wait_done
+.LVL155:
+ sxtw x0, w0
+ b .L133
+.L137:
+.LVL156:
+ .loc 1 586 0
+ mov w0, 5
+ bl mpb_task_wait_done
+.LVL157:
+ .loc 1 587 0
+ bl mpb_quit_load_image
+.LVL158:
+ cbz w0, .L142
+.LVL159:
+.L156:
+ .loc 1 621 0
+ mov x0, 0
+ .loc 1 617 0
+ b .L133
+.LVL160:
+.L142:
+ .loc 1 587 0 discriminator 1
+ mov x0, 136314880
+ ldr x0, [x0, 1360]
+.LVL161:
+.L133:
+ .loc 1 622 0
+ ldp x29, x30, [sp], 48
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+.L138:
+ .cfi_restore_state
+ .loc 1 590 0
+ bl mpb_quit_load_image
+.LVL162:
+ cbnz w0, .L156
+ .loc 1 590 0 is_stmt 0 discriminator 1
+ mov x0, 136314880
+ ldr x0, [x0, 1368]
+ b .L133
+.L139:
+ .loc 1 594 0 is_stmt 1
+ bl mpb_quit_load_image
+.LVL163:
+ cbz w0, .L156
+ .loc 1 596 0
+ mov w0, 6
+ bl mpb_task_wait_done
+.LVL164:
+ .loc 1 597 0
+ mov x0, 1
+ b .L133
+.L140:
+ .loc 1 602 0
+ mov w0, 6
+ b .L155
+.L141:
+ .loc 1 605 0
+ bl mpb_quit_load_image
+.LVL165:
+ cbnz w0, .L156
+.LVL166:
+ .loc 1 609 0
+ mov w0, 5
+ bl mpb_task_wait_done
+.LVL167:
+ cmp w0, 0
+ ble .L144
+.L146:
+ .loc 1 611 0
+ mov x0, 136314880
+ adrp x2, .LC15
+ add x2, x2, :lo12:.LC15
+ mov x1, 32
+ ldr x3, [x0, 1360]
+ add x0, x29, 16
+ bl snprintf
+.LVL168:
+ .loc 1 612 0
+ mov w1, 0
+ add x0, x29, 16
+ bl run_command
+.LVL169:
+.L145:
+ .loc 1 616 0
+ bl mpb_task_dump
+.LVL170:
+ b .L156
+.L144:
+ .loc 1 610 0 discriminator 1
+ mov w0, 4
+ bl mpb_task_wait_done
+.LVL171:
+ .loc 1 609 0 discriminator 1
+ cmp w0, 0
+ bgt .L146
+ b .L145
+.LVL172:
+.L147:
+ .cfi_def_cfa 31, 0
+ .cfi_restore 29
+ .cfi_restore 30
+ .loc 1 621 0
+ mov x0, 0
+.LVL173:
+ ret
+ .cfi_endproc
+.LFE239:
+ .size mpb_post, .-mpb_post
+ .section .rodata
+ .align 3
+ .set .LANCHOR3,. + 0
+.LC0:
+ .word 0
+ .word 2
+ .xword spl_load_baseparamter
+ .word 0
+ .word 0
+ .word 2
+ .word 1
+ .xword spl_init_display
+ .word 0
+ .word 0
+ .section .bss.mpb_gd,"aw",@nobits
+ .align 3
+ .set .LANCHOR2,. + 0
+ .type mpb_gd, %object
+ .size mpb_gd, 8
+mpb_gd:
+ .zero 8
+ .section .bss.once.6657,"aw",@nobits
+ .align 2
+ .set .LANCHOR0,. + 0
+ .type once.6657, %object
+ .size once.6657, 4
+once.6657:
+ .zero 4
+ .section .rodata.core_task_run.part.2.str1.1,"aMS",@progbits,1
+.LC11:
+ .string "-- T%d.%d [%d, %ld]\n"
+.LC12:
+ .string "++ T%d.%d -\n"
+.LC13:
+ .string "++ T%d.%d\n"
+ .section .rodata.mpb_init_x.str1.1,"aMS",@progbits,1
+.LC14:
+ .string "U-Boot SPL MP\n"
+ .section .rodata.mpb_post.str1.1,"aMS",@progbits,1
+.LC15:
+ .string "bootm 0x%lx"
+ .section .rodata.mpb_quit_load_image.str1.1,"aMS",@progbits,1
+.LC1:
+ .string "++ serial boot\n"
+ .section .rodata.mpb_task_dump.str1.1,"aMS",@progbits,1
+.LC2:
+ .string "data: %08lx, %08lx\n"
+.LC3:
+ .string "T%d.%d:[%s]\n"
+.LC4:
+ .string " tid: %d\n"
+.LC5:
+ .string " fn: 0x%08lx\n"
+.LC6:
+ .string " state: 0x%08x\n"
+.LC7:
+ .string " ret: %d\n"
+.LC8:
+ .string " ms: %ld\n"
+.LC9:
+ .string " ptid_mask: 0x%08x\n"
+.LC10:
+ .string " rip_fail: %d\n\n"
+ .section .rodata.str1.1,"aMS",@progbits,1
+.LC16:
+ .string "none"
+.LC17:
+ .string "init-display"
+.LC18:
+ .string "load-baseparameter"
+.LC19:
+ .string "load-uboot"
+.LC20:
+ .string "load-fit"
+.LC21:
+ .string "load-android"
+.LC22:
+ .string "hash-android"
+.LC23:
+ .string "run-uboot"
+ .section .rodata.tid_name,"a",@progbits
+ .align 3
+ .set .LANCHOR1,. + 0
+ .type tid_name, %object
+ .size tid_name, 64
+tid_name:
+ .xword .LC16
+ .xword .LC17
+ .xword .LC18
+ .xword .LC19
+ .xword .LC20
+ .xword .LC21
+ .xword .LC22
+ .xword .LC23
+ .text
+.Letext0:
+ .file 4 "include/common.h"
+ .file 5 "./arch/arm/include/asm/types.h"
+ .file 6 "include/linux/types.h"
+ .file 7 "include/errno.h"
+ .file 8 "include/linux/string.h"
+ .file 9 "include/efi.h"
+ .file 10 "include/ide.h"
+ .file 11 "include/linux/list.h"
+ .file 12 "include/part.h"
+ .file 13 "include/flash.h"
+ .file 14 "include/lmb.h"
+ .file 15 "include/asm-generic/u-boot.h"
+ .file 16 "./arch/arm/include/asm/u-boot-arm.h"
+ .file 17 "include/linux/libfdt_env.h"
+ .file 18 "include/linux/../../scripts/dtc/libfdt/fdt.h"
+ .file 19 "include/linux/libfdt.h"
+ .file 20 "include/image.h"
+ .file 21 "./arch/arm/include/asm/global_data.h"
+ .file 22 "include/asm-generic/global_data.h"
+ .file 23 "include/net.h"
+ .file 24 "include/dm/uclass-id.h"
+ .file 25 "./arch/arm/include/asm/spl.h"
+ .file 26 "include/spl.h"
+ .file 27 "include/mp_boot.h"
+ .file 28 "include/boot_rkimg.h"
+ .file 29 "include/log.h"
+ .file 30 "include/vsprintf.h"
+ .file 31 "include/stdio.h"
+ .section .debug_info,"",@progbits
+.Ldebug_info0:
+ .4byte 0x2575
+ .2byte 0x4
+ .4byte .Ldebug_abbrev0
+ .byte 0x8
+ .uleb128 0x1
+ .4byte .LASF447
+ .byte 0xc
+ .4byte .LASF448
+ .4byte .LASF449
+ .4byte .Ldebug_ranges0+0x230
+ .8byte 0
+ .4byte .Ldebug_line0
+ .uleb128 0x2
+ .4byte .LASF4
+ .byte 0x4
+ .byte 0xd
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF0
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF1
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x7
+ .4byte .LASF2
+ .uleb128 0x4
+ .4byte .LASF20
+ .byte 0x7
+ .byte 0xc
+ .4byte 0x54
+ .uleb128 0x5
+ .byte 0x4
+ .byte 0x5
+ .string "int"
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x6
+ .4byte .LASF3
+ .uleb128 0x2
+ .4byte .LASF5
+ .byte 0x5
+ .byte 0xc
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x5
+ .4byte .LASF6
+ .uleb128 0x2
+ .4byte .LASF7
+ .byte 0x5
+ .byte 0x12
+ .4byte 0x7f
+ .uleb128 0x3
+ .byte 0x4
+ .byte 0x7
+ .4byte .LASF8
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF9
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF10
+ .uleb128 0x6
+ .string "u8"
+ .byte 0x5
+ .byte 0x1f
+ .4byte 0x34
+ .uleb128 0x7
+ .4byte 0x94
+ .uleb128 0x6
+ .string "u32"
+ .byte 0x5
+ .byte 0x25
+ .4byte 0x7f
+ .uleb128 0x6
+ .string "u64"
+ .byte 0x5
+ .byte 0x28
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF11
+ .byte 0x5
+ .byte 0x31
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF12
+ .byte 0x5
+ .byte 0x32
+ .4byte 0x8d
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF13
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe3
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF14
+ .uleb128 0x7
+ .4byte 0xdc
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF15
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xdc
+ .uleb128 0x2
+ .4byte .LASF16
+ .byte 0x6
+ .byte 0x59
+ .4byte 0x42
+ .uleb128 0x2
+ .4byte .LASF17
+ .byte 0x6
+ .byte 0x5b
+ .4byte 0x3b
+ .uleb128 0x9
+ .4byte 0x100
+ .uleb128 0x2
+ .4byte .LASF18
+ .byte 0x6
+ .byte 0x69
+ .4byte 0x62
+ .uleb128 0x2
+ .4byte .LASF19
+ .byte 0x6
+ .byte 0x97
+ .4byte 0x74
+ .uleb128 0xa
+ .byte 0x8
+ .uleb128 0x4
+ .4byte .LASF21
+ .byte 0x8
+ .byte 0xb
+ .4byte 0xef
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x2
+ .4byte .LASF22
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0x145
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF23
+ .byte 0x9
+ .2byte 0x140
+ .4byte 0x13a
+ .uleb128 0xd
+ .4byte .LASF24
+ .byte 0x9
+ .2byte 0x143
+ .4byte 0x13a
+ .uleb128 0xd
+ .4byte .LASF25
+ .byte 0x9
+ .2byte 0x143
+ .4byte 0x13a
+ .uleb128 0xe
+ .4byte .LASF38
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x169
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x17a
+ .uleb128 0xf
+ .uleb128 0xb
+ .4byte 0x100
+ .4byte 0x186
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF26
+ .byte 0xa
+ .byte 0x10
+ .4byte 0x17b
+ .uleb128 0xb
+ .4byte 0x34
+ .4byte 0x1a1
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x5
+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF29
+ .byte 0x10
+ .byte 0xb
+ .byte 0x16
+ .4byte 0x1c6
+ .uleb128 0x12
+ .4byte .LASF27
+ .byte 0xb
+ .byte 0x17
+ .4byte 0x1c6
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF28
+ .byte 0xb
+ .byte 0x17
+ .4byte 0x1c6
+ .byte 0x8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1a1
+ .uleb128 0x11
+ .4byte .LASF30
+ .byte 0x10
+ .byte 0xc
+ .byte 0xf
+ .4byte 0x1f1
+ .uleb128 0x12
+ .4byte .LASF31
+ .byte 0xc
+ .byte 0x10
+ .4byte 0xef
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF32
+ .byte 0xc
+ .byte 0x11
+ .4byte 0x20a
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x1cc
+ .uleb128 0x13
+ .4byte 0x54
+ .4byte 0x20a
+ .uleb128 0x14
+ .4byte 0x54
+ .uleb128 0x14
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1f6
+ .uleb128 0xb
+ .4byte 0x1f1
+ .4byte 0x21b
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x210
+ .uleb128 0x4
+ .4byte .LASF30
+ .byte 0xc
+ .byte 0xe1
+ .4byte 0x21b
+ .uleb128 0x15
+ .2byte 0x1220
+ .byte 0xd
+ .byte 0x13
+ .4byte 0x27f
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xd
+ .byte 0x14
+ .4byte 0x100
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF34
+ .byte 0xd
+ .byte 0x15
+ .4byte 0xf5
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF35
+ .byte 0xd
+ .byte 0x16
+ .4byte 0x100
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF36
+ .byte 0xd
+ .byte 0x17
+ .4byte 0x27f
+ .byte 0x18
+ .uleb128 0x16
+ .4byte .LASF37
+ .byte 0xd
+ .byte 0x18
+ .4byte 0x290
+ .2byte 0x1018
+ .uleb128 0x17
+ .string "mtd"
+ .byte 0xd
+ .byte 0x31
+ .4byte 0x2a6
+ .2byte 0x1218
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x100
+ .4byte 0x290
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x29
+ .4byte 0x2a1
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF39
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x2a1
+ .uleb128 0x2
+ .4byte .LASF40
+ .byte 0xd
+ .byte 0x37
+ .4byte 0x22b
+ .uleb128 0xb
+ .4byte 0x2ac
+ .4byte 0x2c2
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF41
+ .byte 0xd
+ .byte 0x39
+ .4byte 0x2b7
+ .uleb128 0x3
+ .byte 0x10
+ .byte 0x4
+ .4byte .LASF42
+ .uleb128 0x11
+ .4byte .LASF43
+ .byte 0x10
+ .byte 0xe
+ .byte 0x10
+ .4byte 0x2f9
+ .uleb128 0x12
+ .4byte .LASF44
+ .byte 0xe
+ .byte 0x11
+ .4byte 0xb9
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xe
+ .byte 0x12
+ .4byte 0xc4
+ .byte 0x8
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF45
+ .2byte 0x120
+ .byte 0xe
+ .byte 0x15
+ .4byte 0x32b
+ .uleb128 0x1a
+ .string "cnt"
+ .byte 0xe
+ .byte 0x16
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xe
+ .byte 0x17
+ .4byte 0xc4
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF46
+ .byte 0xe
+ .byte 0x18
+ .4byte 0x32b
+ .byte 0x10
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x2d4
+ .4byte 0x33b
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x10
+ .byte 0
+ .uleb128 0x1b
+ .string "lmb"
+ .2byte 0x240
+ .byte 0xe
+ .byte 0x1b
+ .4byte 0x362
+ .uleb128 0x12
+ .4byte .LASF47
+ .byte 0xe
+ .byte 0x1c
+ .4byte 0x2f9
+ .byte 0
+ .uleb128 0x16
+ .4byte .LASF48
+ .byte 0xe
+ .byte 0x1d
+ .4byte 0x2f9
+ .2byte 0x120
+ .byte 0
+ .uleb128 0x1c
+ .string "lmb"
+ .byte 0xe
+ .byte 0x20
+ .4byte 0x33b
+ .uleb128 0x1d
+ .byte 0x10
+ .byte 0xf
+ .byte 0x5b
+ .4byte 0x38e
+ .uleb128 0x12
+ .4byte .LASF36
+ .byte 0xf
+ .byte 0x5c
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xf
+ .byte 0x5d
+ .4byte 0xae
+ .byte 0x8
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF49
+ .2byte 0x148
+ .byte 0xf
+ .byte 0x1b
+ .4byte 0x480
+ .uleb128 0x12
+ .4byte .LASF50
+ .byte 0xf
+ .byte 0x1c
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF51
+ .byte 0xf
+ .byte 0x1d
+ .4byte 0xc4
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF52
+ .byte 0xf
+ .byte 0x1e
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF53
+ .byte 0xf
+ .byte 0x1f
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF54
+ .byte 0xf
+ .byte 0x20
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF55
+ .byte 0xf
+ .byte 0x21
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF56
+ .byte 0xf
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0x12
+ .4byte .LASF57
+ .byte 0xf
+ .byte 0x24
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0x12
+ .4byte .LASF58
+ .byte 0xf
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0x12
+ .4byte .LASF59
+ .byte 0xf
+ .byte 0x26
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0x12
+ .4byte .LASF60
+ .byte 0xf
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0x12
+ .4byte .LASF61
+ .byte 0xf
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0x12
+ .4byte .LASF62
+ .byte 0xf
+ .byte 0x33
+ .4byte 0x191
+ .byte 0x60
+ .uleb128 0x12
+ .4byte .LASF63
+ .byte 0xf
+ .byte 0x34
+ .4byte 0x42
+ .byte 0x66
+ .uleb128 0x12
+ .4byte .LASF64
+ .byte 0xf
+ .byte 0x35
+ .4byte 0x3b
+ .byte 0x68
+ .uleb128 0x12
+ .4byte .LASF65
+ .byte 0xf
+ .byte 0x36
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0x12
+ .4byte .LASF66
+ .byte 0xf
+ .byte 0x57
+ .4byte 0x100
+ .byte 0x78
+ .uleb128 0x12
+ .4byte .LASF67
+ .byte 0xf
+ .byte 0x58
+ .4byte 0x100
+ .byte 0x80
+ .uleb128 0x12
+ .4byte .LASF68
+ .byte 0xf
+ .byte 0x5e
+ .4byte 0x480
+ .byte 0x88
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x36d
+ .4byte 0x490
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0xb
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF69
+ .byte 0xf
+ .byte 0x60
+ .4byte 0x38e
+ .uleb128 0x4
+ .4byte .LASF70
+ .byte 0x10
+ .byte 0x13
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF71
+ .byte 0x10
+ .byte 0x14
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF72
+ .byte 0x10
+ .byte 0x15
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF73
+ .byte 0x10
+ .byte 0x16
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF74
+ .byte 0x10
+ .byte 0x17
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF75
+ .byte 0x10
+ .byte 0x18
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF76
+ .byte 0x10
+ .byte 0x19
+ .4byte 0x100
+ .uleb128 0x2
+ .4byte .LASF77
+ .byte 0x11
+ .byte 0x11
+ .4byte 0x11b
+ .uleb128 0x11
+ .4byte .LASF78
+ .byte 0x28
+ .byte 0x12
+ .byte 0x39
+ .4byte 0x578
+ .uleb128 0x12
+ .4byte .LASF79
+ .byte 0x12
+ .byte 0x3a
+ .4byte 0x4e8
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF80
+ .byte 0x12
+ .byte 0x3b
+ .4byte 0x4e8
+ .byte 0x4
+ .uleb128 0x12
+ .4byte .LASF81
+ .byte 0x12
+ .byte 0x3c
+ .4byte 0x4e8
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF82
+ .byte 0x12
+ .byte 0x3d
+ .4byte 0x4e8
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF83
+ .byte 0x12
+ .byte 0x3e
+ .4byte 0x4e8
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF84
+ .byte 0x12
+ .byte 0x3f
+ .4byte 0x4e8
+ .byte 0x14
+ .uleb128 0x12
+ .4byte .LASF85
+ .byte 0x12
+ .byte 0x40
+ .4byte 0x4e8
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF86
+ .byte 0x12
+ .byte 0x43
+ .4byte 0x4e8
+ .byte 0x1c
+ .uleb128 0x12
+ .4byte .LASF87
+ .byte 0x12
+ .byte 0x46
+ .4byte 0x4e8
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF88
+ .byte 0x12
+ .byte 0x49
+ .4byte 0x4e8
+ .byte 0x24
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF89
+ .byte 0x13
+ .2byte 0x136
+ .4byte 0x584
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x4f3
+ .uleb128 0x1e
+ .4byte .LASF90
+ .byte 0x40
+ .byte 0x14
+ .2byte 0x137
+ .4byte 0x634
+ .uleb128 0x1f
+ .4byte .LASF91
+ .byte 0x14
+ .2byte 0x138
+ .4byte 0x11b
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF92
+ .byte 0x14
+ .2byte 0x139
+ .4byte 0x11b
+ .byte 0x4
+ .uleb128 0x1f
+ .4byte .LASF93
+ .byte 0x14
+ .2byte 0x13a
+ .4byte 0x11b
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF94
+ .byte 0x14
+ .2byte 0x13b
+ .4byte 0x11b
+ .byte 0xc
+ .uleb128 0x1f
+ .4byte .LASF95
+ .byte 0x14
+ .2byte 0x13c
+ .4byte 0x11b
+ .byte 0x10
+ .uleb128 0x1f
+ .4byte .LASF96
+ .byte 0x14
+ .2byte 0x13d
+ .4byte 0x11b
+ .byte 0x14
+ .uleb128 0x1f
+ .4byte .LASF97
+ .byte 0x14
+ .2byte 0x13e
+ .4byte 0x11b
+ .byte 0x18
+ .uleb128 0x1f
+ .4byte .LASF98
+ .byte 0x14
+ .2byte 0x13f
+ .4byte 0x110
+ .byte 0x1c
+ .uleb128 0x1f
+ .4byte .LASF99
+ .byte 0x14
+ .2byte 0x140
+ .4byte 0x110
+ .byte 0x1d
+ .uleb128 0x1f
+ .4byte .LASF100
+ .byte 0x14
+ .2byte 0x141
+ .4byte 0x110
+ .byte 0x1e
+ .uleb128 0x1f
+ .4byte .LASF101
+ .byte 0x14
+ .2byte 0x142
+ .4byte 0x110
+ .byte 0x1f
+ .uleb128 0x1f
+ .4byte .LASF102
+ .byte 0x14
+ .2byte 0x143
+ .4byte 0x634
+ .byte 0x20
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x110
+ .4byte 0x644
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x20
+ .4byte .LASF103
+ .byte 0x14
+ .2byte 0x144
+ .4byte 0x58a
+ .uleb128 0x1e
+ .4byte .LASF104
+ .byte 0x30
+ .byte 0x14
+ .2byte 0x146
+ .4byte 0x6d2
+ .uleb128 0x1f
+ .4byte .LASF36
+ .byte 0x14
+ .2byte 0x147
+ .4byte 0x100
+ .byte 0
+ .uleb128 0x21
+ .string "end"
+ .byte 0x14
+ .2byte 0x147
+ .4byte 0x100
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF105
+ .byte 0x14
+ .2byte 0x148
+ .4byte 0x100
+ .byte 0x10
+ .uleb128 0x1f
+ .4byte .LASF106
+ .byte 0x14
+ .2byte 0x148
+ .4byte 0x100
+ .byte 0x18
+ .uleb128 0x1f
+ .4byte .LASF107
+ .byte 0x14
+ .2byte 0x149
+ .4byte 0x100
+ .byte 0x20
+ .uleb128 0x1f
+ .4byte .LASF108
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x28
+ .uleb128 0x1f
+ .4byte .LASF109
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x29
+ .uleb128 0x21
+ .string "os"
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x2a
+ .uleb128 0x1f
+ .4byte .LASF110
+ .byte 0x14
+ .2byte 0x14b
+ .4byte 0x110
+ .byte 0x2b
+ .byte 0
+ .uleb128 0x20
+ .4byte .LASF111
+ .byte 0x14
+ .2byte 0x14c
+ .4byte 0x650
+ .uleb128 0x22
+ .4byte .LASF112
+ .2byte 0x380
+ .byte 0x14
+ .2byte 0x152
+ .4byte 0x87b
+ .uleb128 0x1f
+ .4byte .LASF113
+ .byte 0x14
+ .2byte 0x158
+ .4byte 0x87b
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF114
+ .byte 0x14
+ .2byte 0x159
+ .4byte 0x644
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF115
+ .byte 0x14
+ .2byte 0x15a
+ .4byte 0x100
+ .byte 0x48
+ .uleb128 0x1f
+ .4byte .LASF116
+ .byte 0x14
+ .2byte 0x15d
+ .4byte 0xd6
+ .byte 0x50
+ .uleb128 0x1f
+ .4byte .LASF117
+ .byte 0x14
+ .2byte 0x15f
+ .4byte 0x126
+ .byte 0x58
+ .uleb128 0x1f
+ .4byte .LASF118
+ .byte 0x14
+ .2byte 0x160
+ .4byte 0xd6
+ .byte 0x60
+ .uleb128 0x1f
+ .4byte .LASF119
+ .byte 0x14
+ .2byte 0x161
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0x1f
+ .4byte .LASF120
+ .byte 0x14
+ .2byte 0x163
+ .4byte 0x126
+ .byte 0x70
+ .uleb128 0x1f
+ .4byte .LASF121
+ .byte 0x14
+ .2byte 0x164
+ .4byte 0xd6
+ .byte 0x78
+ .uleb128 0x1f
+ .4byte .LASF122
+ .byte 0x14
+ .2byte 0x165
+ .4byte 0x54
+ .byte 0x80
+ .uleb128 0x1f
+ .4byte .LASF123
+ .byte 0x14
+ .2byte 0x167
+ .4byte 0x126
+ .byte 0x88
+ .uleb128 0x1f
+ .4byte .LASF124
+ .byte 0x14
+ .2byte 0x168
+ .4byte 0xd6
+ .byte 0x90
+ .uleb128 0x1f
+ .4byte .LASF125
+ .byte 0x14
+ .2byte 0x169
+ .4byte 0x54
+ .byte 0x98
+ .uleb128 0x1f
+ .4byte .LASF126
+ .byte 0x14
+ .2byte 0x16b
+ .4byte 0x126
+ .byte 0xa0
+ .uleb128 0x1f
+ .4byte .LASF127
+ .byte 0x14
+ .2byte 0x16c
+ .4byte 0xd6
+ .byte 0xa8
+ .uleb128 0x1f
+ .4byte .LASF128
+ .byte 0x14
+ .2byte 0x16d
+ .4byte 0x54
+ .byte 0xb0
+ .uleb128 0x21
+ .string "os"
+ .byte 0x14
+ .2byte 0x171
+ .4byte 0x6d2
+ .byte 0xb8
+ .uleb128 0x21
+ .string "ep"
+ .byte 0x14
+ .2byte 0x172
+ .4byte 0x100
+ .byte 0xe8
+ .uleb128 0x1f
+ .4byte .LASF129
+ .byte 0x14
+ .2byte 0x174
+ .4byte 0x100
+ .byte 0xf0
+ .uleb128 0x1f
+ .4byte .LASF130
+ .byte 0x14
+ .2byte 0x174
+ .4byte 0x100
+ .byte 0xf8
+ .uleb128 0x23
+ .4byte .LASF131
+ .byte 0x14
+ .2byte 0x176
+ .4byte 0xef
+ .2byte 0x100
+ .uleb128 0x23
+ .4byte .LASF132
+ .byte 0x14
+ .2byte 0x177
+ .4byte 0x100
+ .2byte 0x108
+ .uleb128 0x23
+ .4byte .LASF133
+ .byte 0x14
+ .2byte 0x179
+ .4byte 0x100
+ .2byte 0x110
+ .uleb128 0x23
+ .4byte .LASF134
+ .byte 0x14
+ .2byte 0x17a
+ .4byte 0x100
+ .2byte 0x118
+ .uleb128 0x23
+ .4byte .LASF135
+ .byte 0x14
+ .2byte 0x17b
+ .4byte 0x100
+ .2byte 0x120
+ .uleb128 0x23
+ .4byte .LASF136
+ .byte 0x14
+ .2byte 0x17c
+ .4byte 0x100
+ .2byte 0x128
+ .uleb128 0x24
+ .string "kbd"
+ .byte 0x14
+ .2byte 0x17d
+ .4byte 0x881
+ .2byte 0x130
+ .uleb128 0x23
+ .4byte .LASF137
+ .byte 0x14
+ .2byte 0x180
+ .4byte 0x54
+ .2byte 0x138
+ .uleb128 0x23
+ .4byte .LASF138
+ .byte 0x14
+ .2byte 0x18d
+ .4byte 0x54
+ .2byte 0x13c
+ .uleb128 0x24
+ .string "lmb"
+ .byte 0x14
+ .2byte 0x190
+ .4byte 0x33b
+ .2byte 0x140
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x644
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x490
+ .uleb128 0x20
+ .4byte .LASF139
+ .byte 0x14
+ .2byte 0x196
+ .4byte 0x6de
+ .uleb128 0xd
+ .4byte .LASF140
+ .byte 0x14
+ .2byte 0x198
+ .4byte 0x887
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0x8b0
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x3ff
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF331
+ .byte 0x4
+ .4byte 0x54
+ .byte 0x18
+ .byte 0xe
+ .4byte 0xb19
+ .uleb128 0x26
+ .4byte .LASF141
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF142
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF143
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF144
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF145
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF146
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF147
+ .byte 0x6
+ .uleb128 0x26
+ .4byte .LASF148
+ .byte 0x7
+ .uleb128 0x26
+ .4byte .LASF149
+ .byte 0x8
+ .uleb128 0x26
+ .4byte .LASF150
+ .byte 0x9
+ .uleb128 0x26
+ .4byte .LASF151
+ .byte 0xa
+ .uleb128 0x26
+ .4byte .LASF152
+ .byte 0xb
+ .uleb128 0x26
+ .4byte .LASF153
+ .byte 0xc
+ .uleb128 0x26
+ .4byte .LASF154
+ .byte 0xd
+ .uleb128 0x26
+ .4byte .LASF155
+ .byte 0xe
+ .uleb128 0x26
+ .4byte .LASF156
+ .byte 0xf
+ .uleb128 0x26
+ .4byte .LASF157
+ .byte 0x10
+ .uleb128 0x26
+ .4byte .LASF158
+ .byte 0x11
+ .uleb128 0x26
+ .4byte .LASF159
+ .byte 0x12
+ .uleb128 0x26
+ .4byte .LASF160
+ .byte 0x13
+ .uleb128 0x26
+ .4byte .LASF161
+ .byte 0x14
+ .uleb128 0x26
+ .4byte .LASF162
+ .byte 0x15
+ .uleb128 0x26
+ .4byte .LASF163
+ .byte 0x16
+ .uleb128 0x26
+ .4byte .LASF164
+ .byte 0x17
+ .uleb128 0x26
+ .4byte .LASF165
+ .byte 0x18
+ .uleb128 0x26
+ .4byte .LASF166
+ .byte 0x19
+ .uleb128 0x26
+ .4byte .LASF167
+ .byte 0x1a
+ .uleb128 0x26
+ .4byte .LASF168
+ .byte 0x1b
+ .uleb128 0x26
+ .4byte .LASF169
+ .byte 0x1c
+ .uleb128 0x26
+ .4byte .LASF170
+ .byte 0x1d
+ .uleb128 0x26
+ .4byte .LASF171
+ .byte 0x1e
+ .uleb128 0x26
+ .4byte .LASF172
+ .byte 0x1f
+ .uleb128 0x26
+ .4byte .LASF173
+ .byte 0x20
+ .uleb128 0x26
+ .4byte .LASF174
+ .byte 0x21
+ .uleb128 0x26
+ .4byte .LASF175
+ .byte 0x22
+ .uleb128 0x26
+ .4byte .LASF176
+ .byte 0x23
+ .uleb128 0x26
+ .4byte .LASF177
+ .byte 0x24
+ .uleb128 0x26
+ .4byte .LASF178
+ .byte 0x25
+ .uleb128 0x26
+ .4byte .LASF179
+ .byte 0x26
+ .uleb128 0x26
+ .4byte .LASF180
+ .byte 0x27
+ .uleb128 0x26
+ .4byte .LASF181
+ .byte 0x28
+ .uleb128 0x26
+ .4byte .LASF182
+ .byte 0x29
+ .uleb128 0x26
+ .4byte .LASF183
+ .byte 0x2a
+ .uleb128 0x26
+ .4byte .LASF184
+ .byte 0x2b
+ .uleb128 0x26
+ .4byte .LASF185
+ .byte 0x2c
+ .uleb128 0x26
+ .4byte .LASF186
+ .byte 0x2d
+ .uleb128 0x26
+ .4byte .LASF187
+ .byte 0x2e
+ .uleb128 0x26
+ .4byte .LASF188
+ .byte 0x2f
+ .uleb128 0x26
+ .4byte .LASF189
+ .byte 0x30
+ .uleb128 0x26
+ .4byte .LASF190
+ .byte 0x31
+ .uleb128 0x26
+ .4byte .LASF191
+ .byte 0x32
+ .uleb128 0x26
+ .4byte .LASF192
+ .byte 0x33
+ .uleb128 0x26
+ .4byte .LASF193
+ .byte 0x34
+ .uleb128 0x26
+ .4byte .LASF194
+ .byte 0x35
+ .uleb128 0x26
+ .4byte .LASF195
+ .byte 0x36
+ .uleb128 0x26
+ .4byte .LASF196
+ .byte 0x37
+ .uleb128 0x26
+ .4byte .LASF197
+ .byte 0x38
+ .uleb128 0x26
+ .4byte .LASF198
+ .byte 0x39
+ .uleb128 0x26
+ .4byte .LASF199
+ .byte 0x3a
+ .uleb128 0x26
+ .4byte .LASF200
+ .byte 0x3b
+ .uleb128 0x26
+ .4byte .LASF201
+ .byte 0x3c
+ .uleb128 0x26
+ .4byte .LASF202
+ .byte 0x3d
+ .uleb128 0x26
+ .4byte .LASF203
+ .byte 0x3e
+ .uleb128 0x26
+ .4byte .LASF204
+ .byte 0x3f
+ .uleb128 0x26
+ .4byte .LASF205
+ .byte 0x40
+ .uleb128 0x26
+ .4byte .LASF206
+ .byte 0x41
+ .uleb128 0x26
+ .4byte .LASF207
+ .byte 0x42
+ .uleb128 0x26
+ .4byte .LASF208
+ .byte 0x43
+ .uleb128 0x26
+ .4byte .LASF209
+ .byte 0x44
+ .uleb128 0x26
+ .4byte .LASF210
+ .byte 0x45
+ .uleb128 0x26
+ .4byte .LASF211
+ .byte 0x46
+ .uleb128 0x26
+ .4byte .LASF212
+ .byte 0x47
+ .uleb128 0x26
+ .4byte .LASF213
+ .byte 0x48
+ .uleb128 0x26
+ .4byte .LASF214
+ .byte 0x49
+ .uleb128 0x26
+ .4byte .LASF215
+ .byte 0x4a
+ .uleb128 0x26
+ .4byte .LASF216
+ .byte 0x4b
+ .uleb128 0x26
+ .4byte .LASF217
+ .byte 0x4c
+ .uleb128 0x26
+ .4byte .LASF218
+ .byte 0x4d
+ .uleb128 0x26
+ .4byte .LASF219
+ .byte 0x4e
+ .uleb128 0x26
+ .4byte .LASF220
+ .byte 0x4f
+ .uleb128 0x26
+ .4byte .LASF221
+ .byte 0x50
+ .uleb128 0x26
+ .4byte .LASF222
+ .byte 0x51
+ .uleb128 0x26
+ .4byte .LASF223
+ .byte 0x52
+ .uleb128 0x26
+ .4byte .LASF224
+ .byte 0x53
+ .uleb128 0x26
+ .4byte .LASF225
+ .byte 0x54
+ .uleb128 0x26
+ .4byte .LASF226
+ .byte 0x55
+ .uleb128 0x26
+ .4byte .LASF227
+ .byte 0x56
+ .uleb128 0x26
+ .4byte .LASF228
+ .byte 0x57
+ .uleb128 0x26
+ .4byte .LASF229
+ .byte 0x58
+ .uleb128 0x26
+ .4byte .LASF230
+ .byte 0x59
+ .uleb128 0x26
+ .4byte .LASF231
+ .byte 0x5a
+ .uleb128 0x26
+ .4byte .LASF232
+ .byte 0x5b
+ .uleb128 0x26
+ .4byte .LASF233
+ .byte 0x5c
+ .uleb128 0x26
+ .4byte .LASF234
+ .byte 0x5d
+ .uleb128 0x26
+ .4byte .LASF235
+ .byte 0x5e
+ .uleb128 0x26
+ .4byte .LASF236
+ .byte 0x5f
+ .uleb128 0x26
+ .4byte .LASF237
+ .byte 0x60
+ .uleb128 0x26
+ .4byte .LASF238
+ .byte 0x61
+ .uleb128 0x26
+ .4byte .LASF239
+ .byte 0x62
+ .uleb128 0x27
+ .4byte .LASF240
+ .sleb128 -1
+ .byte 0
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1d
+ .byte 0xf6
+ .4byte 0xb2c
+ .uleb128 0x26
+ .4byte .LASF241
+ .byte 0x5
+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF242
+ .byte 0x40
+ .byte 0x15
+ .byte 0xc
+ .4byte 0xba5
+ .uleb128 0x12
+ .4byte .LASF243
+ .byte 0x15
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x1a
+ .string "tbu"
+ .byte 0x15
+ .byte 0x23
+ .4byte 0x7f
+ .byte 0x8
+ .uleb128 0x1a
+ .string "tbl"
+ .byte 0x15
+ .byte 0x24
+ .4byte 0x7f
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF244
+ .byte 0x15
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF245
+ .byte 0x15
+ .byte 0x26
+ .4byte 0x8d
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF246
+ .byte 0x15
+ .byte 0x29
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF247
+ .byte 0x15
+ .byte 0x2a
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF248
+ .byte 0x15
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0x12
+ .4byte .LASF249
+ .byte 0x15
+ .byte 0x2d
+ .4byte 0x3b
+ .byte 0x38
+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF250
+ .byte 0x18
+ .byte 0x16
+ .byte 0x22
+ .4byte 0xbed
+ .uleb128 0x12
+ .4byte .LASF251
+ .byte 0x16
+ .byte 0x23
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF252
+ .byte 0x16
+ .byte 0x24
+ .4byte 0xa3
+ .byte 0x4
+ .uleb128 0x1a
+ .string "id"
+ .byte 0x16
+ .byte 0x25
+ .4byte 0xa3
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF253
+ .byte 0x16
+ .byte 0x26
+ .4byte 0xa3
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF254
+ .byte 0x16
+ .byte 0x27
+ .4byte 0x100
+ .byte 0x10
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF255
+ .2byte 0x1c8
+ .byte 0x16
+ .byte 0x2a
+ .4byte 0xe23
+ .uleb128 0x1a
+ .string "bd"
+ .byte 0x16
+ .byte 0x2b
+ .4byte 0x881
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF256
+ .byte 0x16
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF253
+ .byte 0x16
+ .byte 0x2d
+ .4byte 0x7f
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF257
+ .byte 0x16
+ .byte 0x2e
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF258
+ .byte 0x16
+ .byte 0x2f
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF259
+ .byte 0x16
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF260
+ .byte 0x16
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0x12
+ .4byte .LASF261
+ .byte 0x16
+ .byte 0x3e
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0x12
+ .4byte .LASF262
+ .byte 0x16
+ .byte 0x42
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0x12
+ .4byte .LASF263
+ .byte 0x16
+ .byte 0x43
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0x12
+ .4byte .LASF264
+ .byte 0x16
+ .byte 0x45
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0x12
+ .4byte .LASF265
+ .byte 0x16
+ .byte 0x46
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0x12
+ .4byte .LASF266
+ .byte 0x16
+ .byte 0x47
+ .4byte 0x3b
+ .byte 0x60
+ .uleb128 0x12
+ .4byte .LASF267
+ .byte 0x16
+ .byte 0x48
+ .4byte 0xc4
+ .byte 0x68
+ .uleb128 0x12
+ .4byte .LASF268
+ .byte 0x16
+ .byte 0x49
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0x12
+ .4byte .LASF269
+ .byte 0x16
+ .byte 0x4a
+ .4byte 0x3b
+ .byte 0x78
+ .uleb128 0x12
+ .4byte .LASF270
+ .byte 0x16
+ .byte 0x4b
+ .4byte 0x3b
+ .byte 0x80
+ .uleb128 0x12
+ .4byte .LASF271
+ .byte 0x16
+ .byte 0x4c
+ .4byte 0x3b
+ .byte 0x88
+ .uleb128 0x12
+ .4byte .LASF272
+ .byte 0x16
+ .byte 0x4d
+ .4byte 0xe23
+ .byte 0x90
+ .uleb128 0x12
+ .4byte .LASF273
+ .byte 0x16
+ .byte 0x50
+ .4byte 0x16e
+ .byte 0x98
+ .uleb128 0x12
+ .4byte .LASF274
+ .byte 0x16
+ .byte 0x51
+ .4byte 0x16e
+ .byte 0xa0
+ .uleb128 0x12
+ .4byte .LASF275
+ .byte 0x16
+ .byte 0x52
+ .4byte 0x1a1
+ .byte 0xa8
+ .uleb128 0x12
+ .4byte .LASF276
+ .byte 0x16
+ .byte 0x57
+ .4byte 0x174
+ .byte 0xb8
+ .uleb128 0x12
+ .4byte .LASF277
+ .byte 0x16
+ .byte 0x58
+ .4byte 0x126
+ .byte 0xc0
+ .uleb128 0x12
+ .4byte .LASF278
+ .byte 0x16
+ .byte 0x59
+ .4byte 0x3b
+ .byte 0xc8
+ .uleb128 0x12
+ .4byte .LASF279
+ .byte 0x16
+ .byte 0x5b
+ .4byte 0xe2e
+ .byte 0xd0
+ .uleb128 0x12
+ .4byte .LASF280
+ .byte 0x16
+ .byte 0x5c
+ .4byte 0xe2e
+ .byte 0xd8
+ .uleb128 0x12
+ .4byte .LASF281
+ .byte 0x16
+ .byte 0x5e
+ .4byte 0x174
+ .byte 0xe0
+ .uleb128 0x12
+ .4byte .LASF282
+ .byte 0x16
+ .byte 0x5f
+ .4byte 0x174
+ .byte 0xe8
+ .uleb128 0x1a
+ .string "jt"
+ .byte 0x16
+ .byte 0x60
+ .4byte 0xe39
+ .byte 0xf0
+ .uleb128 0x12
+ .4byte .LASF283
+ .byte 0x16
+ .byte 0x61
+ .4byte 0xe3f
+ .byte 0xf8
+ .uleb128 0x16
+ .4byte .LASF284
+ .byte 0x16
+ .byte 0x6b
+ .4byte 0x7f
+ .2byte 0x118
+ .uleb128 0x16
+ .4byte .LASF285
+ .byte 0x16
+ .byte 0x6c
+ .4byte 0x7f
+ .2byte 0x11c
+ .uleb128 0x16
+ .4byte .LASF286
+ .byte 0x16
+ .byte 0x6e
+ .4byte 0x3b
+ .2byte 0x120
+ .uleb128 0x16
+ .4byte .LASF287
+ .byte 0x16
+ .byte 0x6f
+ .4byte 0x3b
+ .2byte 0x128
+ .uleb128 0x16
+ .4byte .LASF288
+ .byte 0x16
+ .byte 0x70
+ .4byte 0x3b
+ .2byte 0x130
+ .uleb128 0x16
+ .4byte .LASF289
+ .byte 0x16
+ .byte 0x79
+ .4byte 0x16e
+ .2byte 0x138
+ .uleb128 0x16
+ .4byte .LASF110
+ .byte 0x16
+ .byte 0x7a
+ .4byte 0xb2c
+ .2byte 0x140
+ .uleb128 0x16
+ .4byte .LASF290
+ .byte 0x16
+ .byte 0x80
+ .4byte 0x100
+ .2byte 0x180
+ .uleb128 0x16
+ .4byte .LASF291
+ .byte 0x16
+ .byte 0x81
+ .4byte 0x100
+ .2byte 0x188
+ .uleb128 0x16
+ .4byte .LASF292
+ .byte 0x16
+ .byte 0x87
+ .4byte 0xb9
+ .2byte 0x190
+ .uleb128 0x16
+ .4byte .LASF293
+ .byte 0x16
+ .byte 0x8a
+ .4byte 0x54
+ .2byte 0x198
+ .uleb128 0x16
+ .4byte .LASF294
+ .byte 0x16
+ .byte 0x8c
+ .4byte 0xba5
+ .2byte 0x1a0
+ .uleb128 0x16
+ .4byte .LASF295
+ .byte 0x16
+ .byte 0x8d
+ .4byte 0x100
+ .2byte 0x1b8
+ .uleb128 0x16
+ .4byte .LASF296
+ .byte 0x16
+ .byte 0x8e
+ .4byte 0x54
+ .2byte 0x1c0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xbed
+ .uleb128 0xe
+ .4byte .LASF297
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe29
+ .uleb128 0xe
+ .4byte .LASF298
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe34
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0xe4f
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF299
+ .byte 0x16
+ .byte 0x9b
+ .4byte 0xbed
+ .uleb128 0x9
+ .4byte 0xe4f
+ .uleb128 0x4
+ .4byte .LASF300
+ .byte 0x4
+ .byte 0xad
+ .4byte 0x100
+ .uleb128 0xb
+ .4byte 0x94
+ .4byte 0xe75
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF301
+ .byte 0x4
+ .byte 0xaf
+ .4byte 0xe6a
+ .uleb128 0x4
+ .4byte .LASF302
+ .byte 0x4
+ .byte 0xb0
+ .4byte 0xe6a
+ .uleb128 0x4
+ .4byte .LASF303
+ .byte 0x4
+ .byte 0xfe
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF304
+ .byte 0x4
+ .byte 0xff
+ .4byte 0x100
+ .uleb128 0xd
+ .4byte .LASF305
+ .byte 0x4
+ .2byte 0x100
+ .4byte 0x100
+ .uleb128 0x11
+ .4byte .LASF306
+ .byte 0x4
+ .byte 0x17
+ .byte 0x2e
+ .4byte 0xec6
+ .uleb128 0x12
+ .4byte .LASF307
+ .byte 0x17
+ .byte 0x2f
+ .4byte 0x11b
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x29
+ .uleb128 0xb
+ .4byte 0x94
+ .4byte 0xedc
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x5
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF308
+ .byte 0x17
+ .2byte 0x1fd
+ .4byte 0xead
+ .uleb128 0xd
+ .4byte .LASF309
+ .byte 0x17
+ .2byte 0x1fe
+ .4byte 0xead
+ .uleb128 0xd
+ .4byte .LASF310
+ .byte 0x17
+ .2byte 0x200
+ .4byte 0xead
+ .uleb128 0xd
+ .4byte .LASF311
+ .byte 0x17
+ .2byte 0x205
+ .4byte 0xe3f
+ .uleb128 0xd
+ .4byte .LASF312
+ .byte 0x17
+ .2byte 0x206
+ .4byte 0xe3f
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0xf28
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x3f
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF313
+ .byte 0x17
+ .2byte 0x207
+ .4byte 0xf18
+ .uleb128 0xd
+ .4byte .LASF314
+ .byte 0x17
+ .2byte 0x209
+ .4byte 0xecc
+ .uleb128 0xd
+ .4byte .LASF315
+ .byte 0x17
+ .2byte 0x20a
+ .4byte 0xecc
+ .uleb128 0xd
+ .4byte .LASF316
+ .byte 0x17
+ .2byte 0x20b
+ .4byte 0xead
+ .uleb128 0xd
+ .4byte .LASF317
+ .byte 0x17
+ .2byte 0x20c
+ .4byte 0xead
+ .uleb128 0xd
+ .4byte .LASF318
+ .byte 0x17
+ .2byte 0x20d
+ .4byte 0xec6
+ .uleb128 0xb
+ .4byte 0xec6
+ .4byte 0xf80
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x3
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF319
+ .byte 0x17
+ .2byte 0x20e
+ .4byte 0xf70
+ .uleb128 0xd
+ .4byte .LASF320
+ .byte 0x17
+ .2byte 0x20f
+ .4byte 0xec6
+ .uleb128 0xd
+ .4byte .LASF321
+ .byte 0x17
+ .2byte 0x210
+ .4byte 0x54
+ .uleb128 0xb
+ .4byte 0x9e
+ .4byte 0xfb4
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x5
+ .byte 0
+ .uleb128 0x7
+ .4byte 0xfa4
+ .uleb128 0xd
+ .4byte .LASF322
+ .byte 0x17
+ .2byte 0x211
+ .4byte 0xfb4
+ .uleb128 0xd
+ .4byte .LASF323
+ .byte 0x17
+ .2byte 0x212
+ .4byte 0xfb4
+ .uleb128 0xd
+ .4byte .LASF324
+ .byte 0x17
+ .2byte 0x216
+ .4byte 0xf5
+ .uleb128 0xd
+ .4byte .LASF325
+ .byte 0x17
+ .2byte 0x217
+ .4byte 0xf5
+ .uleb128 0xd
+ .4byte .LASF326
+ .byte 0x17
+ .2byte 0x219
+ .4byte 0x54
+ .uleb128 0xd
+ .4byte .LASF327
+ .byte 0x17
+ .2byte 0x220
+ .4byte 0x89f
+ .uleb128 0xd
+ .4byte .LASF328
+ .byte 0x17
+ .2byte 0x222
+ .4byte 0xa3
+ .uleb128 0xd
+ .4byte .LASF329
+ .byte 0x17
+ .2byte 0x224
+ .4byte 0xa3
+ .uleb128 0xd
+ .4byte .LASF330
+ .byte 0x17
+ .2byte 0x230
+ .4byte 0xead
+ .uleb128 0x29
+ .4byte .LASF332
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x17
+ .2byte 0x286
+ .4byte 0x104f
+ .uleb128 0x26
+ .4byte .LASF333
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF334
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF335
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF336
+ .byte 0x3
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF337
+ .byte 0x17
+ .2byte 0x28c
+ .4byte 0x1025
+ .uleb128 0x4
+ .4byte .LASF338
+ .byte 0x19
+ .byte 0x2b
+ .4byte 0x13a
+ .uleb128 0x4
+ .4byte .LASF339
+ .byte 0x19
+ .byte 0x2b
+ .4byte 0x13a
+ .uleb128 0x11
+ .4byte .LASF340
+ .byte 0x28
+ .byte 0x1a
+ .byte 0x39
+ .4byte 0x10ba
+ .uleb128 0x1a
+ .string "dev"
+ .byte 0x1a
+ .byte 0x3a
+ .4byte 0x126
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF341
+ .byte 0x1a
+ .byte 0x3b
+ .4byte 0x126
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF342
+ .byte 0x1a
+ .byte 0x3c
+ .4byte 0x54
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF343
+ .byte 0x1a
+ .byte 0x3d
+ .4byte 0xd6
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF344
+ .byte 0x1a
+ .byte 0x3e
+ .4byte 0x10de
+ .byte 0x20
+ .byte 0
+ .uleb128 0x13
+ .4byte 0x100
+ .4byte 0x10d8
+ .uleb128 0x14
+ .4byte 0x10d8
+ .uleb128 0x14
+ .4byte 0x100
+ .uleb128 0x14
+ .4byte 0x100
+ .uleb128 0x14
+ .4byte 0x126
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1071
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x10ba
+ .uleb128 0x11
+ .4byte .LASF345
+ .byte 0x38
+ .byte 0x1b
+ .byte 0xc
+ .4byte 0x1115
+ .uleb128 0x12
+ .4byte .LASF346
+ .byte 0x1b
+ .byte 0xd
+ .4byte 0x1071
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF347
+ .byte 0x1b
+ .byte 0x10
+ .4byte 0x126
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF348
+ .byte 0x1b
+ .byte 0x11
+ .4byte 0x100
+ .byte 0x30
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF349
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1c
+ .byte 0xb
+ .4byte 0x116e
+ .uleb128 0x26
+ .4byte .LASF350
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF351
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF352
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF353
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF354
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF355
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF356
+ .byte 0x6
+ .uleb128 0x26
+ .4byte .LASF357
+ .byte 0x7
+ .uleb128 0x26
+ .4byte .LASF358
+ .byte 0x8
+ .uleb128 0x26
+ .4byte .LASF359
+ .byte 0x9
+ .uleb128 0x26
+ .4byte .LASF360
+ .byte 0xa
+ .uleb128 0x26
+ .4byte .LASF361
+ .byte 0xb
+ .byte 0
+ .uleb128 0x2a
+ .string "gd"
+ .byte 0x1
+ .byte 0xf
+ .4byte 0x1178
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe5a
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1
+ .byte 0x40
+ .4byte 0x11a3
+ .uleb128 0x26
+ .4byte .LASF362
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF363
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF364
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF365
+ .byte 0x3
+ .byte 0
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1
+ .byte 0x47
+ .4byte 0x11da
+ .uleb128 0x26
+ .4byte .LASF366
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF367
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF368
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF369
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF370
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF371
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF372
+ .byte 0x6
+ .byte 0
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1
+ .byte 0x51
+ .4byte 0x121d
+ .uleb128 0x26
+ .4byte .LASF373
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF374
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF375
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF376
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF377
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF378
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF379
+ .byte 0x6
+ .uleb128 0x26
+ .4byte .LASF380
+ .byte 0x7
+ .uleb128 0x26
+ .4byte .LASF381
+ .byte 0x8
+ .byte 0
+ .uleb128 0xb
+ .4byte 0xd6
+ .4byte 0x122d
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x7
+ .byte 0
+ .uleb128 0x2b
+ .4byte .LASF382
+ .byte 0x1
+ .byte 0x5d
+ .4byte 0x121d
+ .uleb128 0x9
+ .byte 0x3
+ .8byte tid_name
+ .uleb128 0x2
+ .4byte .LASF383
+ .byte 0x1
+ .byte 0x68
+ .4byte 0x124d
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1253
+ .uleb128 0x13
+ .4byte 0x54
+ .4byte 0x1262
+ .uleb128 0x14
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x10e4
+ .uleb128 0x11
+ .4byte .LASF384
+ .byte 0x28
+ .byte 0x1
+ .byte 0x69
+ .4byte 0x12c7
+ .uleb128 0x1a
+ .string "fn"
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x1242
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF138
+ .byte 0x1
+ .byte 0x6b
+ .4byte 0xa3
+ .byte 0x8
+ .uleb128 0x1a
+ .string "tid"
+ .byte 0x1
+ .byte 0x6c
+ .4byte 0xa3
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF385
+ .byte 0x1
+ .byte 0x6d
+ .4byte 0xa3
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF386
+ .byte 0x1
+ .byte 0x6e
+ .4byte 0xa3
+ .byte 0x14
+ .uleb128 0x1a
+ .string "ret"
+ .byte 0x1
+ .byte 0x6f
+ .4byte 0x54
+ .byte 0x18
+ .uleb128 0x1a
+ .string "ms"
+ .byte 0x1
+ .byte 0x70
+ .4byte 0x100
+ .byte 0x20
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF387
+ .2byte 0x148
+ .byte 0x1
+ .byte 0x73
+ .4byte 0x12ee
+ .uleb128 0x12
+ .4byte .LASF388
+ .byte 0x1
+ .byte 0x74
+ .4byte 0x12ee
+ .byte 0
+ .uleb128 0x17
+ .string "num"
+ .byte 0x1
+ .byte 0x75
+ .4byte 0x94
+ .2byte 0x140
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x1268
+ .4byte 0x12fe
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x7
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF389
+ .2byte 0x560
+ .byte 0x1
+ .byte 0x78
+ .4byte 0x1331
+ .uleb128 0x12
+ .4byte .LASF390
+ .byte 0x1
+ .byte 0x79
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x1a
+ .string "cpu"
+ .byte 0x1
+ .byte 0x7a
+ .4byte 0x1331
+ .byte 0x8
+ .uleb128 0x16
+ .4byte .LASF391
+ .byte 0x1
+ .byte 0x7b
+ .4byte 0x10e4
+ .2byte 0x528
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x12c7
+ .4byte 0x1341
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x3
+ .byte 0
+ .uleb128 0x2c
+ .string "mpb"
+ .byte 0x1
+ .byte 0x7e
+ .4byte 0x134c
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12fe
+ .uleb128 0x2b
+ .4byte .LASF392
+ .byte 0x1
+ .byte 0x7f
+ .4byte 0x100
+ .uleb128 0x9
+ .byte 0x3
+ .8byte mpb_gd
+ .uleb128 0x11
+ .4byte .LASF393
+ .byte 0x18
+ .byte 0x1
+ .byte 0x95
+ .4byte 0x13af
+ .uleb128 0x1a
+ .string "cid"
+ .byte 0x1
+ .byte 0x96
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x1a
+ .string "tid"
+ .byte 0x1
+ .byte 0x97
+ .4byte 0xa3
+ .byte 0x4
+ .uleb128 0x1a
+ .string "fn"
+ .byte 0x1
+ .byte 0x98
+ .4byte 0x1242
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF385
+ .byte 0x1
+ .byte 0x99
+ .4byte 0xa3
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF386
+ .byte 0x1
+ .byte 0x9a
+ .4byte 0xa3
+ .byte 0x14
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF406
+ .byte 0x1
+ .2byte 0x23f
+ .4byte 0x100
+ .8byte .LFB239
+ .8byte .LFE239-.LFB239
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x14ef
+ .uleb128 0x2e
+ .string "evt"
+ .byte 0x1
+ .2byte 0x23f
+ .4byte 0x54
+ .4byte .LLST61
+ .uleb128 0x2f
+ .4byte .LASF394
+ .byte 0x1
+ .2byte 0x241
+ .4byte 0x54
+ .4byte .LLST62
+ .uleb128 0x30
+ .string "cmd"
+ .byte 0x1
+ .2byte 0x242
+ .4byte 0xe3f
+ .uleb128 0x2
+ .byte 0x91
+ .sleb128 -32
+ .uleb128 0x31
+ .8byte .LVL155
+ .4byte 0x1b59
+ .uleb128 0x32
+ .8byte .LVL157
+ .4byte 0x1b59
+ .4byte 0x1424
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x35
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL158
+ .4byte 0x14ef
+ .uleb128 0x31
+ .8byte .LVL162
+ .4byte 0x14ef
+ .uleb128 0x31
+ .8byte .LVL163
+ .4byte 0x14ef
+ .uleb128 0x32
+ .8byte .LVL164
+ .4byte 0x1b59
+ .4byte 0x1462
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x36
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL165
+ .4byte 0x14ef
+ .uleb128 0x32
+ .8byte .LVL167
+ .4byte 0x1b59
+ .4byte 0x1486
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x35
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL168
+ .4byte 0x24b5
+ .4byte 0x14b1
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8f
+ .sleb128 16
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x20
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC15
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL169
+ .4byte 0x24c0
+ .4byte 0x14ce
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8f
+ .sleb128 16
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL170
+ .4byte 0x1cdf
+ .uleb128 0x34
+ .8byte .LVL171
+ .4byte 0x1b59
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x34
+ .byte 0
+ .byte 0
+ .uleb128 0x35
+ .4byte .LASF402
+ .byte 0x1
+ .2byte 0x22f
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x150d
+ .uleb128 0x36
+ .4byte .LASF395
+ .byte 0x1
+ .2byte 0x231
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x37
+ .4byte .LASF396
+ .byte 0x1
+ .2byte 0x219
+ .8byte .LFB237
+ .8byte .LFE237-.LFB237
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x16f6
+ .uleb128 0x2e
+ .string "evt"
+ .byte 0x1
+ .2byte 0x219
+ .4byte 0x54
+ .4byte .LLST53
+ .uleb128 0x38
+ .4byte 0x178a
+ .8byte .LBB124
+ .4byte .Ldebug_ranges0+0x1c0
+ .byte 0x1
+ .2byte 0x21d
+ .4byte 0x1665
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x1c0
+ .uleb128 0x3a
+ .4byte 0x1797
+ .uleb128 0x2
+ .byte 0x91
+ .sleb128 -48
+ .uleb128 0x3b
+ .4byte 0x17a3
+ .4byte .LLST54
+ .uleb128 0x38
+ .4byte 0x2027
+ .8byte .LBB126
+ .4byte .Ldebug_ranges0+0x1f0
+ .byte 0x1
+ .2byte 0x203
+ .4byte 0x15ac
+ .uleb128 0x3c
+ .4byte 0x2037
+ .4byte .LLST55
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x1f0
+ .uleb128 0x3b
+ .4byte 0x2042
+ .4byte .LLST56
+ .uleb128 0x3b
+ .4byte 0x204d
+ .4byte .LLST57
+ .uleb128 0x3b
+ .4byte 0x2058
+ .4byte .LLST58
+ .byte 0
+ .byte 0
+ .uleb128 0x3d
+ .8byte .LBB131
+ .8byte .LBE131-.LBB131
+ .4byte 0x15c7
+ .uleb128 0x3e
+ .4byte 0x17b2
+ .byte 0
+ .uleb128 0x3d
+ .8byte .LBB132
+ .8byte .LBE132-.LBB132
+ .4byte 0x15e6
+ .uleb128 0x3b
+ .4byte 0x17c0
+ .4byte .LLST59
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL130
+ .4byte 0x24cb
+ .4byte 0x1611
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8f
+ .sleb128 16
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR3
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x30
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL131
+ .4byte 0x24d4
+ .4byte 0x1630
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC14
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL132
+ .4byte 0x24df
+ .4byte 0x1656
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x4
+ .byte 0x8
+ .byte 0x82
+ .byte 0x44
+ .byte 0x24
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x560
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL135
+ .4byte 0x24ea
+ .byte 0
+ .byte 0
+ .uleb128 0x3f
+ .4byte 0x2149
+ .8byte .LBB136
+ .8byte .LBE136-.LBB136
+ .byte 0x1
+ .2byte 0x226
+ .4byte 0x16a0
+ .uleb128 0x3c
+ .4byte 0x2155
+ .4byte .LLST60
+ .uleb128 0x40
+ .8byte .LVL150
+ .4byte 0x24f6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL147
+ .4byte 0x1edd
+ .4byte 0x16c6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x33
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x6
+ .byte 0x11
+ .sleb128 -559087616
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL148
+ .4byte 0x24ea
+ .uleb128 0x40
+ .8byte .LVL152
+ .4byte 0x1edd
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x37
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x6
+ .byte 0x11
+ .sleb128 -559087616
+ .byte 0
+ .byte 0
+ .uleb128 0x37
+ .4byte .LASF397
+ .byte 0x1
+ .2byte 0x20e
+ .8byte .LFB236
+ .8byte .LFE236-.LFB236
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x178a
+ .uleb128 0x41
+ .4byte .LASF346
+ .byte 0x1
+ .2byte 0x20e
+ .4byte 0x1071
+ .uleb128 0x2
+ .byte 0x70
+ .sleb128 0
+ .uleb128 0x32
+ .8byte .LVL124
+ .4byte 0x24cb
+ .4byte 0x173b
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x28
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL125
+ .4byte 0x19bc
+ .4byte 0x1757
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x32
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL126
+ .4byte 0x1edd
+ .4byte 0x177c
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x33
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x11111111
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL127
+ .4byte 0x24ea
+ .byte 0
+ .uleb128 0x42
+ .4byte .LASF419
+ .byte 0x1
+ .2byte 0x1e9
+ .byte 0x1
+ .4byte 0x17ce
+ .uleb128 0x36
+ .4byte .LASF398
+ .byte 0x1
+ .2byte 0x1ee
+ .4byte 0x17ce
+ .uleb128 0x43
+ .string "i"
+ .byte 0x1
+ .2byte 0x1fb
+ .4byte 0x54
+ .uleb128 0x44
+ .4byte 0x17bf
+ .uleb128 0x43
+ .string "__v"
+ .byte 0x1
+ .2byte 0x206
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x45
+ .uleb128 0x43
+ .string "__v"
+ .byte 0x1
+ .2byte 0x207
+ .4byte 0xa3
+ .byte 0
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x1367
+ .4byte 0x17de
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1
+ .byte 0
+ .uleb128 0x37
+ .4byte .LASF399
+ .byte 0x1
+ .2byte 0x1bf
+ .8byte .LFB234
+ .8byte .LFE234-.LFB234
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x18d6
+ .uleb128 0x2e
+ .string "cpu"
+ .byte 0x1
+ .2byte 0x1bf
+ .4byte 0xa3
+ .4byte .LLST51
+ .uleb128 0x3f
+ .4byte 0x2086
+ .8byte .LBB110
+ .8byte .LBE110-.LBB110
+ .byte 0x1
+ .2byte 0x1c2
+ .4byte 0x1832
+ .uleb128 0x3c
+ .4byte 0x2092
+ .4byte .LLST52
+ .byte 0
+ .uleb128 0x46
+ .4byte 0x2141
+ .8byte .LBB112
+ .8byte .LBE112-.LBB112
+ .byte 0x1
+ .2byte 0x1d6
+ .uleb128 0x46
+ .4byte 0x207e
+ .8byte .LBB114
+ .8byte .LBE114-.LBB114
+ .byte 0x1
+ .2byte 0x1da
+ .uleb128 0x31
+ .8byte .LVL116
+ .4byte 0x2501
+ .uleb128 0x32
+ .8byte .LVL117
+ .4byte 0x18d6
+ .4byte 0x1887
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL118
+ .4byte 0x24ea
+ .uleb128 0x31
+ .8byte .LVL119
+ .4byte 0x250d
+ .uleb128 0x31
+ .8byte .LVL120
+ .4byte 0x2519
+ .uleb128 0x31
+ .8byte .LVL121
+ .4byte 0x2525
+ .uleb128 0x31
+ .8byte .LVL122
+ .4byte 0x2531
+ .uleb128 0x31
+ .8byte .LVL123
+ .4byte 0x253d
+ .byte 0
+ .uleb128 0x37
+ .4byte .LASF400
+ .byte 0x1
+ .2byte 0x1b1
+ .8byte .LFB233
+ .8byte .LFE233-.LFB233
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x19b6
+ .uleb128 0x2e
+ .string "cpu"
+ .byte 0x1
+ .2byte 0x1b1
+ .4byte 0xa3
+ .4byte .LLST42
+ .uleb128 0x2f
+ .4byte .LASF388
+ .byte 0x1
+ .2byte 0x1b3
+ .4byte 0x19b6
+ .4byte .LLST43
+ .uleb128 0x47
+ .string "i"
+ .byte 0x1
+ .2byte 0x1b4
+ .4byte 0x54
+ .4byte .LLST44
+ .uleb128 0x48
+ .4byte 0x1ae8
+ .8byte .LBB102
+ .4byte .Ldebug_ranges0+0x160
+ .byte 0x1
+ .2byte 0x1b8
+ .uleb128 0x3c
+ .4byte 0x1b1c
+ .4byte .LLST45
+ .uleb128 0x3c
+ .4byte 0x1b10
+ .4byte .LLST46
+ .uleb128 0x3c
+ .4byte 0x1b05
+ .4byte .LLST47
+ .uleb128 0x3c
+ .4byte 0x1af9
+ .4byte .LLST48
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x160
+ .uleb128 0x3e
+ .4byte 0x1b28
+ .uleb128 0x3e
+ .4byte 0x1b34
+ .uleb128 0x3b
+ .4byte 0x1b40
+ .4byte .LLST49
+ .uleb128 0x3b
+ .4byte 0x1b4c
+ .4byte .LLST50
+ .uleb128 0x38
+ .4byte 0x2062
+ .8byte .LBB104
+ .4byte .Ldebug_ranges0+0x190
+ .byte 0x1
+ .2byte 0x179
+ .4byte 0x1999
+ .uleb128 0x49
+ .4byte 0x2072
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL110
+ .4byte 0x21f4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x87
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1268
+ .uleb128 0x37
+ .4byte .LASF401
+ .byte 0x1
+ .2byte 0x1a3
+ .8byte .LFB232
+ .8byte .LFE232-.LFB232
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1ae8
+ .uleb128 0x2e
+ .string "cid"
+ .byte 0x1
+ .2byte 0x1a3
+ .4byte 0xa3
+ .4byte .LLST31
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x1a3
+ .4byte 0xa3
+ .4byte .LLST32
+ .uleb128 0x2f
+ .4byte .LASF388
+ .byte 0x1
+ .2byte 0x1a5
+ .4byte 0x19b6
+ .4byte .LLST33
+ .uleb128 0x47
+ .string "i"
+ .byte 0x1
+ .2byte 0x1a6
+ .4byte 0x54
+ .4byte .LLST34
+ .uleb128 0x38
+ .4byte 0x2062
+ .8byte .LBB90
+ .4byte .Ldebug_ranges0+0x130
+ .byte 0x1
+ .2byte 0x1a8
+ .4byte 0x1a3a
+ .uleb128 0x3c
+ .4byte 0x2072
+ .4byte .LLST35
+ .byte 0
+ .uleb128 0x4a
+ .4byte 0x1ae8
+ .8byte .LBB94
+ .8byte .LBE94-.LBB94
+ .byte 0x1
+ .2byte 0x1ad
+ .uleb128 0x3c
+ .4byte 0x1b1c
+ .4byte .LLST36
+ .uleb128 0x3c
+ .4byte 0x1b10
+ .4byte .LLST37
+ .uleb128 0x3c
+ .4byte 0x1b05
+ .4byte .LLST38
+ .uleb128 0x3c
+ .4byte 0x1af9
+ .4byte .LLST39
+ .uleb128 0x4b
+ .8byte .LBB95
+ .8byte .LBE95-.LBB95
+ .uleb128 0x3e
+ .4byte 0x1b28
+ .uleb128 0x3e
+ .4byte 0x1b34
+ .uleb128 0x3b
+ .4byte 0x1b40
+ .4byte .LLST40
+ .uleb128 0x3b
+ .4byte 0x1b4c
+ .4byte .LLST41
+ .uleb128 0x3f
+ .4byte 0x2062
+ .8byte .LBB96
+ .8byte .LBE96-.LBB96
+ .byte 0x1
+ .2byte 0x179
+ .4byte 0x1ac5
+ .uleb128 0x49
+ .4byte 0x2072
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL99
+ .4byte 0x21f4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x87
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x35
+ .4byte .LASF403
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1b59
+ .uleb128 0x4c
+ .string "cid"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x4c
+ .string "id"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0x94
+ .uleb128 0x4c
+ .string "tid"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x4d
+ .4byte .LASF385
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x36
+ .4byte .LASF404
+ .byte 0x1
+ .2byte 0x174
+ .4byte 0x8d
+ .uleb128 0x36
+ .4byte .LASF405
+ .byte 0x1
+ .2byte 0x175
+ .4byte 0x54
+ .uleb128 0x43
+ .string "ret"
+ .byte 0x1
+ .2byte 0x176
+ .4byte 0x54
+ .uleb128 0x43
+ .string "run"
+ .byte 0x1
+ .2byte 0x177
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF407
+ .byte 0x1
+ .2byte 0x16d
+ .4byte 0x54
+ .8byte .LFB230
+ .8byte .LFE230-.LFB230
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1c3c
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x16d
+ .4byte 0xa3
+ .4byte .LLST28
+ .uleb128 0x48
+ .4byte 0x1c3c
+ .8byte .LBB78
+ .4byte .Ldebug_ranges0+0x100
+ .byte 0x1
+ .2byte 0x16f
+ .uleb128 0x4e
+ .4byte 0x1c59
+ .byte 0
+ .uleb128 0x3c
+ .4byte 0x1c4d
+ .4byte .LLST29
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x100
+ .uleb128 0x3e
+ .4byte 0x1c65
+ .uleb128 0x3f
+ .4byte 0x2149
+ .8byte .LBB80
+ .8byte .LBE80-.LBB80
+ .byte 0x1
+ .2byte 0x164
+ .4byte 0x1c0c
+ .uleb128 0x3c
+ .4byte 0x2155
+ .4byte .LLST30
+ .uleb128 0x32
+ .8byte .LVL86
+ .4byte 0x24f6
+ .4byte 0x1bf6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL87
+ .4byte 0x24f6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL84
+ .4byte 0x1e3e
+ .4byte 0x1c24
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x40
+ .8byte .LVL89
+ .4byte 0x1e3e
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x35
+ .4byte .LASF408
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1c70
+ .uleb128 0x4c
+ .string "tid"
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0xa3
+ .uleb128 0x4d
+ .4byte .LASF409
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0xa3
+ .uleb128 0x43
+ .string "i"
+ .byte 0x1
+ .2byte 0x161
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x35
+ .4byte .LASF410
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1cdf
+ .uleb128 0x4c
+ .string "cid"
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x4c
+ .string "tid"
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x4d
+ .4byte .LASF385
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x36
+ .4byte .LASF405
+ .byte 0x1
+ .2byte 0x13a
+ .4byte 0x54
+ .uleb128 0x43
+ .string "us"
+ .byte 0x1
+ .2byte 0x13b
+ .4byte 0x54
+ .uleb128 0x43
+ .string "i"
+ .byte 0x1
+ .2byte 0x13c
+ .4byte 0x54
+ .uleb128 0x36
+ .4byte .LASF411
+ .byte 0x1
+ .2byte 0x13c
+ .4byte 0x54
+ .uleb128 0x36
+ .4byte .LASF412
+ .byte 0x1
+ .2byte 0x13d
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x37
+ .4byte .LASF413
+ .byte 0x1
+ .2byte 0x121
+ .8byte .LFB227
+ .8byte .LFE227-.LFB227
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1e3e
+ .uleb128 0x2f
+ .4byte .LASF388
+ .byte 0x1
+ .2byte 0x123
+ .4byte 0x19b6
+ .4byte .LLST8
+ .uleb128 0x47
+ .string "cid"
+ .byte 0x1
+ .2byte 0x124
+ .4byte 0x54
+ .4byte .LLST9
+ .uleb128 0x47
+ .string "i"
+ .byte 0x1
+ .2byte 0x124
+ .4byte 0x54
+ .4byte .LLST10
+ .uleb128 0x32
+ .8byte .LVL26
+ .4byte 0x24d4
+ .4byte 0x1d4a
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC2
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL29
+ .4byte 0x24d4
+ .4byte 0x1d68
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x88
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL30
+ .4byte 0x24d4
+ .4byte 0x1d87
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC4
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL31
+ .4byte 0x24d4
+ .4byte 0x1da6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC5
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL32
+ .4byte 0x24d4
+ .4byte 0x1dc5
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC6
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL33
+ .4byte 0x24d4
+ .4byte 0x1de4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC7
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL34
+ .4byte 0x24d4
+ .4byte 0x1e03
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC8
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL35
+ .4byte 0x24d4
+ .4byte 0x1e22
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC9
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL36
+ .4byte 0x24d4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC10
+ .byte 0
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF414
+ .byte 0x1
+ .2byte 0x104
+ .4byte 0x54
+ .8byte .LFB226
+ .8byte .LFE226-.LFB226
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1ed7
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x104
+ .4byte 0xa3
+ .4byte .LLST5
+ .uleb128 0x43
+ .string "cid"
+ .byte 0x1
+ .2byte 0x106
+ .4byte 0x54
+ .uleb128 0x47
+ .string "i"
+ .byte 0x1
+ .2byte 0x106
+ .4byte 0x54
+ .4byte .LLST6
+ .uleb128 0x47
+ .string "ptr"
+ .byte 0x1
+ .2byte 0x107
+ .4byte 0x1ed7
+ .4byte .LLST7
+ .uleb128 0x3f
+ .4byte 0x2062
+ .8byte .LBB40
+ .8byte .LBE40-.LBB40
+ .byte 0x1
+ .2byte 0x109
+ .4byte 0x1ebc
+ .uleb128 0x49
+ .4byte 0x2072
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL23
+ .4byte 0x2549
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xa3
+ .uleb128 0x4f
+ .4byte .LASF450
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0x54
+ .8byte .LFB225
+ .8byte .LFE225-.LFB225
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1faa
+ .uleb128 0x50
+ .string "cid"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST0
+ .uleb128 0x50
+ .string "tid"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST1
+ .uleb128 0x50
+ .string "st"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST2
+ .uleb128 0x51
+ .4byte .LASF31
+ .byte 0x1
+ .byte 0xe4
+ .4byte 0xef
+ .uleb128 0x2c
+ .string "ptr"
+ .byte 0x1
+ .byte 0xe5
+ .4byte 0x1ed7
+ .uleb128 0x2c
+ .string "id"
+ .byte 0x1
+ .byte 0xe6
+ .4byte 0x54
+ .uleb128 0x52
+ .4byte 0x2062
+ .8byte .LBB30
+ .8byte .LBE30-.LBB30
+ .byte 0x1
+ .byte 0xe8
+ .4byte 0x1f6b
+ .uleb128 0x49
+ .4byte 0x2072
+ .byte 0
+ .uleb128 0x53
+ .4byte 0x1ff7
+ .8byte .LBB32
+ .4byte .Ldebug_ranges0+0
+ .byte 0x1
+ .byte 0xeb
+ .4byte 0x1f9c
+ .uleb128 0x49
+ .4byte 0x2012
+ .uleb128 0x49
+ .4byte 0x2007
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0
+ .uleb128 0x3b
+ .4byte 0x201d
+ .4byte .LLST3
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL8
+ .4byte 0x2555
+ .byte 0
+ .uleb128 0x54
+ .4byte .LASF415
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1ff1
+ .uleb128 0x55
+ .string "cid"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x55
+ .string "tid"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x55
+ .string "ret"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "ptr"
+ .byte 0x1
+ .byte 0xd1
+ .4byte 0x1ff1
+ .uleb128 0x2c
+ .string "id"
+ .byte 0x1
+ .byte 0xd2
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x54
+ .uleb128 0x54
+ .4byte .LASF416
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x2027
+ .uleb128 0x55
+ .string "cid"
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0xa3
+ .uleb128 0x55
+ .string "tid"
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "i"
+ .byte 0x1
+ .byte 0xc5
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x54
+ .4byte .LASF417
+ .byte 0x1
+ .byte 0x9d
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x2062
+ .uleb128 0x56
+ .4byte .LASF398
+ .byte 0x1
+ .byte 0x9d
+ .4byte 0x1367
+ .uleb128 0x2c
+ .string "cid"
+ .byte 0x1
+ .byte 0x9f
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "tid"
+ .byte 0x1
+ .byte 0xa0
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "i"
+ .byte 0x1
+ .byte 0xa1
+ .4byte 0x94
+ .byte 0
+ .uleb128 0x54
+ .4byte .LASF418
+ .byte 0x1
+ .byte 0x90
+ .4byte 0x54
+ .byte 0x3
+ .4byte 0x207e
+ .uleb128 0x55
+ .string "tid"
+ .byte 0x1
+ .byte 0x90
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x57
+ .4byte .LASF427
+ .byte 0x1
+ .byte 0x86
+ .byte 0x3
+ .uleb128 0x58
+ .4byte .LASF420
+ .byte 0x1
+ .byte 0x81
+ .byte 0x3
+ .4byte 0x209e
+ .uleb128 0x55
+ .string "ptr"
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF451
+ .byte 0x1
+ .byte 0x34
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x20ba
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x34
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x5a
+ .4byte .LASF422
+ .byte 0x1
+ .byte 0x33
+ .4byte 0x54
+ .4byte 0x20d5
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x33
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x5a
+ .4byte .LASF423
+ .byte 0x1
+ .byte 0x32
+ .4byte 0x54
+ .4byte 0x20f0
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x32
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x5a
+ .4byte .LASF424
+ .byte 0x1
+ .byte 0x31
+ .4byte 0x54
+ .4byte 0x210b
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x31
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x5a
+ .4byte .LASF425
+ .byte 0x1
+ .byte 0x30
+ .4byte 0x54
+ .4byte 0x2126
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x30
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x5a
+ .4byte .LASF426
+ .byte 0x1
+ .byte 0x2f
+ .4byte 0x54
+ .4byte 0x2141
+ .uleb128 0x56
+ .4byte .LASF421
+ .byte 0x1
+ .byte 0x2f
+ .4byte 0x1262
+ .byte 0
+ .uleb128 0x57
+ .4byte .LASF428
+ .byte 0x3
+ .byte 0xbf
+ .byte 0x3
+ .uleb128 0x58
+ .4byte .LASF429
+ .byte 0x2
+ .byte 0xd
+ .byte 0x3
+ .4byte 0x2161
+ .uleb128 0x56
+ .4byte .LASF430
+ .byte 0x2
+ .byte 0xd
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x5b
+ .4byte 0x14ef
+ .8byte .LFB238
+ .8byte .LFE238-.LFB238
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x21cf
+ .uleb128 0x3a
+ .4byte 0x1500
+ .uleb128 0x9
+ .byte 0x3
+ .8byte once.6657
+ .uleb128 0x3d
+ .8byte .LBB39
+ .8byte .LBE39-.LBB39
+ .4byte 0x21c1
+ .uleb128 0x3e
+ .4byte 0x217c
+ .uleb128 0x34
+ .8byte .LVL10
+ .4byte 0x24d4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC1
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL9
+ .4byte 0x2561
+ .byte 0
+ .uleb128 0x5b
+ .4byte 0x209e
+ .8byte .LFB218
+ .8byte .LFE218-.LFB218
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x21f4
+ .uleb128 0x3c
+ .4byte 0x20ae
+ .4byte .LLST4
+ .byte 0
+ .uleb128 0x5c
+ .4byte 0x1ae8
+ .8byte .LFB242
+ .8byte .LFE242-.LFB242
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x24b5
+ .uleb128 0x3c
+ .4byte 0x1af9
+ .4byte .LLST11
+ .uleb128 0x3c
+ .4byte 0x1b05
+ .4byte .LLST12
+ .uleb128 0x3c
+ .4byte 0x1b10
+ .4byte .LLST13
+ .uleb128 0x3c
+ .4byte 0x1b1c
+ .4byte .LLST14
+ .uleb128 0x3b
+ .4byte 0x1b28
+ .4byte .LLST15
+ .uleb128 0x3e
+ .4byte 0x1b34
+ .uleb128 0x3b
+ .4byte 0x1b40
+ .4byte .LLST16
+ .uleb128 0x3b
+ .4byte 0x1b4c
+ .4byte .LLST17
+ .uleb128 0x38
+ .4byte 0x1c70
+ .8byte .LBB52
+ .4byte .Ldebug_ranges0+0x30
+ .byte 0x1
+ .2byte 0x17f
+ .4byte 0x2308
+ .uleb128 0x3c
+ .4byte 0x1c81
+ .4byte .LLST18
+ .uleb128 0x3c
+ .4byte 0x1c8d
+ .4byte .LLST19
+ .uleb128 0x3c
+ .4byte 0x1c99
+ .4byte .LLST20
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x30
+ .uleb128 0x3b
+ .4byte 0x1ca5
+ .4byte .LLST21
+ .uleb128 0x5d
+ .4byte 0x1cb1
+ .byte 0x64
+ .uleb128 0x3e
+ .4byte 0x1cbc
+ .uleb128 0x3b
+ .4byte 0x1cc6
+ .4byte .LLST22
+ .uleb128 0x3b
+ .4byte 0x1cd2
+ .4byte .LLST23
+ .uleb128 0x32
+ .8byte .LVL43
+ .4byte 0x1e3e
+ .4byte 0x22c9
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL44
+ .4byte 0x1e3e
+ .4byte 0x22e1
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL53
+ .4byte 0x24f6
+ .4byte 0x22f9
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x64
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL56
+ .4byte 0x1cdf
+ .byte 0
+ .byte 0
+ .uleb128 0x38
+ .4byte 0x1faa
+ .8byte .LBB56
+ .4byte .Ldebug_ranges0+0x60
+ .byte 0x1
+ .2byte 0x19e
+ .4byte 0x23ab
+ .uleb128 0x3c
+ .4byte 0x1fd0
+ .4byte .LLST24
+ .uleb128 0x3c
+ .4byte 0x1fc5
+ .4byte .LLST25
+ .uleb128 0x3c
+ .4byte 0x1fba
+ .4byte .LLST26
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0x60
+ .uleb128 0x3e
+ .4byte 0x1fdb
+ .uleb128 0x3e
+ .4byte 0x1fe6
+ .uleb128 0x52
+ .4byte 0x2062
+ .8byte .LBB58
+ .8byte .LBE58-.LBB58
+ .byte 0x1
+ .byte 0xd4
+ .4byte 0x236b
+ .uleb128 0x49
+ .4byte 0x2072
+ .byte 0
+ .uleb128 0x53
+ .4byte 0x1ff7
+ .8byte .LBB60
+ .4byte .Ldebug_ranges0+0xd0
+ .byte 0x1
+ .byte 0xd7
+ .4byte 0x239c
+ .uleb128 0x49
+ .4byte 0x2012
+ .uleb128 0x49
+ .4byte 0x2007
+ .uleb128 0x39
+ .4byte .Ldebug_ranges0+0xd0
+ .uleb128 0x3b
+ .4byte 0x201d
+ .4byte .LLST27
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .8byte .LVL81
+ .4byte 0x2555
+ .byte 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL50
+ .4byte 0x24d4
+ .4byte 0x23d6
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC12
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL51
+ .4byte 0x1edd
+ .4byte 0x23fd
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x55555555
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL59
+ .4byte 0x24d4
+ .4byte 0x2428
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC13
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL60
+ .4byte 0x256c
+ .uleb128 0x32
+ .8byte .LVL63
+ .4byte 0x1edd
+ .4byte 0x245c
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x11111111
+ .byte 0
+ .uleb128 0x32
+ .8byte .LVL67
+ .4byte 0x1edd
+ .4byte 0x247a
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x31
+ .8byte .LVL68
+ .4byte 0x256c
+ .uleb128 0x34
+ .8byte .LVL70
+ .4byte 0x24d4
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC11
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x33
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .4byte .LASF431
+ .4byte .LASF431
+ .byte 0x1e
+ .byte 0x8e
+ .uleb128 0x5f
+ .4byte .LASF432
+ .4byte .LASF432
+ .byte 0x4
+ .byte 0x6b
+ .uleb128 0x60
+ .4byte .LASF452
+ .4byte .LASF452
+ .uleb128 0x5f
+ .4byte .LASF433
+ .4byte .LASF433
+ .byte 0x1f
+ .byte 0x13
+ .uleb128 0x5f
+ .4byte .LASF434
+ .4byte .LASF434
+ .byte 0x8
+ .byte 0x66
+ .uleb128 0x61
+ .4byte .LASF435
+ .4byte .LASF435
+ .byte 0x4
+ .2byte 0x260
+ .uleb128 0x5f
+ .4byte .LASF436
+ .4byte .LASF436
+ .byte 0x2
+ .byte 0xb
+ .uleb128 0x61
+ .4byte .LASF437
+ .4byte .LASF437
+ .byte 0x4
+ .2byte 0x1f3
+ .uleb128 0x61
+ .4byte .LASF438
+ .4byte .LASF438
+ .byte 0x4
+ .2byte 0x248
+ .uleb128 0x61
+ .4byte .LASF439
+ .4byte .LASF439
+ .byte 0x4
+ .2byte 0x1f1
+ .uleb128 0x61
+ .4byte .LASF440
+ .4byte .LASF440
+ .byte 0x4
+ .2byte 0x264
+ .uleb128 0x61
+ .4byte .LASF441
+ .4byte .LASF441
+ .byte 0x4
+ .2byte 0x1f4
+ .uleb128 0x61
+ .4byte .LASF442
+ .4byte .LASF442
+ .byte 0x4
+ .2byte 0x263
+ .uleb128 0x61
+ .4byte .LASF443
+ .4byte .LASF443
+ .byte 0x4
+ .2byte 0x262
+ .uleb128 0x61
+ .4byte .LASF444
+ .4byte .LASF444
+ .byte 0x4
+ .2byte 0x261
+ .uleb128 0x5f
+ .4byte .LASF445
+ .4byte .LASF445
+ .byte 0x1c
+ .byte 0x50
+ .uleb128 0x61
+ .4byte .LASF446
+ .4byte .LASF446
+ .byte 0x4
+ .2byte 0x276
+ .byte 0
+ .section .debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+ .uleb128 0x1
+ .uleb128 0x11
+ .byte 0x1
+ .uleb128 0x25
+ .uleb128 0xe
+ .uleb128 0x13
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1b
+ .uleb128 0xe
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x10
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x2
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x4
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x5
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0x8
+ .byte 0
+ .byte 0
+ .uleb128 0x6
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x7
+ .uleb128 0x26
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x9
+ .uleb128 0x35
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0x1
+ .byte 0x1
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xc
+ .uleb128 0x21
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0xd
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0xe
+ .uleb128 0x13
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0xf
+ .uleb128 0x26
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x10
+ .uleb128 0x21
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2f
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x12
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
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+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x55
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x56
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x57
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x58
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x59
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5a
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5b
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5c
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2116
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5d
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .uleb128 0x4109
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x2115
+ .uleb128 0x19
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x60
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x61
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .byte 0
+ .section .debug_loc,"",@progbits
+.Ldebug_loc0:
+.LLST61:
+ .8byte .LVL153
+ .8byte .LVL154
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL154
+ .8byte .LVL172
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL172
+ .8byte .LVL173
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL173
+ .8byte .LFE239
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST62:
+ .8byte .LVL156
+ .8byte .LVL159
+ .2byte 0x2
+ .byte 0x35
+ .byte 0x9f
+ .8byte .LVL160
+ .8byte .LVL161
+ .2byte 0x2
+ .byte 0x35
+ .byte 0x9f
+ .8byte .LVL166
+ .8byte .LVL172
+ .2byte 0x2
+ .byte 0x35
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST53:
+ .8byte .LVL128
+ .8byte .LVL129
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL129
+ .8byte .LVL145
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL145
+ .8byte .LVL146
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL146
+ .8byte .LVL150
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL150
+ .8byte .LVL151
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL151
+ .8byte .LFE237
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST54:
+ .8byte .LVL133
+ .8byte .LVL134
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST55:
+ .8byte .LVL138
+ .8byte .LVL139
+ .2byte 0x7
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x53
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x93
+ .uleb128 0x10
+ .8byte .LVL139
+ .8byte .LVL143
+ .2byte 0xe
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x53
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte .LVL143
+ .8byte .LVL144
+ .2byte 0xf
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x71
+ .sleb128 20
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte .LVL144
+ .8byte .LVL145
+ .2byte 0xb
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte 0
+ .8byte 0
+.LLST56:
+ .8byte .LVL139
+ .8byte .LVL141
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL141
+ .8byte .LVL142
+ .2byte 0x2
+ .byte 0x70
+ .sleb128 0
+ .8byte 0
+ .8byte 0
+.LLST57:
+ .8byte .LVL139
+ .8byte .LVL143
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL143
+ .8byte .LVL144
+ .2byte 0x2
+ .byte 0x71
+ .sleb128 20
+ .8byte 0
+ .8byte 0
+.LLST58:
+ .8byte .LVL140
+ .8byte .LVL141
+ .2byte 0x11
+ .byte 0x71
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200148
+ .8byte .LVL141
+ .8byte .LVL142
+ .2byte 0x13
+ .byte 0x70
+ .sleb128 0
+ .byte 0x94
+ .byte 0x4
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200148
+ .8byte 0
+ .8byte 0
+.LLST59:
+ .8byte .LVL136
+ .8byte .LVL137
+ .2byte 0x6
+ .byte 0x9e
+ .uleb128 0x4
+ .4byte 0xdeadbeaf
+ .8byte 0
+ .8byte 0
+.LLST60:
+ .8byte .LVL149
+ .8byte .LVL150
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST51:
+ .8byte .LVL112
+ .8byte .LVL113
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL113
+ .8byte .LFE234
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST52:
+ .8byte .LVL114
+ .8byte .LVL115
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST42:
+ .8byte .LVL101
+ .8byte .LVL102
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL102
+ .8byte .LVL104
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL104
+ .8byte .LVL107
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL107
+ .8byte .LFE233
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST43:
+ .8byte .LVL103
+ .8byte .LVL104
+ .2byte 0x12
+ .byte 0x86
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL104
+ .8byte .LVL107
+ .2byte 0x12
+ .byte 0x87
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL107
+ .8byte .LVL108
+ .2byte 0x13
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL108
+ .8byte .LFE233
+ .2byte 0x12
+ .byte 0x87
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST44:
+ .8byte .LVL103
+ .8byte .LVL105
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL105
+ .8byte .LVL106
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL108
+ .8byte .LFE233
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST45:
+ .8byte .LVL109
+ .8byte .LVL110-1
+ .2byte 0x2
+ .byte 0x83
+ .sleb128 16
+ .8byte 0
+ .8byte 0
+.LLST46:
+ .8byte .LVL109
+ .8byte .LVL110-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte 0
+ .8byte 0
+.LLST47:
+ .8byte .LVL109
+ .8byte .LVL110
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST48:
+ .8byte .LVL109
+ .8byte .LVL110
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST49:
+ .8byte .LVL109
+ .8byte .LVL110
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST50:
+ .8byte .LVL109
+ .8byte .LVL110
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST31:
+ .8byte .LVL90
+ .8byte .LVL93
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL93
+ .8byte .LVL94
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL94
+ .8byte .LVL96
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL96
+ .8byte .LFE232
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST32:
+ .8byte .LVL90
+ .8byte .LVL95
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL95
+ .8byte .LVL96
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL97
+ .8byte .LFE232
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST33:
+ .8byte .LVL90
+ .8byte .LVL92
+ .2byte 0x12
+ .byte 0x70
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL92
+ .8byte .LVL94
+ .2byte 0xc
+ .byte 0x89
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL94
+ .8byte .LVL96
+ .2byte 0xc
+ .byte 0x86
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x13
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL97
+ .8byte .LFE232
+ .2byte 0xc
+ .byte 0x86
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST34:
+ .8byte .LVL95
+ .8byte .LVL96
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL97
+ .8byte .LFE232
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST35:
+ .8byte .LVL90
+ .8byte .LVL91
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST36:
+ .8byte .LVL98
+ .8byte .LVL99-1
+ .2byte 0x2
+ .byte 0x83
+ .sleb128 16
+ .8byte 0
+ .8byte 0
+.LLST37:
+ .8byte .LVL98
+ .8byte .LVL99
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST38:
+ .8byte .LVL98
+ .8byte .LVL99
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST39:
+ .8byte .LVL98
+ .8byte .LVL99
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST40:
+ .8byte .LVL98
+ .8byte .LVL99
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST41:
+ .8byte .LVL98
+ .8byte .LVL99
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST28:
+ .8byte .LVL82
+ .8byte .LVL83
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL83
+ .8byte .LVL88
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL88
+ .8byte .LVL89-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL89-1
+ .8byte .LFE230
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST29:
+ .8byte .LVL83
+ .8byte .LVL88
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL88
+ .8byte .LVL89-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL89-1
+ .8byte .LFE230
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST30:
+ .8byte .LVL85
+ .8byte .LVL86
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte .LVL86
+ .8byte .LVL87
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST8:
+ .8byte .LVL27
+ .8byte .LVL28
+ .2byte 0x1e
+ .byte 0x86
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0x8
+ .byte 0x28
+ .byte 0x1e
+ .byte 0x85
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x22
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL28
+ .8byte .LVL36
+ .2byte 0x1e
+ .byte 0x86
+ .sleb128 -1
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0x8
+ .byte 0x28
+ .byte 0x1e
+ .byte 0x85
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x22
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST9:
+ .8byte .LVL26
+ .8byte .LVL38
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST10:
+ .8byte .LVL27
+ .8byte .LVL28
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL28
+ .8byte .LVL36
+ .2byte 0x3
+ .byte 0x86
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL36
+ .8byte .LVL38
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST5:
+ .8byte .LVL13
+ .8byte .LVL14
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL14
+ .8byte .LVL19
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL19
+ .8byte .LVL21
+ .2byte 0x5
+ .byte 0x8b
+ .sleb128 65536
+ .byte 0x9f
+ .8byte .LVL21
+ .8byte .LVL22
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL22
+ .8byte .LVL24
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL24
+ .8byte .LVL25
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL25
+ .8byte .LFE226
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST6:
+ .8byte .LVL15
+ .8byte .LVL20
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL22
+ .8byte .LVL24
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST7:
+ .8byte .LVL22
+ .8byte .LVL24
+ .2byte 0x3
+ .byte 0x84
+ .sleb128 -4
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST0:
+ .8byte .LVL0
+ .8byte .LVL1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL1
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x55
+ .8byte .LVL3
+ .8byte .LFE225
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST1:
+ .8byte .LVL0
+ .8byte .LVL7
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL7
+ .8byte .LFE225
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST2:
+ .8byte .LVL0
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL8-1
+ .8byte .LFE225
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST3:
+ .8byte .LVL2
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL4
+ .8byte .LVL6
+ .2byte 0x1
+ .byte 0x53
+ .8byte 0
+ .8byte 0
+.LLST4:
+ .8byte .LVL11
+ .8byte .LVL12
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL12
+ .8byte .LFE218
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST11:
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL41
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL71
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL73
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST12:
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL41
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL69
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST13:
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL41
+ .8byte .LVL74
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL74
+ .8byte .LVL76
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL76
+ .8byte .LVL79
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL79
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST14:
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL41
+ .8byte .LVL49
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL49
+ .8byte .LVL52
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL52
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL57
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST15:
+ .8byte .LVL61
+ .8byte .LVL62
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL62
+ .8byte .LVL70
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST16:
+ .8byte .LVL65
+ .8byte .LVL66
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL66
+ .8byte .LVL75
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL76
+ .8byte .LVL80
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL80
+ .8byte .LVL81-1
+ .2byte 0x2
+ .byte 0x72
+ .sleb128 32
+ .8byte 0
+ .8byte 0
+.LLST17:
+ .8byte .LVL48
+ .8byte .LVL52
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL58
+ .8byte .LVL70
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST18:
+ .8byte .LVL40
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL41
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL71
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL73
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST19:
+ .8byte .LVL40
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL41
+ .8byte .LVL74
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL74
+ .8byte .LVL76
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL76
+ .8byte .LVL79
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL79
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST20:
+ .8byte .LVL40
+ .8byte .LVL41
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL41
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL52
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST21:
+ .8byte .LVL40
+ .8byte .LVL41
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL41
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL52
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST22:
+ .8byte .LVL41
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL52
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST23:
+ .8byte .LVL42
+ .8byte .LVL45
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL52
+ .8byte .LVL53
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL53
+ .8byte .LVL54
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e21
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL54
+ .8byte .LVL55
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL55
+ .8byte .LVL57
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST24:
+ .8byte .LVL70
+ .8byte .LVL75
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL76
+ .8byte .LVL80
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL80
+ .8byte .LVL81-1
+ .2byte 0x2
+ .byte 0x72
+ .sleb128 32
+ .8byte 0
+ .8byte 0
+.LLST25:
+ .8byte .LVL70
+ .8byte .LVL74
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL74
+ .8byte .LVL76
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL76
+ .8byte .LVL79
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL79
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST26:
+ .8byte .LVL70
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL71
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL73
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST27:
+ .8byte .LVL72
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL76
+ .8byte .LVL78
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+ .section .debug_aranges,"",@progbits
+ .4byte 0xec
+ .2byte 0x2
+ .4byte .Ldebug_info0
+ .byte 0x8
+ .byte 0
+ .2byte 0
+ .2byte 0
+ .8byte .LFB225
+ .8byte .LFE225-.LFB225
+ .8byte .LFB238
+ .8byte .LFE238-.LFB238
+ .8byte .LFB218
+ .8byte .LFE218-.LFB218
+ .8byte .LFB226
+ .8byte .LFE226-.LFB226
+ .8byte .LFB227
+ .8byte .LFE227-.LFB227
+ .8byte .LFB242
+ .8byte .LFE242-.LFB242
+ .8byte .LFB230
+ .8byte .LFE230-.LFB230
+ .8byte .LFB232
+ .8byte .LFE232-.LFB232
+ .8byte .LFB233
+ .8byte .LFE233-.LFB233
+ .8byte .LFB234
+ .8byte .LFE234-.LFB234
+ .8byte .LFB236
+ .8byte .LFE236-.LFB236
+ .8byte .LFB237
+ .8byte .LFE237-.LFB237
+ .8byte .LFB239
+ .8byte .LFE239-.LFB239
+ .8byte 0
+ .8byte 0
+ .section .debug_ranges,"",@progbits
+.Ldebug_ranges0:
+ .8byte .LBB32
+ .8byte .LBE32
+ .8byte .LBB35
+ .8byte .LBE35
+ .8byte 0
+ .8byte 0
+ .8byte .LBB52
+ .8byte .LBE52
+ .8byte .LBB55
+ .8byte .LBE55
+ .8byte 0
+ .8byte 0
+ .8byte .LBB56
+ .8byte .LBE56
+ .8byte .LBB69
+ .8byte .LBE69
+ .8byte .LBB70
+ .8byte .LBE70
+ .8byte .LBB71
+ .8byte .LBE71
+ .8byte .LBB72
+ .8byte .LBE72
+ .8byte .LBB73
+ .8byte .LBE73
+ .8byte 0
+ .8byte 0
+ .8byte .LBB60
+ .8byte .LBE60
+ .8byte .LBB63
+ .8byte .LBE63
+ .8byte 0
+ .8byte 0
+ .8byte .LBB78
+ .8byte .LBE78
+ .8byte .LBB83
+ .8byte .LBE83
+ .8byte 0
+ .8byte 0
+ .8byte .LBB90
+ .8byte .LBE90
+ .8byte .LBB93
+ .8byte .LBE93
+ .8byte 0
+ .8byte 0
+ .8byte .LBB102
+ .8byte .LBE102
+ .8byte .LBB109
+ .8byte .LBE109
+ .8byte 0
+ .8byte 0
+ .8byte .LBB104
+ .8byte .LBE104
+ .8byte .LBB107
+ .8byte .LBE107
+ .8byte 0
+ .8byte 0
+ .8byte .LBB124
+ .8byte .LBE124
+ .8byte .LBB135
+ .8byte .LBE135
+ .8byte 0
+ .8byte 0
+ .8byte .LBB126
+ .8byte .LBE126
+ .8byte .LBB130
+ .8byte .LBE130
+ .8byte .LBB133
+ .8byte .LBE133
+ .8byte 0
+ .8byte 0
+ .8byte .LFB225
+ .8byte .LFE225
+ .8byte .LFB238
+ .8byte .LFE238
+ .8byte .LFB218
+ .8byte .LFE218
+ .8byte .LFB226
+ .8byte .LFE226
+ .8byte .LFB227
+ .8byte .LFE227
+ .8byte .LFB242
+ .8byte .LFE242
+ .8byte .LFB230
+ .8byte .LFE230
+ .8byte .LFB232
+ .8byte .LFE232
+ .8byte .LFB233
+ .8byte .LFE233
+ .8byte .LFB234
+ .8byte .LFE234
+ .8byte .LFB236
+ .8byte .LFE236
+ .8byte .LFB237
+ .8byte .LFE237
+ .8byte .LFB239
+ .8byte .LFE239
+ .8byte 0
+ .8byte 0
+ .section .debug_line,"",@progbits
+.Ldebug_line0:
+ .section .debug_str,"MS",@progbits,1
+.LASF83:
+ .string "off_mem_rsvmap"
+.LASF166:
+ .string "UCLASS_I2C_EEPROM"
+.LASF298:
+ .string "jt_funcs"
+.LASF171:
+ .string "UCLASS_IRQ"
+.LASF133:
+ .string "initrd_start"
+.LASF165:
+ .string "UCLASS_I2C"
+.LASF13:
+ .string "sizetype"
+.LASF312:
+ .string "net_hostname"
+.LASF36:
+ .string "start"
+.LASF206:
+ .string "UCLASS_SPI"
+.LASF169:
+ .string "UCLASS_I2S"
+.LASF334:
+ .string "NETLOOP_RESTART"
+.LASF167:
+ .string "UCLASS_I2C_GENERIC"
+.LASF179:
+ .string "UCLASS_MOD_EXP"
+.LASF230:
+ .string "UCLASS_IO_DOMAIN"
+.LASF251:
+ .string "using_pre_serial"
+.LASF200:
+ .string "UCLASS_RKNAND"
+.LASF142:
+ .string "UCLASS_DEMO"
+.LASF386:
+ .string "rip_fail"
+.LASF91:
+ .string "ih_magic"
+.LASF29:
+ .string "list_head"
+.LASF292:
+ .string "pm_ctx_phys"
+.LASF146:
+ .string "UCLASS_TEST_PROBE"
+.LASF226:
+ .string "UCLASS_KEY"
+.LASF64:
+ .string "bi_intfreq"
+.LASF11:
+ .string "phys_addr_t"
+.LASF221:
+ .string "UCLASS_VIDEO_BRIDGE"
+.LASF291:
+ .string "video_bottom"
+.LASF5:
+ .string "__u8"
+.LASF390:
+ .string "task_list"
+.LASF333:
+ .string "NETLOOP_CONTINUE"
+.LASF209:
+ .string "UCLASS_SPI_GENERIC"
+.LASF286:
+ .string "malloc_base"
+.LASF382:
+ .string "tid_name"
+.LASF40:
+ .string "flash_info_t"
+.LASF184:
+ .string "UCLASS_PANEL"
+.LASF108:
+ .string "comp"
+.LASF103:
+ .string "image_header_t"
+.LASF138:
+ .string "state"
+.LASF428:
+ .string "disable_serror"
+.LASF159:
+ .string "UCLASS_CROS_EC"
+.LASF360:
+ .string "BOOT_MODE_QUIESCENT"
+.LASF58:
+ .string "bi_dsp_freq"
+.LASF105:
+ .string "image_start"
+.LASF350:
+ .string "BOOT_MODE_NORMAL"
+.LASF440:
+ .string "invalidate_icache_all"
+.LASF438:
+ .string "disable_interrupts"
+.LASF144:
+ .string "UCLASS_TEST_FDT"
+.LASF49:
+ .string "bd_info"
+.LASF331:
+ .string "uclass_id"
+.LASF95:
+ .string "ih_load"
+.LASF215:
+ .string "UCLASS_UFS"
+.LASF302:
+ .string "__dtb_dt_spl_begin"
+.LASF376:
+ .string "TASK_LOAD_UBOOT"
+.LASF7:
+ .string "__u32"
+.LASF149:
+ .string "UCLASS_PCI_EMUL"
+.LASF449:
+ .string "/home4/cjh/uboot-nextdev-v3"
+.LASF289:
+ .string "cur_serial_dev"
+.LASF351:
+ .string "BOOT_MODE_RECOVERY"
+.LASF318:
+ .string "net_tx_packet"
+.LASF225:
+ .string "UCLASS_FG"
+.LASF317:
+ .string "net_server_ip"
+.LASF325:
+ .string "net_native_vlan"
+.LASF265:
+ .string "ram_top_ext_size"
+.LASF223:
+ .string "UCLASS_VIDEO_CRTC"
+.LASF158:
+ .string "UCLASS_CODEC"
+.LASF447:
+ .ascii "GNU C11 6.3.1 20170404 -ms"
+ .string "trict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -fno-pic -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
+.LASF283:
+ .string "env_buf"
+.LASF20:
+ .string "errno"
+.LASF15:
+ .string "long int"
+.LASF53:
+ .string "bi_flashsize"
+.LASF339:
+ .string "__bss_end"
+.LASF189:
+ .string "UCLASS_PHY"
+.LASF76:
+ .string "IRQ_STACK_START_IN"
+.LASF87:
+ .string "size_dt_strings"
+.LASF220:
+ .string "UCLASS_VIDEO"
+.LASF369:
+ .string "EVT_CRYPTO"
+.LASF266:
+ .string "relocaddr"
+.LASF406:
+ .string "mpb_post"
+.LASF448:
+ .string "common/mp_boot.c"
+.LASF328:
+ .string "net_boot_file_size"
+.LASF387:
+ .string "cpu_core"
+.LASF432:
+ .string "run_command"
+.LASF97:
+ .string "ih_dcrc"
+.LASF63:
+ .string "bi_ethspeed"
+.LASF141:
+ .string "UCLASS_ROOT"
+.LASF26:
+ .string "ide_bus_offset"
+.LASF374:
+ .string "TASK_INIT_DISPLAY"
+.LASF315:
+ .string "net_server_ethaddr"
+.LASF66:
+ .string "bi_arch_number"
+.LASF3:
+ .string "signed char"
+.LASF172:
+ .string "UCLASS_KEYBOARD"
+.LASF18:
+ .string "uint8_t"
+.LASF38:
+ .string "udevice"
+.LASF436:
+ .string "udelay"
+.LASF99:
+ .string "ih_arch"
+.LASF80:
+ .string "totalsize"
+.LASF92:
+ .string "ih_hcrc"
+.LASF268:
+ .string "mon_len"
+.LASF107:
+ .string "load"
+.LASF214:
+ .string "UCLASS_TPM"
+.LASF43:
+ .string "lmb_property"
+.LASF85:
+ .string "last_comp_version"
+.LASF0:
+ .string "unsigned char"
+.LASF140:
+ .string "images"
+.LASF341:
+ .string "priv"
+.LASF229:
+ .string "UCLASS_DVFS"
+.LASF59:
+ .string "bi_ddr_freq"
+.LASF419:
+ .string "mpb_initial"
+.LASF173:
+ .string "UCLASS_LED"
+.LASF94:
+ .string "ih_size"
+.LASF445:
+ .string "rockchip_get_boot_mode"
+.LASF437:
+ .string "dcache_enable"
+.LASF203:
+ .string "UCLASS_SCMI_AGENT"
+.LASF233:
+ .string "UCLASS_MDIO"
+.LASF22:
+ .string "_Bool"
+.LASF337:
+ .string "net_state"
+.LASF168:
+ .string "UCLASS_I2C_MUX"
+.LASF14:
+ .string "char"
+.LASF24:
+ .string "_binary_u_boot_bin_start"
+.LASF219:
+ .string "UCLASS_USB_GADGET_GENERIC"
+.LASF335:
+ .string "NETLOOP_SUCCESS"
+.LASF433:
+ .string "printf"
+.LASF385:
+ .string "ptid_mask"
+.LASF332:
+ .string "net_loop_state"
+.LASF247:
+ .string "tlb_size"
+.LASF274:
+ .string "dm_root_f"
+.LASF157:
+ .string "UCLASS_AMP"
+.LASF195:
+ .string "UCLASS_PWRSEQ"
+.LASF123:
+ .string "fit_hdr_fdt"
+.LASF326:
+ .string "net_restart_wrap"
+.LASF314:
+ .string "net_ethaddr"
+.LASF256:
+ .string "flags"
+.LASF100:
+ .string "ih_type"
+.LASF368:
+ .string "EVT_BOOT_SIZE"
+.LASF81:
+ .string "off_dt_struct"
+.LASF429:
+ .string "mdelay"
+.LASF54:
+ .string "bi_flashoffset"
+.LASF327:
+ .string "net_boot_file_name"
+.LASF143:
+ .string "UCLASS_TEST"
+.LASF413:
+ .string "mpb_task_dump"
+.LASF93:
+ .string "ih_time"
+.LASF258:
+ .string "bus_clk"
+.LASF196:
+ .string "UCLASS_RAM"
+.LASF162:
+ .string "UCLASS_ETH"
+.LASF377:
+ .string "TASK_LOAD_FIT"
+.LASF104:
+ .string "image_info"
+.LASF110:
+ .string "arch"
+.LASF260:
+ .string "mem_clk"
+.LASF257:
+ .string "cpu_clk"
+.LASF32:
+ .string "select_hwpart"
+.LASF319:
+ .string "net_rx_packets"
+.LASF75:
+ .string "_datarelro_start_ofs"
+.LASF17:
+ .string "ulong"
+.LASF384:
+ .string "task_fn"
+.LASF96:
+ .string "ih_ep"
+.LASF45:
+ .string "lmb_region"
+.LASF388:
+ .string "task"
+.LASF408:
+ .string "mpb_task_wait_timeout_done"
+.LASF416:
+ .string "tid_to_task_index"
+.LASF118:
+ .string "fit_uname_os"
+.LASF60:
+ .string "bi_bootflags"
+.LASF316:
+ .string "net_ip"
+.LASF278:
+ .string "fdt_size"
+.LASF310:
+ .string "net_dns_server"
+.LASF338:
+ .string "__bss_start"
+.LASF330:
+ .string "net_ping_ip"
+.LASF47:
+ .string "memory"
+.LASF78:
+ .string "fdt_header"
+.LASF175:
+ .string "UCLASS_MAILBOX"
+.LASF343:
+ .string "filename"
+.LASF130:
+ .string "rd_end"
+.LASF269:
+ .string "irq_sp"
+.LASF135:
+ .string "cmdline_start"
+.LASF255:
+ .string "global_data"
+.LASF371:
+ .string "EVT_SIMPLE_BOOTM"
+.LASF379:
+ .string "TASK_HASH_ANDROID"
+.LASF204:
+ .string "UCLASS_SCSI"
+.LASF217:
+ .string "UCLASS_USB_DEV_GENERIC"
+.LASF176:
+ .string "UCLASS_MASS_STORAGE"
+.LASF1:
+ .string "long unsigned int"
+.LASF151:
+ .string "UCLASS_SIMPLE_BUS"
+.LASF299:
+ .string "gd_t"
+.LASF311:
+ .string "net_nis_domain"
+.LASF125:
+ .string "fit_noffset_fdt"
+.LASF370:
+ .string "EVT_LINUX"
+.LASF342:
+ .string "bl_len"
+.LASF446:
+ .string "get_ticks"
+.LASF336:
+ .string "NETLOOP_FAIL"
+.LASF224:
+ .string "UCLASS_WDT"
+.LASF245:
+ .string "timer_reset_value"
+.LASF270:
+ .string "start_addr_sp"
+.LASF55:
+ .string "bi_sramstart"
+.LASF25:
+ .string "_binary_u_boot_bin_end"
+.LASF271:
+ .string "reloc_off"
+.LASF86:
+ .string "boot_cpuid_phys"
+.LASF244:
+ .string "lastinc"
+.LASF248:
+ .string "tlb_fillptr"
+.LASF121:
+ .string "fit_uname_rd"
+.LASF210:
+ .string "UCLASS_SYSCON"
+.LASF116:
+ .string "fit_uname_cfg"
+.LASF205:
+ .string "UCLASS_SERIAL"
+.LASF324:
+ .string "net_our_vlan"
+.LASF294:
+ .string "serial"
+.LASF154:
+ .string "UCLASS_BLK"
+.LASF111:
+ .string "image_info_t"
+.LASF150:
+ .string "UCLASS_USB_EMUL"
+.LASF439:
+ .string "icache_disable"
+.LASF246:
+ .string "tlb_addr"
+.LASF354:
+ .string "BOOT_MODE_CHARGING"
+.LASF188:
+ .string "UCLASS_PCI_GENERIC"
+.LASF383:
+ .string "task_t"
+.LASF423:
+ .string "spl_load_android"
+.LASF404:
+ .string "ticks"
+.LASF106:
+ .string "image_len"
+.LASF375:
+ .string "TASK_LOAD_BASEPARAMETER"
+.LASF394:
+ .string "wait_evt"
+.LASF61:
+ .string "bi_ip_addr"
+.LASF409:
+ .string "timeout_ms"
+.LASF190:
+ .string "UCLASS_PINCONFIG"
+.LASF399:
+ .string "smp_entry"
+.LASF212:
+ .string "UCLASS_THERMAL"
+.LASF114:
+ .string "legacy_hdr_os_copy"
+.LASF367:
+ .string "EVT_BOOT_ADDR"
+.LASF9:
+ .string "long long int"
+.LASF277:
+ .string "new_fdt"
+.LASF21:
+ .string "___strtok"
+.LASF329:
+ .string "net_boot_file_expected_size_in_blocks"
+.LASF252:
+ .string "enable"
+.LASF411:
+ .string "ptid"
+.LASF183:
+ .string "UCLASS_NVME"
+.LASF249:
+ .string "tlb_emerg"
+.LASF112:
+ .string "bootm_headers"
+.LASF37:
+ .string "protect"
+.LASF216:
+ .string "UCLASS_USB"
+.LASF227:
+ .string "UCLASS_RC"
+.LASF414:
+ .string "mpb_task_is_done"
+.LASF284:
+ .string "timebase_h"
+.LASF285:
+ .string "timebase_l"
+.LASF160:
+ .string "UCLASS_DISPLAY"
+.LASF323:
+ .string "net_null_ethaddr"
+.LASF263:
+ .string "env_valid"
+.LASF228:
+ .string "UCLASS_CHARGE_DISPLAY"
+.LASF303:
+ .string "load_addr"
+.LASF117:
+ .string "fit_hdr_os"
+.LASF73:
+ .string "_datarelrolocal_start_ofs"
+.LASF412:
+ .string "timeout"
+.LASF361:
+ .string "BOOT_MODE_UNDEFINE"
+.LASF254:
+ .string "addr"
+.LASF344:
+ .string "read"
+.LASF355:
+ .string "BOOT_MODE_UMS"
+.LASF8:
+ .string "unsigned int"
+.LASF16:
+ .string "ushort"
+.LASF418:
+ .string "task_is_registered"
+.LASF281:
+ .string "ufdt_blob"
+.LASF426:
+ .string "spl_init_display"
+.LASF287:
+ .string "malloc_limit"
+.LASF417:
+ .string "mpb_task_register"
+.LASF192:
+ .string "UCLASS_PMIC"
+.LASF113:
+ .string "legacy_hdr_os"
+.LASF82:
+ .string "off_dt_strings"
+.LASF397:
+ .string "mpb_init_1"
+.LASF300:
+ .string "monitor_flash_len"
+.LASF177:
+ .string "UCLASS_MISC"
+.LASF51:
+ .string "bi_memsize"
+.LASF410:
+ .string "mpb_task_wait_parent"
+.LASF23:
+ .string "image_base"
+.LASF395:
+ .string "once"
+.LASF211:
+ .string "UCLASS_SYSRESET"
+.LASF164:
+ .string "UCLASS_FIRMWARE"
+.LASF443:
+ .string "invalidate_dcache_range"
+.LASF174:
+ .string "UCLASS_LPC"
+.LASF170:
+ .string "UCLASS_IDE"
+.LASF290:
+ .string "video_top"
+.LASF431:
+ .string "snprintf"
+.LASF280:
+ .string "of_root_f"
+.LASF139:
+ .string "bootm_headers_t"
+.LASF57:
+ .string "bi_arm_freq"
+.LASF198:
+ .string "UCLASS_REMOTEPROC"
+.LASF109:
+ .string "type"
+.LASF120:
+ .string "fit_hdr_rd"
+.LASF405:
+ .string "fail"
+.LASF262:
+ .string "env_addr"
+.LASF56:
+ .string "bi_sramsize"
+.LASF348:
+ .string "boot_size"
+.LASF407:
+ .string "mpb_task_wait_done"
+.LASF422:
+ .string "spl_hash_android"
+.LASF275:
+ .string "uclass_root"
+.LASF163:
+ .string "UCLASS_GPIO"
+.LASF193:
+ .string "UCLASS_PWM"
+.LASF420:
+ .string "set_gd"
+.LASF42:
+ .string "long double"
+.LASF264:
+ .string "ram_top"
+.LASF296:
+ .string "console_evt"
+.LASF396:
+ .string "mpb_init_x"
+.LASF450:
+ .string "mpb_task_set_state"
+.LASF129:
+ .string "rd_start"
+.LASF194:
+ .string "UCLASS_POWER_DOMAIN"
+.LASF197:
+ .string "UCLASS_REGULATOR"
+.LASF305:
+ .string "save_size"
+.LASF430:
+ .string "msec"
+.LASF155:
+ .string "UCLASS_CLK"
+.LASF403:
+ .string "core_task_run"
+.LASF346:
+ .string "info"
+.LASF72:
+ .string "_datarel_start_ofs"
+.LASF250:
+ .string "pre_serial"
+.LASF102:
+ .string "ih_name"
+.LASF98:
+ .string "ih_os"
+.LASF345:
+ .string "task_data"
+.LASF136:
+ .string "cmdline_end"
+.LASF320:
+ .string "net_rx_packet"
+.LASF241:
+ .string "LOGF_MAX_CATEGORIES"
+.LASF276:
+ .string "fdt_blob"
+.LASF33:
+ .string "size"
+.LASF357:
+ .string "BOOT_MODE_PANIC"
+.LASF10:
+ .string "long long unsigned int"
+.LASF90:
+ .string "image_header"
+.LASF363:
+ .string "CPU_1"
+.LASF19:
+ .string "__be32"
+.LASF402:
+ .string "mpb_quit_load_image"
+.LASF52:
+ .string "bi_flashstart"
+.LASF119:
+ .string "fit_noffset_os"
+.LASF415:
+ .string "mpb_task_set_result"
+.LASF178:
+ .string "UCLASS_MMC"
+.LASF240:
+ .string "UCLASS_INVALID"
+.LASF389:
+ .string "mpb_core"
+.LASF218:
+ .string "UCLASS_USB_HUB"
+.LASF279:
+ .string "of_root"
+.LASF234:
+ .string "UCLASS_EBC"
+.LASF340:
+ .string "spl_load_info"
+.LASF293:
+ .string "new_line"
+.LASF434:
+ .string "memset"
+.LASF41:
+ .string "flash_info"
+.LASF84:
+ .string "version"
+.LASF46:
+ .string "region"
+.LASF88:
+ .string "size_dt_struct"
+.LASF273:
+ .string "dm_root"
+.LASF236:
+ .string "UCLASS_RNG"
+.LASF295:
+ .string "sys_start_tick"
+.LASF180:
+ .string "UCLASS_MTD"
+.LASF352:
+ .string "BOOT_MODE_BOOTLOADER"
+.LASF77:
+ .string "fdt32_t"
+.LASF272:
+ .string "new_gd"
+.LASF182:
+ .string "UCLASS_NORTHBRIDGE"
+.LASF62:
+ .string "bi_enetaddr"
+.LASF39:
+ .string "mtd_info"
+.LASF306:
+ .string "in_addr"
+.LASF353:
+ .string "BOOT_MODE_LOADER"
+.LASF321:
+ .string "net_rx_packet_len"
+.LASF398:
+ .string "init"
+.LASF301:
+ .string "__dtb_dt_begin"
+.LASF199:
+ .string "UCLASS_RESET"
+.LASF122:
+ .string "fit_noffset_rd"
+.LASF153:
+ .string "UCLASS_AHCI"
+.LASF12:
+ .string "phys_size_t"
+.LASF156:
+ .string "UCLASS_CPU"
+.LASF71:
+ .string "FIQ_STACK_START"
+.LASF137:
+ .string "verify"
+.LASF31:
+ .string "name"
+.LASF235:
+ .string "UCLASS_EINK_DISPLAY"
+.LASF185:
+ .string "UCLASS_PANEL_BACKLIGHT"
+.LASF213:
+ .string "UCLASS_TIMER"
+.LASF208:
+ .string "UCLASS_SPI_FLASH"
+.LASF261:
+ .string "have_console"
+.LASF65:
+ .string "bi_busfreq"
+.LASF6:
+ .string "short int"
+.LASF347:
+ .string "boot_addr"
+.LASF191:
+ .string "UCLASS_PINCTRL"
+.LASF201:
+ .string "UCLASS_RAMDISK"
+.LASF148:
+ .string "UCLASS_I2C_EMUL"
+.LASF378:
+ .string "TASK_LOAD_ANDROID"
+.LASF207:
+ .string "UCLASS_SPMI"
+.LASF391:
+ .string "tdata"
+.LASF145:
+ .string "UCLASS_TEST_BUS"
+.LASF435:
+ .string "flush_dcache_all"
+.LASF304:
+ .string "save_addr"
+.LASF444:
+ .string "flush_dcache_range"
+.LASF288:
+ .string "malloc_ptr"
+.LASF427:
+ .string "cpuectlr_disable"
+.LASF401:
+ .string "mpb_task_run"
+.LASF424:
+ .string "spl_load_fit"
+.LASF134:
+ .string "initrd_end"
+.LASF372:
+ .string "EVT_VIDEO_BP"
+.LASF253:
+ .string "baudrate"
+.LASF74:
+ .string "_datarellocal_start_ofs"
+.LASF242:
+ .string "arch_global_data"
+.LASF239:
+ .string "UCLASS_COUNT"
+.LASF362:
+ .string "CPU_0"
+.LASF259:
+ .string "pci_clk"
+.LASF364:
+ .string "CPU_2"
+.LASF365:
+ .string "CPU_3"
+.LASF30:
+ .string "block_drvr"
+.LASF452:
+ .string "memcpy"
+.LASF35:
+ .string "flash_id"
+.LASF231:
+ .string "UCLASS_CRYPTO"
+.LASF297:
+ .string "device_node"
+.LASF267:
+ .string "ram_size"
+.LASF128:
+ .string "fit_noffset_setup"
+.LASF89:
+ .string "working_fdt"
+.LASF282:
+ .string "fdt_blob_kern"
+.LASF313:
+ .string "net_root_path"
+.LASF161:
+ .string "UCLASS_DMA"
+.LASF69:
+ .string "bd_t"
+.LASF237:
+ .string "UCLASS_DMC"
+.LASF307:
+ .string "s_addr"
+.LASF322:
+ .string "net_bcast_ethaddr"
+.LASF392:
+ .string "mpb_gd"
+.LASF67:
+ .string "bi_boot_params"
+.LASF359:
+ .string "BOOT_MODE_DFU"
+.LASF308:
+ .string "net_gateway"
+.LASF50:
+ .string "bi_memstart"
+.LASF222:
+ .string "UCLASS_VIDEO_CONSOLE"
+.LASF48:
+ .string "reserved"
+.LASF373:
+ .string "TASK_NONE"
+.LASF238:
+ .string "UCLASS_PD"
+.LASF441:
+ .string "dcache_disable"
+.LASF68:
+ .string "bi_dram"
+.LASF2:
+ .string "short unsigned int"
+.LASF79:
+ .string "magic"
+.LASF126:
+ .string "fit_hdr_setup"
+.LASF115:
+ .string "legacy_hdr_valid"
+.LASF381:
+ .string "TASK_MAX"
+.LASF44:
+ .string "base"
+.LASF451:
+ .string "spl_dummy"
+.LASF202:
+ .string "UCLASS_RTC"
+.LASF366:
+ .string "EVT_BOOT_DEV"
+.LASF243:
+ .string "timer_rate_hz"
+.LASF34:
+ .string "sector_count"
+.LASF101:
+ .string "ih_comp"
+.LASF400:
+ .string "core_main"
+.LASF131:
+ .string "ft_addr"
+.LASF232:
+ .string "UCLASS_ETH_PHY"
+.LASF393:
+ .string "task_init"
+.LASF4:
+ .string "uchar"
+.LASF132:
+ .string "ft_len"
+.LASF27:
+ .string "next"
+.LASF421:
+ .string "data"
+.LASF181:
+ .string "UCLASS_NOP"
+.LASF380:
+ .string "TASK_RUN_UBOOT"
+.LASF349:
+ .string "_boot_mode"
+.LASF127:
+ .string "fit_uname_setup"
+.LASF28:
+ .string "prev"
+.LASF442:
+ .string "invalidate_dcache_all"
+.LASF186:
+ .string "UCLASS_PCH"
+.LASF187:
+ .string "UCLASS_PCI"
+.LASF309:
+ .string "net_netmask"
+.LASF358:
+ .string "BOOT_MODE_WATCHDOG"
+.LASF70:
+ .string "IRQ_STACK_START"
+.LASF152:
+ .string "UCLASS_ADC"
+.LASF356:
+ .string "BOOT_MODE_BROM_DOWNLOAD"
+.LASF147:
+ .string "UCLASS_SPI_EMUL"
+.LASF425:
+ .string "spl_load_baseparamter"
+.LASF124:
+ .string "fit_uname_fdt"
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
+ .section .note.GNU-stack,"",@progbits
diff --git a/u-boot/common/spl/Kconfig b/u-boot/common/spl/Kconfig
index c62938c..dfa3fcd 100644
--- a/u-boot/common/spl/Kconfig
+++ b/u-boot/common/spl/Kconfig
@@ -144,6 +144,17 @@
The SPL code will be relocated to a high memory if you say no here.
Only ARM64 and PowerPC SPL support relocate now.
+config SPL_BOOT_IMAGE
+ bool "SPL boot image load support"
+ default n
+ help
+ This enable SPL boot image load support
+
+config SPL_BOOT_IMAGE_BUF
+ hex "SPL boot image memory buffer"
+ depends on SPL_BOOT_IMAGE
+ default 0x10000000
+
config SPL_RELOC_TEXT_BASE
hex "Address the SPL relocate to"
depends on !SPL_SKIP_RELOCATE
@@ -598,6 +609,12 @@
boot. This enables the drivers in drivers/pch as part of an SPL
build.
+config SPL_PCIE_EP_SUPPORT
+ bool "Support loading from PCIE EP"
+ help
+ Enable support for PCIE EP driver in SPL. The RC will download the
+ image as a RAM partition for firmware.
+
config SPL_POST_MEM_SUPPORT
bool "Support POST drivers"
help
@@ -900,6 +917,13 @@
help
Enable boot kernel in SPL.
+config SPL_KERNEL_BOOT_PREBUILT
+ bool "Enable boot kernel in SPL with prebuilt program"
+ depends on SPL_KERNEL_BOOT
+ default y
+ help
+ Enable boot kernel in SPL with prebuilt program.
+
config SPL_KERNEL_BOOT_SECTOR
hex "Sector address to load kernel in SPL"
depends on SPL_KERNEL_BOOT
diff --git a/u-boot/common/spl/Makefile b/u-boot/common/spl/Makefile
index 3bab93f..cf9d874 100644
--- a/u-boot/common/spl/Makefile
+++ b/u-boot/common/spl/Makefile
@@ -24,7 +24,7 @@
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o
-ifdef CONFIG_SPL_KERNEL_BOOT
+ifdef CONFIG_SPL_KERNEL_BOOT_PREBUILT
ifdef CONFIG_ARM64
obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit_tb_arm64.o
else
@@ -57,4 +57,5 @@
obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o
obj-$(CONFIG_$(SPL_TPL_)RAM_SUPPORT) += spl_ram.o
obj-$(CONFIG_$(SPL_TPL_)USB_SDP_SUPPORT) += spl_sdp.o
+obj-$(CONFIG_$(SPL_TPL_)BOOT_IMAGE) += spl_boot_image.o
endif
diff --git a/u-boot/common/spl/spl.c b/u-boot/common/spl/spl.c
index 6836796..bcb37ec 100644
--- a/u-boot/common/spl/spl.c
+++ b/u-boot/common/spl/spl.c
@@ -17,6 +17,7 @@
#include <version.h>
#include <image.h>
#include <malloc.h>
+#include <mp_boot.h>
#include <dm/root.h>
#include <linux/compiler.h>
#include <fdt_support.h>
@@ -547,6 +548,10 @@
memset(&spl_image, '\0', sizeof(spl_image));
+#ifdef CONFIG_MP_BOOT
+ mpb_init_x(0);
+#endif
+
#if CONFIG_IS_ENABLED(ATF)
/*
* Bl32 ep is optional, initial it as an invalid value.
@@ -574,6 +579,10 @@
}
spl_perform_fixups(&spl_image);
+
+#ifdef CONFIG_MP_BOOT
+ mpb_init_x(2);
+#endif
#ifdef CONFIG_CPU_V7M
spl_image.entry_point |= 0x1;
@@ -710,7 +719,7 @@
/* cleanup before jump to next stage */
void spl_cleanup_before_jump(struct spl_image_info *spl_image)
{
- ulong us;
+ ulong us, tt_us;
spl_board_prepare_for_jump(spl_image);
@@ -738,5 +747,6 @@
isb();
us = (get_ticks() - gd->sys_start_tick) / 24UL;
- printf("Total: %ld.%ld ms\n\n", us / 1000, us % 1000);
+ tt_us = get_ticks() / (COUNTER_FREQUENCY / 1000000);
+ printf("Total: %ld.%ld/%ld.%ld ms\n\n", us / 1000, us % 1000, tt_us / 1000, tt_us % 1000);
}
diff --git a/u-boot/common/spl/spl_ab.c b/u-boot/common/spl/spl_ab.c
index 31b63f7..842c36c 100644
--- a/u-boot/common/spl/spl_ab.c
+++ b/u-boot/common/spl/spl_ab.c
@@ -319,3 +319,38 @@
out:
return ret;
}
+
+/*
+ * If boot A/B system fail, tries-remaining decrease 1
+ * and do reset automatically if still bootable.
+ */
+int spl_ab_decrease_reset(struct blk_desc *dev_desc)
+{
+ AvbABData ab_data;
+ int ret;
+
+ ret = spl_ab_data_read(dev_desc, &ab_data, "misc");
+ if (ret)
+ return ret;
+
+ /* If current device cannot boot, return and try other devices. */
+ if (!spl_slot_is_bootable(&ab_data.slots[0]) &&
+ !spl_slot_is_bootable(&ab_data.slots[1])) {
+ printf("A/B: no bootable slot\n");
+ return -ENODEV;
+ }
+
+ /* If current device still can boot, decrease and do reset. */
+ ret = spl_ab_decrease_tries(dev_desc);
+ if (ret)
+ return ret;
+
+ printf("A/B: slot boot fail, do reset\n");
+ do_reset(NULL, 0, 0, NULL);
+
+ /*
+ * Only do_reset() fail will arrive here, return a
+ * negative number, then enter maskrom in the caller.
+ */
+ return -EINVAL;
+}
diff --git a/u-boot/common/spl/spl_boot_image.c b/u-boot/common/spl/spl_boot_image.c
new file mode 100644
index 0000000..dd49817
--- /dev/null
+++ b/u-boot/common/spl/spl_boot_image.c
@@ -0,0 +1,305 @@
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <android_image.h>
+#include <crypto.h>
+#include <image.h>
+#include <mp_boot.h>
+#include <part.h>
+#include <spl.h>
+#include <asm/io.h>
+
+#define BLK_CNT(_num_bytes, _block_size) \
+ ((_num_bytes + _block_size - 1) / _block_size)
+
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+static int android_check_header(const struct andr_img_hdr *hdr)
+{
+ return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
+}
+
+static void print_hash(const char *label, u8 *hash, int len)
+{
+ int i;
+
+ printf("%s:\n 0x", label ? : "Hash");
+ for (i = 0; i < len; i++)
+ printf("%02x", hash[i]);
+ printf("\n");
+}
+
+#if 0
+static void spl_android_print_contents(const struct andr_img_hdr *hdr)
+{
+ const char * const p = IMAGE_INDENT_STRING;
+ /* os_version = ver << 11 | lvl */
+ u32 os_ver = hdr->os_version >> 11;
+ u32 os_lvl = hdr->os_version & ((1U << 11) - 1);
+ u32 header_version = hdr->header_version;
+
+ printf("%skernel size: %x\n", p, hdr->kernel_size);
+ printf("%skernel address: %x\n", p, hdr->kernel_addr);
+ printf("%sramdisk size: %x\n", p, hdr->ramdisk_size);
+ printf("%sramdisk address: %x\n", p, hdr->ramdisk_addr);
+ printf("%ssecond size: %x\n", p, hdr->second_size);
+ printf("%ssecond address: %x\n", p, hdr->second_addr);
+ printf("%stags address: %x\n", p, hdr->tags_addr);
+ printf("%spage size: %x\n", p, hdr->page_size);
+ printf("%sheader_version: %x\n", p, header_version);
+ /* ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
+ * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M) */
+ printf("%sos_version: %x (ver: %u.%u.%u, level: %u.%u)\n",
+ p, hdr->os_version,
+ (os_ver >> 7) & 0x7F, (os_ver >> 14) & 0x7F, os_ver & 0x7F,
+ (os_lvl >> 4) + 2000, os_lvl & 0x0F);
+ printf("%sname: %s\n", p, hdr->name);
+ printf("%scmdline: %s\n", p, hdr->cmdline);
+
+ if (header_version == 1 || header_version == 2) {
+ printf("%srecovery dtbo size: %x\n", p, hdr->recovery_dtbo_size);
+ printf("%srecovery dtbo offset: %llx\n", p, hdr->recovery_dtbo_offset);
+ printf("%sheader size: %x\n", p, hdr->header_size);
+ }
+
+ if (header_version == 2 || header_version == 3) {
+ printf("%sdtb size: %x\n", p, hdr->dtb_size);
+ printf("%sdtb addr: %llx\n", p, hdr->dtb_addr);
+ }
+
+ if (header_version >= 3) {
+ printf("%scmdline: %s\n", p, hdr->total_cmdline);
+ printf("%svendor ramdisk size: %x\n", p, hdr->vendor_ramdisk_size);
+ printf("%svendor page size: %x\n", p, hdr->vendor_page_size);
+ printf("%svendor header version: %d\n", p, hdr->vendor_header_version);
+ printf("%svendor header size: %x\n", p, hdr->vendor_header_size);
+ }
+
+ if (header_version >= 4) {
+ printf("%svendor ramdisk table size: %x\n",
+ p, hdr->vendor_ramdisk_table_size);
+ printf("%svendor ramdisk table entry num: %x\n",
+ p, hdr->vendor_ramdisk_table_entry_num);
+ printf("%svendor ramdisk table entry size: %x\n",
+ p, hdr->vendor_ramdisk_table_entry_size);
+ printf("%svendor bootconfig size: %d\n",
+ p, hdr->vendor_bootconfig_size);
+ }
+}
+#endif
+
+static ulong android_size(struct andr_img_hdr *hdr)
+{
+ ulong len;
+
+ len = hdr->page_size +
+ ALIGN(hdr->kernel_size, hdr->page_size) +
+ ALIGN(hdr->ramdisk_size, hdr->page_size) +
+ ALIGN(hdr->second_size, hdr->page_size);
+ if (hdr->header_version > 0)
+ len += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+ if (hdr->header_version > 1)
+ len += ALIGN(hdr->dtb_size, hdr->page_size);
+#if 0
+ spl_android_print_contents(hdr);
+#endif
+
+ return len;
+}
+
+int spl_load_android(struct task_data *data)
+{
+ struct spl_load_info *info = &data->info;
+ void *buf = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
+ disk_partition_t part;
+ ulong blkcnt;
+
+ debug("== Android: load start\n");
+
+ if (part_get_info_by_name(info->dev, "boot", &part) < 0) {
+ printf("No boot partition\n");
+ return -ENOENT;
+ }
+
+ blkcnt = BLK_CNT(sizeof(struct andr_img_hdr), info->bl_len);
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
+ return -EIO;
+
+ if (android_check_header(buf))
+ return -EINVAL;
+
+ blkcnt = BLK_CNT(android_size(buf), info->bl_len);
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
+ return -EIO;
+
+ data->boot_addr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
+ data->boot_size = blkcnt * info->bl_len;
+
+ flush_dcache_range((ulong)data, (ulong)data + sizeof(*data));
+ flush_dcache_range((ulong)buf, (ulong)buf + blkcnt);
+
+ debug("== Android: load 0x%08lx size OK\n", blkcnt * info->bl_len);
+
+ return 0;
+}
+
+#ifdef CONFIG_ARMV8_CE_SHA1
+int spl_hash_android(struct task_data *data)
+{
+ struct andr_img_hdr *hdr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
+ sha1_context ctx;
+ uchar hash[32];
+ void *buf;
+
+ printf("== Android: hash start\n");
+
+ if (hdr->header_version >= 3)
+ return -EINVAL;
+
+ sha1_starts(&ctx);
+
+ buf = (void *)hdr + hdr->page_size;
+ sha1_update(&ctx, (const uchar *)buf, hdr->kernel_size);
+ sha1_update(&ctx, (const uchar *)&hdr->kernel_size, sizeof(hdr->kernel_size));
+
+ buf += ALIGN(hdr->kernel_size, hdr->page_size);
+ sha1_update(&ctx, (const uchar *)buf, hdr->ramdisk_size);
+ sha1_update(&ctx, (const uchar *)&hdr->ramdisk_size, sizeof(hdr->ramdisk_size));
+
+ buf += ALIGN(hdr->ramdisk_size, hdr->page_size);
+ sha1_update(&ctx, (const uchar *)buf, hdr->second_size);
+ sha1_update(&ctx, (const uchar *)&hdr->second_size, sizeof(hdr->second_size));
+
+ if (hdr->header_version > 0) {
+ buf += ALIGN(hdr->second_size, hdr->page_size);
+ sha1_update(&ctx, (const uchar *)buf, hdr->recovery_dtbo_size);
+ sha1_update(&ctx, (const uchar *)&hdr->recovery_dtbo_size, sizeof(hdr->recovery_dtbo_size));
+ }
+ if (hdr->header_version > 1) {
+ buf += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+ sha1_update(&ctx, (const uchar *)buf, hdr->dtb_size);
+ sha1_update(&ctx, (const uchar *)&hdr->dtb_size, sizeof(hdr->dtb_size));
+ }
+
+ sha1_finish(&ctx, hash);
+
+ if (memcmp(hash, hdr->id, 20)) {
+ print_hash("Hash from header", (u8 *)hdr->id, 20);
+ print_hash("Hash real", (u8 *)hash, 20);
+ return -EBADFD;
+ }
+
+ printf("== Android: hash OK, 0x%08lx\n", (ulong)data->boot_addr);
+
+ return 0;
+}
+
+#else
+int spl_hash_android(struct task_data *data)
+{
+ struct andr_img_hdr *hdr = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
+ struct udevice *dev;
+ sha_context ctx;
+ uchar hash[32];
+ void *buf;
+
+ debug("== Android: hash start\n");
+
+ if (hdr->header_version >= 3)
+ return -EINVAL;
+
+ ctx.algo = CRYPTO_SHA1;
+ dev = crypto_get_device(ctx.algo);
+ if (!dev) {
+ printf("No crypto device for sha1\n");
+ return -ENODEV;
+ }
+
+ ctx.length = hdr->kernel_size + sizeof(hdr->kernel_size) +
+ hdr->ramdisk_size + sizeof(hdr->ramdisk_size) +
+ hdr->second_size + sizeof(hdr->second_size);
+ if (hdr->header_version > 0)
+ ctx.length += hdr->recovery_dtbo_size + sizeof(hdr->recovery_dtbo_size);
+ if (hdr->header_version > 1)
+ ctx.length += hdr->dtb_size + sizeof(hdr->dtb_size);
+
+ crypto_sha_init(dev, &ctx);
+
+ buf = (void *)hdr + hdr->page_size;
+ crypto_sha_update(dev, buf, hdr->kernel_size);
+ crypto_sha_update(dev, &hdr->kernel_size, sizeof(hdr->kernel_size));
+
+ buf += ALIGN(hdr->kernel_size, hdr->page_size);
+ crypto_sha_update(dev, buf, hdr->ramdisk_size);
+ crypto_sha_update(dev, &hdr->ramdisk_size, sizeof(hdr->ramdisk_size));
+
+ buf += ALIGN(hdr->ramdisk_size, hdr->page_size);
+ crypto_sha_update(dev, buf, hdr->second_size);
+ crypto_sha_update(dev, &hdr->second_size, sizeof(hdr->second_size));
+
+ if (hdr->header_version > 0) {
+ buf += ALIGN(hdr->second_size, hdr->page_size);
+ crypto_sha_update(dev, buf, hdr->recovery_dtbo_size);
+ crypto_sha_update(dev, &hdr->recovery_dtbo_size, sizeof(hdr->recovery_dtbo_size));
+ }
+ if (hdr->header_version > 1) {
+ buf += ALIGN(hdr->recovery_dtbo_size, hdr->page_size);
+ crypto_sha_update(dev, buf, hdr->dtb_size);
+ crypto_sha_update(dev, &hdr->dtb_size, sizeof(hdr->dtb_size));
+ }
+
+ crypto_sha_final(dev, &ctx, hash);
+
+ if (memcmp(hash, hdr->id, 20)) {
+ print_hash("Hash from header", (u8 *)hdr->id, 20);
+ print_hash("Hash real", (u8 *)hash, 20);
+ return -EBADFD;
+ }
+
+ debug("== Android: hash OK, 0x%08lx\n", (ulong)data->boot_addr);
+
+ return 0;
+}
+
+#endif
+#endif
+
+#ifdef CONFIG_ROCKCHIP_FIT_IMAGE
+int spl_load_fit(struct task_data *data)
+{
+ struct spl_load_info *info = &data->info;
+ void *buf = (void *)CONFIG_SPL_BOOT_IMAGE_BUF;
+ disk_partition_t part;
+ ulong blkcnt;
+ int size;
+
+ debug("== FIT: load start\n");
+
+ if (part_get_info_by_name(info->dev, "boot", &part) < 0) {
+ printf("No boot partition\n");
+ return -ENOENT;
+ }
+
+ blkcnt = BLK_CNT(sizeof(struct fdt_header), info->bl_len);
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
+ return -EIO;
+
+ if (fdt_check_header(buf))
+ return -EINVAL;
+
+ size = fit_get_totalsize(buf, &size);
+ blkcnt = BLK_CNT(size, info->bl_len);
+ if (info->read(info, part.start, blkcnt, buf) != blkcnt)
+ return -EIO;
+
+ flush_dcache_range((ulong)buf, (ulong)buf + blkcnt);
+
+ debug("== FIT: load 0x%08x size OK\n", size);
+
+ return 0;
+}
+#endif
+
diff --git a/u-boot/common/spl/spl_fit.c b/u-boot/common/spl/spl_fit.c
index b19e0c6..29f9436 100644
--- a/u-boot/common/spl/spl_fit.c
+++ b/u-boot/common/spl/spl_fit.c
@@ -12,6 +12,7 @@
#include <image.h>
#include <malloc.h>
#include <mtd_blk.h>
+#include <mp_boot.h>
#include <spl.h>
#include <spl_ab.h>
#include <linux/libfdt.h>
@@ -481,6 +482,8 @@
#else
sector = CONFIG_SPL_KERNEL_BOOT_SECTOR;
#endif
+ printf("Trying kernel at 0x%x sector from '%s' part\n", sector, part_name);
+
if (info->read(info, sector, 1, &fit_header) != 1) {
debug("%s: Failed to read header\n", __func__);
return -EIO;
@@ -793,6 +796,10 @@
int ret = -EINVAL;
int i;
+#ifdef CONFIG_MP_BOOT
+ mpb_init_1(*info);
+#endif
+
printf("Trying fit image at 0x%lx sector\n", sector_offs);
for (i = 0; i < CONFIG_SPL_FIT_IMAGE_MULTIPLE; i++) {
if (i > 0) {
@@ -820,15 +827,18 @@
}
}
#ifdef CONFIG_SPL_AB
+ /* If boot fail in spl, spl must decrease 1 and do_reset. */
+ if (ret)
+ return spl_ab_decrease_reset(info->dev);
/*
- * If boot fail in spl, spl must decrease 1. If boot
- * successfully, it is no need to do that and U-boot will
- * always to decrease 1. If in thunderboot process,
- * always need to decrease 1.
+ * If boot successfully, it is no need to do decrease
+ * and U-boot will always decrease 1.
+ * If in thunderboot process, always need to decrease 1.
*/
- if (IS_ENABLED(CONFIG_SPL_KERNEL_BOOT) || ret)
+ if (spl_image->next_stage == SPL_NEXT_STAGE_KERNEL)
spl_ab_decrease_tries(info->dev);
#endif
+
return ret;
}
diff --git a/u-boot/common/spl_mp_boot_rk3528.S b/u-boot/common/spl_mp_boot_rk3528.S
new file mode 100644
index 0000000..6c1f25a
--- /dev/null
+++ b/u-boot/common/spl_mp_boot_rk3528.S
@@ -0,0 +1,9214 @@
+ .arch armv8-a+nosimd
+ .file "mp_boot.c"
+ .text
+.Ltext0:
+ .cfi_sections .debug_frame
+ .section .text.mpb_task_set_state,"ax",@progbits
+ .align 2
+ .type mpb_task_set_state, %function
+mpb_task_set_state:
+.LFB227:
+ .file 1 "common/mp_boot.c"
+ .loc 1 227 0
+ .cfi_startproc
+.LVL0:
+.LBB30:
+.LBB31:
+ .loc 1 146 0
+ mov x4, 136314880
+ mov w3, 1
+ lsl w3, w3, w1
+ ldr w5, [x4]
+.LBE31:
+.LBE30:
+ .loc 1 232 0
+ tst w3, w5
+ beq .L11
+.LBB32:
+.LBB33:
+ .loc 1 199 0
+ uxtw x5, w0
+ mov x3, 328
+ umull x0, w0, w3
+.LVL1:
+ madd x4, x5, x3, x4
+ mov w3, 0
+ ldrb w6, [x4, 328]
+ mov x4, 20
+ movk x4, 0x820, lsl 16
+ add x4, x0, x4
+.L3:
+.LVL2:
+ cmp w3, w6
+ blt .L5
+.LVL3:
+.L11:
+.LBE33:
+.LBE32:
+ .loc 1 252 0
+ mov w0, 0
+ ret
+.LVL4:
+.L5:
+.LBB35:
+.LBB34:
+ .loc 1 200 0
+ ldr w7, [x4], 40
+ cmp w1, w7
+ beq .L4
+ .loc 1 199 0
+ add w3, w3, 1
+.LVL5:
+ b .L3
+.L4:
+.LVL6:
+.LBE34:
+.LBE35:
+ .loc 1 239 0
+ mov x8, 328
+ sxtw x4, w3
+ mov x7, 40
+ .loc 1 240 0
+ add x0, x0, 16
+ .loc 1 239 0
+ mul x5, x5, x8
+ .loc 1 227 0
+ stp x29, x30, [sp, -16]!
+ .cfi_def_cfa_offset 16
+ .cfi_offset 29, -16
+ .cfi_offset 30, -8
+ .loc 1 239 0
+ nop // between mem op and mult-accumulate
+ madd x4, x4, x7, x5
+ mov x6, 136314880
+ .loc 1 240 0
+ smaddl x3, w3, w7, x0
+ .loc 1 227 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 239 0
+ add x4, x6, x4
+ .loc 1 227 0
+ .loc 1 239 0
+ add w1, w1, w2
+.LVL7:
+ .loc 1 240 0
+ add x0, x3, x6
+ .loc 1 239 0
+ str w1, [x4, 16]
+ .loc 1 241 0
+ add x1, x0, 4
+ bl flush_dcache_range
+.LVL8:
+ .loc 1 252 0
+ mov w0, 0
+ ldp x29, x30, [sp], 16
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE227:
+ .size mpb_task_set_state, .-mpb_task_set_state
+ .section .text.spl_init_display,"ax",@progbits
+ .align 2
+ .weak spl_init_display
+ .type spl_init_display, %function
+spl_init_display:
+.LFB252:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE252:
+ .size spl_init_display, .-spl_init_display
+ .section .text.spl_load_baseparamter,"ax",@progbits
+ .align 2
+ .weak spl_load_baseparamter
+ .type spl_load_baseparamter, %function
+spl_load_baseparamter:
+.LFB250:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE250:
+ .size spl_load_baseparamter, .-spl_load_baseparamter
+ .section .text.spl_load_fit,"ax",@progbits
+ .align 2
+ .weak spl_load_fit
+ .type spl_load_fit, %function
+spl_load_fit:
+.LFB248:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE248:
+ .size spl_load_fit, .-spl_load_fit
+ .section .text.spl_load_android,"ax",@progbits
+ .align 2
+ .weak spl_load_android
+ .type spl_load_android, %function
+spl_load_android:
+.LFB246:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE246:
+ .size spl_load_android, .-spl_load_android
+ .section .text.spl_hash_android,"ax",@progbits
+ .align 2
+ .weak spl_hash_android
+ .type spl_hash_android, %function
+spl_hash_android:
+.LFB244:
+ .cfi_startproc
+ mov w0, 0
+ ret
+ .cfi_endproc
+.LFE244:
+ .size spl_hash_android, .-spl_hash_android
+ .section .text.spl_dummy,"ax",@progbits
+ .align 2
+ .weak spl_dummy
+ .type spl_dummy, %function
+spl_dummy:
+.LFB220:
+ .loc 1 52 0
+ .cfi_startproc
+.LVL9:
+ .loc 1 52 0
+ mov w0, 0
+.LVL10:
+ ret
+ .cfi_endproc
+.LFE220:
+ .size spl_dummy, .-spl_dummy
+ .section .text.mpb_task_is_done,"ax",@progbits
+ .align 2
+ .global mpb_task_is_done
+ .type mpb_task_is_done, %function
+mpb_task_is_done:
+.LFB228:
+ .loc 1 261 0
+ .cfi_startproc
+.LVL11:
+.LBB36:
+.LBB37:
+ .loc 1 146 0
+ mov x2, 136314880
+ mov w1, 1
+ lsl w1, w1, w0
+ ldr w2, [x2]
+.LBE37:
+.LBE36:
+ .loc 1 265 0
+ tst w1, w2
+ beq .L35
+ .loc 1 261 0
+ stp x29, x30, [sp, -96]!
+ .cfi_def_cfa_offset 96
+ .cfi_offset 29, -96
+ .cfi_offset 30, -88
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -80
+ .cfi_offset 20, -72
+ mov w19, w0
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -48
+ .cfi_offset 24, -40
+ .loc 1 275 0
+ mov w24, -559087616
+ .loc 1 261 0
+ str x27, [sp, 80]
+ .loc 1 275 0
+ add w24, w0, w24
+ .cfi_offset 27, -16
+ .loc 1 277 0
+ sub w27, w0, #65536
+ .loc 1 261 0
+ stp x21, x22, [sp, 32]
+ stp x25, x26, [sp, 64]
+ .cfi_offset 21, -64
+ .cfi_offset 22, -56
+ .cfi_offset 25, -32
+ .cfi_offset 26, -24
+ mov x21, 0
+.LVL12:
+.L27:
+ mov x22, 16
+ mov x20, 20
+ .loc 1 269 0
+ mov x26, 328
+ movk x22, 0x820, lsl 16
+ movk x20, 0x820, lsl 16
+ add x22, x21, x22
+ add x20, x21, x20
+ .loc 1 261 0
+ mov w23, 0
+ .loc 1 269 0
+ movk x26, 0x820, lsl 16
+ .loc 1 279 0
+ mov w25, 1431655765
+ b .L23
+.LVL13:
+.L26:
+ .loc 1 270 0
+ ldr w0, [x20]
+ cmp w19, w0
+ beq .L22
+.L25:
+ .loc 1 269 0
+ add w23, w23, 1
+.LVL14:
+ add x22, x22, 40
+ add x20, x20, 40
+.LVL15:
+.L23:
+ .loc 1 269 0 is_stmt 0 discriminator 1
+ ldrb w0, [x21, x26]
+ cmp w23, w0
+ blt .L26
+.LVL16:
+ add x21, x21, 328
+ .loc 1 268 0 is_stmt 1 discriminator 2
+ cmp x21, 1312
+ bne .L27
+ .loc 1 286 0
+ mov w0, 0
+.L19:
+ .loc 1 287 0
+ ldp x19, x20, [sp, 16]
+.LVL17:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL18:
+ ldp x25, x26, [sp, 64]
+ ldr x27, [sp, 80]
+.LVL19:
+ ldp x29, x30, [sp], 96
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL20:
+.L22:
+ .cfi_restore_state
+ .loc 1 272 0
+ mov x0, x22
+ mov x1, x20
+ bl invalidate_dcache_range
+.LVL21:
+ .loc 1 275 0
+ ldr w0, [x22]
+ cmp w0, w24
+ beq .L28
+ .loc 1 277 0
+ cmp w0, w27
+ beq .L20
+ .loc 1 279 0
+ add w1, w19, w25
+ cmp w0, w1
+ bne .L25
+ .loc 1 280 0
+ mov w0, -2
+ b .L19
+.L20:
+ .loc 1 266 0
+ mov w0, -1
+ b .L19
+.L28:
+ .loc 1 276 0
+ mov w0, 1
+ b .L19
+.LVL22:
+.L35:
+ .cfi_def_cfa 31, 0
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 27
+ .cfi_restore 29
+ .cfi_restore 30
+ .loc 1 266 0
+ mov w0, -1
+.LVL23:
+ .loc 1 287 0
+ ret
+ .cfi_endproc
+.LFE228:
+ .size mpb_task_is_done, .-mpb_task_is_done
+ .section .text.mpb_task_dump,"ax",@progbits
+ .align 2
+ .global mpb_task_dump
+ .type mpb_task_dump, %function
+mpb_task_dump:
+.LFB229:
+ .loc 1 290 0
+ .cfi_startproc
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ .loc 1 294 0
+ mov x0, 136314880
+ .loc 1 290 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 294 0
+ ldr x1, [x0, 1360]
+ ldr x2, [x0, 1368]
+ adrp x0, .LC1
+ .loc 1 290 0
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .loc 1 294 0
+ mov x20, 20
+ .loc 1 290 0
+ stp x23, x24, [sp, 48]
+ .loc 1 294 0
+ movk x20, 0x820, lsl 16
+ .loc 1 290 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .loc 1 299 0
+ adrp x23, .LANCHOR0
+ adrp x24, .LC2
+ .loc 1 296 0
+ mov w21, 0
+ .loc 1 299 0
+ add x23, x23, :lo12:.LANCHOR0
+ add x24, x24, :lo12:.LC2
+ .loc 1 294 0
+ add x0, x0, :lo12:.LC1
+ .loc 1 290 0
+ str x25, [sp, 64]
+ .cfi_offset 25, -16
+ .loc 1 294 0
+ bl printf
+.LVL24:
+.L39:
+ .loc 1 290 0
+ mov x19, x20
+ mov w22, 0
+ .loc 1 300 0
+ adrp x25, .LC3
+ b .L42
+.LVL25:
+.L40:
+ .loc 1 299 0 discriminator 3
+ ldr w2, [x19]
+ mov w1, w21
+ mov x0, x24
+ .loc 1 297 0 discriminator 3
+ add w22, w22, 1
+.LVL26:
+ add x19, x19, 40
+ .loc 1 299 0 discriminator 3
+ ldr x3, [x23, w2, uxtw 3]
+ bl printf
+.LVL27:
+ .loc 1 300 0 discriminator 3
+ ldr w1, [x19, -40]
+ add x0, x25, :lo12:.LC3
+ bl printf
+.LVL28:
+ .loc 1 301 0 discriminator 3
+ ldr x1, [x19, -52]
+ adrp x0, .LC4
+ add x0, x0, :lo12:.LC4
+ bl printf
+.LVL29:
+ .loc 1 302 0 discriminator 3
+ ldr w1, [x19, -44]
+ adrp x0, .LC5
+ add x0, x0, :lo12:.LC5
+ bl printf
+.LVL30:
+ .loc 1 303 0 discriminator 3
+ ldr w1, [x19, -28]
+ adrp x0, .LC6
+ add x0, x0, :lo12:.LC6
+ bl printf
+.LVL31:
+ .loc 1 304 0 discriminator 3
+ ldr x1, [x19, -20]
+ adrp x0, .LC7
+ add x0, x0, :lo12:.LC7
+ bl printf
+.LVL32:
+ .loc 1 305 0 discriminator 3
+ ldr w1, [x19, -36]
+ adrp x0, .LC8
+ add x0, x0, :lo12:.LC8
+ bl printf
+.LVL33:
+ .loc 1 306 0 discriminator 3
+ ldr w1, [x19, -32]
+ adrp x0, .LC9
+ add x0, x0, :lo12:.LC9
+ bl printf
+.LVL34:
+.L42:
+ .loc 1 297 0 discriminator 1
+ ldrb w0, [x20, 308]
+ cmp w22, w0
+ blt .L40
+ .loc 1 296 0 discriminator 2
+ add w21, w21, 1
+.LVL35:
+ add x20, x20, 328
+ cmp w21, 4
+ bne .L39
+ .loc 1 310 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+.LVL36:
+ ldp x23, x24, [sp, 48]
+ ldr x25, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE229:
+ .size mpb_task_dump, .-mpb_task_dump
+ .section .text.core_task_run.part.1,"ax",@progbits
+ .align 2
+ .type core_task_run.part.1, %function
+core_task_run.part.1:
+.LFB242:
+ .loc 1 370 0
+ .cfi_startproc
+.LVL37:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ mov w19, w0
+ stp x21, x22, [sp, 32]
+ mov w20, w2
+.LVL38:
+ stp x23, x24, [sp, 48]
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ and x22, x1, 255
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -16
+ .cfi_offset 26, -8
+.LBB48:
+.LBB49:
+ .loc 1 319 0
+ cbz w3, .L45
+ mov w25, w3
+ mov w23, 0
+ mov w21, 0
+ .loc 1 324 0
+ mov w26, 1
+.LVL39:
+.L50:
+ lsl w0, w26, w21
+ tst w0, w25
+ beq .L46
+.L47:
+ .loc 1 319 0
+ mov w24, 20000
+.L48:
+.LVL40:
+ .loc 1 329 0
+ mov w0, w21
+ bl mpb_task_is_done
+.LVL41:
+ cbz w0, .L49
+ .loc 1 344 0
+ mov w0, w21
+ bl mpb_task_is_done
+.LVL42:
+ .loc 1 345 0
+ cmp w0, 0
+ cinc w23, w23, lt
+.LVL43:
+.L46:
+ .loc 1 323 0
+ add w21, w21, 1
+.LVL44:
+ cmp w21, 8
+ bne .L50
+.LVL45:
+.LBE49:
+.LBE48:
+ .loc 1 387 0
+ cbz w23, .L45
+.LVL46:
+ .loc 1 389 0
+ uxtw x1, w19
+ mov x2, 328
+ sxtw x0, w22
+ mul x1, x1, x2
+ mov x2, 40
+ madd x0, x0, x2, x1
+ mov x1, 136314880
+ add x0, x1, x0
+ ldr w0, [x0, 28]
+ cbnz w0, .L51
+.LVL47:
+.L52:
+ .loc 1 410 0
+ mov w2, w20
+ mov w1, w19
+ adrp x0, .LC11
+ add x0, x0, :lo12:.LC11
+ bl printf
+.LVL48:
+ .loc 1 374 0
+ mov w21, 0
+ .loc 1 411 0
+ mov w2, 1431655765
+ mov w1, w20
+ mov w0, w19
+ bl mpb_task_set_state
+.LVL49:
+ b .L58
+.LVL50:
+.L49:
+.LBB51:
+.LBB50:
+ .loc 1 330 0
+ mov x0, 100
+ bl udelay
+.LVL51:
+ .loc 1 333 0
+ subs w24, w24, #1
+.LVL52:
+ bne .L48
+.LVL53:
+ .loc 1 337 0
+ bl mpb_task_dump
+.LVL54:
+ b .L47
+.LVL55:
+.L45:
+.LBE50:
+.LBE51:
+ .loc 1 392 0
+ uxtw x1, w19
+ mov x2, 328
+ sxtw x0, w22
+ mul x1, x1, x2
+ mov x2, 40
+ madd x0, x0, x2, x1
+ mov x1, 136314880
+ add x0, x1, x0
+ ldr w0, [x0, 28]
+ cbnz w0, .L52
+.L51:
+.LVL56:
+ .loc 1 397 0
+ mov w2, w20
+ mov w1, w19
+ adrp x0, .LC12
+ add x0, x0, :lo12:.LC12
+ bl printf
+.LVL57:
+ .loc 1 401 0
+ uxtw x24, w19
+ .loc 1 398 0
+ bl get_ticks
+.LVL58:
+ mov x23, x0
+.LVL59:
+ .loc 1 400 0
+ mov w2, 286331153
+ mov w1, w20
+ mov w0, w19
+.LVL60:
+ bl mpb_task_set_state
+.LVL61:
+ .loc 1 401 0
+ mov x1, 328
+ mov x0, 40
+ mul x1, x24, x1
+ madd x1, x22, x0, x1
+ mov x0, 8
+ movk x0, 0x820, lsl 16
+ ldr x1, [x0, x1]
+ mov x0, 1320
+ movk x0, 0x820, lsl 16
+ blr x1
+.LVL62:
+ mov w21, w0
+.LVL63:
+ .loc 1 402 0
+ cbnz w0, .L59
+ .loc 1 405 0
+ mov w2, -559087616
+ b .L77
+.L59:
+ .loc 1 403 0
+ mov w2, -65536
+.L77:
+ .loc 1 405 0
+ mov w1, w20
+ mov w0, w19
+.LVL64:
+ bl mpb_task_set_state
+.LVL65:
+ .loc 1 407 0
+ bl get_ticks
+.LVL66:
+ sub x0, x0, x23
+ mov x4, 24000
+ .loc 1 408 0
+ mov w3, w21
+ mov w2, w20
+ mov w1, w19
+ .loc 1 407 0
+ udiv x4, x0, x4
+ mov x0, 328
+ mul x0, x24, x0
+ mov x24, 40
+ madd x24, x22, x24, x0
+ mov x22, 40
+.LVL67:
+ movk x22, 0x820, lsl 16
+ .loc 1 408 0
+ adrp x0, .LC10
+ add x0, x0, :lo12:.LC10
+ .loc 1 407 0
+ str x4, [x22, x24]
+ .loc 1 408 0
+ bl printf
+.LVL68:
+.L58:
+.LBB52:
+.LBB53:
+.LBB54:
+.LBB55:
+ .loc 1 146 0
+ mov x0, 136314880
+ mov w1, 1
+ lsl w1, w1, w20
+ ldr w2, [x0]
+.LBE55:
+.LBE54:
+ .loc 1 212 0
+ tst w1, w2
+ beq .L44
+.LBB56:
+.LBB57:
+ .loc 1 199 0
+ uxtw x3, w19
+ mov x1, 328
+ umull x19, w19, w1
+.LVL69:
+ madd x0, x3, x1, x0
+ mov w1, 0
+ ldrb w2, [x0, 328]
+ mov x0, 20
+ movk x0, 0x820, lsl 16
+ add x0, x19, x0
+.L55:
+.LVL70:
+ cmp w1, w2
+ blt .L57
+.LVL71:
+.L44:
+.LBE57:
+.LBE56:
+.LBE53:
+.LBE52:
+ .loc 1 417 0
+ ldp x19, x20, [sp, 16]
+.LVL72:
+ ldp x21, x22, [sp, 32]
+.LVL73:
+ ldp x23, x24, [sp, 48]
+ ldp x25, x26, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL74:
+.L57:
+ .cfi_restore_state
+.LBB65:
+.LBB60:
+.LBB59:
+.LBB58:
+ .loc 1 200 0
+ ldr w4, [x0], 40
+ cmp w20, w4
+ beq .L56
+ .loc 1 199 0
+ add w1, w1, 1
+.LVL75:
+ b .L55
+.L56:
+.LVL76:
+.LBE58:
+.LBE59:
+ .loc 1 219 0
+ sxtw x2, w1
+ mov x5, 328
+ mov x4, 40
+ .loc 1 220 0
+ add x19, x19, 32
+ .loc 1 219 0
+ mul x3, x3, x5
+ mov x0, 136314880
+ madd x2, x2, x4, x3
+ .loc 1 220 0
+ smaddl x19, w1, w4, x19
+ .loc 1 219 0
+ add x2, x0, x2
+.LBE60:
+.LBE65:
+ .loc 1 417 0
+ ldp x23, x24, [sp, 48]
+.LBB66:
+.LBB61:
+ .loc 1 220 0
+ add x0, x19, x0
+.LBE61:
+.LBE66:
+ .loc 1 417 0
+ ldp x25, x26, [sp, 64]
+.LBB67:
+.LBB62:
+ .loc 1 221 0
+ add x1, x0, 4
+.LBE62:
+.LBE67:
+ .loc 1 417 0
+ ldp x19, x20, [sp, 16]
+.LVL77:
+.LBB68:
+.LBB63:
+ .loc 1 219 0
+ str w21, [x2, 32]
+.LBE63:
+.LBE68:
+ .loc 1 417 0
+ ldp x21, x22, [sp, 32]
+.LVL78:
+ ldp x29, x30, [sp], 80
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+.LBB69:
+.LBB64:
+ .loc 1 221 0
+ b flush_dcache_range
+.LVL79:
+.LBE64:
+.LBE69:
+ .cfi_endproc
+.LFE242:
+ .size core_task_run.part.1, .-core_task_run.part.1
+ .section .text.mpb_task_wait_done,"ax",@progbits
+ .align 2
+ .global mpb_task_wait_done
+ .type mpb_task_wait_done, %function
+mpb_task_wait_done:
+.LFB232:
+ .loc 1 366 0
+ .cfi_startproc
+.LVL80:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ mov w19, w0
+.LVL81:
+.L80:
+.LBB74:
+.LBB75:
+ .loc 1 355 0
+ mov w0, w19
+ bl mpb_task_is_done
+.LVL82:
+ cbnz w0, .L79
+.LVL83:
+.LBB76:
+.LBB77:
+ .file 2 "include/linux/delay.h"
+ .loc 2 16 0
+ mov x0, 1000
+ bl udelay
+.LVL84:
+ mov x0, 1000
+ bl udelay
+.LVL85:
+ b .L80
+.L79:
+.LBE77:
+.LBE76:
+ .loc 1 362 0
+ mov w0, w19
+.LBE75:
+.LBE74:
+ .loc 1 368 0
+ ldr x19, [sp, 16]
+.LVL86:
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+.LBB79:
+.LBB78:
+ .loc 1 362 0
+ b mpb_task_is_done
+.LVL87:
+.LBE78:
+.LBE79:
+ .cfi_endproc
+.LFE232:
+ .size mpb_task_wait_done, .-mpb_task_wait_done
+ .section .text.mpb_task_run,"ax",@progbits
+ .align 2
+ .global mpb_task_run
+ .type mpb_task_run, %function
+mpb_task_run:
+.LFB234:
+ .loc 1 420 0
+ .cfi_startproc
+.LVL88:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+.LBB86:
+.LBB87:
+ .loc 1 146 0
+ mov x3, 136314880
+.LBE87:
+.LBE86:
+ .loc 1 420 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+.LBB89:
+.LBB88:
+ .loc 1 146 0
+ mov w24, 1
+ ldr w2, [x3]
+ lsl w24, w24, w1
+.LVL89:
+.LBE88:
+.LBE89:
+ .loc 1 420 0
+ stp x19, x20, [sp, 16]
+ stp x21, x22, [sp, 32]
+ .loc 1 424 0
+ tst w24, w2
+ .loc 1 420 0
+ str x25, [sp, 64]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ .cfi_offset 25, -16
+ .loc 1 424 0
+ beq .L82
+ .loc 1 424 0 is_stmt 0 discriminator 1
+ cbz w1, .L82
+ uxtw x25, w0
+.LVL90:
+ .loc 1 421 0 is_stmt 1
+ mov w19, 328
+ mov x0, 8
+.LVL91:
+ mov x22, x25
+ mov w21, w1
+ .loc 1 427 0
+ mov x20, x3
+ .loc 1 421 0
+ umaddl x19, w25, w19, x0
+ .loc 1 427 0
+ mov x0, 328
+ .loc 1 421 0
+ mov w23, 0
+ .loc 1 427 0
+ madd x25, x25, x0, x3
+.LVL92:
+ .loc 1 421 0
+ add x19, x19, x3
+.LVL93:
+.L85:
+ .loc 1 427 0 discriminator 1
+ ldrb w0, [x25, 328]
+ cmp w23, w0
+ blt .L87
+.LVL94:
+.L82:
+ .loc 1 431 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+ ldr x25, [sp, 64]
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL95:
+.L87:
+ .cfi_restore_state
+ .loc 1 428 0
+ ldr w0, [x19, 12]
+ cmp w21, w0
+ bne .L86
+ .loc 1 428 0 is_stmt 0 discriminator 1
+ ldr x0, [x19]
+ cbz x0, .L86
+.LVL96:
+.LBB90:
+.LBB91:
+.LBB92:
+.LBB93:
+ .loc 1 146 0 is_stmt 1
+ ldr w0, [x20]
+.LBE93:
+.LBE92:
+ .loc 1 377 0
+ tst w24, w0
+ beq .L86
+ ldr w3, [x19, 16]
+ mov w2, w21
+ mov w1, w23
+ mov w0, w22
+ bl core_task_run.part.1
+.LVL97:
+.L86:
+.LBE91:
+.LBE90:
+ .loc 1 427 0 discriminator 2
+ add w23, w23, 1
+.LVL98:
+ add x19, x19, 40
+ b .L85
+ .cfi_endproc
+.LFE234:
+ .size mpb_task_run, .-mpb_task_run
+ .section .text.core_main,"ax",@progbits
+ .align 2
+ .global core_main
+ .type core_main, %function
+core_main:
+.LFB235:
+ .loc 1 434 0
+ .cfi_startproc
+.LVL99:
+ stp x29, x30, [sp, -64]!
+ .cfi_def_cfa_offset 64
+ .cfi_offset 29, -64
+ .cfi_offset 30, -56
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -32
+ .cfi_offset 22, -24
+ uxtw x22, w0
+ stp x19, x20, [sp, 16]
+ .loc 1 435 0
+ mov x0, 8
+.LVL100:
+ .cfi_offset 19, -48
+ .cfi_offset 20, -40
+ mov w19, 328
+ mov x20, 136314880
+ .loc 1 434 0
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -16
+ .cfi_offset 24, -8
+ .loc 1 434 0
+ mov x23, x22
+.LVL101:
+ .loc 1 435 0
+ umaddl x19, w22, w19, x0
+ .loc 1 438 0
+ mov x0, 328
+ mov w21, 0
+.LBB98:
+.LBB99:
+.LBB100:
+.LBB101:
+ .loc 1 146 0
+ mov w24, 1
+.LBE101:
+.LBE100:
+.LBE99:
+.LBE98:
+ .loc 1 438 0
+ madd x22, x22, x0, x20
+.LVL102:
+ .loc 1 435 0
+ add x19, x19, x20
+.LVL103:
+.L99:
+ .loc 1 438 0 discriminator 1
+ ldrb w0, [x22, 328]
+ cmp w21, w0
+ blt .L101
+ .loc 1 442 0
+ ldp x19, x20, [sp, 16]
+ ldp x21, x22, [sp, 32]
+.LVL104:
+ ldp x23, x24, [sp, 48]
+.LVL105:
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL106:
+.L101:
+ .cfi_restore_state
+ .loc 1 439 0
+ ldr x0, [x19]
+ cbz x0, .L100
+ .loc 1 440 0
+ ldr w2, [x19, 12]
+.LVL107:
+.LBB105:
+.LBB104:
+.LBB103:
+.LBB102:
+ .loc 1 146 0
+ ldr w0, [x20]
+ lsl w1, w24, w2
+.LBE102:
+.LBE103:
+ .loc 1 377 0
+ tst w1, w0
+ beq .L100
+ ldr w3, [x19, 16]
+ mov w1, w21
+ mov w0, w23
+ bl core_task_run.part.1
+.LVL108:
+.L100:
+.LBE104:
+.LBE105:
+ .loc 1 438 0 discriminator 2
+ add w21, w21, 1
+.LVL109:
+ add x19, x19, 40
+ b .L99
+ .cfi_endproc
+.LFE235:
+ .size core_main, .-core_main
+ .section .text.smp_entry,"ax",@progbits
+ .align 2
+ .global smp_entry
+ .type smp_entry, %function
+smp_entry:
+.LFB236:
+ .loc 1 448 0
+ .cfi_startproc
+.LVL110:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ .loc 1 448 0
+ mov w19, w0
+ .loc 1 450 0
+ adrp x0, .LANCHOR1
+.LVL111:
+ ldr x0, [x0, #:lo12:.LANCHOR1]
+.LVL112:
+.LBB106:
+.LBB107:
+ .loc 1 131 0
+#APP
+// 131 "common/mp_boot.c" 1
+ mov x18, x0
+
+// 0 "" 2
+.LVL113:
+#NO_APP
+.LBE107:
+.LBE106:
+ .loc 1 451 0
+ bl dcache_enable
+.LVL114:
+ .loc 1 455 0
+ cmp w19, 1
+ bne .L110
+.L114:
+ .loc 1 460 0
+ mov w0, w19
+ bl core_main
+.LVL115:
+ b .L111
+.L110:
+ .loc 1 459 0
+ cmp w19, 2
+ beq .L114
+.L111:
+ .loc 1 468 0
+ bl flush_dcache_all
+.LVL116:
+ .loc 1 469 0
+ bl disable_interrupts
+.LVL117:
+.LBB108:
+.LBB109:
+ .file 3 "./arch/arm/include/asm/system.h"
+ .loc 3 193 0
+#APP
+// 193 "./arch/arm/include/asm/system.h" 1
+ msr daifset, #0x04
+// 0 "" 2
+#NO_APP
+.LBE109:
+.LBE108:
+ .loc 1 471 0
+ bl icache_disable
+.LVL118:
+ .loc 1 472 0
+ bl invalidate_icache_all
+.LVL119:
+ .loc 1 473 0
+ bl dcache_disable
+.LVL120:
+.LBB110:
+.LBB111:
+ .loc 1 138 0
+#APP
+// 138 "common/mp_boot.c" 1
+ mrs x0, S3_1_c15_c2_1
+// 0 "" 2
+ .loc 1 139 0
+// 139 "common/mp_boot.c" 1
+ bic x0, x0, #0x40
+// 0 "" 2
+ .loc 1 140 0
+// 140 "common/mp_boot.c" 1
+ msr S3_1_c15_c2_1, x0
+// 0 "" 2
+#NO_APP
+.LBE111:
+.LBE110:
+ .loc 1 475 0
+ bl invalidate_dcache_all
+.LVL121:
+ .loc 1 478 0
+#APP
+// 478 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 479 0
+// 479 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+#NO_APP
+.L112:
+ .loc 1 481 0 discriminator 1
+#APP
+// 481 "common/mp_boot.c" 1
+ wfe
+// 0 "" 2
+#NO_APP
+ b .L112
+ .cfi_endproc
+.LFE236:
+ .size smp_entry, .-smp_entry
+ .section .text.mpb_init_1,"ax",@progbits
+ .align 2
+ .global mpb_init_1
+ .type mpb_init_1, %function
+mpb_init_1:
+.LFB238:
+ .loc 1 527 0
+ .cfi_startproc
+ stp x29, x30, [sp, -16]!
+ .cfi_def_cfa_offset 16
+ .cfi_offset 29, -16
+ .cfi_offset 30, -8
+ .loc 1 528 0
+ mov x2, 40
+ mov x1, x0
+ mov x0, 1320
+ .loc 1 527 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 528 0
+ movk x0, 0x820, lsl 16
+ .loc 1 527 0
+ .loc 1 528 0
+ bl memcpy
+.LVL122:
+ .loc 1 530 0
+ mov w1, 2
+ mov w0, 0
+ bl mpb_task_run
+.LVL123:
+ .loc 1 531 0
+ mov w2, 286331153
+ mov w1, 3
+ mov w0, 0
+ bl mpb_task_set_state
+.LVL124:
+ .loc 1 532 0
+ bl flush_dcache_all
+.LVL125:
+ .loc 1 533 0
+#APP
+// 533 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 534 0
+// 534 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+ .loc 1 535 0
+#NO_APP
+ ldp x29, x30, [sp], 16
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE238:
+ .size mpb_init_1, .-mpb_init_1
+ .section .text.mpb_init_x,"ax",@progbits
+ .align 2
+ .global mpb_init_x
+ .type mpb_init_x, %function
+mpb_init_x:
+.LFB239:
+ .loc 1 538 0
+ .cfi_startproc
+.LVL126:
+ stp x29, x30, [sp, -64]!
+ .cfi_def_cfa_offset 64
+ .cfi_offset 29, -64
+ .cfi_offset 30, -56
+ .loc 1 539 0
+ cmp w0, 2
+ .loc 1 538 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 539 0
+ beq .L119
+ cmp w0, 3
+ beq .L120
+ cbnz w0, .L117
+.LBB120:
+.LBB121:
+ .loc 1 494 0
+ adrp x1, .LANCHOR2
+ add x1, x1, :lo12:.LANCHOR2
+ mov x2, 48
+ add x0, x29, 16
+.LVL127:
+ bl memcpy
+.LVL128:
+ .loc 1 509 0
+ adrp x0, .LC13
+ add x0, x0, :lo12:.LC13
+ bl printf
+.LVL129:
+ .loc 1 511 0
+ mov x2, 1376
+ mov w1, 0
+ mov x0, 136314880
+ bl memset
+.LVL130:
+ .loc 1 512 0
+ adrp x0, .LANCHOR1
+ add x6, x29, 64
+.LBB122:
+.LBB123:
+ .loc 1 177 0
+ mov x4, 136314880
+ mov x7, 328
+.LBE123:
+.LBE122:
+ .loc 1 512 0
+ str x18, [x0, #:lo12:.LANCHOR1]
+.LVL131:
+ add x0, x29, 16
+.LBB126:
+.LBB124:
+ .loc 1 179 0
+ mov x8, 40
+ .loc 1 185 0
+ mov w10, 1
+.LVL132:
+.L122:
+.LBE124:
+.LBE126:
+ .loc 1 514 0
+ cmp x6, x0
+ bne .L124
+ .loc 1 517 0
+ bl flush_dcache_all
+.LVL133:
+.LBB127:
+ .loc 1 518 0
+#APP
+// 518 "common/mp_boot.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov x1, 8
+ adrp x0, save_boot_params_ret
+ movk x1, 0xfe48, lsl 16
+ add x0, x0, :lo12:save_boot_params_ret
+ str w0, [x1]
+.LVL134:
+.LBE127:
+.LBB128:
+ .loc 1 519 0
+#APP
+// 519 "common/mp_boot.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov x0, 4
+ mov w1, 48815
+ movk x0, 0xfe48, lsl 16
+ movk w1, 0xdead, lsl 16
+ str w1, [x0]
+.LBE128:
+ .loc 1 520 0
+#APP
+// 520 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 522 0
+// 522 "common/mp_boot.c" 1
+ sev
+// 0 "" 2
+ .loc 1 523 0
+// 523 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+.LVL135:
+#NO_APP
+.L117:
+.LBE121:
+.LBE120:
+ .loc 1 556 0
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+.L124:
+ .cfi_restore_state
+ ldp w1, w3, [x0]
+.LVL136:
+ ldp w12, w11, [x0, 16]
+.LBB131:
+.LBB130:
+.LBB129:
+.LBB125:
+ .loc 1 172 0
+ cmp w1, 3
+ ldr x13, [x0, 8]
+.LVL137:
+ beq .L123
+ .loc 1 176 0
+ sub w2, w3, #1
+ cmp w2, 6
+ bhi .L123
+.LVL138:
+ .loc 1 177 0
+ uxtw x1, w1
+ mul x2, x1, x7
+ add x5, x4, x2
+ .loc 1 179 0
+ ldrb w1, [x5, 328]
+.LVL139:
+ madd x1, x1, x8, x2
+ add x1, x4, x1
+ .loc 1 181 0
+ stp w3, w12, [x1, 20]
+.LVL140:
+ .loc 1 185 0
+ lsl w3, w10, w3
+.LVL141:
+ .loc 1 183 0
+ stp w11, wzr, [x1, 28]
+ .loc 1 179 0
+ str x13, [x1, 8]
+ .loc 1 184 0
+ str xzr, [x1, 40]
+ .loc 1 185 0
+ ldr w1, [x4]
+.LVL142:
+ orr w3, w1, w3
+ str w3, [x4]
+ .loc 1 186 0
+ ldrb w1, [x5, 328]
+ add w1, w1, 1
+ strb w1, [x5, 328]
+.L123:
+ add x0, x0, 24
+ b .L122
+.LVL143:
+.L119:
+.LBE125:
+.LBE129:
+.LBE130:
+.LBE131:
+ .loc 1 544 0
+ mov w2, -559087616
+ mov w1, 3
+ mov w0, 0
+.LVL144:
+ bl mpb_task_set_state
+.LVL145:
+ .loc 1 545 0
+ bl flush_dcache_all
+.LVL146:
+ .loc 1 546 0
+#APP
+// 546 "common/mp_boot.c" 1
+ dsb sy
+// 0 "" 2
+ .loc 1 547 0
+// 547 "common/mp_boot.c" 1
+ isb sy
+// 0 "" 2
+.LVL147:
+ .loc 1 556 0
+#NO_APP
+ ldp x29, x30, [sp], 64
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+.LBB132:
+.LBB133:
+ .loc 2 16 0
+ mov x0, 1000
+ b udelay
+.LVL148:
+.L120:
+ .cfi_restore_state
+.LBE133:
+.LBE132:
+ .loc 1 556 0
+ ldp x29, x30, [sp], 64
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ .loc 1 553 0
+ mov w2, -559087616
+ mov w1, 7
+ mov w0, 0
+.LVL149:
+ b mpb_task_set_state
+.LVL150:
+ .cfi_endproc
+.LFE239:
+ .size mpb_init_x, .-mpb_init_x
+ .section .text.mpb_post,"ax",@progbits
+ .align 2
+ .global mpb_post
+ .type mpb_post, %function
+mpb_post:
+.LFB240:
+ .loc 1 626 0
+ .cfi_startproc
+.LVL151:
+ .loc 1 627 0
+ cmp w0, 6
+ bne .L133
+ .loc 1 626 0
+ stp x29, x30, [sp, -16]!
+ .cfi_def_cfa_offset 16
+ .cfi_offset 29, -16
+ .cfi_offset 30, -8
+ .loc 1 629 0
+ mov w0, 2
+.LVL152:
+ .loc 1 626 0
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ .loc 1 629 0
+ bl mpb_task_wait_done
+.LVL153:
+ sxtw x0, w0
+ .loc 1 633 0
+ ldp x29, x30, [sp], 16
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_def_cfa 31, 0
+ ret
+.LVL154:
+.L133:
+ .loc 1 632 0
+ mov x0, 0
+.LVL155:
+ ret
+ .cfi_endproc
+.LFE240:
+ .size mpb_post, .-mpb_post
+ .section .rodata
+ .align 3
+ .set .LANCHOR2,. + 0
+.LC0:
+ .word 0
+ .word 2
+ .xword spl_load_baseparamter
+ .word 0
+ .word 0
+ .word 2
+ .word 1
+ .xword spl_init_display
+ .word 0
+ .word 0
+ .section .bss.mpb_gd,"aw",@nobits
+ .align 3
+ .set .LANCHOR1,. + 0
+ .type mpb_gd, %object
+ .size mpb_gd, 8
+mpb_gd:
+ .zero 8
+ .section .rodata.core_task_run.part.1.str1.1,"aMS",@progbits,1
+.LC10:
+ .string "-- T%d.%d [%d, %ld]\n"
+.LC11:
+ .string "++ T%d.%d -\n"
+.LC12:
+ .string "++ T%d.%d\n"
+ .section .rodata.mpb_init_x.str1.1,"aMS",@progbits,1
+.LC13:
+ .string "U-Boot SPL MP\n"
+ .section .rodata.mpb_task_dump.str1.1,"aMS",@progbits,1
+.LC1:
+ .string "data: %08lx, %08lx\n"
+.LC2:
+ .string "T%d.%d:[%s]\n"
+.LC3:
+ .string " tid: %d\n"
+.LC4:
+ .string " fn: 0x%08lx\n"
+.LC5:
+ .string " state: 0x%08x\n"
+.LC6:
+ .string " ret: %d\n"
+.LC7:
+ .string " ms: %ld\n"
+.LC8:
+ .string " ptid_mask: 0x%08x\n"
+.LC9:
+ .string " rip_fail: %d\n\n"
+ .section .rodata.str1.1,"aMS",@progbits,1
+.LC14:
+ .string "none"
+.LC15:
+ .string "init-display"
+.LC16:
+ .string "load-baseparameter"
+.LC17:
+ .string "load-uboot"
+.LC18:
+ .string "load-fit"
+.LC19:
+ .string "load-android"
+.LC20:
+ .string "hash-android"
+.LC21:
+ .string "run-uboot"
+ .section .rodata.tid_name,"a",@progbits
+ .align 3
+ .set .LANCHOR0,. + 0
+ .type tid_name, %object
+ .size tid_name, 64
+tid_name:
+ .xword .LC14
+ .xword .LC15
+ .xword .LC16
+ .xword .LC17
+ .xword .LC18
+ .xword .LC19
+ .xword .LC20
+ .xword .LC21
+ .text
+.Letext0:
+ .file 4 "include/common.h"
+ .file 5 "./arch/arm/include/asm/types.h"
+ .file 6 "include/linux/types.h"
+ .file 7 "include/errno.h"
+ .file 8 "include/linux/string.h"
+ .file 9 "include/efi.h"
+ .file 10 "include/ide.h"
+ .file 11 "include/linux/list.h"
+ .file 12 "include/part.h"
+ .file 13 "include/flash.h"
+ .file 14 "include/lmb.h"
+ .file 15 "include/asm-generic/u-boot.h"
+ .file 16 "./arch/arm/include/asm/u-boot-arm.h"
+ .file 17 "include/linux/libfdt_env.h"
+ .file 18 "include/linux/../../scripts/dtc/libfdt/fdt.h"
+ .file 19 "include/linux/libfdt.h"
+ .file 20 "include/image.h"
+ .file 21 "./arch/arm/include/asm/global_data.h"
+ .file 22 "include/asm-generic/global_data.h"
+ .file 23 "include/net.h"
+ .file 24 "include/dm/uclass-id.h"
+ .file 25 "./arch/arm/include/asm/spl.h"
+ .file 26 "include/spl.h"
+ .file 27 "include/mp_boot.h"
+ .file 28 "include/log.h"
+ .file 29 "include/stdio.h"
+ .section .debug_info,"",@progbits
+.Ldebug_info0:
+ .4byte 0x2374
+ .2byte 0x4
+ .4byte .Ldebug_abbrev0
+ .byte 0x8
+ .uleb128 0x1
+ .4byte .LASF428
+ .byte 0xc
+ .4byte .LASF429
+ .4byte .LASF430
+ .4byte .Ldebug_ranges0+0x230
+ .8byte 0
+ .4byte .Ldebug_line0
+ .uleb128 0x2
+ .4byte .LASF4
+ .byte 0x4
+ .byte 0xd
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF0
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF1
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x7
+ .4byte .LASF2
+ .uleb128 0x4
+ .4byte .LASF20
+ .byte 0x7
+ .byte 0xc
+ .4byte 0x54
+ .uleb128 0x5
+ .byte 0x4
+ .byte 0x5
+ .string "int"
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x6
+ .4byte .LASF3
+ .uleb128 0x2
+ .4byte .LASF5
+ .byte 0x5
+ .byte 0xc
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x5
+ .4byte .LASF6
+ .uleb128 0x2
+ .4byte .LASF7
+ .byte 0x5
+ .byte 0x12
+ .4byte 0x7f
+ .uleb128 0x3
+ .byte 0x4
+ .byte 0x7
+ .4byte .LASF8
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF9
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF10
+ .uleb128 0x6
+ .string "u8"
+ .byte 0x5
+ .byte 0x1f
+ .4byte 0x34
+ .uleb128 0x7
+ .4byte 0x94
+ .uleb128 0x6
+ .string "u32"
+ .byte 0x5
+ .byte 0x25
+ .4byte 0x7f
+ .uleb128 0x6
+ .string "u64"
+ .byte 0x5
+ .byte 0x28
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF11
+ .byte 0x5
+ .byte 0x31
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF12
+ .byte 0x5
+ .byte 0x32
+ .4byte 0x8d
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF13
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe3
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF14
+ .uleb128 0x7
+ .4byte 0xdc
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF15
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xdc
+ .uleb128 0x2
+ .4byte .LASF16
+ .byte 0x6
+ .byte 0x59
+ .4byte 0x42
+ .uleb128 0x2
+ .4byte .LASF17
+ .byte 0x6
+ .byte 0x5b
+ .4byte 0x3b
+ .uleb128 0x9
+ .4byte 0x100
+ .uleb128 0x2
+ .4byte .LASF18
+ .byte 0x6
+ .byte 0x69
+ .4byte 0x62
+ .uleb128 0x2
+ .4byte .LASF19
+ .byte 0x6
+ .byte 0x97
+ .4byte 0x74
+ .uleb128 0xa
+ .byte 0x8
+ .uleb128 0x4
+ .4byte .LASF21
+ .byte 0x8
+ .byte 0xb
+ .4byte 0xef
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x2
+ .4byte .LASF22
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0x145
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF23
+ .byte 0x9
+ .2byte 0x140
+ .4byte 0x13a
+ .uleb128 0xd
+ .4byte .LASF24
+ .byte 0x9
+ .2byte 0x143
+ .4byte 0x13a
+ .uleb128 0xd
+ .4byte .LASF25
+ .byte 0x9
+ .2byte 0x143
+ .4byte 0x13a
+ .uleb128 0xe
+ .4byte .LASF38
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x169
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x17a
+ .uleb128 0xf
+ .uleb128 0xb
+ .4byte 0x100
+ .4byte 0x186
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF26
+ .byte 0xa
+ .byte 0x10
+ .4byte 0x17b
+ .uleb128 0xb
+ .4byte 0x34
+ .4byte 0x1a1
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x5
+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF29
+ .byte 0x10
+ .byte 0xb
+ .byte 0x16
+ .4byte 0x1c6
+ .uleb128 0x12
+ .4byte .LASF27
+ .byte 0xb
+ .byte 0x17
+ .4byte 0x1c6
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF28
+ .byte 0xb
+ .byte 0x17
+ .4byte 0x1c6
+ .byte 0x8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1a1
+ .uleb128 0x11
+ .4byte .LASF30
+ .byte 0x10
+ .byte 0xc
+ .byte 0xf
+ .4byte 0x1f1
+ .uleb128 0x12
+ .4byte .LASF31
+ .byte 0xc
+ .byte 0x10
+ .4byte 0xef
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF32
+ .byte 0xc
+ .byte 0x11
+ .4byte 0x20a
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x1cc
+ .uleb128 0x13
+ .4byte 0x54
+ .4byte 0x20a
+ .uleb128 0x14
+ .4byte 0x54
+ .uleb128 0x14
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1f6
+ .uleb128 0xb
+ .4byte 0x1f1
+ .4byte 0x21b
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x210
+ .uleb128 0x4
+ .4byte .LASF30
+ .byte 0xc
+ .byte 0xe1
+ .4byte 0x21b
+ .uleb128 0x15
+ .2byte 0x1220
+ .byte 0xd
+ .byte 0x13
+ .4byte 0x27f
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xd
+ .byte 0x14
+ .4byte 0x100
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF34
+ .byte 0xd
+ .byte 0x15
+ .4byte 0xf5
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF35
+ .byte 0xd
+ .byte 0x16
+ .4byte 0x100
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF36
+ .byte 0xd
+ .byte 0x17
+ .4byte 0x27f
+ .byte 0x18
+ .uleb128 0x16
+ .4byte .LASF37
+ .byte 0xd
+ .byte 0x18
+ .4byte 0x290
+ .2byte 0x1018
+ .uleb128 0x17
+ .string "mtd"
+ .byte 0xd
+ .byte 0x31
+ .4byte 0x2a6
+ .2byte 0x1218
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x100
+ .4byte 0x290
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x29
+ .4byte 0x2a1
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF39
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x2a1
+ .uleb128 0x2
+ .4byte .LASF40
+ .byte 0xd
+ .byte 0x37
+ .4byte 0x22b
+ .uleb128 0xb
+ .4byte 0x2ac
+ .4byte 0x2c2
+ .uleb128 0xc
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF41
+ .byte 0xd
+ .byte 0x39
+ .4byte 0x2b7
+ .uleb128 0x3
+ .byte 0x10
+ .byte 0x4
+ .4byte .LASF42
+ .uleb128 0x11
+ .4byte .LASF43
+ .byte 0x10
+ .byte 0xe
+ .byte 0x10
+ .4byte 0x2f9
+ .uleb128 0x12
+ .4byte .LASF44
+ .byte 0xe
+ .byte 0x11
+ .4byte 0xb9
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xe
+ .byte 0x12
+ .4byte 0xc4
+ .byte 0x8
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF45
+ .2byte 0x120
+ .byte 0xe
+ .byte 0x15
+ .4byte 0x32b
+ .uleb128 0x1a
+ .string "cnt"
+ .byte 0xe
+ .byte 0x16
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xe
+ .byte 0x17
+ .4byte 0xc4
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF46
+ .byte 0xe
+ .byte 0x18
+ .4byte 0x32b
+ .byte 0x10
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x2d4
+ .4byte 0x33b
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x10
+ .byte 0
+ .uleb128 0x1b
+ .string "lmb"
+ .2byte 0x240
+ .byte 0xe
+ .byte 0x1b
+ .4byte 0x362
+ .uleb128 0x12
+ .4byte .LASF47
+ .byte 0xe
+ .byte 0x1c
+ .4byte 0x2f9
+ .byte 0
+ .uleb128 0x16
+ .4byte .LASF48
+ .byte 0xe
+ .byte 0x1d
+ .4byte 0x2f9
+ .2byte 0x120
+ .byte 0
+ .uleb128 0x1c
+ .string "lmb"
+ .byte 0xe
+ .byte 0x20
+ .4byte 0x33b
+ .uleb128 0x1d
+ .byte 0x10
+ .byte 0xf
+ .byte 0x5b
+ .4byte 0x38e
+ .uleb128 0x12
+ .4byte .LASF36
+ .byte 0xf
+ .byte 0x5c
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF33
+ .byte 0xf
+ .byte 0x5d
+ .4byte 0xae
+ .byte 0x8
+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF49
+ .byte 0xa8
+ .byte 0xf
+ .byte 0x1b
+ .4byte 0x47f
+ .uleb128 0x12
+ .4byte .LASF50
+ .byte 0xf
+ .byte 0x1c
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF51
+ .byte 0xf
+ .byte 0x1d
+ .4byte 0xc4
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF52
+ .byte 0xf
+ .byte 0x1e
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF53
+ .byte 0xf
+ .byte 0x1f
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF54
+ .byte 0xf
+ .byte 0x20
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF55
+ .byte 0xf
+ .byte 0x21
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF56
+ .byte 0xf
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0x12
+ .4byte .LASF57
+ .byte 0xf
+ .byte 0x24
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0x12
+ .4byte .LASF58
+ .byte 0xf
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0x12
+ .4byte .LASF59
+ .byte 0xf
+ .byte 0x26
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0x12
+ .4byte .LASF60
+ .byte 0xf
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0x12
+ .4byte .LASF61
+ .byte 0xf
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0x12
+ .4byte .LASF62
+ .byte 0xf
+ .byte 0x33
+ .4byte 0x191
+ .byte 0x60
+ .uleb128 0x12
+ .4byte .LASF63
+ .byte 0xf
+ .byte 0x34
+ .4byte 0x42
+ .byte 0x66
+ .uleb128 0x12
+ .4byte .LASF64
+ .byte 0xf
+ .byte 0x35
+ .4byte 0x3b
+ .byte 0x68
+ .uleb128 0x12
+ .4byte .LASF65
+ .byte 0xf
+ .byte 0x36
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0x12
+ .4byte .LASF66
+ .byte 0xf
+ .byte 0x57
+ .4byte 0x100
+ .byte 0x78
+ .uleb128 0x12
+ .4byte .LASF67
+ .byte 0xf
+ .byte 0x58
+ .4byte 0x100
+ .byte 0x80
+ .uleb128 0x12
+ .4byte .LASF68
+ .byte 0xf
+ .byte 0x5e
+ .4byte 0x47f
+ .byte 0x88
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x36d
+ .4byte 0x48f
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF69
+ .byte 0xf
+ .byte 0x60
+ .4byte 0x38e
+ .uleb128 0x4
+ .4byte .LASF70
+ .byte 0x10
+ .byte 0x13
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF71
+ .byte 0x10
+ .byte 0x14
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF72
+ .byte 0x10
+ .byte 0x15
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF73
+ .byte 0x10
+ .byte 0x16
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF74
+ .byte 0x10
+ .byte 0x17
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF75
+ .byte 0x10
+ .byte 0x18
+ .4byte 0x100
+ .uleb128 0x4
+ .4byte .LASF76
+ .byte 0x10
+ .byte 0x19
+ .4byte 0x100
+ .uleb128 0x2
+ .4byte .LASF77
+ .byte 0x11
+ .byte 0x11
+ .4byte 0x11b
+ .uleb128 0x11
+ .4byte .LASF78
+ .byte 0x28
+ .byte 0x12
+ .byte 0x39
+ .4byte 0x577
+ .uleb128 0x12
+ .4byte .LASF79
+ .byte 0x12
+ .byte 0x3a
+ .4byte 0x4e7
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF80
+ .byte 0x12
+ .byte 0x3b
+ .4byte 0x4e7
+ .byte 0x4
+ .uleb128 0x12
+ .4byte .LASF81
+ .byte 0x12
+ .byte 0x3c
+ .4byte 0x4e7
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF82
+ .byte 0x12
+ .byte 0x3d
+ .4byte 0x4e7
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF83
+ .byte 0x12
+ .byte 0x3e
+ .4byte 0x4e7
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF84
+ .byte 0x12
+ .byte 0x3f
+ .4byte 0x4e7
+ .byte 0x14
+ .uleb128 0x12
+ .4byte .LASF85
+ .byte 0x12
+ .byte 0x40
+ .4byte 0x4e7
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF86
+ .byte 0x12
+ .byte 0x43
+ .4byte 0x4e7
+ .byte 0x1c
+ .uleb128 0x12
+ .4byte .LASF87
+ .byte 0x12
+ .byte 0x46
+ .4byte 0x4e7
+ .byte 0x20
+ .uleb128 0x12
+ .4byte .LASF88
+ .byte 0x12
+ .byte 0x49
+ .4byte 0x4e7
+ .byte 0x24
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF89
+ .byte 0x13
+ .2byte 0x136
+ .4byte 0x583
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x4f2
+ .uleb128 0x1e
+ .4byte .LASF90
+ .byte 0x40
+ .byte 0x14
+ .2byte 0x137
+ .4byte 0x633
+ .uleb128 0x1f
+ .4byte .LASF91
+ .byte 0x14
+ .2byte 0x138
+ .4byte 0x11b
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF92
+ .byte 0x14
+ .2byte 0x139
+ .4byte 0x11b
+ .byte 0x4
+ .uleb128 0x1f
+ .4byte .LASF93
+ .byte 0x14
+ .2byte 0x13a
+ .4byte 0x11b
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF94
+ .byte 0x14
+ .2byte 0x13b
+ .4byte 0x11b
+ .byte 0xc
+ .uleb128 0x1f
+ .4byte .LASF95
+ .byte 0x14
+ .2byte 0x13c
+ .4byte 0x11b
+ .byte 0x10
+ .uleb128 0x1f
+ .4byte .LASF96
+ .byte 0x14
+ .2byte 0x13d
+ .4byte 0x11b
+ .byte 0x14
+ .uleb128 0x1f
+ .4byte .LASF97
+ .byte 0x14
+ .2byte 0x13e
+ .4byte 0x11b
+ .byte 0x18
+ .uleb128 0x1f
+ .4byte .LASF98
+ .byte 0x14
+ .2byte 0x13f
+ .4byte 0x110
+ .byte 0x1c
+ .uleb128 0x1f
+ .4byte .LASF99
+ .byte 0x14
+ .2byte 0x140
+ .4byte 0x110
+ .byte 0x1d
+ .uleb128 0x1f
+ .4byte .LASF100
+ .byte 0x14
+ .2byte 0x141
+ .4byte 0x110
+ .byte 0x1e
+ .uleb128 0x1f
+ .4byte .LASF101
+ .byte 0x14
+ .2byte 0x142
+ .4byte 0x110
+ .byte 0x1f
+ .uleb128 0x1f
+ .4byte .LASF102
+ .byte 0x14
+ .2byte 0x143
+ .4byte 0x633
+ .byte 0x20
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x110
+ .4byte 0x643
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x20
+ .4byte .LASF103
+ .byte 0x14
+ .2byte 0x144
+ .4byte 0x589
+ .uleb128 0x1e
+ .4byte .LASF104
+ .byte 0x30
+ .byte 0x14
+ .2byte 0x146
+ .4byte 0x6d1
+ .uleb128 0x1f
+ .4byte .LASF36
+ .byte 0x14
+ .2byte 0x147
+ .4byte 0x100
+ .byte 0
+ .uleb128 0x21
+ .string "end"
+ .byte 0x14
+ .2byte 0x147
+ .4byte 0x100
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF105
+ .byte 0x14
+ .2byte 0x148
+ .4byte 0x100
+ .byte 0x10
+ .uleb128 0x1f
+ .4byte .LASF106
+ .byte 0x14
+ .2byte 0x148
+ .4byte 0x100
+ .byte 0x18
+ .uleb128 0x1f
+ .4byte .LASF107
+ .byte 0x14
+ .2byte 0x149
+ .4byte 0x100
+ .byte 0x20
+ .uleb128 0x1f
+ .4byte .LASF108
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x28
+ .uleb128 0x1f
+ .4byte .LASF109
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x29
+ .uleb128 0x21
+ .string "os"
+ .byte 0x14
+ .2byte 0x14a
+ .4byte 0x110
+ .byte 0x2a
+ .uleb128 0x1f
+ .4byte .LASF110
+ .byte 0x14
+ .2byte 0x14b
+ .4byte 0x110
+ .byte 0x2b
+ .byte 0
+ .uleb128 0x20
+ .4byte .LASF111
+ .byte 0x14
+ .2byte 0x14c
+ .4byte 0x64f
+ .uleb128 0x22
+ .4byte .LASF112
+ .2byte 0x380
+ .byte 0x14
+ .2byte 0x152
+ .4byte 0x87a
+ .uleb128 0x1f
+ .4byte .LASF113
+ .byte 0x14
+ .2byte 0x158
+ .4byte 0x87a
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF114
+ .byte 0x14
+ .2byte 0x159
+ .4byte 0x643
+ .byte 0x8
+ .uleb128 0x1f
+ .4byte .LASF115
+ .byte 0x14
+ .2byte 0x15a
+ .4byte 0x100
+ .byte 0x48
+ .uleb128 0x1f
+ .4byte .LASF116
+ .byte 0x14
+ .2byte 0x15d
+ .4byte 0xd6
+ .byte 0x50
+ .uleb128 0x1f
+ .4byte .LASF117
+ .byte 0x14
+ .2byte 0x15f
+ .4byte 0x126
+ .byte 0x58
+ .uleb128 0x1f
+ .4byte .LASF118
+ .byte 0x14
+ .2byte 0x160
+ .4byte 0xd6
+ .byte 0x60
+ .uleb128 0x1f
+ .4byte .LASF119
+ .byte 0x14
+ .2byte 0x161
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0x1f
+ .4byte .LASF120
+ .byte 0x14
+ .2byte 0x163
+ .4byte 0x126
+ .byte 0x70
+ .uleb128 0x1f
+ .4byte .LASF121
+ .byte 0x14
+ .2byte 0x164
+ .4byte 0xd6
+ .byte 0x78
+ .uleb128 0x1f
+ .4byte .LASF122
+ .byte 0x14
+ .2byte 0x165
+ .4byte 0x54
+ .byte 0x80
+ .uleb128 0x1f
+ .4byte .LASF123
+ .byte 0x14
+ .2byte 0x167
+ .4byte 0x126
+ .byte 0x88
+ .uleb128 0x1f
+ .4byte .LASF124
+ .byte 0x14
+ .2byte 0x168
+ .4byte 0xd6
+ .byte 0x90
+ .uleb128 0x1f
+ .4byte .LASF125
+ .byte 0x14
+ .2byte 0x169
+ .4byte 0x54
+ .byte 0x98
+ .uleb128 0x1f
+ .4byte .LASF126
+ .byte 0x14
+ .2byte 0x16b
+ .4byte 0x126
+ .byte 0xa0
+ .uleb128 0x1f
+ .4byte .LASF127
+ .byte 0x14
+ .2byte 0x16c
+ .4byte 0xd6
+ .byte 0xa8
+ .uleb128 0x1f
+ .4byte .LASF128
+ .byte 0x14
+ .2byte 0x16d
+ .4byte 0x54
+ .byte 0xb0
+ .uleb128 0x21
+ .string "os"
+ .byte 0x14
+ .2byte 0x171
+ .4byte 0x6d1
+ .byte 0xb8
+ .uleb128 0x21
+ .string "ep"
+ .byte 0x14
+ .2byte 0x172
+ .4byte 0x100
+ .byte 0xe8
+ .uleb128 0x1f
+ .4byte .LASF129
+ .byte 0x14
+ .2byte 0x174
+ .4byte 0x100
+ .byte 0xf0
+ .uleb128 0x1f
+ .4byte .LASF130
+ .byte 0x14
+ .2byte 0x174
+ .4byte 0x100
+ .byte 0xf8
+ .uleb128 0x23
+ .4byte .LASF131
+ .byte 0x14
+ .2byte 0x176
+ .4byte 0xef
+ .2byte 0x100
+ .uleb128 0x23
+ .4byte .LASF132
+ .byte 0x14
+ .2byte 0x177
+ .4byte 0x100
+ .2byte 0x108
+ .uleb128 0x23
+ .4byte .LASF133
+ .byte 0x14
+ .2byte 0x179
+ .4byte 0x100
+ .2byte 0x110
+ .uleb128 0x23
+ .4byte .LASF134
+ .byte 0x14
+ .2byte 0x17a
+ .4byte 0x100
+ .2byte 0x118
+ .uleb128 0x23
+ .4byte .LASF135
+ .byte 0x14
+ .2byte 0x17b
+ .4byte 0x100
+ .2byte 0x120
+ .uleb128 0x23
+ .4byte .LASF136
+ .byte 0x14
+ .2byte 0x17c
+ .4byte 0x100
+ .2byte 0x128
+ .uleb128 0x24
+ .string "kbd"
+ .byte 0x14
+ .2byte 0x17d
+ .4byte 0x880
+ .2byte 0x130
+ .uleb128 0x23
+ .4byte .LASF137
+ .byte 0x14
+ .2byte 0x180
+ .4byte 0x54
+ .2byte 0x138
+ .uleb128 0x23
+ .4byte .LASF138
+ .byte 0x14
+ .2byte 0x18d
+ .4byte 0x54
+ .2byte 0x13c
+ .uleb128 0x24
+ .string "lmb"
+ .byte 0x14
+ .2byte 0x190
+ .4byte 0x33b
+ .2byte 0x140
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x643
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x48f
+ .uleb128 0x20
+ .4byte .LASF139
+ .byte 0x14
+ .2byte 0x196
+ .4byte 0x6dd
+ .uleb128 0xd
+ .4byte .LASF140
+ .byte 0x14
+ .2byte 0x198
+ .4byte 0x886
+ .uleb128 0xb
+ .4byte 0xdc
+ .4byte 0x8af
+ .uleb128 0x18
+ .4byte 0xcf
+ .2byte 0x3ff
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF331
+ .byte 0x4
+ .4byte 0x54
+ .byte 0x18
+ .byte 0xe
+ .4byte 0xb18
+ .uleb128 0x26
+ .4byte .LASF141
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF142
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF143
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF144
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF145
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF146
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF147
+ .byte 0x6
+ .uleb128 0x26
+ .4byte .LASF148
+ .byte 0x7
+ .uleb128 0x26
+ .4byte .LASF149
+ .byte 0x8
+ .uleb128 0x26
+ .4byte .LASF150
+ .byte 0x9
+ .uleb128 0x26
+ .4byte .LASF151
+ .byte 0xa
+ .uleb128 0x26
+ .4byte .LASF152
+ .byte 0xb
+ .uleb128 0x26
+ .4byte .LASF153
+ .byte 0xc
+ .uleb128 0x26
+ .4byte .LASF154
+ .byte 0xd
+ .uleb128 0x26
+ .4byte .LASF155
+ .byte 0xe
+ .uleb128 0x26
+ .4byte .LASF156
+ .byte 0xf
+ .uleb128 0x26
+ .4byte .LASF157
+ .byte 0x10
+ .uleb128 0x26
+ .4byte .LASF158
+ .byte 0x11
+ .uleb128 0x26
+ .4byte .LASF159
+ .byte 0x12
+ .uleb128 0x26
+ .4byte .LASF160
+ .byte 0x13
+ .uleb128 0x26
+ .4byte .LASF161
+ .byte 0x14
+ .uleb128 0x26
+ .4byte .LASF162
+ .byte 0x15
+ .uleb128 0x26
+ .4byte .LASF163
+ .byte 0x16
+ .uleb128 0x26
+ .4byte .LASF164
+ .byte 0x17
+ .uleb128 0x26
+ .4byte .LASF165
+ .byte 0x18
+ .uleb128 0x26
+ .4byte .LASF166
+ .byte 0x19
+ .uleb128 0x26
+ .4byte .LASF167
+ .byte 0x1a
+ .uleb128 0x26
+ .4byte .LASF168
+ .byte 0x1b
+ .uleb128 0x26
+ .4byte .LASF169
+ .byte 0x1c
+ .uleb128 0x26
+ .4byte .LASF170
+ .byte 0x1d
+ .uleb128 0x26
+ .4byte .LASF171
+ .byte 0x1e
+ .uleb128 0x26
+ .4byte .LASF172
+ .byte 0x1f
+ .uleb128 0x26
+ .4byte .LASF173
+ .byte 0x20
+ .uleb128 0x26
+ .4byte .LASF174
+ .byte 0x21
+ .uleb128 0x26
+ .4byte .LASF175
+ .byte 0x22
+ .uleb128 0x26
+ .4byte .LASF176
+ .byte 0x23
+ .uleb128 0x26
+ .4byte .LASF177
+ .byte 0x24
+ .uleb128 0x26
+ .4byte .LASF178
+ .byte 0x25
+ .uleb128 0x26
+ .4byte .LASF179
+ .byte 0x26
+ .uleb128 0x26
+ .4byte .LASF180
+ .byte 0x27
+ .uleb128 0x26
+ .4byte .LASF181
+ .byte 0x28
+ .uleb128 0x26
+ .4byte .LASF182
+ .byte 0x29
+ .uleb128 0x26
+ .4byte .LASF183
+ .byte 0x2a
+ .uleb128 0x26
+ .4byte .LASF184
+ .byte 0x2b
+ .uleb128 0x26
+ .4byte .LASF185
+ .byte 0x2c
+ .uleb128 0x26
+ .4byte .LASF186
+ .byte 0x2d
+ .uleb128 0x26
+ .4byte .LASF187
+ .byte 0x2e
+ .uleb128 0x26
+ .4byte .LASF188
+ .byte 0x2f
+ .uleb128 0x26
+ .4byte .LASF189
+ .byte 0x30
+ .uleb128 0x26
+ .4byte .LASF190
+ .byte 0x31
+ .uleb128 0x26
+ .4byte .LASF191
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+ .4byte .LASF193
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+ .4byte .LASF194
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+ .4byte .LASF195
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+ .4byte .LASF196
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+ .uleb128 0x26
+ .4byte .LASF197
+ .byte 0x38
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+ .4byte .LASF198
+ .byte 0x39
+ .uleb128 0x26
+ .4byte .LASF199
+ .byte 0x3a
+ .uleb128 0x26
+ .4byte .LASF200
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+ .uleb128 0x26
+ .4byte .LASF201
+ .byte 0x3c
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+ .4byte .LASF202
+ .byte 0x3d
+ .uleb128 0x26
+ .4byte .LASF203
+ .byte 0x3e
+ .uleb128 0x26
+ .4byte .LASF204
+ .byte 0x3f
+ .uleb128 0x26
+ .4byte .LASF205
+ .byte 0x40
+ .uleb128 0x26
+ .4byte .LASF206
+ .byte 0x41
+ .uleb128 0x26
+ .4byte .LASF207
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+ .uleb128 0x26
+ .4byte .LASF208
+ .byte 0x43
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+ .4byte .LASF209
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+ .4byte .LASF211
+ .byte 0x46
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+ .4byte .LASF212
+ .byte 0x47
+ .uleb128 0x26
+ .4byte .LASF213
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+ .4byte .LASF214
+ .byte 0x49
+ .uleb128 0x26
+ .4byte .LASF215
+ .byte 0x4a
+ .uleb128 0x26
+ .4byte .LASF216
+ .byte 0x4b
+ .uleb128 0x26
+ .4byte .LASF217
+ .byte 0x4c
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+ .4byte .LASF218
+ .byte 0x4d
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+ .uleb128 0x26
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+ .4byte .LASF222
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+ .4byte .LASF224
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+ .4byte .LASF226
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+ .4byte .LASF227
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+ .4byte .LASF229
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+ .4byte .LASF231
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+ .byte 0x5b
+ .uleb128 0x26
+ .4byte .LASF233
+ .byte 0x5c
+ .uleb128 0x26
+ .4byte .LASF234
+ .byte 0x5d
+ .uleb128 0x26
+ .4byte .LASF235
+ .byte 0x5e
+ .uleb128 0x26
+ .4byte .LASF236
+ .byte 0x5f
+ .uleb128 0x26
+ .4byte .LASF237
+ .byte 0x60
+ .uleb128 0x26
+ .4byte .LASF238
+ .byte 0x61
+ .uleb128 0x26
+ .4byte .LASF239
+ .byte 0x62
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+ .4byte .LASF240
+ .sleb128 -1
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+ .byte 0xf6
+ .4byte 0xb2b
+ .uleb128 0x26
+ .4byte .LASF241
+ .byte 0x5
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+ .4byte .LASF242
+ .byte 0x40
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+ .4byte 0xba4
+ .uleb128 0x12
+ .4byte .LASF243
+ .byte 0x15
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x1a
+ .string "tbu"
+ .byte 0x15
+ .byte 0x23
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+ .byte 0x8
+ .uleb128 0x1a
+ .string "tbl"
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+ .byte 0x24
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+ .uleb128 0x12
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+ .byte 0x15
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+ .4byte .LASF245
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+ .uleb128 0x12
+ .4byte .LASF246
+ .byte 0x15
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+ .4byte .LASF247
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+ .4byte .LASF248
+ .byte 0x15
+ .byte 0x2c
+ .4byte 0x3b
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+ .uleb128 0x12
+ .4byte .LASF249
+ .byte 0x15
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+ .4byte 0x3b
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+ .byte 0
+ .uleb128 0x11
+ .4byte .LASF250
+ .byte 0x18
+ .byte 0x16
+ .byte 0x22
+ .4byte 0xbec
+ .uleb128 0x12
+ .4byte .LASF251
+ .byte 0x16
+ .byte 0x23
+ .4byte 0xa3
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+ .4byte .LASF252
+ .byte 0x16
+ .byte 0x24
+ .4byte 0xa3
+ .byte 0x4
+ .uleb128 0x1a
+ .string "id"
+ .byte 0x16
+ .byte 0x25
+ .4byte 0xa3
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF253
+ .byte 0x16
+ .byte 0x26
+ .4byte 0xa3
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF254
+ .byte 0x16
+ .byte 0x27
+ .4byte 0x100
+ .byte 0x10
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF255
+ .2byte 0x1c8
+ .byte 0x16
+ .byte 0x2a
+ .4byte 0xe22
+ .uleb128 0x1a
+ .string "bd"
+ .byte 0x16
+ .byte 0x2b
+ .4byte 0x880
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF256
+ .byte 0x16
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+ .uleb128 0x12
+ .4byte .LASF253
+ .byte 0x16
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+ .uleb128 0x12
+ .4byte .LASF257
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+ .4byte .LASF258
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+ .uleb128 0x12
+ .4byte .LASF259
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+ .4byte .LASF261
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+ .uleb128 0x12
+ .4byte .LASF262
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+ .4byte .LASF263
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+ .uleb128 0x12
+ .4byte .LASF264
+ .byte 0x16
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+ .uleb128 0x12
+ .4byte .LASF265
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+ .byte 0x58
+ .uleb128 0x12
+ .4byte .LASF266
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+ .4byte .LASF271
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+ .4byte .LASF274
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+ .uleb128 0x12
+ .4byte .LASF275
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+ .4byte .LASF276
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+ .byte 0xb8
+ .uleb128 0x12
+ .4byte .LASF277
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+ .4byte .LASF278
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+ .4byte .LASF279
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+ .uleb128 0x12
+ .4byte .LASF280
+ .byte 0x16
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+ .4byte .LASF281
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+ .4byte .LASF282
+ .byte 0x16
+ .byte 0x5f
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+ .byte 0xe8
+ .uleb128 0x1a
+ .string "jt"
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+ .byte 0x60
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+ .uleb128 0x12
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+ .4byte .LASF285
+ .byte 0x16
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+ .uleb128 0x16
+ .4byte .LASF286
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+ .4byte .LASF288
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+ .uleb128 0x16
+ .4byte .LASF289
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+ .uleb128 0x16
+ .4byte .LASF290
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+ .uleb128 0x16
+ .4byte .LASF291
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+ .byte 0x81
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+ .uleb128 0x16
+ .4byte .LASF292
+ .byte 0x16
+ .byte 0x87
+ .4byte 0xb9
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+ .uleb128 0x16
+ .4byte .LASF293
+ .byte 0x16
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+ .2byte 0x198
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+ .4byte .LASF294
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+ .4byte .LASF296
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+ .uleb128 0xe
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+ .uleb128 0xe
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+ .uleb128 0x4
+ .4byte .LASF300
+ .byte 0x4
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+ .4byte 0xe74
+ .uleb128 0xc
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+ .uleb128 0x4
+ .4byte .LASF301
+ .byte 0x4
+ .byte 0xaf
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+ .uleb128 0x4
+ .4byte .LASF302
+ .byte 0x4
+ .byte 0xb0
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+ .uleb128 0x4
+ .4byte .LASF303
+ .byte 0x4
+ .byte 0xfe
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+ .uleb128 0x4
+ .4byte .LASF304
+ .byte 0x4
+ .byte 0xff
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+ .uleb128 0xd
+ .4byte .LASF305
+ .byte 0x4
+ .2byte 0x100
+ .4byte 0x100
+ .uleb128 0x11
+ .4byte .LASF306
+ .byte 0x4
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+ .byte 0x2e
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+ .uleb128 0x12
+ .4byte .LASF307
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+ .uleb128 0xd
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+ .uleb128 0xd
+ .4byte .LASF309
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+ .2byte 0x1fe
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+ .uleb128 0xd
+ .4byte .LASF310
+ .byte 0x17
+ .2byte 0x200
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+ .uleb128 0xd
+ .4byte .LASF311
+ .byte 0x17
+ .2byte 0x205
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+ .uleb128 0xd
+ .4byte .LASF312
+ .byte 0x17
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+ .uleb128 0x10
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+ .byte 0x3f
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF313
+ .byte 0x17
+ .2byte 0x207
+ .4byte 0xf17
+ .uleb128 0xd
+ .4byte .LASF314
+ .byte 0x17
+ .2byte 0x209
+ .4byte 0xecb
+ .uleb128 0xd
+ .4byte .LASF315
+ .byte 0x17
+ .2byte 0x20a
+ .4byte 0xecb
+ .uleb128 0xd
+ .4byte .LASF316
+ .byte 0x17
+ .2byte 0x20b
+ .4byte 0xeac
+ .uleb128 0xd
+ .4byte .LASF317
+ .byte 0x17
+ .2byte 0x20c
+ .4byte 0xeac
+ .uleb128 0xd
+ .4byte .LASF318
+ .byte 0x17
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+ .uleb128 0xb
+ .4byte 0xec5
+ .4byte 0xf7f
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x3
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF319
+ .byte 0x17
+ .2byte 0x20e
+ .4byte 0xf6f
+ .uleb128 0xd
+ .4byte .LASF320
+ .byte 0x17
+ .2byte 0x20f
+ .4byte 0xec5
+ .uleb128 0xd
+ .4byte .LASF321
+ .byte 0x17
+ .2byte 0x210
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+ .uleb128 0xb
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+ .4byte 0xfb3
+ .uleb128 0x10
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+ .byte 0x5
+ .byte 0
+ .uleb128 0x7
+ .4byte 0xfa3
+ .uleb128 0xd
+ .4byte .LASF322
+ .byte 0x17
+ .2byte 0x211
+ .4byte 0xfb3
+ .uleb128 0xd
+ .4byte .LASF323
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+ .2byte 0x212
+ .4byte 0xfb3
+ .uleb128 0xd
+ .4byte .LASF324
+ .byte 0x17
+ .2byte 0x216
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+ .uleb128 0xd
+ .4byte .LASF325
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+ .uleb128 0xd
+ .4byte .LASF326
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+ .uleb128 0xd
+ .4byte .LASF327
+ .byte 0x17
+ .2byte 0x220
+ .4byte 0x89e
+ .uleb128 0xd
+ .4byte .LASF328
+ .byte 0x17
+ .2byte 0x222
+ .4byte 0xa3
+ .uleb128 0xd
+ .4byte .LASF329
+ .byte 0x17
+ .2byte 0x224
+ .4byte 0xa3
+ .uleb128 0xd
+ .4byte .LASF330
+ .byte 0x17
+ .2byte 0x230
+ .4byte 0xeac
+ .uleb128 0x29
+ .4byte .LASF332
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x17
+ .2byte 0x286
+ .4byte 0x104e
+ .uleb128 0x26
+ .4byte .LASF333
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF334
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF335
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF336
+ .byte 0x3
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF337
+ .byte 0x17
+ .2byte 0x28c
+ .4byte 0x1024
+ .uleb128 0x4
+ .4byte .LASF338
+ .byte 0x19
+ .byte 0x2b
+ .4byte 0x13a
+ .uleb128 0x4
+ .4byte .LASF339
+ .byte 0x19
+ .byte 0x2b
+ .4byte 0x13a
+ .uleb128 0x11
+ .4byte .LASF340
+ .byte 0x28
+ .byte 0x1a
+ .byte 0x39
+ .4byte 0x10b9
+ .uleb128 0x1a
+ .string "dev"
+ .byte 0x1a
+ .byte 0x3a
+ .4byte 0x126
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF341
+ .byte 0x1a
+ .byte 0x3b
+ .4byte 0x126
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF342
+ .byte 0x1a
+ .byte 0x3c
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+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF343
+ .byte 0x1a
+ .byte 0x3d
+ .4byte 0xd6
+ .byte 0x18
+ .uleb128 0x12
+ .4byte .LASF344
+ .byte 0x1a
+ .byte 0x3e
+ .4byte 0x10dd
+ .byte 0x20
+ .byte 0
+ .uleb128 0x13
+ .4byte 0x100
+ .4byte 0x10d7
+ .uleb128 0x14
+ .4byte 0x10d7
+ .uleb128 0x14
+ .4byte 0x100
+ .uleb128 0x14
+ .4byte 0x100
+ .uleb128 0x14
+ .4byte 0x126
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1070
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x10b9
+ .uleb128 0x11
+ .4byte .LASF345
+ .byte 0x38
+ .byte 0x1b
+ .byte 0xc
+ .4byte 0x1114
+ .uleb128 0x12
+ .4byte .LASF346
+ .byte 0x1b
+ .byte 0xd
+ .4byte 0x1070
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF347
+ .byte 0x1b
+ .byte 0x10
+ .4byte 0x126
+ .byte 0x28
+ .uleb128 0x12
+ .4byte .LASF348
+ .byte 0x1b
+ .byte 0x11
+ .4byte 0x100
+ .byte 0x30
+ .byte 0
+ .uleb128 0x2a
+ .string "gd"
+ .byte 0x1
+ .byte 0xf
+ .4byte 0x111e
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe59
+ .uleb128 0x28
+ .byte 0x4
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+ .byte 0x40
+ .4byte 0x1149
+ .uleb128 0x26
+ .4byte .LASF349
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF350
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF351
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF352
+ .byte 0x3
+ .byte 0
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1
+ .byte 0x47
+ .4byte 0x1180
+ .uleb128 0x26
+ .4byte .LASF353
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF354
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF355
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF356
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF357
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF358
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF359
+ .byte 0x6
+ .byte 0
+ .uleb128 0x28
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1
+ .byte 0x51
+ .4byte 0x11c3
+ .uleb128 0x26
+ .4byte .LASF360
+ .byte 0
+ .uleb128 0x26
+ .4byte .LASF361
+ .byte 0x1
+ .uleb128 0x26
+ .4byte .LASF362
+ .byte 0x2
+ .uleb128 0x26
+ .4byte .LASF363
+ .byte 0x3
+ .uleb128 0x26
+ .4byte .LASF364
+ .byte 0x4
+ .uleb128 0x26
+ .4byte .LASF365
+ .byte 0x5
+ .uleb128 0x26
+ .4byte .LASF366
+ .byte 0x6
+ .uleb128 0x26
+ .4byte .LASF367
+ .byte 0x7
+ .uleb128 0x26
+ .4byte .LASF368
+ .byte 0x8
+ .byte 0
+ .uleb128 0xb
+ .4byte 0xd6
+ .4byte 0x11d3
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x7
+ .byte 0
+ .uleb128 0x2b
+ .4byte .LASF369
+ .byte 0x1
+ .byte 0x5d
+ .4byte 0x11c3
+ .uleb128 0x9
+ .byte 0x3
+ .8byte tid_name
+ .uleb128 0x2
+ .4byte .LASF370
+ .byte 0x1
+ .byte 0x68
+ .4byte 0x11f3
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x11f9
+ .uleb128 0x13
+ .4byte 0x54
+ .4byte 0x1208
+ .uleb128 0x14
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x10e3
+ .uleb128 0x11
+ .4byte .LASF371
+ .byte 0x28
+ .byte 0x1
+ .byte 0x69
+ .4byte 0x126d
+ .uleb128 0x1a
+ .string "fn"
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x11e8
+ .byte 0
+ .uleb128 0x12
+ .4byte .LASF138
+ .byte 0x1
+ .byte 0x6b
+ .4byte 0xa3
+ .byte 0x8
+ .uleb128 0x1a
+ .string "tid"
+ .byte 0x1
+ .byte 0x6c
+ .4byte 0xa3
+ .byte 0xc
+ .uleb128 0x12
+ .4byte .LASF372
+ .byte 0x1
+ .byte 0x6d
+ .4byte 0xa3
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF373
+ .byte 0x1
+ .byte 0x6e
+ .4byte 0xa3
+ .byte 0x14
+ .uleb128 0x1a
+ .string "ret"
+ .byte 0x1
+ .byte 0x6f
+ .4byte 0x54
+ .byte 0x18
+ .uleb128 0x1a
+ .string "ms"
+ .byte 0x1
+ .byte 0x70
+ .4byte 0x100
+ .byte 0x20
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF374
+ .2byte 0x148
+ .byte 0x1
+ .byte 0x73
+ .4byte 0x1294
+ .uleb128 0x12
+ .4byte .LASF375
+ .byte 0x1
+ .byte 0x74
+ .4byte 0x1294
+ .byte 0
+ .uleb128 0x17
+ .string "num"
+ .byte 0x1
+ .byte 0x75
+ .4byte 0x94
+ .2byte 0x140
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x120e
+ .4byte 0x12a4
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x7
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF376
+ .2byte 0x560
+ .byte 0x1
+ .byte 0x78
+ .4byte 0x12d7
+ .uleb128 0x12
+ .4byte .LASF377
+ .byte 0x1
+ .byte 0x79
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x1a
+ .string "cpu"
+ .byte 0x1
+ .byte 0x7a
+ .4byte 0x12d7
+ .byte 0x8
+ .uleb128 0x16
+ .4byte .LASF378
+ .byte 0x1
+ .byte 0x7b
+ .4byte 0x10e3
+ .2byte 0x528
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x126d
+ .4byte 0x12e7
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x3
+ .byte 0
+ .uleb128 0x2c
+ .string "mpb"
+ .byte 0x1
+ .byte 0x7e
+ .4byte 0x12f2
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12a4
+ .uleb128 0x2b
+ .4byte .LASF379
+ .byte 0x1
+ .byte 0x7f
+ .4byte 0x100
+ .uleb128 0x9
+ .byte 0x3
+ .8byte mpb_gd
+ .uleb128 0x11
+ .4byte .LASF380
+ .byte 0x18
+ .byte 0x1
+ .byte 0x95
+ .4byte 0x1355
+ .uleb128 0x1a
+ .string "cid"
+ .byte 0x1
+ .byte 0x96
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x1a
+ .string "tid"
+ .byte 0x1
+ .byte 0x97
+ .4byte 0xa3
+ .byte 0x4
+ .uleb128 0x1a
+ .string "fn"
+ .byte 0x1
+ .byte 0x98
+ .4byte 0x11e8
+ .byte 0x8
+ .uleb128 0x12
+ .4byte .LASF372
+ .byte 0x1
+ .byte 0x99
+ .4byte 0xa3
+ .byte 0x10
+ .uleb128 0x12
+ .4byte .LASF373
+ .byte 0x1
+ .byte 0x9a
+ .4byte 0xa3
+ .byte 0x14
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF389
+ .byte 0x1
+ .2byte 0x271
+ .4byte 0x100
+ .8byte .LFB240
+ .8byte .LFE240-.LFB240
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x139b
+ .uleb128 0x2e
+ .string "evt"
+ .byte 0x1
+ .2byte 0x271
+ .4byte 0x54
+ .4byte .LLST61
+ .uleb128 0x2f
+ .8byte .LVL153
+ .4byte 0x19e7
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x32
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF381
+ .byte 0x1
+ .2byte 0x219
+ .8byte .LFB239
+ .8byte .LFE239-.LFB239
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1584
+ .uleb128 0x2e
+ .string "evt"
+ .byte 0x1
+ .2byte 0x219
+ .4byte 0x54
+ .4byte .LLST53
+ .uleb128 0x32
+ .4byte 0x1618
+ .8byte .LBB120
+ .4byte .Ldebug_ranges0+0x1c0
+ .byte 0x1
+ .2byte 0x21d
+ .4byte 0x14f3
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x1c0
+ .uleb128 0x34
+ .4byte 0x1625
+ .uleb128 0x2
+ .byte 0x91
+ .sleb128 -48
+ .uleb128 0x35
+ .4byte 0x1631
+ .4byte .LLST54
+ .uleb128 0x32
+ .4byte 0x1eb5
+ .8byte .LBB122
+ .4byte .Ldebug_ranges0+0x1f0
+ .byte 0x1
+ .2byte 0x203
+ .4byte 0x143a
+ .uleb128 0x36
+ .4byte 0x1ec5
+ .4byte .LLST55
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x1f0
+ .uleb128 0x35
+ .4byte 0x1ed0
+ .4byte .LLST56
+ .uleb128 0x35
+ .4byte 0x1edb
+ .4byte .LLST57
+ .uleb128 0x35
+ .4byte 0x1ee6
+ .4byte .LLST58
+ .byte 0
+ .byte 0
+ .uleb128 0x37
+ .8byte .LBB127
+ .8byte .LBE127-.LBB127
+ .4byte 0x1455
+ .uleb128 0x38
+ .4byte 0x1640
+ .byte 0
+ .uleb128 0x37
+ .8byte .LBB128
+ .8byte .LBE128-.LBB128
+ .4byte 0x1474
+ .uleb128 0x35
+ .4byte 0x164e
+ .4byte .LLST59
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL128
+ .4byte 0x22d5
+ .4byte 0x149f
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8f
+ .sleb128 16
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR2
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x30
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL129
+ .4byte 0x22de
+ .4byte 0x14be
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC13
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL130
+ .4byte 0x22e9
+ .4byte 0x14e4
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x4
+ .byte 0x8
+ .byte 0x82
+ .byte 0x44
+ .byte 0x24
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x560
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL133
+ .4byte 0x22f4
+ .byte 0
+ .byte 0
+ .uleb128 0x3b
+ .4byte 0x1fd7
+ .8byte .LBB132
+ .8byte .LBE132-.LBB132
+ .byte 0x1
+ .2byte 0x226
+ .4byte 0x152e
+ .uleb128 0x36
+ .4byte 0x1fe3
+ .4byte .LLST60
+ .uleb128 0x3c
+ .8byte .LVL148
+ .4byte 0x2300
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL145
+ .4byte 0x1d6b
+ .4byte 0x1554
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x33
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x6
+ .byte 0x11
+ .sleb128 -559087616
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL146
+ .4byte 0x22f4
+ .uleb128 0x3c
+ .8byte .LVL150
+ .4byte 0x1d6b
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x37
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x6
+ .byte 0x11
+ .sleb128 -559087616
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF382
+ .byte 0x1
+ .2byte 0x20e
+ .8byte .LFB238
+ .8byte .LFE238-.LFB238
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1618
+ .uleb128 0x3d
+ .4byte .LASF346
+ .byte 0x1
+ .2byte 0x20e
+ .4byte 0x1070
+ .uleb128 0x2
+ .byte 0x70
+ .sleb128 0
+ .uleb128 0x39
+ .8byte .LVL122
+ .4byte 0x22d5
+ .4byte 0x15c9
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x28
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL123
+ .4byte 0x184a
+ .4byte 0x15e5
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x32
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL124
+ .4byte 0x1d6b
+ .4byte 0x160a
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x30
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x33
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x11111111
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL125
+ .4byte 0x22f4
+ .byte 0
+ .uleb128 0x3e
+ .4byte .LASF403
+ .byte 0x1
+ .2byte 0x1e9
+ .byte 0x1
+ .4byte 0x165c
+ .uleb128 0x3f
+ .4byte .LASF383
+ .byte 0x1
+ .2byte 0x1ee
+ .4byte 0x165c
+ .uleb128 0x40
+ .string "i"
+ .byte 0x1
+ .2byte 0x1fb
+ .4byte 0x54
+ .uleb128 0x41
+ .4byte 0x164d
+ .uleb128 0x40
+ .string "__v"
+ .byte 0x1
+ .2byte 0x206
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x42
+ .uleb128 0x40
+ .string "__v"
+ .byte 0x1
+ .2byte 0x207
+ .4byte 0xa3
+ .byte 0
+ .byte 0
+ .uleb128 0xb
+ .4byte 0x130d
+ .4byte 0x166c
+ .uleb128 0x10
+ .4byte 0xcf
+ .byte 0x1
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF384
+ .byte 0x1
+ .2byte 0x1bf
+ .8byte .LFB236
+ .8byte .LFE236-.LFB236
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1764
+ .uleb128 0x2e
+ .string "cpu"
+ .byte 0x1
+ .2byte 0x1bf
+ .4byte 0xa3
+ .4byte .LLST51
+ .uleb128 0x3b
+ .4byte 0x1f14
+ .8byte .LBB106
+ .8byte .LBE106-.LBB106
+ .byte 0x1
+ .2byte 0x1c2
+ .4byte 0x16c0
+ .uleb128 0x36
+ .4byte 0x1f20
+ .4byte .LLST52
+ .byte 0
+ .uleb128 0x43
+ .4byte 0x1fcf
+ .8byte .LBB108
+ .8byte .LBE108-.LBB108
+ .byte 0x1
+ .2byte 0x1d6
+ .uleb128 0x43
+ .4byte 0x1f0c
+ .8byte .LBB110
+ .8byte .LBE110-.LBB110
+ .byte 0x1
+ .2byte 0x1da
+ .uleb128 0x3a
+ .8byte .LVL114
+ .4byte 0x230b
+ .uleb128 0x39
+ .8byte .LVL115
+ .4byte 0x1764
+ .4byte 0x1715
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL116
+ .4byte 0x22f4
+ .uleb128 0x3a
+ .8byte .LVL117
+ .4byte 0x2317
+ .uleb128 0x3a
+ .8byte .LVL118
+ .4byte 0x2323
+ .uleb128 0x3a
+ .8byte .LVL119
+ .4byte 0x232f
+ .uleb128 0x3a
+ .8byte .LVL120
+ .4byte 0x233b
+ .uleb128 0x3a
+ .8byte .LVL121
+ .4byte 0x2347
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF385
+ .byte 0x1
+ .2byte 0x1b1
+ .8byte .LFB235
+ .8byte .LFE235-.LFB235
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1844
+ .uleb128 0x2e
+ .string "cpu"
+ .byte 0x1
+ .2byte 0x1b1
+ .4byte 0xa3
+ .4byte .LLST42
+ .uleb128 0x44
+ .4byte .LASF375
+ .byte 0x1
+ .2byte 0x1b3
+ .4byte 0x1844
+ .4byte .LLST43
+ .uleb128 0x45
+ .string "i"
+ .byte 0x1
+ .2byte 0x1b4
+ .4byte 0x54
+ .4byte .LLST44
+ .uleb128 0x46
+ .4byte 0x1976
+ .8byte .LBB98
+ .4byte .Ldebug_ranges0+0x160
+ .byte 0x1
+ .2byte 0x1b8
+ .uleb128 0x36
+ .4byte 0x19aa
+ .4byte .LLST45
+ .uleb128 0x36
+ .4byte 0x199e
+ .4byte .LLST46
+ .uleb128 0x36
+ .4byte 0x1993
+ .4byte .LLST47
+ .uleb128 0x36
+ .4byte 0x1987
+ .4byte .LLST48
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x160
+ .uleb128 0x38
+ .4byte 0x19b6
+ .uleb128 0x38
+ .4byte 0x19c2
+ .uleb128 0x35
+ .4byte 0x19ce
+ .4byte .LLST49
+ .uleb128 0x35
+ .4byte 0x19da
+ .4byte .LLST50
+ .uleb128 0x32
+ .4byte 0x1ef0
+ .8byte .LBB100
+ .4byte .Ldebug_ranges0+0x190
+ .byte 0x1
+ .2byte 0x179
+ .4byte 0x1827
+ .uleb128 0x47
+ .4byte 0x1f00
+ .byte 0
+ .uleb128 0x2f
+ .8byte .LVL108
+ .4byte 0x2014
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x87
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x120e
+ .uleb128 0x31
+ .4byte .LASF386
+ .byte 0x1
+ .2byte 0x1a3
+ .8byte .LFB234
+ .8byte .LFE234-.LFB234
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1976
+ .uleb128 0x2e
+ .string "cid"
+ .byte 0x1
+ .2byte 0x1a3
+ .4byte 0xa3
+ .4byte .LLST31
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x1a3
+ .4byte 0xa3
+ .4byte .LLST32
+ .uleb128 0x44
+ .4byte .LASF375
+ .byte 0x1
+ .2byte 0x1a5
+ .4byte 0x1844
+ .4byte .LLST33
+ .uleb128 0x45
+ .string "i"
+ .byte 0x1
+ .2byte 0x1a6
+ .4byte 0x54
+ .4byte .LLST34
+ .uleb128 0x32
+ .4byte 0x1ef0
+ .8byte .LBB86
+ .4byte .Ldebug_ranges0+0x130
+ .byte 0x1
+ .2byte 0x1a8
+ .4byte 0x18c8
+ .uleb128 0x36
+ .4byte 0x1f00
+ .4byte .LLST35
+ .byte 0
+ .uleb128 0x48
+ .4byte 0x1976
+ .8byte .LBB90
+ .8byte .LBE90-.LBB90
+ .byte 0x1
+ .2byte 0x1ad
+ .uleb128 0x36
+ .4byte 0x19aa
+ .4byte .LLST36
+ .uleb128 0x36
+ .4byte 0x199e
+ .4byte .LLST37
+ .uleb128 0x36
+ .4byte 0x1993
+ .4byte .LLST38
+ .uleb128 0x36
+ .4byte 0x1987
+ .4byte .LLST39
+ .uleb128 0x49
+ .8byte .LBB91
+ .8byte .LBE91-.LBB91
+ .uleb128 0x38
+ .4byte 0x19b6
+ .uleb128 0x38
+ .4byte 0x19c2
+ .uleb128 0x35
+ .4byte 0x19ce
+ .4byte .LLST40
+ .uleb128 0x35
+ .4byte 0x19da
+ .4byte .LLST41
+ .uleb128 0x3b
+ .4byte 0x1ef0
+ .8byte .LBB92
+ .8byte .LBE92-.LBB92
+ .byte 0x1
+ .2byte 0x179
+ .4byte 0x1953
+ .uleb128 0x47
+ .4byte 0x1f00
+ .byte 0
+ .uleb128 0x2f
+ .8byte .LVL97
+ .4byte 0x2014
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x87
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x4a
+ .4byte .LASF391
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x19e7
+ .uleb128 0x4b
+ .string "cid"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x4b
+ .string "id"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0x94
+ .uleb128 0x4b
+ .string "tid"
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x4c
+ .4byte .LASF372
+ .byte 0x1
+ .2byte 0x172
+ .4byte 0xa3
+ .uleb128 0x3f
+ .4byte .LASF387
+ .byte 0x1
+ .2byte 0x174
+ .4byte 0x8d
+ .uleb128 0x3f
+ .4byte .LASF388
+ .byte 0x1
+ .2byte 0x175
+ .4byte 0x54
+ .uleb128 0x40
+ .string "ret"
+ .byte 0x1
+ .2byte 0x176
+ .4byte 0x54
+ .uleb128 0x40
+ .string "run"
+ .byte 0x1
+ .2byte 0x177
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF390
+ .byte 0x1
+ .2byte 0x16d
+ .4byte 0x54
+ .8byte .LFB232
+ .8byte .LFE232-.LFB232
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1aca
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x16d
+ .4byte 0xa3
+ .4byte .LLST28
+ .uleb128 0x46
+ .4byte 0x1aca
+ .8byte .LBB74
+ .4byte .Ldebug_ranges0+0x100
+ .byte 0x1
+ .2byte 0x16f
+ .uleb128 0x4d
+ .4byte 0x1ae7
+ .byte 0
+ .uleb128 0x36
+ .4byte 0x1adb
+ .4byte .LLST29
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x100
+ .uleb128 0x38
+ .4byte 0x1af3
+ .uleb128 0x3b
+ .4byte 0x1fd7
+ .8byte .LBB76
+ .8byte .LBE76-.LBB76
+ .byte 0x1
+ .2byte 0x164
+ .4byte 0x1a9a
+ .uleb128 0x36
+ .4byte 0x1fe3
+ .4byte .LLST30
+ .uleb128 0x39
+ .8byte .LVL84
+ .4byte 0x2300
+ .4byte 0x1a84
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .uleb128 0x2f
+ .8byte .LVL85
+ .4byte 0x2300
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xa
+ .2byte 0x3e8
+ .byte 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL82
+ .4byte 0x1ccc
+ .4byte 0x1ab2
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3c
+ .8byte .LVL87
+ .4byte 0x1ccc
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x4a
+ .4byte .LASF392
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1afe
+ .uleb128 0x4b
+ .string "tid"
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0xa3
+ .uleb128 0x4c
+ .4byte .LASF393
+ .byte 0x1
+ .2byte 0x15f
+ .4byte 0xa3
+ .uleb128 0x40
+ .string "i"
+ .byte 0x1
+ .2byte 0x161
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x4a
+ .4byte .LASF394
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1b6d
+ .uleb128 0x4b
+ .string "cid"
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x4b
+ .string "tid"
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x4c
+ .4byte .LASF372
+ .byte 0x1
+ .2byte 0x138
+ .4byte 0xa3
+ .uleb128 0x3f
+ .4byte .LASF388
+ .byte 0x1
+ .2byte 0x13a
+ .4byte 0x54
+ .uleb128 0x40
+ .string "us"
+ .byte 0x1
+ .2byte 0x13b
+ .4byte 0x54
+ .uleb128 0x40
+ .string "i"
+ .byte 0x1
+ .2byte 0x13c
+ .4byte 0x54
+ .uleb128 0x3f
+ .4byte .LASF395
+ .byte 0x1
+ .2byte 0x13c
+ .4byte 0x54
+ .uleb128 0x3f
+ .4byte .LASF396
+ .byte 0x1
+ .2byte 0x13d
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF397
+ .byte 0x1
+ .2byte 0x121
+ .8byte .LFB229
+ .8byte .LFE229-.LFB229
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1ccc
+ .uleb128 0x44
+ .4byte .LASF375
+ .byte 0x1
+ .2byte 0x123
+ .4byte 0x1844
+ .4byte .LLST8
+ .uleb128 0x45
+ .string "cid"
+ .byte 0x1
+ .2byte 0x124
+ .4byte 0x54
+ .4byte .LLST9
+ .uleb128 0x45
+ .string "i"
+ .byte 0x1
+ .2byte 0x124
+ .4byte 0x54
+ .4byte .LLST10
+ .uleb128 0x39
+ .8byte .LVL24
+ .4byte 0x22de
+ .4byte 0x1bd8
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC1
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL27
+ .4byte 0x22de
+ .4byte 0x1bf6
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x88
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL28
+ .4byte 0x22de
+ .4byte 0x1c15
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC3
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL29
+ .4byte 0x22de
+ .4byte 0x1c34
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC4
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL30
+ .4byte 0x22de
+ .4byte 0x1c53
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC5
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL31
+ .4byte 0x22de
+ .4byte 0x1c72
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC6
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL32
+ .4byte 0x22de
+ .4byte 0x1c91
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC7
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL33
+ .4byte 0x22de
+ .4byte 0x1cb0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC8
+ .byte 0
+ .uleb128 0x2f
+ .8byte .LVL34
+ .4byte 0x22de
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC9
+ .byte 0
+ .byte 0
+ .uleb128 0x2d
+ .4byte .LASF398
+ .byte 0x1
+ .2byte 0x104
+ .4byte 0x54
+ .8byte .LFB228
+ .8byte .LFE228-.LFB228
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1d65
+ .uleb128 0x2e
+ .string "tid"
+ .byte 0x1
+ .2byte 0x104
+ .4byte 0xa3
+ .4byte .LLST5
+ .uleb128 0x40
+ .string "cid"
+ .byte 0x1
+ .2byte 0x106
+ .4byte 0x54
+ .uleb128 0x45
+ .string "i"
+ .byte 0x1
+ .2byte 0x106
+ .4byte 0x54
+ .4byte .LLST6
+ .uleb128 0x45
+ .string "ptr"
+ .byte 0x1
+ .2byte 0x107
+ .4byte 0x1d65
+ .4byte .LLST7
+ .uleb128 0x3b
+ .4byte 0x1ef0
+ .8byte .LBB36
+ .8byte .LBE36-.LBB36
+ .byte 0x1
+ .2byte 0x109
+ .4byte 0x1d4a
+ .uleb128 0x47
+ .4byte 0x1f00
+ .byte 0
+ .uleb128 0x2f
+ .8byte .LVL21
+ .4byte 0x2353
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xa3
+ .uleb128 0x4e
+ .4byte .LASF431
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0x54
+ .8byte .LFB227
+ .8byte .LFE227-.LFB227
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1e38
+ .uleb128 0x4f
+ .string "cid"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST0
+ .uleb128 0x4f
+ .string "tid"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST1
+ .uleb128 0x4f
+ .string "st"
+ .byte 0x1
+ .byte 0xe2
+ .4byte 0xa3
+ .4byte .LLST2
+ .uleb128 0x50
+ .4byte .LASF31
+ .byte 0x1
+ .byte 0xe4
+ .4byte 0xef
+ .uleb128 0x2c
+ .string "ptr"
+ .byte 0x1
+ .byte 0xe5
+ .4byte 0x1d65
+ .uleb128 0x2c
+ .string "id"
+ .byte 0x1
+ .byte 0xe6
+ .4byte 0x54
+ .uleb128 0x51
+ .4byte 0x1ef0
+ .8byte .LBB30
+ .8byte .LBE30-.LBB30
+ .byte 0x1
+ .byte 0xe8
+ .4byte 0x1df9
+ .uleb128 0x47
+ .4byte 0x1f00
+ .byte 0
+ .uleb128 0x52
+ .4byte 0x1e85
+ .8byte .LBB32
+ .4byte .Ldebug_ranges0+0
+ .byte 0x1
+ .byte 0xeb
+ .4byte 0x1e2a
+ .uleb128 0x47
+ .4byte 0x1ea0
+ .uleb128 0x47
+ .4byte 0x1e95
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0
+ .uleb128 0x35
+ .4byte 0x1eab
+ .4byte .LLST3
+ .byte 0
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL8
+ .4byte 0x235f
+ .byte 0
+ .uleb128 0x53
+ .4byte .LASF399
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1e7f
+ .uleb128 0x54
+ .string "cid"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x54
+ .string "tid"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x54
+ .string "ret"
+ .byte 0x1
+ .byte 0xcf
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "ptr"
+ .byte 0x1
+ .byte 0xd1
+ .4byte 0x1e7f
+ .uleb128 0x2c
+ .string "id"
+ .byte 0x1
+ .byte 0xd2
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x54
+ .uleb128 0x53
+ .4byte .LASF400
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1eb5
+ .uleb128 0x54
+ .string "cid"
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0xa3
+ .uleb128 0x54
+ .string "tid"
+ .byte 0x1
+ .byte 0xc3
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "i"
+ .byte 0x1
+ .byte 0xc5
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x53
+ .4byte .LASF401
+ .byte 0x1
+ .byte 0x9d
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1ef0
+ .uleb128 0x55
+ .4byte .LASF383
+ .byte 0x1
+ .byte 0x9d
+ .4byte 0x130d
+ .uleb128 0x2c
+ .string "cid"
+ .byte 0x1
+ .byte 0x9f
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "tid"
+ .byte 0x1
+ .byte 0xa0
+ .4byte 0xa3
+ .uleb128 0x2c
+ .string "i"
+ .byte 0x1
+ .byte 0xa1
+ .4byte 0x94
+ .byte 0
+ .uleb128 0x53
+ .4byte .LASF402
+ .byte 0x1
+ .byte 0x90
+ .4byte 0x54
+ .byte 0x3
+ .4byte 0x1f0c
+ .uleb128 0x54
+ .string "tid"
+ .byte 0x1
+ .byte 0x90
+ .4byte 0xa3
+ .byte 0
+ .uleb128 0x56
+ .4byte .LASF411
+ .byte 0x1
+ .byte 0x86
+ .byte 0x3
+ .uleb128 0x57
+ .4byte .LASF404
+ .byte 0x1
+ .byte 0x81
+ .byte 0x3
+ .4byte 0x1f2c
+ .uleb128 0x54
+ .string "ptr"
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0x58
+ .4byte .LASF432
+ .byte 0x1
+ .byte 0x34
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x1f48
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x34
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF406
+ .byte 0x1
+ .byte 0x33
+ .4byte 0x54
+ .4byte 0x1f63
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x33
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF407
+ .byte 0x1
+ .byte 0x32
+ .4byte 0x54
+ .4byte 0x1f7e
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x32
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF408
+ .byte 0x1
+ .byte 0x31
+ .4byte 0x54
+ .4byte 0x1f99
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x31
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF409
+ .byte 0x1
+ .byte 0x30
+ .4byte 0x54
+ .4byte 0x1fb4
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x30
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x59
+ .4byte .LASF410
+ .byte 0x1
+ .byte 0x2f
+ .4byte 0x54
+ .4byte 0x1fcf
+ .uleb128 0x55
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x2f
+ .4byte 0x1208
+ .byte 0
+ .uleb128 0x56
+ .4byte .LASF412
+ .byte 0x3
+ .byte 0xbf
+ .byte 0x3
+ .uleb128 0x57
+ .4byte .LASF413
+ .byte 0x2
+ .byte 0xd
+ .byte 0x3
+ .4byte 0x1fef
+ .uleb128 0x55
+ .4byte .LASF414
+ .byte 0x2
+ .byte 0xd
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0x5a
+ .4byte 0x1f2c
+ .8byte .LFB220
+ .8byte .LFE220-.LFB220
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x2014
+ .uleb128 0x36
+ .4byte 0x1f3c
+ .4byte .LLST4
+ .byte 0
+ .uleb128 0x5b
+ .4byte 0x1976
+ .8byte .LFB242
+ .8byte .LFE242-.LFB242
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x22d5
+ .uleb128 0x36
+ .4byte 0x1987
+ .4byte .LLST11
+ .uleb128 0x36
+ .4byte 0x1993
+ .4byte .LLST12
+ .uleb128 0x36
+ .4byte 0x199e
+ .4byte .LLST13
+ .uleb128 0x36
+ .4byte 0x19aa
+ .4byte .LLST14
+ .uleb128 0x35
+ .4byte 0x19b6
+ .4byte .LLST15
+ .uleb128 0x38
+ .4byte 0x19c2
+ .uleb128 0x35
+ .4byte 0x19ce
+ .4byte .LLST16
+ .uleb128 0x35
+ .4byte 0x19da
+ .4byte .LLST17
+ .uleb128 0x32
+ .4byte 0x1afe
+ .8byte .LBB48
+ .4byte .Ldebug_ranges0+0x30
+ .byte 0x1
+ .2byte 0x17f
+ .4byte 0x2128
+ .uleb128 0x36
+ .4byte 0x1b0f
+ .4byte .LLST18
+ .uleb128 0x36
+ .4byte 0x1b1b
+ .4byte .LLST19
+ .uleb128 0x36
+ .4byte 0x1b27
+ .4byte .LLST20
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x30
+ .uleb128 0x35
+ .4byte 0x1b33
+ .4byte .LLST21
+ .uleb128 0x5c
+ .4byte 0x1b3f
+ .byte 0x64
+ .uleb128 0x38
+ .4byte 0x1b4a
+ .uleb128 0x35
+ .4byte 0x1b54
+ .4byte .LLST22
+ .uleb128 0x35
+ .4byte 0x1b60
+ .4byte .LLST23
+ .uleb128 0x39
+ .8byte .LVL41
+ .4byte 0x1ccc
+ .4byte 0x20e9
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL42
+ .4byte 0x1ccc
+ .4byte 0x2101
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL51
+ .4byte 0x2300
+ .4byte 0x2119
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x64
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL54
+ .4byte 0x1b6d
+ .byte 0
+ .byte 0
+ .uleb128 0x32
+ .4byte 0x1e38
+ .8byte .LBB52
+ .4byte .Ldebug_ranges0+0x60
+ .byte 0x1
+ .2byte 0x19e
+ .4byte 0x21cb
+ .uleb128 0x36
+ .4byte 0x1e5e
+ .4byte .LLST24
+ .uleb128 0x36
+ .4byte 0x1e53
+ .4byte .LLST25
+ .uleb128 0x36
+ .4byte 0x1e48
+ .4byte .LLST26
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0x60
+ .uleb128 0x38
+ .4byte 0x1e69
+ .uleb128 0x38
+ .4byte 0x1e74
+ .uleb128 0x51
+ .4byte 0x1ef0
+ .8byte .LBB54
+ .8byte .LBE54-.LBB54
+ .byte 0x1
+ .byte 0xd4
+ .4byte 0x218b
+ .uleb128 0x47
+ .4byte 0x1f00
+ .byte 0
+ .uleb128 0x52
+ .4byte 0x1e85
+ .8byte .LBB56
+ .4byte .Ldebug_ranges0+0xd0
+ .byte 0x1
+ .byte 0xd7
+ .4byte 0x21bc
+ .uleb128 0x47
+ .4byte 0x1ea0
+ .uleb128 0x47
+ .4byte 0x1e95
+ .uleb128 0x33
+ .4byte .Ldebug_ranges0+0xd0
+ .uleb128 0x35
+ .4byte 0x1eab
+ .4byte .LLST27
+ .byte 0
+ .byte 0
+ .uleb128 0x5d
+ .8byte .LVL79
+ .4byte 0x235f
+ .byte 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL48
+ .4byte 0x22de
+ .4byte 0x21f6
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC11
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL49
+ .4byte 0x1d6b
+ .4byte 0x221d
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x55555555
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL57
+ .4byte 0x22de
+ .4byte 0x2248
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC12
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL58
+ .4byte 0x236b
+ .uleb128 0x39
+ .8byte .LVL61
+ .4byte 0x1d6b
+ .4byte 0x227c
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x5
+ .byte 0xc
+ .4byte 0x11111111
+ .byte 0
+ .uleb128 0x39
+ .8byte .LVL65
+ .4byte 0x1d6b
+ .4byte 0x229a
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3a
+ .8byte .LVL66
+ .4byte 0x236b
+ .uleb128 0x2f
+ .8byte .LVL68
+ .4byte 0x22de
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC10
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x30
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x2
+ .byte 0x85
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .4byte .LASF433
+ .4byte .LASF433
+ .uleb128 0x5f
+ .4byte .LASF415
+ .4byte .LASF415
+ .byte 0x1d
+ .byte 0x13
+ .uleb128 0x5f
+ .4byte .LASF416
+ .4byte .LASF416
+ .byte 0x8
+ .byte 0x66
+ .uleb128 0x60
+ .4byte .LASF417
+ .4byte .LASF417
+ .byte 0x4
+ .2byte 0x260
+ .uleb128 0x5f
+ .4byte .LASF418
+ .4byte .LASF418
+ .byte 0x2
+ .byte 0xb
+ .uleb128 0x60
+ .4byte .LASF419
+ .4byte .LASF419
+ .byte 0x4
+ .2byte 0x1f3
+ .uleb128 0x60
+ .4byte .LASF420
+ .4byte .LASF420
+ .byte 0x4
+ .2byte 0x248
+ .uleb128 0x60
+ .4byte .LASF421
+ .4byte .LASF421
+ .byte 0x4
+ .2byte 0x1f1
+ .uleb128 0x60
+ .4byte .LASF422
+ .4byte .LASF422
+ .byte 0x4
+ .2byte 0x264
+ .uleb128 0x60
+ .4byte .LASF423
+ .4byte .LASF423
+ .byte 0x4
+ .2byte 0x1f4
+ .uleb128 0x60
+ .4byte .LASF424
+ .4byte .LASF424
+ .byte 0x4
+ .2byte 0x263
+ .uleb128 0x60
+ .4byte .LASF425
+ .4byte .LASF425
+ .byte 0x4
+ .2byte 0x262
+ .uleb128 0x60
+ .4byte .LASF426
+ .4byte .LASF426
+ .byte 0x4
+ .2byte 0x261
+ .uleb128 0x60
+ .4byte .LASF427
+ .4byte .LASF427
+ .byte 0x4
+ .2byte 0x276
+ .byte 0
+ .section .debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+ .uleb128 0x1
+ .uleb128 0x11
+ .byte 0x1
+ .uleb128 0x25
+ .uleb128 0xe
+ .uleb128 0x13
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1b
+ .uleb128 0xe
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x10
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x2
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x4
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x5
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0x8
+ .byte 0
+ .byte 0
+ .uleb128 0x6
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x7
+ .uleb128 0x26
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x9
+ .uleb128 0x35
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0x1
+ .byte 0x1
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xc
+ .uleb128 0x21
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0xd
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0xe
+ .uleb128 0x13
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0xf
+ .uleb128 0x26
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x10
+ .uleb128 0x21
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2f
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x12
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x13
+ .uleb128 0x15
+ .byte 0x1
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x14
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x15
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x16
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x17
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x18
+ .uleb128 0x21
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2f
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x19
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x1a
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x1b
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x1c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x1d
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x1e
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x1f
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x20
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x21
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x22
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x23
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x24
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x25
+ .uleb128 0x4
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x26
+ .uleb128 0x28
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x27
+ .uleb128 0x28
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1c
+ .uleb128 0xd
+ .byte 0
+ .byte 0
+ .uleb128 0x28
+ .uleb128 0x4
+ .byte 0x1
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x29
+ .uleb128 0x4
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x2a
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x2b
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x2c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x2d
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x2e
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x2f
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x30
+ .uleb128 0x410a
+ .byte 0
+ .uleb128 0x2
+ .uleb128 0x18
+ .uleb128 0x2111
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x32
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x52
+ .uleb128 0x1
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0x5
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x33
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x55
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x34
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x35
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x36
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x37
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x38
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x39
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3a
+ .uleb128 0x4109
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3b
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0x5
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3c
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x2115
+ .uleb128 0x19
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3d
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x3e
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x40
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x41
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x42
+ .uleb128 0xb
+ .byte 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x43
+ .uleb128 0x1d
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x44
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x46
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x52
+ .uleb128 0x1
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x47
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x48
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .byte 0
+ .byte 0
+ .uleb128 0x4a
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4b
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4c
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4d
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x4e
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4f
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x50
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x52
+ .uleb128 0x1d
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x52
+ .uleb128 0x1
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x58
+ .uleb128 0xb
+ .uleb128 0x59
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x53
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x54
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x55
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x56
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x57
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x58
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x59
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5a
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5b
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2116
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x5d
+ .uleb128 0x4109
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x2115
+ .uleb128 0x19
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x60
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .byte 0
+ .section .debug_loc,"",@progbits
+.Ldebug_loc0:
+.LLST61:
+ .8byte .LVL151
+ .8byte .LVL152
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL152
+ .8byte .LVL154
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL154
+ .8byte .LVL155
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL155
+ .8byte .LFE240
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST53:
+ .8byte .LVL126
+ .8byte .LVL127
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL127
+ .8byte .LVL143
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL143
+ .8byte .LVL144
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL144
+ .8byte .LVL148
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL148
+ .8byte .LVL149
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL149
+ .8byte .LFE239
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST54:
+ .8byte .LVL131
+ .8byte .LVL132
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST55:
+ .8byte .LVL136
+ .8byte .LVL137
+ .2byte 0x7
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x53
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x93
+ .uleb128 0x10
+ .8byte .LVL137
+ .8byte .LVL141
+ .2byte 0xe
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x53
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte .LVL141
+ .8byte .LVL142
+ .2byte 0xf
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x71
+ .sleb128 20
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte .LVL142
+ .8byte .LVL143
+ .2byte 0xb
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5d
+ .byte 0x93
+ .uleb128 0x8
+ .byte 0x5c
+ .byte 0x93
+ .uleb128 0x4
+ .byte 0x5b
+ .byte 0x93
+ .uleb128 0x4
+ .8byte 0
+ .8byte 0
+.LLST56:
+ .8byte .LVL137
+ .8byte .LVL139
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL139
+ .8byte .LVL140
+ .2byte 0x2
+ .byte 0x70
+ .sleb128 0
+ .8byte 0
+ .8byte 0
+.LLST57:
+ .8byte .LVL137
+ .8byte .LVL141
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL141
+ .8byte .LVL142
+ .2byte 0x2
+ .byte 0x71
+ .sleb128 20
+ .8byte 0
+ .8byte 0
+.LLST58:
+ .8byte .LVL138
+ .8byte .LVL139
+ .2byte 0x11
+ .byte 0x71
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200148
+ .8byte .LVL139
+ .8byte .LVL140
+ .2byte 0x13
+ .byte 0x70
+ .sleb128 0
+ .byte 0x94
+ .byte 0x4
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200148
+ .8byte 0
+ .8byte 0
+.LLST59:
+ .8byte .LVL134
+ .8byte .LVL135
+ .2byte 0x6
+ .byte 0x9e
+ .uleb128 0x4
+ .4byte 0xdeadbeaf
+ .8byte 0
+ .8byte 0
+.LLST60:
+ .8byte .LVL147
+ .8byte .LVL148
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST51:
+ .8byte .LVL110
+ .8byte .LVL111
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL111
+ .8byte .LFE236
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST52:
+ .8byte .LVL112
+ .8byte .LVL113
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST42:
+ .8byte .LVL99
+ .8byte .LVL100
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL100
+ .8byte .LVL102
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL102
+ .8byte .LVL105
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL105
+ .8byte .LFE235
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST43:
+ .8byte .LVL101
+ .8byte .LVL102
+ .2byte 0x12
+ .byte 0x86
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL102
+ .8byte .LVL105
+ .2byte 0x12
+ .byte 0x87
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL105
+ .8byte .LVL106
+ .2byte 0x13
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL106
+ .8byte .LFE235
+ .2byte 0x12
+ .byte 0x87
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST44:
+ .8byte .LVL101
+ .8byte .LVL103
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL103
+ .8byte .LVL104
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL106
+ .8byte .LFE235
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST45:
+ .8byte .LVL107
+ .8byte .LVL108-1
+ .2byte 0x2
+ .byte 0x83
+ .sleb128 16
+ .8byte 0
+ .8byte 0
+.LLST46:
+ .8byte .LVL107
+ .8byte .LVL108-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte 0
+ .8byte 0
+.LLST47:
+ .8byte .LVL107
+ .8byte .LVL108
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST48:
+ .8byte .LVL107
+ .8byte .LVL108
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST49:
+ .8byte .LVL107
+ .8byte .LVL108
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST50:
+ .8byte .LVL107
+ .8byte .LVL108
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST31:
+ .8byte .LVL88
+ .8byte .LVL91
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL91
+ .8byte .LVL92
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL92
+ .8byte .LVL94
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL94
+ .8byte .LFE234
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST32:
+ .8byte .LVL88
+ .8byte .LVL93
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL93
+ .8byte .LVL94
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL94
+ .8byte .LVL95
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL95
+ .8byte .LFE234
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST33:
+ .8byte .LVL88
+ .8byte .LVL90
+ .2byte 0x12
+ .byte 0x70
+ .sleb128 0
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL90
+ .8byte .LVL92
+ .2byte 0xc
+ .byte 0x89
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL92
+ .8byte .LVL94
+ .2byte 0xc
+ .byte 0x86
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL94
+ .8byte .LVL95
+ .2byte 0x13
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0xc
+ .4byte 0xffffffff
+ .byte 0x1a
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL95
+ .8byte .LFE234
+ .2byte 0xc
+ .byte 0x86
+ .sleb128 0
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST34:
+ .8byte .LVL93
+ .8byte .LVL94
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL95
+ .8byte .LFE234
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST35:
+ .8byte .LVL88
+ .8byte .LVL89
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST36:
+ .8byte .LVL96
+ .8byte .LVL97-1
+ .2byte 0x2
+ .byte 0x83
+ .sleb128 16
+ .8byte 0
+ .8byte 0
+.LLST37:
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST38:
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST39:
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST40:
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST41:
+ .8byte .LVL96
+ .8byte .LVL97
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST28:
+ .8byte .LVL80
+ .8byte .LVL81
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL81
+ .8byte .LVL86
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL86
+ .8byte .LVL87-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL87-1
+ .8byte .LFE232
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST29:
+ .8byte .LVL81
+ .8byte .LVL86
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL86
+ .8byte .LVL87-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL87-1
+ .8byte .LFE232
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST30:
+ .8byte .LVL83
+ .8byte .LVL84
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte .LVL84
+ .8byte .LVL85
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST8:
+ .8byte .LVL25
+ .8byte .LVL26
+ .2byte 0x1e
+ .byte 0x86
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0x8
+ .byte 0x28
+ .byte 0x1e
+ .byte 0x85
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x22
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte .LVL26
+ .8byte .LVL34
+ .2byte 0x1e
+ .byte 0x86
+ .sleb128 -1
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0x8
+ .byte 0x28
+ .byte 0x1e
+ .byte 0x85
+ .sleb128 0
+ .byte 0x8
+ .byte 0x20
+ .byte 0x24
+ .byte 0x8
+ .byte 0x20
+ .byte 0x26
+ .byte 0xa
+ .2byte 0x148
+ .byte 0x1e
+ .byte 0x22
+ .byte 0x23
+ .uleb128 0x8200008
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST9:
+ .8byte .LVL24
+ .8byte .LVL36
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST10:
+ .8byte .LVL25
+ .8byte .LVL26
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL26
+ .8byte .LVL34
+ .2byte 0x3
+ .byte 0x86
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL34
+ .8byte .LVL36
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST5:
+ .8byte .LVL11
+ .8byte .LVL12
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL12
+ .8byte .LVL17
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL17
+ .8byte .LVL19
+ .2byte 0x5
+ .byte 0x8b
+ .sleb128 65536
+ .byte 0x9f
+ .8byte .LVL19
+ .8byte .LVL20
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL20
+ .8byte .LVL22
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL22
+ .8byte .LVL23
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL23
+ .8byte .LFE228
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST6:
+ .8byte .LVL13
+ .8byte .LVL18
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL20
+ .8byte .LVL22
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST7:
+ .8byte .LVL20
+ .8byte .LVL22
+ .2byte 0x3
+ .byte 0x84
+ .sleb128 -4
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST0:
+ .8byte .LVL0
+ .8byte .LVL1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL1
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x55
+ .8byte .LVL3
+ .8byte .LFE227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST1:
+ .8byte .LVL0
+ .8byte .LVL7
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL7
+ .8byte .LFE227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST2:
+ .8byte .LVL0
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL8-1
+ .8byte .LFE227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST3:
+ .8byte .LVL2
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL4
+ .8byte .LVL6
+ .2byte 0x1
+ .byte 0x53
+ .8byte 0
+ .8byte 0
+.LLST4:
+ .8byte .LVL9
+ .8byte .LVL10
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL10
+ .8byte .LFE220
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST11:
+ .8byte .LVL37
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL39
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL69
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL71
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST12:
+ .8byte .LVL37
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL39
+ .8byte .LVL67
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL67
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST13:
+ .8byte .LVL37
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL39
+ .8byte .LVL72
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL72
+ .8byte .LVL74
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL74
+ .8byte .LVL77
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL77
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST14:
+ .8byte .LVL37
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL39
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL47
+ .8byte .LVL50
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL50
+ .8byte .LVL55
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL55
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST15:
+ .8byte .LVL59
+ .8byte .LVL60
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL60
+ .8byte .LVL68
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST16:
+ .8byte .LVL63
+ .8byte .LVL64
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL64
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL74
+ .8byte .LVL78
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL78
+ .8byte .LVL79-1
+ .2byte 0x2
+ .byte 0x72
+ .sleb128 32
+ .8byte 0
+ .8byte 0
+.LLST17:
+ .8byte .LVL46
+ .8byte .LVL50
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL56
+ .8byte .LVL68
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST18:
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL39
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL69
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL71
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST19:
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL39
+ .8byte .LVL72
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL72
+ .8byte .LVL74
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL74
+ .8byte .LVL77
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL77
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST20:
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL39
+ .8byte .LVL45
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL50
+ .8byte .LVL55
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST21:
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL39
+ .8byte .LVL45
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL50
+ .8byte .LVL55
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST22:
+ .8byte .LVL39
+ .8byte .LVL45
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL50
+ .8byte .LVL55
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST23:
+ .8byte .LVL40
+ .8byte .LVL43
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL50
+ .8byte .LVL51
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL51
+ .8byte .LVL52
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e21
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL52
+ .8byte .LVL53
+ .2byte 0x7
+ .byte 0xa
+ .2byte 0x4e20
+ .byte 0x88
+ .sleb128 0
+ .byte 0x1c
+ .byte 0x9f
+ .8byte .LVL53
+ .8byte .LVL55
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST24:
+ .8byte .LVL68
+ .8byte .LVL73
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL74
+ .8byte .LVL78
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL78
+ .8byte .LVL79-1
+ .2byte 0x2
+ .byte 0x72
+ .sleb128 32
+ .8byte 0
+ .8byte 0
+.LLST25:
+ .8byte .LVL68
+ .8byte .LVL72
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL72
+ .8byte .LVL74
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL74
+ .8byte .LVL77
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL77
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST26:
+ .8byte .LVL68
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL69
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL71
+ .8byte .LFE242
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST27:
+ .8byte .LVL70
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL74
+ .8byte .LVL76
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+ .section .debug_aranges,"",@progbits
+ .4byte 0xdc
+ .2byte 0x2
+ .4byte .Ldebug_info0
+ .byte 0x8
+ .byte 0
+ .2byte 0
+ .2byte 0
+ .8byte .LFB227
+ .8byte .LFE227-.LFB227
+ .8byte .LFB220
+ .8byte .LFE220-.LFB220
+ .8byte .LFB228
+ .8byte .LFE228-.LFB228
+ .8byte .LFB229
+ .8byte .LFE229-.LFB229
+ .8byte .LFB242
+ .8byte .LFE242-.LFB242
+ .8byte .LFB232
+ .8byte .LFE232-.LFB232
+ .8byte .LFB234
+ .8byte .LFE234-.LFB234
+ .8byte .LFB235
+ .8byte .LFE235-.LFB235
+ .8byte .LFB236
+ .8byte .LFE236-.LFB236
+ .8byte .LFB238
+ .8byte .LFE238-.LFB238
+ .8byte .LFB239
+ .8byte .LFE239-.LFB239
+ .8byte .LFB240
+ .8byte .LFE240-.LFB240
+ .8byte 0
+ .8byte 0
+ .section .debug_ranges,"",@progbits
+.Ldebug_ranges0:
+ .8byte .LBB32
+ .8byte .LBE32
+ .8byte .LBB35
+ .8byte .LBE35
+ .8byte 0
+ .8byte 0
+ .8byte .LBB48
+ .8byte .LBE48
+ .8byte .LBB51
+ .8byte .LBE51
+ .8byte 0
+ .8byte 0
+ .8byte .LBB52
+ .8byte .LBE52
+ .8byte .LBB65
+ .8byte .LBE65
+ .8byte .LBB66
+ .8byte .LBE66
+ .8byte .LBB67
+ .8byte .LBE67
+ .8byte .LBB68
+ .8byte .LBE68
+ .8byte .LBB69
+ .8byte .LBE69
+ .8byte 0
+ .8byte 0
+ .8byte .LBB56
+ .8byte .LBE56
+ .8byte .LBB59
+ .8byte .LBE59
+ .8byte 0
+ .8byte 0
+ .8byte .LBB74
+ .8byte .LBE74
+ .8byte .LBB79
+ .8byte .LBE79
+ .8byte 0
+ .8byte 0
+ .8byte .LBB86
+ .8byte .LBE86
+ .8byte .LBB89
+ .8byte .LBE89
+ .8byte 0
+ .8byte 0
+ .8byte .LBB98
+ .8byte .LBE98
+ .8byte .LBB105
+ .8byte .LBE105
+ .8byte 0
+ .8byte 0
+ .8byte .LBB100
+ .8byte .LBE100
+ .8byte .LBB103
+ .8byte .LBE103
+ .8byte 0
+ .8byte 0
+ .8byte .LBB120
+ .8byte .LBE120
+ .8byte .LBB131
+ .8byte .LBE131
+ .8byte 0
+ .8byte 0
+ .8byte .LBB122
+ .8byte .LBE122
+ .8byte .LBB126
+ .8byte .LBE126
+ .8byte .LBB129
+ .8byte .LBE129
+ .8byte 0
+ .8byte 0
+ .8byte .LFB227
+ .8byte .LFE227
+ .8byte .LFB220
+ .8byte .LFE220
+ .8byte .LFB228
+ .8byte .LFE228
+ .8byte .LFB229
+ .8byte .LFE229
+ .8byte .LFB242
+ .8byte .LFE242
+ .8byte .LFB232
+ .8byte .LFE232
+ .8byte .LFB234
+ .8byte .LFE234
+ .8byte .LFB235
+ .8byte .LFE235
+ .8byte .LFB236
+ .8byte .LFE236
+ .8byte .LFB238
+ .8byte .LFE238
+ .8byte .LFB239
+ .8byte .LFE239
+ .8byte .LFB240
+ .8byte .LFE240
+ .8byte 0
+ .8byte 0
+ .section .debug_line,"",@progbits
+.Ldebug_line0:
+ .section .debug_str,"MS",@progbits,1
+.LASF83:
+ .string "off_mem_rsvmap"
+.LASF166:
+ .string "UCLASS_I2C_EEPROM"
+.LASF298:
+ .string "jt_funcs"
+.LASF171:
+ .string "UCLASS_IRQ"
+.LASF133:
+ .string "initrd_start"
+.LASF165:
+ .string "UCLASS_I2C"
+.LASF13:
+ .string "sizetype"
+.LASF312:
+ .string "net_hostname"
+.LASF36:
+ .string "start"
+.LASF206:
+ .string "UCLASS_SPI"
+.LASF169:
+ .string "UCLASS_I2S"
+.LASF334:
+ .string "NETLOOP_RESTART"
+.LASF167:
+ .string "UCLASS_I2C_GENERIC"
+.LASF179:
+ .string "UCLASS_MOD_EXP"
+.LASF230:
+ .string "UCLASS_IO_DOMAIN"
+.LASF251:
+ .string "using_pre_serial"
+.LASF200:
+ .string "UCLASS_RKNAND"
+.LASF142:
+ .string "UCLASS_DEMO"
+.LASF373:
+ .string "rip_fail"
+.LASF91:
+ .string "ih_magic"
+.LASF29:
+ .string "list_head"
+.LASF292:
+ .string "pm_ctx_phys"
+.LASF146:
+ .string "UCLASS_TEST_PROBE"
+.LASF226:
+ .string "UCLASS_KEY"
+.LASF64:
+ .string "bi_intfreq"
+.LASF11:
+ .string "phys_addr_t"
+.LASF221:
+ .string "UCLASS_VIDEO_BRIDGE"
+.LASF291:
+ .string "video_bottom"
+.LASF5:
+ .string "__u8"
+.LASF377:
+ .string "task_list"
+.LASF333:
+ .string "NETLOOP_CONTINUE"
+.LASF209:
+ .string "UCLASS_SPI_GENERIC"
+.LASF286:
+ .string "malloc_base"
+.LASF369:
+ .string "tid_name"
+.LASF40:
+ .string "flash_info_t"
+.LASF184:
+ .string "UCLASS_PANEL"
+.LASF108:
+ .string "comp"
+.LASF103:
+ .string "image_header_t"
+.LASF138:
+ .string "state"
+.LASF412:
+ .string "disable_serror"
+.LASF159:
+ .string "UCLASS_CROS_EC"
+.LASF58:
+ .string "bi_dsp_freq"
+.LASF105:
+ .string "image_start"
+.LASF422:
+ .string "invalidate_icache_all"
+.LASF420:
+ .string "disable_interrupts"
+.LASF144:
+ .string "UCLASS_TEST_FDT"
+.LASF49:
+ .string "bd_info"
+.LASF331:
+ .string "uclass_id"
+.LASF95:
+ .string "ih_load"
+.LASF215:
+ .string "UCLASS_UFS"
+.LASF302:
+ .string "__dtb_dt_spl_begin"
+.LASF363:
+ .string "TASK_LOAD_UBOOT"
+.LASF7:
+ .string "__u32"
+.LASF149:
+ .string "UCLASS_PCI_EMUL"
+.LASF430:
+ .string "/home4/cjh/uboot-nextdev-v3"
+.LASF289:
+ .string "cur_serial_dev"
+.LASF318:
+ .string "net_tx_packet"
+.LASF225:
+ .string "UCLASS_FG"
+.LASF317:
+ .string "net_server_ip"
+.LASF325:
+ .string "net_native_vlan"
+.LASF265:
+ .string "ram_top_ext_size"
+.LASF223:
+ .string "UCLASS_VIDEO_CRTC"
+.LASF158:
+ .string "UCLASS_CODEC"
+.LASF283:
+ .string "env_buf"
+.LASF20:
+ .string "errno"
+.LASF15:
+ .string "long int"
+.LASF53:
+ .string "bi_flashsize"
+.LASF339:
+ .string "__bss_end"
+.LASF189:
+ .string "UCLASS_PHY"
+.LASF76:
+ .string "IRQ_STACK_START_IN"
+.LASF87:
+ .string "size_dt_strings"
+.LASF220:
+ .string "UCLASS_VIDEO"
+.LASF356:
+ .string "EVT_CRYPTO"
+.LASF266:
+ .string "relocaddr"
+.LASF389:
+ .string "mpb_post"
+.LASF429:
+ .string "common/mp_boot.c"
+.LASF328:
+ .string "net_boot_file_size"
+.LASF374:
+ .string "cpu_core"
+.LASF97:
+ .string "ih_dcrc"
+.LASF63:
+ .string "bi_ethspeed"
+.LASF141:
+ .string "UCLASS_ROOT"
+.LASF26:
+ .string "ide_bus_offset"
+.LASF361:
+ .string "TASK_INIT_DISPLAY"
+.LASF315:
+ .string "net_server_ethaddr"
+.LASF66:
+ .string "bi_arch_number"
+.LASF3:
+ .string "signed char"
+.LASF172:
+ .string "UCLASS_KEYBOARD"
+.LASF18:
+ .string "uint8_t"
+.LASF38:
+ .string "udevice"
+.LASF418:
+ .string "udelay"
+.LASF99:
+ .string "ih_arch"
+.LASF80:
+ .string "totalsize"
+.LASF92:
+ .string "ih_hcrc"
+.LASF268:
+ .string "mon_len"
+.LASF107:
+ .string "load"
+.LASF214:
+ .string "UCLASS_TPM"
+.LASF43:
+ .string "lmb_property"
+.LASF85:
+ .string "last_comp_version"
+.LASF0:
+ .string "unsigned char"
+.LASF140:
+ .string "images"
+.LASF341:
+ .string "priv"
+.LASF229:
+ .string "UCLASS_DVFS"
+.LASF59:
+ .string "bi_ddr_freq"
+.LASF403:
+ .string "mpb_initial"
+.LASF173:
+ .string "UCLASS_LED"
+.LASF94:
+ .string "ih_size"
+.LASF419:
+ .string "dcache_enable"
+.LASF203:
+ .string "UCLASS_SCMI_AGENT"
+.LASF233:
+ .string "UCLASS_MDIO"
+.LASF22:
+ .string "_Bool"
+.LASF337:
+ .string "net_state"
+.LASF168:
+ .string "UCLASS_I2C_MUX"
+.LASF14:
+ .string "char"
+.LASF24:
+ .string "_binary_u_boot_bin_start"
+.LASF219:
+ .string "UCLASS_USB_GADGET_GENERIC"
+.LASF335:
+ .string "NETLOOP_SUCCESS"
+.LASF415:
+ .string "printf"
+.LASF372:
+ .string "ptid_mask"
+.LASF332:
+ .string "net_loop_state"
+.LASF247:
+ .string "tlb_size"
+.LASF274:
+ .string "dm_root_f"
+.LASF157:
+ .string "UCLASS_AMP"
+.LASF195:
+ .string "UCLASS_PWRSEQ"
+.LASF123:
+ .string "fit_hdr_fdt"
+.LASF326:
+ .string "net_restart_wrap"
+.LASF314:
+ .string "net_ethaddr"
+.LASF256:
+ .string "flags"
+.LASF100:
+ .string "ih_type"
+.LASF355:
+ .string "EVT_BOOT_SIZE"
+.LASF81:
+ .string "off_dt_struct"
+.LASF413:
+ .string "mdelay"
+.LASF54:
+ .string "bi_flashoffset"
+.LASF327:
+ .string "net_boot_file_name"
+.LASF143:
+ .string "UCLASS_TEST"
+.LASF397:
+ .string "mpb_task_dump"
+.LASF93:
+ .string "ih_time"
+.LASF258:
+ .string "bus_clk"
+.LASF196:
+ .string "UCLASS_RAM"
+.LASF162:
+ .string "UCLASS_ETH"
+.LASF364:
+ .string "TASK_LOAD_FIT"
+.LASF104:
+ .string "image_info"
+.LASF110:
+ .string "arch"
+.LASF260:
+ .string "mem_clk"
+.LASF257:
+ .string "cpu_clk"
+.LASF32:
+ .string "select_hwpart"
+.LASF319:
+ .string "net_rx_packets"
+.LASF75:
+ .string "_datarelro_start_ofs"
+.LASF17:
+ .string "ulong"
+.LASF371:
+ .string "task_fn"
+.LASF96:
+ .string "ih_ep"
+.LASF45:
+ .string "lmb_region"
+.LASF375:
+ .string "task"
+.LASF392:
+ .string "mpb_task_wait_timeout_done"
+.LASF400:
+ .string "tid_to_task_index"
+.LASF118:
+ .string "fit_uname_os"
+.LASF60:
+ .string "bi_bootflags"
+.LASF316:
+ .string "net_ip"
+.LASF278:
+ .string "fdt_size"
+.LASF310:
+ .string "net_dns_server"
+.LASF338:
+ .string "__bss_start"
+.LASF330:
+ .string "net_ping_ip"
+.LASF47:
+ .string "memory"
+.LASF78:
+ .string "fdt_header"
+.LASF175:
+ .string "UCLASS_MAILBOX"
+.LASF343:
+ .string "filename"
+.LASF130:
+ .string "rd_end"
+.LASF269:
+ .string "irq_sp"
+.LASF135:
+ .string "cmdline_start"
+.LASF255:
+ .string "global_data"
+.LASF358:
+ .string "EVT_SIMPLE_BOOTM"
+.LASF366:
+ .string "TASK_HASH_ANDROID"
+.LASF204:
+ .string "UCLASS_SCSI"
+.LASF217:
+ .string "UCLASS_USB_DEV_GENERIC"
+.LASF176:
+ .string "UCLASS_MASS_STORAGE"
+.LASF1:
+ .string "long unsigned int"
+.LASF151:
+ .string "UCLASS_SIMPLE_BUS"
+.LASF299:
+ .string "gd_t"
+.LASF311:
+ .string "net_nis_domain"
+.LASF125:
+ .string "fit_noffset_fdt"
+.LASF342:
+ .string "bl_len"
+.LASF427:
+ .string "get_ticks"
+.LASF336:
+ .string "NETLOOP_FAIL"
+.LASF224:
+ .string "UCLASS_WDT"
+.LASF245:
+ .string "timer_reset_value"
+.LASF270:
+ .string "start_addr_sp"
+.LASF55:
+ .string "bi_sramstart"
+.LASF25:
+ .string "_binary_u_boot_bin_end"
+.LASF271:
+ .string "reloc_off"
+.LASF86:
+ .string "boot_cpuid_phys"
+.LASF244:
+ .string "lastinc"
+.LASF248:
+ .string "tlb_fillptr"
+.LASF121:
+ .string "fit_uname_rd"
+.LASF210:
+ .string "UCLASS_SYSCON"
+.LASF116:
+ .string "fit_uname_cfg"
+.LASF205:
+ .string "UCLASS_SERIAL"
+.LASF324:
+ .string "net_our_vlan"
+.LASF294:
+ .string "serial"
+.LASF154:
+ .string "UCLASS_BLK"
+.LASF111:
+ .string "image_info_t"
+.LASF150:
+ .string "UCLASS_USB_EMUL"
+.LASF421:
+ .string "icache_disable"
+.LASF246:
+ .string "tlb_addr"
+.LASF188:
+ .string "UCLASS_PCI_GENERIC"
+.LASF370:
+ .string "task_t"
+.LASF407:
+ .string "spl_load_android"
+.LASF387:
+ .string "ticks"
+.LASF106:
+ .string "image_len"
+.LASF362:
+ .string "TASK_LOAD_BASEPARAMETER"
+.LASF61:
+ .string "bi_ip_addr"
+.LASF393:
+ .string "timeout_ms"
+.LASF190:
+ .string "UCLASS_PINCONFIG"
+.LASF384:
+ .string "smp_entry"
+.LASF212:
+ .string "UCLASS_THERMAL"
+.LASF114:
+ .string "legacy_hdr_os_copy"
+.LASF354:
+ .string "EVT_BOOT_ADDR"
+.LASF9:
+ .string "long long int"
+.LASF277:
+ .string "new_fdt"
+.LASF21:
+ .string "___strtok"
+.LASF329:
+ .string "net_boot_file_expected_size_in_blocks"
+.LASF252:
+ .string "enable"
+.LASF395:
+ .string "ptid"
+.LASF183:
+ .string "UCLASS_NVME"
+.LASF249:
+ .string "tlb_emerg"
+.LASF112:
+ .string "bootm_headers"
+.LASF37:
+ .string "protect"
+.LASF216:
+ .string "UCLASS_USB"
+.LASF227:
+ .string "UCLASS_RC"
+.LASF398:
+ .string "mpb_task_is_done"
+.LASF284:
+ .string "timebase_h"
+.LASF285:
+ .string "timebase_l"
+.LASF160:
+ .string "UCLASS_DISPLAY"
+.LASF323:
+ .string "net_null_ethaddr"
+.LASF263:
+ .string "env_valid"
+.LASF228:
+ .string "UCLASS_CHARGE_DISPLAY"
+.LASF303:
+ .string "load_addr"
+.LASF117:
+ .string "fit_hdr_os"
+.LASF73:
+ .string "_datarelrolocal_start_ofs"
+.LASF396:
+ .string "timeout"
+.LASF254:
+ .string "addr"
+.LASF344:
+ .string "read"
+.LASF8:
+ .string "unsigned int"
+.LASF16:
+ .string "ushort"
+.LASF402:
+ .string "task_is_registered"
+.LASF281:
+ .string "ufdt_blob"
+.LASF410:
+ .string "spl_init_display"
+.LASF287:
+ .string "malloc_limit"
+.LASF401:
+ .string "mpb_task_register"
+.LASF192:
+ .string "UCLASS_PMIC"
+.LASF113:
+ .string "legacy_hdr_os"
+.LASF82:
+ .string "off_dt_strings"
+.LASF300:
+ .string "monitor_flash_len"
+.LASF177:
+ .string "UCLASS_MISC"
+.LASF51:
+ .string "bi_memsize"
+.LASF394:
+ .string "mpb_task_wait_parent"
+.LASF23:
+ .string "image_base"
+.LASF382:
+ .string "mpb_init_1"
+.LASF211:
+ .string "UCLASS_SYSRESET"
+.LASF164:
+ .string "UCLASS_FIRMWARE"
+.LASF425:
+ .string "invalidate_dcache_range"
+.LASF174:
+ .string "UCLASS_LPC"
+.LASF170:
+ .string "UCLASS_IDE"
+.LASF290:
+ .string "video_top"
+.LASF280:
+ .string "of_root_f"
+.LASF139:
+ .string "bootm_headers_t"
+.LASF57:
+ .string "bi_arm_freq"
+.LASF198:
+ .string "UCLASS_REMOTEPROC"
+.LASF109:
+ .string "type"
+.LASF120:
+ .string "fit_hdr_rd"
+.LASF388:
+ .string "fail"
+.LASF262:
+ .string "env_addr"
+.LASF56:
+ .string "bi_sramsize"
+.LASF348:
+ .string "boot_size"
+.LASF390:
+ .string "mpb_task_wait_done"
+.LASF406:
+ .string "spl_hash_android"
+.LASF275:
+ .string "uclass_root"
+.LASF163:
+ .string "UCLASS_GPIO"
+.LASF193:
+ .string "UCLASS_PWM"
+.LASF404:
+ .string "set_gd"
+.LASF42:
+ .string "long double"
+.LASF264:
+ .string "ram_top"
+.LASF296:
+ .string "console_evt"
+.LASF381:
+ .string "mpb_init_x"
+.LASF431:
+ .string "mpb_task_set_state"
+.LASF129:
+ .string "rd_start"
+.LASF194:
+ .string "UCLASS_POWER_DOMAIN"
+.LASF197:
+ .string "UCLASS_REGULATOR"
+.LASF305:
+ .string "save_size"
+.LASF414:
+ .string "msec"
+.LASF155:
+ .string "UCLASS_CLK"
+.LASF391:
+ .string "core_task_run"
+.LASF346:
+ .string "info"
+.LASF72:
+ .string "_datarel_start_ofs"
+.LASF250:
+ .string "pre_serial"
+.LASF428:
+ .ascii "GNU C11 6.3.1 201"
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
+.LASF102:
+ .string "ih_name"
+.LASF98:
+ .string "ih_os"
+.LASF345:
+ .string "task_data"
+.LASF136:
+ .string "cmdline_end"
+.LASF320:
+ .string "net_rx_packet"
+.LASF241:
+ .string "LOGF_MAX_CATEGORIES"
+.LASF276:
+ .string "fdt_blob"
+.LASF33:
+ .string "size"
+.LASF10:
+ .string "long long unsigned int"
+.LASF90:
+ .string "image_header"
+.LASF350:
+ .string "CPU_1"
+.LASF19:
+ .string "__be32"
+.LASF52:
+ .string "bi_flashstart"
+.LASF119:
+ .string "fit_noffset_os"
+.LASF399:
+ .string "mpb_task_set_result"
+.LASF178:
+ .string "UCLASS_MMC"
+.LASF240:
+ .string "UCLASS_INVALID"
+.LASF376:
+ .string "mpb_core"
+.LASF218:
+ .string "UCLASS_USB_HUB"
+.LASF279:
+ .string "of_root"
+.LASF234:
+ .string "UCLASS_EBC"
+.LASF340:
+ .string "spl_load_info"
+.LASF293:
+ .string "new_line"
+.LASF416:
+ .string "memset"
+.LASF41:
+ .string "flash_info"
+.LASF84:
+ .string "version"
+.LASF46:
+ .string "region"
+.LASF88:
+ .string "size_dt_struct"
+.LASF273:
+ .string "dm_root"
+.LASF236:
+ .string "UCLASS_RNG"
+.LASF295:
+ .string "sys_start_tick"
+.LASF180:
+ .string "UCLASS_MTD"
+.LASF77:
+ .string "fdt32_t"
+.LASF272:
+ .string "new_gd"
+.LASF182:
+ .string "UCLASS_NORTHBRIDGE"
+.LASF62:
+ .string "bi_enetaddr"
+.LASF39:
+ .string "mtd_info"
+.LASF306:
+ .string "in_addr"
+.LASF321:
+ .string "net_rx_packet_len"
+.LASF383:
+ .string "init"
+.LASF301:
+ .string "__dtb_dt_begin"
+.LASF199:
+ .string "UCLASS_RESET"
+.LASF122:
+ .string "fit_noffset_rd"
+.LASF153:
+ .string "UCLASS_AHCI"
+.LASF12:
+ .string "phys_size_t"
+.LASF156:
+ .string "UCLASS_CPU"
+.LASF71:
+ .string "FIQ_STACK_START"
+.LASF137:
+ .string "verify"
+.LASF31:
+ .string "name"
+.LASF235:
+ .string "UCLASS_EINK_DISPLAY"
+.LASF185:
+ .string "UCLASS_PANEL_BACKLIGHT"
+.LASF213:
+ .string "UCLASS_TIMER"
+.LASF208:
+ .string "UCLASS_SPI_FLASH"
+.LASF261:
+ .string "have_console"
+.LASF65:
+ .string "bi_busfreq"
+.LASF6:
+ .string "short int"
+.LASF347:
+ .string "boot_addr"
+.LASF191:
+ .string "UCLASS_PINCTRL"
+.LASF201:
+ .string "UCLASS_RAMDISK"
+.LASF148:
+ .string "UCLASS_I2C_EMUL"
+.LASF365:
+ .string "TASK_LOAD_ANDROID"
+.LASF207:
+ .string "UCLASS_SPMI"
+.LASF378:
+ .string "tdata"
+.LASF145:
+ .string "UCLASS_TEST_BUS"
+.LASF417:
+ .string "flush_dcache_all"
+.LASF304:
+ .string "save_addr"
+.LASF426:
+ .string "flush_dcache_range"
+.LASF288:
+ .string "malloc_ptr"
+.LASF411:
+ .string "cpuectlr_disable"
+.LASF386:
+ .string "mpb_task_run"
+.LASF408:
+ .string "spl_load_fit"
+.LASF134:
+ .string "initrd_end"
+.LASF359:
+ .string "EVT_VIDEO_BP"
+.LASF253:
+ .string "baudrate"
+.LASF74:
+ .string "_datarellocal_start_ofs"
+.LASF242:
+ .string "arch_global_data"
+.LASF239:
+ .string "UCLASS_COUNT"
+.LASF349:
+ .string "CPU_0"
+.LASF259:
+ .string "pci_clk"
+.LASF351:
+ .string "CPU_2"
+.LASF352:
+ .string "CPU_3"
+.LASF30:
+ .string "block_drvr"
+.LASF433:
+ .string "memcpy"
+.LASF35:
+ .string "flash_id"
+.LASF231:
+ .string "UCLASS_CRYPTO"
+.LASF297:
+ .string "device_node"
+.LASF267:
+ .string "ram_size"
+.LASF128:
+ .string "fit_noffset_setup"
+.LASF89:
+ .string "working_fdt"
+.LASF282:
+ .string "fdt_blob_kern"
+.LASF313:
+ .string "net_root_path"
+.LASF161:
+ .string "UCLASS_DMA"
+.LASF69:
+ .string "bd_t"
+.LASF237:
+ .string "UCLASS_DMC"
+.LASF307:
+ .string "s_addr"
+.LASF322:
+ .string "net_bcast_ethaddr"
+.LASF379:
+ .string "mpb_gd"
+.LASF67:
+ .string "bi_boot_params"
+.LASF308:
+ .string "net_gateway"
+.LASF50:
+ .string "bi_memstart"
+.LASF222:
+ .string "UCLASS_VIDEO_CONSOLE"
+.LASF48:
+ .string "reserved"
+.LASF360:
+ .string "TASK_NONE"
+.LASF238:
+ .string "UCLASS_PD"
+.LASF423:
+ .string "dcache_disable"
+.LASF68:
+ .string "bi_dram"
+.LASF2:
+ .string "short unsigned int"
+.LASF79:
+ .string "magic"
+.LASF126:
+ .string "fit_hdr_setup"
+.LASF115:
+ .string "legacy_hdr_valid"
+.LASF368:
+ .string "TASK_MAX"
+.LASF44:
+ .string "base"
+.LASF432:
+ .string "spl_dummy"
+.LASF202:
+ .string "UCLASS_RTC"
+.LASF353:
+ .string "EVT_BOOT_DEV"
+.LASF243:
+ .string "timer_rate_hz"
+.LASF34:
+ .string "sector_count"
+.LASF101:
+ .string "ih_comp"
+.LASF385:
+ .string "core_main"
+.LASF131:
+ .string "ft_addr"
+.LASF232:
+ .string "UCLASS_ETH_PHY"
+.LASF380:
+ .string "task_init"
+.LASF4:
+ .string "uchar"
+.LASF132:
+ .string "ft_len"
+.LASF27:
+ .string "next"
+.LASF405:
+ .string "data"
+.LASF181:
+ .string "UCLASS_NOP"
+.LASF367:
+ .string "TASK_RUN_UBOOT"
+.LASF357:
+ .string "EVT_LINUX"
+.LASF127:
+ .string "fit_uname_setup"
+.LASF28:
+ .string "prev"
+.LASF424:
+ .string "invalidate_dcache_all"
+.LASF186:
+ .string "UCLASS_PCH"
+.LASF187:
+ .string "UCLASS_PCI"
+.LASF309:
+ .string "net_netmask"
+.LASF70:
+ .string "IRQ_STACK_START"
+.LASF152:
+ .string "UCLASS_ADC"
+.LASF147:
+ .string "UCLASS_SPI_EMUL"
+.LASF409:
+ .string "spl_load_baseparamter"
+.LASF124:
+ .string "fit_uname_fdt"
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
+ .section .note.GNU-stack,"",@progbits
diff --git a/u-boot/configs/px30-tb_defconfig b/u-boot/configs/px30-tb_defconfig
index 3d6037c..9a084ff 100644
--- a/u-boot/configs/px30-tb_defconfig
+++ b/u-boot/configs/px30-tb_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
CONFIG_ROCKCHIP_PX30=y
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
diff --git a/u-boot/configs/px30_defconfig b/u-boot/configs/px30_defconfig
index 1882d48..0055891 100644
--- a/u-boot/configs/px30_defconfig
+++ b/u-boot/configs/px30_defconfig
@@ -135,6 +135,7 @@
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
+CONFIG_XBC=y
CONFIG_LZ4=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
diff --git a/u-boot/configs/rk-amp.config b/u-boot/configs/rk-amp.config
new file mode 100644
index 0000000..b76e182
--- /dev/null
+++ b/u-boot/configs/rk-amp.config
@@ -0,0 +1,3 @@
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+CONFIG_AMP=y
+CONFIG_ROCKCHIP_AMP=y
diff --git a/u-boot/configs/rk3036_defconfig b/u-boot/configs/rk3036_defconfig
index 2b91aaf..b0ea431 100644
--- a/u-boot/configs/rk3036_defconfig
+++ b/u-boot/configs/rk3036_defconfig
@@ -73,11 +73,13 @@
CONFIG_SYS_I2C_ROCKCHIP=y
CONFIG_DM_KEY=y
CONFIG_ADC_KEY=y
+CONFIG_GPIO_KEY=y
CONFIG_LED=y
CONFIG_MMC_DW=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=20000000
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_REGULATOR_PWM=y
diff --git a/u-boot/configs/rk3126_defconfig b/u-boot/configs/rk3126_defconfig
index a95e38d..f9bdb8e 100644
--- a/u-boot/configs/rk3126_defconfig
+++ b/u-boot/configs/rk3126_defconfig
@@ -15,6 +15,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
+# CONFIG_SKIP_RELOCATE_UBOOT is not set
CONFIG_FASTBOOT_BUF_ADDR=0x60800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
diff --git a/u-boot/configs/rk3128_defconfig b/u-boot/configs/rk3128_defconfig
index e24b274..c1c1ddc 100644
--- a/u-boot/configs/rk3128_defconfig
+++ b/u-boot/configs/rk3128_defconfig
@@ -2,7 +2,6 @@
CONFIG_ARCH_ROCKCHIP=y
CONFIG_SYS_MALLOC_F_LEN=0x38000
CONFIG_ROCKCHIP_RK3128=y
-CONFIG_RKIMG_BOOTLOADER=y
CONFIG_ROCKCHIP_VENDOR_PARTITION=y
CONFIG_DEFAULT_DEVICE_TREE="rk3126-evb"
CONFIG_DEBUG_UART=y
@@ -13,6 +12,7 @@
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_AVB=y
+# CONFIG_SKIP_RELOCATE_UBOOT is not set
CONFIG_FASTBOOT_BUF_ADDR=0x60800800
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
CONFIG_FASTBOOT_FLASH=y
@@ -82,9 +82,6 @@
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_DWC2_OTG=y
CONFIG_USB_GADGET_DOWNLOAD=y
-CONFIG_G_DNL_MANUFACTURER="Rockchip"
-CONFIG_G_DNL_VENDOR_NUM=0x2207
-CONFIG_G_DNL_PRODUCT_NUM=0x310c
CONFIG_DM_VIDEO=y
CONFIG_DISPLAY=y
CONFIG_VIDEO_ROCKCHIP=y
diff --git a/u-boot/configs/rk3128x_defconfig b/u-boot/configs/rk3128x_defconfig
index ada3b40..d0cc774 100644
--- a/u-boot/configs/rk3128x_defconfig
+++ b/u-boot/configs/rk3128x_defconfig
@@ -120,7 +120,7 @@
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
-CONFIG_ROCKCHIP_DRM_TVE=y
+CONFIG_DRM_ROCKCHIP_TVE=y
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
diff --git a/u-boot/configs/rk312x-rkflash.config b/u-boot/configs/rk312x-rkflash.config
new file mode 100644
index 0000000..92ad355
--- /dev/null
+++ b/u-boot/configs/rk312x-rkflash.config
@@ -0,0 +1,6 @@
+CONFIG_RKFLASH=y
+# CONFIG_RKNAND is not set
+CONFIG_CMD_RKSFC=y
+CONFIG_RKNANDC_NAND=y
+CONFIG_RKSFC_NAND=y
+CONFIG_RKSFC_NOR=y
diff --git a/u-boot/configs/rk322x_defconfig b/u-boot/configs/rk322x_defconfig
index a2ead85..22621cd 100644
--- a/u-boot/configs/rk322x_defconfig
+++ b/u-boot/configs/rk322x_defconfig
@@ -115,7 +115,7 @@
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
-CONFIG_ROCKCHIP_DRM_TVE=y
+CONFIG_DRM_ROCKCHIP_TVE=y
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
diff --git a/u-boot/configs/rk3308-amp.config b/u-boot/configs/rk3308-amp.config
new file mode 100644
index 0000000..4e7e3ba
--- /dev/null
+++ b/u-boot/configs/rk3308-amp.config
@@ -0,0 +1,3 @@
+CONFIG_AMP=y
+CONFIG_BASE_DEFCONFIG="rk3308_defconfig"
+CONFIG_ROCKCHIP_AMP=y
diff --git a/u-boot/configs/rk3326_defconfig b/u-boot/configs/rk3326_defconfig
index 290a283..d1f0e1f 100644
--- a/u-boot/configs/rk3326_defconfig
+++ b/u-boot/configs/rk3326_defconfig
@@ -69,6 +69,8 @@
CONFIG_SPL_SYSCON=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
+CONFIG_AMP=y
+CONFIG_ROCKCHIP_AMP=y
CONFIG_DM_CRYPTO=y
CONFIG_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
@@ -128,6 +130,8 @@
CONFIG_LCD=y
CONFIG_USE_TINY_PRINTF=y
CONFIG_SPL_TINY_MEMSET=y
+CONFIG_XBC=y
+CONFIG_SHA256=y
CONFIG_LZ4=y
CONFIG_LZO=y
CONFIG_ERRNO_STR=y
diff --git a/u-boot/configs/rk3328_defconfig b/u-boot/configs/rk3328_defconfig
index 2e7096b..03de227 100644
--- a/u-boot/configs/rk3328_defconfig
+++ b/u-boot/configs/rk3328_defconfig
@@ -129,7 +129,7 @@
CONFIG_DRM_ROCKCHIP_PANEL=y
CONFIG_DRM_ROCKCHIP_DW_HDMI=y
CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
-CONFIG_ROCKCHIP_DRM_TVE=y
+CONFIG_DRM_ROCKCHIP_TVE=y
CONFIG_LCD=y
# CONFIG_IRQ is not set
CONFIG_USE_TINY_PRINTF=y
diff --git a/u-boot/configs/rk3399_defconfig b/u-boot/configs/rk3399_defconfig
index cfadc7b..7c6e123 100644
--- a/u-boot/configs/rk3399_defconfig
+++ b/u-boot/configs/rk3399_defconfig
@@ -90,8 +90,8 @@
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_DM_FUEL_GAUGE=y
-CONFIG_POWER_FG_RK817=y
CONFIG_POWER_FG_RK818=y
+CONFIG_POWER_FG_RK817=y
CONFIG_IO_DOMAIN=y
CONFIG_ROCKCHIP_IO_DOMAIN=y
CONFIG_DM_PMIC=y
@@ -137,6 +137,7 @@
CONFIG_USE_TINY_PRINTF=y
CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
+CONFIG_XBC=y
CONFIG_ERRNO_STR=y
CONFIG_AVB_LIBAVB=y
CONFIG_AVB_LIBAVB_AB=y
diff --git a/u-boot/configs/rk3528-aarch32.config b/u-boot/configs/rk3528-aarch32.config
new file mode 100644
index 0000000..a80ed33
--- /dev/null
+++ b/u-boot/configs/rk3528-aarch32.config
@@ -0,0 +1,24 @@
+CONFIG_ARM64_BOOT_AARCH32=y
+# CONFIG_ARM64_SUPPORT_AARCH32 is not set
+# CONFIG_ARMV7_LPAE is not set
+CONFIG_BASE_DEFCONFIG="rk3528_defconfig"
+CONFIG_BOOTP_PXE_CLIENTARCH=0x15
+CONFIG_BOOTP_VCI_STRING="U-Boot.armv7"
+CONFIG_CPU_V7=y
+# CONFIG_DEBUG_LL is not set
+CONFIG_HAS_THUMB2=y
+CONFIG_HAS_VBAR=y
+CONFIG_HAVE_PRIVATE_LIBGCC=y
+# CONFIG_PHYS_64BIT is not set
+# CONFIG_SPL_OF_LIBFDT is not set
+CONFIG_SPL_SYS_THUMB_BUILD=y
+CONFIG_SPL_USE_ARCH_MEMCPY=y
+CONFIG_SPL_USE_ARCH_MEMSET=y
+CONFIG_SYS_ARM_ARCH=7
+CONFIG_SYS_CPU="armv7"
+CONFIG_SYS_THUMB_BUILD=y
+CONFIG_TPL_USE_ARCH_MEMCPY=y
+CONFIG_TPL_USE_ARCH_MEMSET=y
+CONFIG_USE_ARCH_MEMCPY=y
+CONFIG_USE_ARCH_MEMSET=y
+CONFIG_USE_PRIVATE_LIBGCC=y
diff --git a/u-boot/configs/rk3528_defconfig b/u-boot/configs/rk3528_defconfig
new file mode 100644
index 0000000..cfa8bbb
--- /dev/null
+++ b/u-boot/configs/rk3528_defconfig
@@ -0,0 +1,201 @@
+CONFIG_ARM=y
+CONFIG_ARM_SMCCC=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
+CONFIG_ROCKCHIP_RK3528=y
+CONFIG_ROCKCHIP_FIT_IMAGE=y
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
+CONFIG_USING_KERNEL_DTB_V2=y
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
+CONFIG_ROCKCHIP_NEW_IDB=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3528=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3528-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_HW_CRYPTO=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_HW_CRYPTO=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_BOOTDELAY=0
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ANDROID_BOOTLOADER=y
+CONFIG_ANDROID_AVB=y
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_CRYPTO_SUPPORT=y
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD_WRITE=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SPL_AB=y
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_BOOT_ANDROID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTP_BOOTM=y
+CONFIG_CMD_TFTP_FLASH=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTD_BLK=y
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clock-parents"
+# CONFIG_NET_TFTP_VARS is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DM_CRYPTO=y
+CONFIG_SPL_DM_CRYPTO=y
+CONFIG_ROCKCHIP_CRYPTO_V2=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SPL_SCMI_FIRMWARE=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEY=y
+CONFIG_ADC_KEY=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_MTD_BLK=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_PUYA=y
+CONFIG_SPI_FLASH_FMSH=y
+CONFIG_SPI_FLASH_DOSILICON=y
+CONFIG_SPI_FLASH_BOYA=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_PHY_RK630=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RESET_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_BASE=0xff9f0000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_VIDEO_ROCKCHIP=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_INNO_HDMI_PHY=y
+CONFIG_DRM_ROCKCHIP_TVE=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_N_SIZE=0x200
+CONFIG_RSA_E_SIZE=0x10
+CONFIG_RSA_C_SIZE=0x20
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_SPL_GZIP=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_AVB_LIBAVB=y
+CONFIG_AVB_LIBAVB_AB=y
+CONFIG_AVB_LIBAVB_ATX=y
+CONFIG_AVB_LIBAVB_USER=y
+CONFIG_RK_AVB_LIBAVB_USER=y
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
diff --git a/u-boot/configs/rk3562_defconfig b/u-boot/configs/rk3562_defconfig
new file mode 100644
index 0000000..229e37b
--- /dev/null
+++ b/u-boot/configs/rk3562_defconfig
@@ -0,0 +1,211 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
+CONFIG_ROCKCHIP_RK3562=y
+CONFIG_ROCKCHIP_FIT_IMAGE=y
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
+CONFIG_USING_KERNEL_DTB_V2=y
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
+CONFIG_ROCKCHIP_NEW_IDB=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3562=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3562-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_HW_CRYPTO=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_HW_CRYPTO=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_BOOTDELAY=0
+# CONFIG_CONSOLE_MUX is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ANDROID_BOOTLOADER=y
+CONFIG_ANDROID_AVB=y
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_SPL_MTD_WRITE=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
+CONFIG_SPL_AB=y
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
+CONFIG_FASTBOOT_BUF_SIZE=0x04000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_BOOT_ANDROID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTD_BLK=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_NET_TFTP_VARS is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DM_CRYPTO=y
+CONFIG_SPL_DM_CRYPTO=y
+CONFIG_ROCKCHIP_CRYPTO_V2=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SPL_SCMI_FIRMWARE=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_DM_KEY=y
+CONFIG_RK8XX_PWRKEY=y
+CONFIG_ADC_KEY=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_ROCKCHIP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_MTD=y
+CONFIG_MTD_BLK=y
+CONFIG_MTD_DEVICE=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_SPI_FLASH=y
+CONFIG_SF_DEFAULT_MODE=0x3
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
+CONFIG_SPI_FLASH_XTX=y
+CONFIG_SPI_FLASH_PUYA=y
+CONFIG_SPI_FLASH_FMSH=y
+CONFIG_SPI_FLASH_DOSILICON=y
+CONFIG_SPI_FLASH_BOYA=y
+CONFIG_SPI_FLASH_NORMEM=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_FUEL_GAUGE=y
+CONFIG_POWER_FG_RK817=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_REGULATOR_FAN53555=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK8XX=y
+CONFIG_DM_CHARGE_DISPLAY=y
+CONFIG_CHARGE_ANIMATION=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_DMC=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RESET_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_BASE=0xff210000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_ROCKCHIP_SFC=y
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY=y
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_DRM_ROCKCHIP_LVDS=y
+CONFIG_DRM_ROCKCHIP_RGB=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_N_SIZE=0x200
+CONFIG_RSA_E_SIZE=0x10
+CONFIG_RSA_C_SIZE=0x20
+CONFIG_XBC=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_LZ4=y
+CONFIG_SPL_GZIP=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_AVB_LIBAVB=y
+CONFIG_AVB_LIBAVB_AB=y
+CONFIG_AVB_LIBAVB_ATX=y
+CONFIG_AVB_LIBAVB_USER=y
+CONFIG_RK_AVB_LIBAVB_USER=y
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
diff --git a/u-boot/configs/rk3568-rt.config b/u-boot/configs/rk3568-rt.config
new file mode 100644
index 0000000..8dc3c69
--- /dev/null
+++ b/u-boot/configs/rk3568-rt.config
@@ -0,0 +1,2 @@
+CONFIG_BASE_DEFCONFIG="rk3568_defconfig"
+CONFIG_TRUST_INI="RK3568TRUST_RT.ini"
diff --git a/u-boot/configs/rk3568-spl-spi-nand_defconfig b/u-boot/configs/rk3568-spl-spi-nand_defconfig
index eabdae7..074ccc3 100755
--- a/u-boot/configs/rk3568-spl-spi-nand_defconfig
+++ b/u-boot/configs/rk3568-spl-spi-nand_defconfig
@@ -26,9 +26,6 @@
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_ANDROID_WRITE_KEYBOX is not set
-CONFIG_ANDROID_AVB=y
-# CONFIG_ANDROID_KEYMASTER_CA is not set
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
@@ -183,12 +180,4 @@
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_SHA512=y
-CONFIG_LZ4=y
CONFIG_ERRNO_STR=y
-CONFIG_AVB_LIBAVB=y
-CONFIG_AVB_LIBAVB_AB=y
-CONFIG_AVB_LIBAVB_ATX=y
-CONFIG_AVB_LIBAVB_USER=y
-CONFIG_RK_AVB_LIBAVB_USER=y
-CONFIG_OPTEE_CLIENT=y
-CONFIG_OPTEE_V2=y
diff --git a/u-boot/configs/rk3568_defconfig b/u-boot/configs/rk3568_defconfig
index fbd9820..d157307 100644
--- a/u-boot/configs/rk3568_defconfig
+++ b/u-boot/configs/rk3568_defconfig
@@ -83,6 +83,7 @@
# CONFIG_ISO_PARTITION is not set
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
CONFIG_OF_LIVE=y
CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
# CONFIG_NET_TFTP_VARS is not set
@@ -206,6 +207,7 @@
CONFIG_RSA_N_SIZE=0x200
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
+CONFIG_XBC=y
CONFIG_SHA512=y
CONFIG_LZ4=y
CONFIG_LZMA=y
diff --git a/u-boot/configs/rk3588-ab.config b/u-boot/configs/rk3588-ab.config
new file mode 100644
index 0000000..a67f0d9
--- /dev/null
+++ b/u-boot/configs/rk3588-ab.config
@@ -0,0 +1,3 @@
+CONFIG_ANDROID_AB=y
+CONFIG_BASE_DEFCONFIG="rk3588_defconfig"
+# CONFIG_CMD_ANDROID_AB_SELECT is not set
diff --git a/u-boot/configs/rk3588-qnx_defconfig b/u-boot/configs/rk3588-qnx_defconfig
new file mode 100644
index 0000000..0c42ff1
--- /dev/null
+++ b/u-boot/configs/rk3588-qnx_defconfig
@@ -0,0 +1,212 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ROCKCHIP=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x80000
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.sh"
+CONFIG_ROCKCHIP_RK3588=y
+CONFIG_ROCKCHIP_FIT_IMAGE=y
+CONFIG_ROCKCHIP_HWID_DTB=y
+CONFIG_ROCKCHIP_VENDOR_PARTITION=y
+CONFIG_USING_KERNEL_DTB_V2=y
+CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
+CONFIG_ROCKCHIP_NEW_IDB=y
+CONFIG_PSTORE=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_TARGET_EVB_RK3588=y
+CONFIG_SPL_LIBDISK_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="rk3588-evb"
+CONFIG_DEBUG_UART=y
+CONFIG_FIT=y
+CONFIG_FIT_IMAGE_POST_PROCESS=y
+CONFIG_FIT_HW_CRYPTO=y
+CONFIG_FIT_OMIT_UBOOT=y
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
+CONFIG_SPL_FIT_HW_CRYPTO=y
+# CONFIG_SPL_SYS_DCACHE_OFF is not set
+CONFIG_BOOTDELAY=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_ANDROID_BOOTLOADER=y
+CONFIG_ANDROID_AVB=y
+CONFIG_ANDROID_BOOT_IMAGE_HASH=y
+CONFIG_SPL_BOARD_INIT=y
+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x1
+CONFIG_SPL_MMC_WRITE=y
+CONFIG_SPL_ATF=y
+CONFIG_SPL_KERNEL_BOOT=y
+# CONFIG_SPL_KERNEL_BOOT_PREBUILT is not set
+CONFIG_FASTBOOT_BUF_ADDR=0xc00800
+CONFIG_FASTBOOT_BUF_SIZE=0x07000000
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_IMLS is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+# CONFIG_CMD_FLASH is not set
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_BOOT_ANDROID=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_USB_MASS_STORAGE=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TFTP_BOOTM=y
+CONFIG_CMD_TFTP_FLASH=y
+# CONFIG_CMD_MISC is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_ISO_PARTITION is not set
+CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_DTB_MINIMUM=y
+CONFIG_OF_LIVE=y
+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+CONFIG_OF_U_BOOT_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
+# CONFIG_NET_TFTP_VARS is not set
+CONFIG_REGMAP=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
+# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
+CONFIG_CLK=y
+CONFIG_SPL_CLK=y
+CONFIG_CLK_SCMI=y
+CONFIG_SPL_CLK_SCMI=y
+CONFIG_DM_CRYPTO=y
+CONFIG_SPL_DM_CRYPTO=y
+CONFIG_ROCKCHIP_CRYPTO_V2=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
+CONFIG_DM_RNG=y
+CONFIG_RNG_ROCKCHIP=y
+CONFIG_SCMI_FIRMWARE=y
+CONFIG_SPL_SCMI_FIRMWARE=y
+CONFIG_GPIO_HOG=y
+CONFIG_ROCKCHIP_GPIO=y
+CONFIG_ROCKCHIP_GPIO_V2=y
+CONFIG_SYS_I2C_ROCKCHIP=y
+CONFIG_I2C_MUX=y
+CONFIG_DM_KEY=y
+CONFIG_RK8XX_PWRKEY=y
+CONFIG_ADC_KEY=y
+CONFIG_MISC=y
+CONFIG_SPL_MISC=y
+CONFIG_MISC_DECOMPRESS=y
+CONFIG_SPL_MISC_DECOMPRESS=y
+CONFIG_ROCKCHIP_OTP=y
+CONFIG_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
+CONFIG_SPL_ROCKCHIP_SECURE_OTP=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_SDMA=y
+CONFIG_MMC_SDHCI_ROCKCHIP=y
+CONFIG_DM_ETH=y
+CONFIG_DM_ETH_PHY=y
+CONFIG_DWC_ETH_QOS=y
+CONFIG_GMAC_ROCKCHIP=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_DM_FUEL_GAUGE=y
+CONFIG_POWER_FG_CW201X=y
+CONFIG_POWER_FG_CW221X=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_SPI_RK8XX=y
+CONFIG_DM_POWER_DELIVERY=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+CONFIG_TYPEC_HUSB311=y
+CONFIG_TYPEC_FUSB302=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REGULATOR_RK860X=y
+CONFIG_REGULATOR_RK806=y
+CONFIG_CHARGER_BQ25700=y
+CONFIG_CHARGER_BQ25890=y
+CONFIG_CHARGER_SC8551=y
+CONFIG_CHARGER_SGM41542=y
+CONFIG_DM_CHARGE_DISPLAY=y
+CONFIG_CHARGE_ANIMATION=y
+CONFIG_PWM_ROCKCHIP=y
+CONFIG_RAM=y
+CONFIG_SPL_RAM=y
+CONFIG_TPL_RAM=y
+CONFIG_DM_RAMDISK=y
+CONFIG_RAMDISK_RO=y
+CONFIG_DM_RESET=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_RESET_ROCKCHIP=y
+CONFIG_BAUDRATE=1500000
+CONFIG_DEBUG_UART_BASE=0xFEB50000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART_SHIFT=2
+CONFIG_SYSRESET=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
+CONFIG_USB_GADGET_PRODUCT_NUM=0x350a
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_DM_VIDEO=y
+CONFIG_DISPLAY=y
+CONFIG_DRM_ROCKCHIP=y
+CONFIG_DRM_MAXIM_MAX96745=y
+CONFIG_DRM_MAXIM_MAX96755F=y
+CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
+CONFIG_DRM_ROHM_BU18XL82=y
+CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
+CONFIG_DRM_ROCKCHIP_DW_DP=y
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
+CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_LIB_RAND=y
+CONFIG_SPL_TINY_MEMSET=y
+CONFIG_RSA=y
+CONFIG_SPL_RSA=y
+CONFIG_RSA_N_SIZE=0x200
+CONFIG_RSA_E_SIZE=0x10
+CONFIG_RSA_C_SIZE=0x20
+CONFIG_XBC=y
+CONFIG_LZ4=y
+CONFIG_LZMA=y
+CONFIG_ERRNO_STR=y
+# CONFIG_EFI_LOADER is not set
+CONFIG_AVB_LIBAVB=y
+CONFIG_AVB_LIBAVB_AB=y
+CONFIG_AVB_LIBAVB_ATX=y
+CONFIG_AVB_LIBAVB_USER=y
+CONFIG_RK_AVB_LIBAVB_USER=y
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
+CONFIG_OPTEE_ALWAYS_USE_SECURITY_PARTITION=y
diff --git a/u-boot/configs/rk3588_defconfig b/u-boot/configs/rk3588_defconfig
index 535e9fb..97a9cb8 100644
--- a/u-boot/configs/rk3588_defconfig
+++ b/u-boot/configs/rk3588_defconfig
@@ -12,8 +12,6 @@
CONFIG_USING_KERNEL_DTB_V2=y
CONFIG_ROCKCHIP_FIT_IMAGE_PACK=y
CONFIG_ROCKCHIP_NEW_IDB=y
-CONFIG_LOADER_INI="RK3588MINIALL.ini"
-CONFIG_TRUST_INI="RK3588TRUST.ini"
CONFIG_PSTORE=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
@@ -45,6 +43,7 @@
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_ATF=y
+CONFIG_SPL_AB=y
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
CONFIG_FASTBOOT_BUF_SIZE=0x07000000
CONFIG_FASTBOOT_FLASH=y
@@ -204,14 +203,14 @@
CONFIG_DISPLAY=y
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_MAXIM_MAX96745=y
-CONFIG_DRM_MAXIM_MAX96752F=y
CONFIG_DRM_MAXIM_MAX96755F=y
-CONFIG_DRM_PANEL_MAXIM_DESERIALIZER=y
+CONFIG_DRM_PANEL_ROHM_BU18RL82=y
+CONFIG_DRM_PANEL_MAXIM_MAX96752F=y
CONFIG_DRM_ROHM_BU18XL82=y
CONFIG_DRM_ROCKCHIP_DW_HDMI_QP=y
CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2=y
-CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_DW_DP=y
+CONFIG_DRM_ROCKCHIP_ANALOGIX_DP=y
CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY=y
CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI=y
CONFIG_USE_TINY_PRINTF=y
diff --git a/u-boot/configs/rv1106-display.config b/u-boot/configs/rv1106-display.config
index 842cde0..a03a2bf 100644
--- a/u-boot/configs/rv1106-display.config
+++ b/u-boot/configs/rv1106-display.config
@@ -48,7 +48,7 @@
# CONFIG_REGULATOR_PWM is not set
# CONFIG_REGULATOR_RK860X is not set
CONFIG_ROCKCHIP_CUBIC_LUT_SIZE=0
-# CONFIG_ROCKCHIP_DRM_TVE is not set
+# CONFIG_DRM_ROCKCHIP_TVE is not set
# CONFIG_ROCKCHIP_INNO_HDMI_PHY is not set
# CONFIG_SPL_DM_REGULATOR is not set
# CONFIG_VIDCONSOLE_AS_LCD is not set
diff --git a/u-boot/configs/rv1106-emmc-tb_defconfig b/u-boot/configs/rv1106-emmc-tb_defconfig
index 6929db4..c53ddc0 100644
--- a/u-boot/configs/rv1106-emmc-tb_defconfig
+++ b/u-boot/configs/rv1106-emmc-tb_defconfig
@@ -3,7 +3,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x100000
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
@@ -38,12 +38,12 @@
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
# CONFIG_SKIP_RELOCATE_UBOOT is not set
+CONFIG_SPL_ADC_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_MMC_WRITE=y
-CONFIG_SPL_OPTEE=y
CONFIG_SPL_KERNEL_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
@@ -78,14 +78,19 @@
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-# CONFIG_ADC is not set
# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_SPL_BLK_READ_PREPARE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_DM_CRYPTO=y
+CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_DM_I2C is not set
+CONFIG_SPL_INPUT=y
+CONFIG_DM_KEY=y
+CONFIG_ADC_KEY=y
+CONFIG_SPL_ADC_KEY=y
CONFIG_SPL_MISC=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
diff --git a/u-boot/configs/rv1106-optee.config b/u-boot/configs/rv1106-optee.config
new file mode 100644
index 0000000..dc76adc
--- /dev/null
+++ b/u-boot/configs/rv1106-optee.config
@@ -0,0 +1,5 @@
+CONFIG_BASE_DEFCONFIG="rv1106_defconfig"
+CONFIG_OPTEE_CLIENT=y
+CONFIG_OPTEE_V2=y
+CONFIG_SPL_FIT_IMAGE_KB=512
+CONFIG_SPL_OPTEE=y
diff --git a/u-boot/configs/rv1106-spi-nor-tb_defconfig b/u-boot/configs/rv1106-spi-nor-tb_defconfig
index d518921..e80759e 100644
--- a/u-boot/configs/rv1106-spi-nor-tb_defconfig
+++ b/u-boot/configs/rv1106-spi-nor-tb_defconfig
@@ -3,7 +3,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
@@ -38,13 +38,13 @@
CONFIG_ANDROID_BOOTLOADER=y
CONFIG_ANDROID_BOOT_IMAGE_HASH=y
# CONFIG_SKIP_RELOCATE_UBOOT is not set
+CONFIG_SPL_ADC_SUPPORT=y
CONFIG_SPL_BOARD_INIT=y
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_MTD_BLK_U_BOOT_OFFS=0x200
-CONFIG_SPL_OPTEE=y
CONFIG_SPL_KERNEL_BOOT=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
@@ -81,8 +81,8 @@
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
-# CONFIG_ADC is not set
# CONFIG_SARADC_ROCKCHIP is not set
+CONFIG_SARADC_ROCKCHIP_V2=y
CONFIG_SPL_BLK_READ_PREPARE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
@@ -90,6 +90,10 @@
CONFIG_SPL_ROCKCHIP_CRYPTO_V2=y
CONFIG_ROCKCHIP_GPIO=y
# CONFIG_DM_I2C is not set
+CONFIG_SPL_INPUT=y
+CONFIG_DM_KEY=y
+CONFIG_ADC_KEY=y
+CONFIG_SPL_ADC_KEY=y
CONFIG_SPL_MISC=y
CONFIG_SPL_MISC_DECOMPRESS=y
CONFIG_SPL_ROCKCHIP_HW_DECOMPRESS=y
@@ -104,6 +108,7 @@
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_XMC=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PINCTRL=y
# CONFIG_DM_REGULATOR is not set
diff --git a/u-boot/configs/rv1106-spi-nor_defconfig b/u-boot/configs/rv1106-spi-nor_defconfig
index 47e94ac..d269443 100644
--- a/u-boot/configs/rv1106-spi-nor_defconfig
+++ b/u-boot/configs/rv1106-spi-nor_defconfig
@@ -3,7 +3,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
# CONFIG_ROCKCHIP_RESOURCE_IMAGE is not set
@@ -30,7 +30,7 @@
CONFIG_SPL_FIT_IMAGE_POST_PROCESS=y
CONFIG_SPL_FIT_HW_CRYPTO=y
# CONFIG_SPL_SYS_DCACHE_OFF is not set
-CONFIG_SPL_FIT_IMAGE_KB=128
+CONFIG_SPL_FIT_IMAGE_KB=192
CONFIG_SPL_FIT_IMAGE_MULTIPLE=1
CONFIG_BOOTDELAY=0
CONFIG_SYS_CONSOLE_INFO_QUIET=y
@@ -40,9 +40,7 @@
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
# CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
-CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OPTEE=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
CONFIG_CMD_BOOTZ=y
@@ -63,12 +61,11 @@
CONFIG_RANDOM_UUID=y
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_PART=y
+CONFIG_CMD_MTD=y
# CONFIG_CMD_ITEST is not set
CONFIG_CMD_SCRIPT_UPDATE=y
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_TFTP_BOOTM=y
CONFIG_CMD_TFTP_FLASH=y
CONFIG_CMD_DHCP=y
# CONFIG_CMD_NFS is not set
@@ -154,5 +151,4 @@
CONFIG_RSA_E_SIZE=0x10
CONFIG_RSA_C_SIZE=0x20
CONFIG_SPL_LZMA=y
-CONFIG_SPL_GZIP=y
# CONFIG_EFI_LOADER is not set
diff --git a/u-boot/configs/rv1106-usb.config b/u-boot/configs/rv1106-usb.config
new file mode 100644
index 0000000..dc589f0
--- /dev/null
+++ b/u-boot/configs/rv1106-usb.config
@@ -0,0 +1,17 @@
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CMD_USB=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_STORAGE=y
+CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+# CONFIG_FASTBOOT is not set
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
+CONFIG_USB_GADGET_PRODUCT_NUM=0x110c
+CONFIG_USB_GADGET_VENDOR_NUM=0x2207
diff --git a/u-boot/configs/rv1106_defconfig b/u-boot/configs/rv1106_defconfig
index e797553..9b20bcf 100644
--- a/u-boot/configs/rv1106_defconfig
+++ b/u-boot/configs/rv1106_defconfig
@@ -4,7 +4,7 @@
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x80000
-CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_uboot.sh"
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_optee.sh"
CONFIG_ROCKCHIP_RV1106=y
CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x0
CONFIG_ROCKCHIP_FIT_IMAGE=y
@@ -41,7 +41,6 @@
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y
CONFIG_SPL_MMC_WRITE=y
CONFIG_SPL_MTD_SUPPORT=y
-CONFIG_SPL_OPTEE=y
CONFIG_HUSH_PARSER=y
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
diff --git a/u-boot/configs/rv1126-bat-spi-nor-tb.config b/u-boot/configs/rv1126-bat-spi-nor-tb.config
index 699d8d0..997a6c2 100644
--- a/u-boot/configs/rv1126-bat-spi-nor-tb.config
+++ b/u-boot/configs/rv1126-bat-spi-nor-tb.config
@@ -2,6 +2,6 @@
# CONFIG_MMC is not set
CONFIG_BASE_DEFCONFIG="rv1126-spi-nor-tb.config"
CONFIG_DEFAULT_DEVICE_TREE="rv1126-bat-evb"
-CONFIG_LOADER_INI="RV1126MINIALL_LP4_EMMC_TB.ini"
+CONFIG_LOADER_INI="RV1126MINIALL_SPI_NOR_TB.ini"
CONFIG_OF_LIST="rv1126-bat-evb"
CONFIG_SPL_FIT_IMAGE_KB=320
diff --git a/u-boot/configs/rv1126-ipc.config b/u-boot/configs/rv1126-ipc.config
index 4ab7a51..d4457a0 100644
--- a/u-boot/configs/rv1126-ipc.config
+++ b/u-boot/configs/rv1126-ipc.config
@@ -4,9 +4,11 @@
# CONFIG_EFI_PARTITION is not set
CONFIG_ENVF_LIST="blkdevparts mtdparts sys_bootargs app reserved ipaddr serverip netmask gatewayip ethaddr"
CONFIG_ENVF=y
+CONFIG_ENV_PARTITION=y
CONFIG_LOADER_INI="RV1126MINIALL_IPC.ini"
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_SPL_ENVF=y
+CONFIG_SPL_ENV_PARTITION=y
CONFIG_NETDEVICES=y
CONFIG_GMAC_ROCKCHIP=y
CONFIG_DWC_ETH_QOS=y
diff --git a/u-boot/configs/rv1126-spi-nor-tiny_defconfig b/u-boot/configs/rv1126-spi-nor-tiny_defconfig
index b34446d..eecc02a 100644
--- a/u-boot/configs/rv1126-spi-nor-tiny_defconfig
+++ b/u-boot/configs/rv1126-spi-nor-tiny_defconfig
@@ -126,6 +126,7 @@
CONFIG_ROCKCHIP_SFC=y
CONFIG_SYSRESET=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_LIB_RAND=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_ERRNO_STR=y
# CONFIG_EFI_LOADER is not set
diff --git a/u-boot/disk/Kconfig b/u-boot/disk/Kconfig
index cbc2514..cfc6ae8 100644
--- a/u-boot/disk/Kconfig
+++ b/u-boot/disk/Kconfig
@@ -137,15 +137,15 @@
config ENV_PARTITION
bool "Enable ENV partition table support"
- depends on PARTITIONS && ENVF
- default y
+ depends on PARTITIONS
+ default y if ENVF
help
Say Y here if you would like to use ENV partition table.
config SPL_ENV_PARTITION
bool "Enable ENV partition table support in SPL"
- depends on SPL && PARTITIONS && SPL_ENVF
- default y
+ depends on SPL && PARTITIONS
+ default y if SPL_ENVF
help
Say Y here if you would like to use ENV partition table in SPL.
diff --git a/u-boot/disk/part.c b/u-boot/disk/part.c
index 116a1ae..182c037 100644
--- a/u-boot/disk/part.c
+++ b/u-boot/disk/part.c
@@ -684,8 +684,9 @@
disk_partition_t *info,
bool strict)
{
+ __maybe_unused char name_slot[32] = {0};
struct part_driver *part_drv;
- char name_slot[32] = {0};
+ const char *full_name = name;
int none_slot_try = 1;
int ret, i;
@@ -695,37 +696,35 @@
if (strict) {
none_slot_try = 0;
- strcpy(name_slot, name);
goto lookup;
}
+ /* 1. Query partition with A/B slot suffix */
#if defined(CONFIG_ANDROID_AB) || defined(CONFIG_SPL_AB)
- char *name_suffix = (char *)name + strlen(name) - 2;
+ char *slot = (char *)name + strlen(name) - 2;
- /* Fix can not find partition with suffix "_a" & "_b". If with them, clear */
- if (!memcmp(name_suffix, "_a", strlen("_a")) ||
- !memcmp(name_suffix, "_b", strlen("_b")))
- memset(name_suffix, 0, 2);
+ if (!strcmp(slot, "_a") || !strcmp(slot, "_b"))
+ goto lookup;
#endif
#if defined(CONFIG_ANDROID_AB) && !defined(CONFIG_SPL_BUILD)
- /* 1. Query partition with A/B slot suffix */
if (rk_avb_append_part_slot(name, name_slot))
return -1;
+ full_name = name_slot;
#elif defined(CONFIG_SPL_AB) && defined(CONFIG_SPL_BUILD)
if (spl_ab_append_part_slot(dev_desc, name, name_slot))
return -1;
-#else
- strcpy(name_slot, name);
+ full_name = name_slot;
#endif
+
lookup:
- debug("## Query partition(%d): %s\n", none_slot_try, name_slot);
+ debug("## Query partition(%d): %s\n", none_slot_try, full_name);
for (i = 1; i < part_drv->max_entries; i++) {
ret = part_drv->get_info(dev_desc, i, info);
if (ret != 0) {
/* no more entries in table */
break;
}
- if (strcmp(name_slot, (const char *)info->name) == 0) {
+ if (strcmp(full_name, (const char *)info->name) == 0) {
/* matched */
return i;
}
@@ -734,7 +733,7 @@
/* 2. Query partition without A/B slot suffix if above failed */
if (none_slot_try) {
none_slot_try = 0;
- strcpy(name_slot, name);
+ full_name = name;
goto lookup;
}
diff --git a/u-boot/disk/part_efi.c b/u-boot/disk/part_efi.c
index 27f3e4d..d4d03de 100644
--- a/u-boot/disk/part_efi.c
+++ b/u-boot/disk/part_efi.c
@@ -368,7 +368,7 @@
if (gpt_pte[i - 1].ending_lba <= (dev_desc->lba - 0x22))
return;
/* The last partition size need align to 4KB, here align to 32KB. */
- gpt_pte[i - 1].ending_lba = dev_desc->lba - 0x40;
+ gpt_pte[i - 1].ending_lba = dev_desc->lba - 0x41;
calc_crc32 = efi_crc32((const unsigned char *)gpt_pte,
le32_to_cpu(gpt_head->num_partition_entries) *
le32_to_cpu(gpt_head->sizeof_partition_entry));
@@ -963,7 +963,8 @@
dev_desc->blksz);
if ((le64_to_cpu(gpt_h->alternate_lba) + 1)
- != cpu_to_le64(dev_desc->lba)) {
+ != cpu_to_le64(dev_desc->lba) &&
+ le64_to_cpu(gpt_h->last_usable_lba) != FACTORY_UNKNOWN_LBA) {
printf("%s: failed checking '%s'\n", __func__,
"invalid GPT Disk Size");
return -1;
diff --git a/u-boot/disk/part_env.c b/u-boot/disk/part_env.c
index cb4a903..53c8b39 100644
--- a/u-boot/disk/part_env.c
+++ b/u-boot/disk/part_env.c
@@ -82,14 +82,7 @@
#if CONFIG_IS_ENABLED(ENVF)
parts_list = envf_get_part_table(dev_desc);
#else
- const char *parts_prefix[] = { "mtdparts", "blkdevparts", };
- int i;
-
- for (i = 0; i < ARRAY_SIZE(parts_prefix); i++) {
- parts_list = env_get(parts_prefix[i]);
- if (parts_list)
- break;
- }
+ parts_list = ENV_PARTITIONS;
#endif
if (!parts_list)
return -EINVAL;
diff --git a/u-boot/drivers/Kconfig b/u-boot/drivers/Kconfig
index 21ed0cf..8926208 100644
--- a/u-boot/drivers/Kconfig
+++ b/u-boot/drivers/Kconfig
@@ -102,6 +102,8 @@
source "drivers/usb/Kconfig"
+source "drivers/ufs/Kconfig"
+
source "drivers/video/Kconfig"
source "drivers/watchdog/Kconfig"
diff --git a/u-boot/drivers/Makefile b/u-boot/drivers/Makefile
index 3a9a55a..85c45f4 100644
--- a/u-boot/drivers/Makefile
+++ b/u-boot/drivers/Makefile
@@ -20,6 +20,7 @@
obj-$(CONFIG_$(SPL_TPL_)SPI_SUPPORT) += spi/
obj-$(CONFIG_$(SPL_TPL_)TIMER) += timer/
obj-$(CONFIG_$(SPL_TPL_)IRQ) += irq/
+obj-$(CONFIG_$(SPL_TPL_)DM_VIDEO) += video/
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
@@ -101,7 +102,6 @@
obj-y += spmi/
obj-y += sysreset/
obj-y += tpm/
-obj-y += video/
obj-y += watchdog/
obj-$(CONFIG_QE) += qe/
obj-$(CONFIG_U_QE) += qe/
@@ -113,6 +113,7 @@
obj-y += soc/
obj-$(CONFIG_REMOTEPROC) += remoteproc/
obj-y += thermal/
+obj-y += ufs/
obj-$(CONFIG_MACH_PIC32) += ddr/microchip/
endif
diff --git a/u-boot/drivers/adc/rockchip-saradc-v2.c b/u-boot/drivers/adc/rockchip-saradc-v2.c
index c97142e..52fa2e4 100644
--- a/u-boot/drivers/adc/rockchip-saradc-v2.c
+++ b/u-boot/drivers/adc/rockchip-saradc-v2.c
@@ -181,6 +181,9 @@
if (IS_ERR_VALUE(ret))
return ret;
+ /* Wait until pll stable */
+ mdelay(5);
+
priv->active_channel = -1;
return 0;
@@ -220,9 +223,35 @@
.clk_rate = 1000000,
};
+static const struct rockchip_saradc_data rk3562_saradc_data = {
+ .num_bits = 10,
+ .num_channels = 8,
+ .clk_rate = 1000000,
+};
+
+static const struct rockchip_saradc_data rk1106_saradc_data = {
+ .num_bits = 10,
+ .num_channels = 2,
+ .clk_rate = 1000000,
+};
+
static const struct udevice_id rockchip_saradc_ids[] = {
- { .compatible = "rockchip,rk3588-saradc",
- .data = (ulong)&rk3588_saradc_data },
+ {
+ .compatible = "rockchip,rk3588-saradc",
+ .data = (ulong)&rk3588_saradc_data
+ },
+ {
+ .compatible = "rockchip,rk3528-saradc",
+ .data = (ulong)&rk3588_saradc_data
+ },
+ {
+ .compatible = "rockchip,rk3562-saradc",
+ .data = (ulong)&rk3562_saradc_data
+ },
+ {
+ .compatible = "rockchip,rv1106-saradc",
+ .data = (ulong)&rk1106_saradc_data
+ },
{ }
};
diff --git a/u-boot/drivers/clk/clk-uclass.c b/u-boot/drivers/clk/clk-uclass.c
index a4938c1..0737c3d 100644
--- a/u-boot/drivers/clk/clk-uclass.c
+++ b/u-boot/drivers/clk/clk-uclass.c
@@ -237,10 +237,11 @@
{
int ret;
+#ifndef CONFIG_SPL_BUILD
/* If this is running pre-reloc state, don't take any action. */
if (!(gd->flags & GD_FLG_RELOC))
return 0;
-
+#endif
debug("%s(%s)\n", __func__, dev_read_name(dev));
ret = clk_set_default_parents(dev);
diff --git a/u-boot/drivers/clk/rockchip/Makefile b/u-boot/drivers/clk/rockchip/Makefile
index 260b24e..80b20a2 100644
--- a/u-boot/drivers/clk/rockchip/Makefile
+++ b/u-boot/drivers/clk/rockchip/Makefile
@@ -17,6 +17,8 @@
obj-$(CONFIG_ROCKCHIP_RK3328) += clk_rk3328.o
obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o
obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += clk_rk3528.o
+obj-$(CONFIG_ROCKCHIP_RK3562) += clk_rk3562.o
obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += clk_rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1106) += clk_rv1106.o
diff --git a/u-boot/drivers/clk/rockchip/clk_pll.c b/u-boot/drivers/clk/rockchip/clk_pll.c
index 3c1ee9d..056ffaa 100644
--- a/u-boot/drivers/clk/rockchip/clk_pll.c
+++ b/u-boot/drivers/clk/rockchip/clk_pll.c
@@ -267,9 +267,11 @@
* When power on or changing PLL setting,
* we must force PLL into slow mode to ensure output stable clock.
*/
- rk_clrsetreg(base + pll->mode_offset,
- pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset,
+ pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_SLOW << pll->mode_shift);
+ }
/* Power down */
rk_setreg(base + pll->con_offset + 0x4,
@@ -308,8 +310,11 @@
if (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift)))
printf("%s: wait pll lock timeout! pll_id=%ld\n", __func__, pll_id);
- rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
- RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE)) {
+ rk_clrsetreg(base + pll->mode_offset, pll->mode_mask << pll->mode_shift,
+ RKCLK_PLL_MODE_NORMAL << pll->mode_shift);
+ }
+
debug("PLL at %p: con0=%x con1= %x con2= %x mode= %x\n",
pll, readl(base + pll->con_offset),
readl(base + pll->con_offset + 0x4),
@@ -325,12 +330,18 @@
u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac;
u32 con = 0, shift, mask;
ulong rate;
+ int mode;
con = readl(base + pll->mode_offset);
shift = pll->mode_shift;
mask = pll->mode_mask << shift;
- switch ((con & mask) >> shift) {
+ if (!(pll->pll_flags & ROCKCHIP_PLL_FIXED_MODE))
+ mode = (con & mask) >> shift;
+ else
+ mode = RKCLK_PLL_MODE_NORMAL;
+
+ switch (mode) {
case RKCLK_PLL_MODE_SLOW:
return OSC_HZ;
case RKCLK_PLL_MODE_NORMAL:
diff --git a/u-boot/drivers/clk/rockchip/clk_rk3399.c b/u-boot/drivers/clk/rockchip/clk_rk3399.c
index cce0b48..7fecd68 100644
--- a/u-boot/drivers/clk/rockchip/clk_rk3399.c
+++ b/u-boot/drivers/clk/rockchip/clk_rk3399.c
@@ -773,6 +773,10 @@
ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |
(div - 1) << ACLK_VOP_DIV_CON_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[42],
+ ACLK_VOP_PLL_SEL_MASK | ACLK_VOP_DIV_CON_MASK,
+ ACLK_VOP_PLL_SEL_GPLL << ACLK_VOP_PLL_SEL_SHIFT |
+ (div - 1) << ACLK_VOP_DIV_CON_SHIFT);
if (readl(dclkreg_addr) & DCLK_VOP_PLL_SEL_MASK) {
if (pll_para_config(hz, &cpll_config))
diff --git a/u-boot/drivers/clk/rockchip/clk_rk3528.c b/u-boot/drivers/clk/rockchip/clk_rk3528.c
new file mode 100644
index 0000000..ada7dd4
--- /dev/null
+++ b/u-boot/drivers/clk/rockchip/clk_rk3528.c
@@ -0,0 +1,2145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Fuzhou Rockchip Electronics Co., Ltd
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3528.h>
+#include <asm/arch/grf_rk3528.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3528-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+/*
+ * PLL attention.
+ *
+ * [FRAC PLL]: GPLL, PPLL, DPLL
+ * - frac mode: refdiv can be 1 or 2 only
+ * - int mode: refdiv has no special limit
+ * - VCO range: [950, 3800] MHZ
+ *
+ * [INT PLL]: CPLL, APLL
+ * - int mode: refdiv can be 1 or 2 only
+ * - VCO range: [475, 1900] MHZ
+ *
+ * [PPLL]: normal mode only.
+ *
+ */
+static struct rockchip_pll_rate_table rk3528_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), /* GPLL */
+ RK3036_PLL_RATE(1092000000, 2, 91, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 42, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0), /* PPLL */
+ RK3036_PLL_RATE(996000000, 2, 83, 1, 1, 1, 0), /* CPLL */
+ RK3036_PLL_RATE(960000000, 1, 40, 1, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 50, 2, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 2, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 24, 3, 2, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3528_pll_clks[] = {
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3528_PLL_CON(0),
+ RK3528_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3528_PLL_CON(8),
+ RK3528_MODE_CON, 2, 10, 0, rk3528_pll_rates),
+
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3528_PLL_CON(24),
+ RK3528_MODE_CON, 4, 10, 0, rk3528_pll_rates),
+
+ [PPLL] = PLL(pll_rk3328, PLL_PPLL, RK3528_PCIE_PLL_CON(32),
+ RK3528_MODE_CON, 6, 10, ROCKCHIP_PLL_FIXED_MODE, rk3528_pll_rates),
+
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3528_DDRPHY_PLL_CON(16),
+ RK3528_DDRPHY_MODE_CON, 0, 10, 0, rk3528_pll_rates),
+};
+
+#define RK3528_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
+{ \
+ .rate = _rate##U, \
+ .aclk_div = (_aclk_m_core), \
+ .pclk_div = (_pclk_dbg), \
+}
+
+/* sign-off: _aclk_m_core: 550M, _pclk_dbg: 137.5M, */
+static struct rockchip_cpu_rate_table rk3528_cpu_rates[] = {
+ RK3528_CPUCLK_RATE(1896000000, 1, 13),
+ RK3528_CPUCLK_RATE(1800000000, 1, 12),
+ RK3528_CPUCLK_RATE(1704000000, 1, 11),
+ RK3528_CPUCLK_RATE(1608000000, 1, 11),
+ RK3528_CPUCLK_RATE(1512000000, 1, 11),
+ RK3528_CPUCLK_RATE(1416000000, 1, 9),
+ RK3528_CPUCLK_RATE(1296000000, 1, 8),
+ RK3528_CPUCLK_RATE(1200000000, 1, 8),
+ RK3528_CPUCLK_RATE(1188000000, 1, 8),
+ RK3528_CPUCLK_RATE(1092000000, 1, 7),
+ RK3528_CPUCLK_RATE(1008000000, 1, 6),
+ RK3528_CPUCLK_RATE(1000000000, 1, 6),
+ RK3528_CPUCLK_RATE(996000000, 1, 6),
+ RK3528_CPUCLK_RATE(960000000, 1, 6),
+ RK3528_CPUCLK_RATE(912000000, 1, 6),
+ RK3528_CPUCLK_RATE(816000000, 1, 5),
+ RK3528_CPUCLK_RATE(600000000, 1, 3),
+ RK3528_CPUCLK_RATE(594000000, 1, 3),
+ RK3528_CPUCLK_RATE(408000000, 1, 2),
+ RK3528_CPUCLK_RATE(312000000, 1, 2),
+ RK3528_CPUCLK_RATE(216000000, 1, 1),
+ RK3528_CPUCLK_RATE(96000000, 1, 0),
+};
+
+#ifndef CONFIG_SPL_BUILD
+#define RK3528_CLK_DUMP(_id, _name) \
+{ \
+ .id = _id, \
+ .name = _name, \
+}
+
+static const struct rk3528_clk_info clks_dump[] = {
+ RK3528_CLK_DUMP(PLL_APLL, "apll"),
+ RK3528_CLK_DUMP(PLL_GPLL, "gpll"),
+ RK3528_CLK_DUMP(PLL_CPLL, "cpll"),
+ RK3528_CLK_DUMP(PLL_DPLL, "dpll"),
+ RK3528_CLK_DUMP(PLL_PPLL, "ppll"),
+ RK3528_CLK_DUMP(CLK_MATRIX_50M_SRC, "clk_50m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_100M_SRC, "clk_100m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_150M_SRC, "clk_150m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_200M_SRC, "clk_200m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_250M_SRC, "clk_250m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_300M_SRC, "clk_300m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_339M_SRC, "clk_339m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_400M_SRC, "clk_400m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_500M_SRC, "clk_500m"),
+ RK3528_CLK_DUMP(CLK_MATRIX_600M_SRC, "clk_600m"),
+ RK3528_CLK_DUMP(CLK_PPLL_50M_MATRIX, "clk_ppll_50m"),
+ RK3528_CLK_DUMP(CLK_PPLL_100M_MATRIX, "clk_ppll_100m"),
+ RK3528_CLK_DUMP(CLK_PPLL_125M_MATRIX, "clk_ppll_125m"),
+};
+#endif
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
+static int rk3528_armclk_set_clk(struct rk3528_clk_priv *priv, ulong new_rate)
+{
+ const struct rockchip_cpu_rate_table *rate;
+ struct rk3528_cru *cru = priv->cru;
+ ulong old_rate;
+
+ rate = rockchip_get_cpu_settings(rk3528_cpu_rates, new_rate);
+ if (!rate) {
+ printf("%s unsupported rate\n", __func__);
+ return -EINVAL;
+ }
+
+ /*
+ * set up dependent divisors for DBG and ACLK clocks.
+ */
+ old_rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru, APLL);
+ if (old_rate > new_rate) {
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+ } else if (old_rate < new_rate) {
+ rk_clrsetreg(&cru->clksel_con[40], RK3528_DIV_PCLK_DBG_MASK,
+ rate->pclk_div << RK3528_DIV_PCLK_DBG_SHIFT);
+
+ rk_clrsetreg(&cru->clksel_con[39], RK3528_DIV_ACLK_M_CORE_MASK,
+ rate->aclk_div << RK3528_DIV_ACLK_M_CORE_SHIFT);
+
+ if (rockchip_pll_set_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong rk3528_ppll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+ void *reg;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_GMAC1_RMII_VPU:
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ reg = &cru->pcieclksel_con[1];
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_SRC_VPU:
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+
+ case CLK_GMAC1_VPU_25M:
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ reg = &cru->clksel_con[60];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = (readl(reg) & mask) >> shift;
+
+ return DIV_TO_RATE(priv->ppll_hz, div);
+}
+
+static ulong rk3528_ppll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, div, mask, shift;
+ u8 is_pciecru = 0;
+
+ switch (clk_id) {
+ case CLK_PPLL_50M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_100M_MATRIX:
+ id = 1;
+ mask = PCIE_CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_pciecru = 1;
+ break;
+
+ case CLK_PPLL_125M_MATRIX:
+ id = 60;
+ mask = CLK_MATRIX_125M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_125M_SRC_DIV_SHIFT;
+ break;
+ case CLK_GMAC1_VPU_25M:
+ id = 60;
+ mask = CLK_MATRIX_25M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_25M_SRC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(priv->ppll_hz, rate);
+ if (is_pciecru)
+ rk_clrsetreg(&cru->pcieclksel_con[id], mask, (div - 1) << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, (div - 1) << shift);
+
+ return rk3528_ppll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_cgpll_matrix_get_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ sel = (readl(&cru->clksel_con[con]) & sel_mask) >> sel_shift;
+ if (sel == CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX) // TODO
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ div = (readl(&cru->clksel_con[con]) & mask) >> shift;
+
+ /* NOTE: '-1' to balance the DIV_TO_RATE() 'div+1' */
+ return is_halfdiv ? DIV_TO_RATE(prate * 2, (3 + 2 * div) - 1) : DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_cgpll_matrix_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel, div, mask, shift, con;
+ u32 sel_mask = 0, sel_shift;
+ u8 is_gpll_parent = 1;
+ u8 is_halfdiv = 0;
+ ulong prate = 0;
+
+ switch (clk_id) {
+ case CLK_MATRIX_50M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_50M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_50M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_100M_SRC:
+ con = 0;
+ mask = CLK_MATRIX_100M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_100M_SRC_DIV_SHIFT;
+ is_gpll_parent = 0;
+ break;
+
+ case CLK_MATRIX_150M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_150M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_150M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_200M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_200M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_200M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_250M_SRC:
+ con = 1;
+ mask = CLK_MATRIX_250M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_250M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_250M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_250M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_300M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_300M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_300M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_339M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_339M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_339M_SRC_DIV_SHIFT;
+ is_halfdiv = 1;
+ break;
+
+ case CLK_MATRIX_400M_SRC:
+ con = 2;
+ mask = CLK_MATRIX_400M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_400M_SRC_DIV_SHIFT;
+ break;
+
+ case CLK_MATRIX_500M_SRC:
+ con = 3;
+ mask = CLK_MATRIX_500M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_500M_SRC_DIV_SHIFT;
+ sel_mask = CLK_MATRIX_500M_SRC_SEL_MASK;
+ sel_shift = CLK_MATRIX_500M_SRC_SEL_SHIFT;
+ break;
+
+ case CLK_MATRIX_600M_SRC:
+ con = 4;
+ mask = CLK_MATRIX_600M_SRC_DIV_MASK;
+ shift = CLK_MATRIX_600M_SRC_DIV_SHIFT;
+ break;
+
+ case ACLK_BUS_VOPGL_ROOT:
+ case ACLK_BUS_VOPGL_BIU:
+ con = 43;
+ mask = ACLK_BUS_VOPGL_ROOT_DIV_MASK;
+ shift = ACLK_BUS_VOPGL_ROOT_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (sel_mask) {
+ if (priv->gpll_hz % rate == 0) {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX; // TODO
+ prate = priv->gpll_hz;
+ } else {
+ sel = CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX;
+ prate = priv->cpll_hz;
+ }
+ } else {
+ if (is_gpll_parent)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ }
+
+ if (is_halfdiv)
+ /* NOTE: '+1' to balance the following rk_clrsetreg() 'div-1' */
+ div = DIV_ROUND_UP((prate * 2) - (3 * rate), 2 * rate) + 1;
+ else
+ div = DIV_ROUND_UP(prate, rate);
+
+ rk_clrsetreg(&cru->clksel_con[con], mask, (div - 1) << shift);
+ if (sel_mask)
+ rk_clrsetreg(&cru->clksel_con[con], sel_mask, sel << sel_shift);
+
+ return rk3528_cgpll_matrix_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_i2c_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ u8 is_pmucru = 0;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+ break;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ con = readl(&cru->pmuclksel_con[id]);
+ else
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_I2C3_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C3_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_i2c_set_clk(struct rk3528_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+ u8 is_pmucru = 0;
+
+ if (rate == 200 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate == 100 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate == 50 * MHz)
+ sel = CLK_I2C3_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_I2C3_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_I2C0:
+ id = 79;
+ mask = CLK_I2C0_SEL_MASK;
+ shift = CLK_I2C0_SEL_SHIFT;
+ break;
+
+ case CLK_I2C1:
+ id = 79;
+ mask = CLK_I2C1_SEL_MASK;
+ shift = CLK_I2C1_SEL_SHIFT;
+ break;
+
+ case CLK_I2C2:
+ id = 0;
+ mask = CLK_I2C2_SEL_MASK;
+ shift = CLK_I2C2_SEL_SHIFT;
+ is_pmucru = 1;
+ break;
+
+ case CLK_I2C3:
+ id = 63;
+ mask = CLK_I2C3_SEL_MASK;
+ shift = CLK_I2C3_SEL_SHIFT;
+ break;
+
+ case CLK_I2C4:
+ id = 85;
+ mask = CLK_I2C4_SEL_MASK;
+ shift = CLK_I2C4_SEL_SHIFT;
+ break;
+
+ case CLK_I2C5:
+ id = 63;
+ mask = CLK_I2C5_SEL_MASK;
+ shift = CLK_I2C5_SEL_SHIFT;
+
+ case CLK_I2C6:
+ id = 64;
+ mask = CLK_I2C6_SEL_MASK;
+ shift = CLK_I2C6_SEL_SHIFT;
+ break;
+
+ case CLK_I2C7:
+ id = 86;
+ mask = CLK_I2C7_SEL_MASK;
+ shift = CLK_I2C7_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if (is_pmucru)
+ rk_clrsetreg(&cru->pmuclksel_con[id], mask, sel << shift);
+ else
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_i2c_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_spi_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_SPI1_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else if (sel == CLK_SPI1_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_spi_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate == 200 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate == 100 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate == 50 * MHz)
+ sel = CLK_SPI1_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_SPI1_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_SPI0:
+ id = 79;
+ mask = CLK_SPI0_SEL_MASK;
+ shift = CLK_SPI0_SEL_SHIFT;
+ break;
+
+ case CLK_SPI1:
+ id = 63;
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_spi_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_pwm_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ if (sel == CLK_PWM0_SEL_CLK_MATRIX_50M_SRC)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_pwm_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate == 100 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_100M_SRC;
+ else if (rate == 50 * MHz)
+ sel = CLK_PWM0_SEL_CLK_MATRIX_50M_SRC;
+ else
+ sel = CLK_PWM0_SEL_XIN_OSC0_FUNC;
+
+ switch (clk_id) {
+ case CLK_PWM0:
+ id = 44;
+ mask = CLK_PWM0_SEL_MASK;
+ shift = CLK_PWM0_SEL_SHIFT;
+ break;
+
+ case CLK_PWM1:
+ id = 44;
+ mask = CLK_PWM1_SEL_MASK;
+ shift = CLK_PWM1_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_pwm_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_adc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[74]);
+ switch (clk_id) {
+ case CLK_SARADC:
+ div = (con & CLK_SARADC_DIV_MASK) >>
+ CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+ CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ div = (con & CLK_TSADC_DIV_MASK) >>
+ CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3528_adc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_SARADC:
+ mask = CLK_SARADC_DIV_MASK;
+ shift = CLK_SARADC_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC_TSEN:
+ mask = CLK_TSADC_TSEN_DIV_MASK;
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+
+ case CLK_TSADC:
+ mask = CLK_TSADC_DIV_MASK;
+ shift = CLK_TSADC_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[74], mask, (div - 1) << shift);
+
+ return rk3528_adc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sdmmc_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con;
+ ulong prate;
+
+ con = readl(&cru->clksel_con[85]);
+ div = (con & CCLK_SRC_SDMMC0_DIV_MASK) >>
+ CCLK_SRC_SDMMC0_DIV_SHIFT;
+ sel = (con & CCLK_SRC_SDMMC0_SEL_MASK) >>
+ CCLK_SRC_SDMMC0_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX)
+ prate = priv->cpll_hz;
+ else
+ prate = OSC_HZ;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_sdmmc_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[85],
+ CCLK_SRC_SDMMC0_SEL_MASK |
+ CCLK_SRC_SDMMC0_DIV_MASK,
+ sel << CCLK_SRC_SDMMC0_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_SDMMC0_DIV_SHIFT);
+
+ return rk3528_sdmmc_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_sfc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[61]);
+ div = (con & SCLK_SFC_DIV_MASK) >>
+ SCLK_SFC_DIV_SHIFT;
+ sel = (con & SCLK_SFC_SEL_MASK) >>
+ SCLK_SFC_SEL_SHIFT;
+ if (sel == SCLK_SFC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == SCLK_SFC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_sfc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ int div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = SCLK_SFC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = SCLK_SFC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 63);
+ rk_clrsetreg(&cru->clksel_con[61],
+ SCLK_SFC_SEL_MASK |
+ SCLK_SFC_DIV_MASK,
+ sel << SCLK_SFC_SEL_SHIFT |
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
+
+ return rk3528_sfc_get_clk(priv);
+}
+
+static ulong rk3528_emmc_get_clk(struct rk3528_clk_priv *priv)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->clksel_con[62]);
+ div = (con & CCLK_SRC_EMMC_DIV_MASK) >>
+ CCLK_SRC_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_SRC_EMMC_SEL_MASK) >>
+ CCLK_SRC_EMMC_SEL_SHIFT;
+
+ if (sel == CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX)
+ parent = priv->gpll_hz;
+ else if (sel == CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3528_emmc_set_clk(struct rk3528_clk_priv *priv, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX;
+ }
+
+ assert(div - 1 <= 31);
+ rk_clrsetreg(&cru->clksel_con[62],
+ CCLK_SRC_EMMC_SEL_MASK |
+ CCLK_SRC_EMMC_DIV_MASK,
+ sel << CCLK_SRC_EMMC_SEL_SHIFT |
+ (div - 1) << CCLK_SRC_EMMC_DIV_SHIFT);
+
+ return rk3528_emmc_get_clk(priv);
+}
+
+static ulong rk3528_dclk_vop_get_clk(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, con, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ div = (con & div_mask) >> div_shift;
+ sel = (con & sel_mask) >> sel_shift;
+ if (sel == DCLK_VOP_SRC_SEL_CLK_GPLL_MUX)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3528_dclk_vop_set_clk(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 div_mask, div_shift;
+ u32 sel_mask, sel_shift;
+ u32 id, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case DCLK_VOP0:
+ id = 32;
+ sel_mask = DCLK_VOP_SRC0_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC0_SEL_SHIFT;
+ /* FIXME if need src: clk_hdmiphy_pixel_io */
+ div_mask = DCLK_VOP_SRC0_DIV_MASK;
+ div_shift = DCLK_VOP_SRC0_DIV_SHIFT;
+ break;
+
+ case DCLK_VOP1:
+ id = 33;
+ sel_mask = DCLK_VOP_SRC1_SEL_MASK;
+ sel_shift = DCLK_VOP_SRC1_SEL_SHIFT;
+ div_mask = DCLK_VOP_SRC1_DIV_MASK;
+ div_shift = DCLK_VOP_SRC1_DIV_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ if ((priv->gpll_hz % rate) == 0) {
+ prate = priv->gpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_GPLL_MUX << sel_shift) & sel_mask;
+ } else {
+ prate = priv->cpll_hz;
+ sel = (DCLK_VOP_SRC_SEL_CLK_CPLL_MUX << sel_shift) & sel_mask;
+ }
+
+ div = ((DIV_ROUND_UP(prate, rate) - 1) << div_shift) & div_mask;
+ rk_clrsetreg(&cru->clksel_con[id], sel, div);
+
+ return rk3528_dclk_vop_get_clk(priv, clk_id);
+}
+
+static ulong rk3528_uart_get_rate(struct rk3528_clk_priv *priv, ulong clk_id)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, con, frac_div, div;
+ ulong m, n, rate;
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id - 2]);
+ div = (con & div_mask) >> div_shift;
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & sel_mask) >> sel_shift;
+
+ if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_SRC) {
+ rate = DIV_TO_RATE(priv->gpll_hz, div);
+ } else if (sel == SCLK_UART0_SRC_SEL_CLK_UART0_FRAC) {
+ frac_div = readl(&cru->clksel_con[id - 1]);
+ n = (frac_div & 0xffff0000) >> 16;
+ m = frac_div & 0x0000ffff;
+ rate = DIV_TO_RATE(priv->gpll_hz, div) * n / m;
+ } else {
+ rate = OSC_HZ;
+ }
+
+ return rate;
+}
+
+static ulong rk3528_uart_set_rate(struct rk3528_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 sel_shift, sel_mask, div_shift, div_mask;
+ u32 sel, id, div;
+ ulong m = 0, n = 0, val;
+
+ if (rate == OSC_HZ) {
+ sel = SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC;
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ } else if (priv->gpll_hz % rate == 0) {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else {
+ sel = SCLK_UART0_SRC_SEL_CLK_UART0_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &n, &m);
+ }
+
+ switch (clk_id) {
+ case SCLK_UART0:
+ id = 6;
+ sel_shift = SCLK_UART0_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART0_SRC_SEL_MASK;
+ div_shift = CLK_UART0_SRC_DIV_SHIFT;
+ div_mask = CLK_UART0_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART1:
+ id = 8;
+ sel_shift = SCLK_UART1_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART1_SRC_SEL_MASK;
+ div_shift = CLK_UART1_SRC_DIV_SHIFT;
+ div_mask = CLK_UART1_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART2:
+ id = 10;
+ sel_shift = SCLK_UART2_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART2_SRC_SEL_MASK;
+ div_shift = CLK_UART2_SRC_DIV_SHIFT;
+ div_mask = CLK_UART2_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART3:
+ id = 12;
+ sel_shift = SCLK_UART3_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART3_SRC_SEL_MASK;
+ div_shift = CLK_UART3_SRC_DIV_SHIFT;
+ div_mask = CLK_UART3_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART4:
+ id = 14;
+ sel_shift = SCLK_UART4_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART4_SRC_SEL_MASK;
+ div_shift = CLK_UART4_SRC_DIV_SHIFT;
+ div_mask = CLK_UART4_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART5:
+ id = 16;
+ sel_shift = SCLK_UART5_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART5_SRC_SEL_MASK;
+ div_shift = CLK_UART5_SRC_DIV_SHIFT;
+ div_mask = CLK_UART5_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART6:
+ id = 18;
+ sel_shift = SCLK_UART6_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART6_SRC_SEL_MASK;
+ div_shift = CLK_UART6_SRC_DIV_SHIFT;
+ div_mask = CLK_UART6_SRC_DIV_MASK;
+ break;
+
+ case SCLK_UART7:
+ id = 20;
+ sel_shift = SCLK_UART7_SRC_SEL_SHIFT;
+ sel_mask = SCLK_UART7_SRC_SEL_MASK;
+ div_shift = CLK_UART7_SRC_DIV_SHIFT;
+ div_mask = CLK_UART7_SRC_DIV_MASK;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id - 2], div_mask, (div - 1) << div_shift);
+ rk_clrsetreg(&cru->clksel_con[id], sel_mask, sel << sel_shift);
+ if (m && n) {
+ val = n << 16 | m;
+ writel(val, &cru->clksel_con[id - 1]);
+ }
+
+ return rk3528_uart_get_rate(priv, clk_id);
+}
+
+static ulong rk3528_clk_get_rate(struct clk *clk)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz || !priv->cpll_hz) {
+ printf("%s: gpll=%lu, cpll=%ld\n",
+ __func__, priv->gpll_hz, priv->cpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[APLL], priv->cru,
+ APLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+
+ case PLL_PPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL);
+ break;
+ case PLL_DPLL:
+ rate = rockchip_pll_get_rate(&rk3528_pll_clks[DPLL], priv->cru,
+ DPLL);
+ break;
+
+ case TCLK_WDT_NS:
+ rate = OSC_HZ;
+ break;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ rate = rk3528_i2c_get_clk(priv, clk->id);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ rate = rk3528_spi_get_clk(priv, clk->id);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ rate = rk3528_pwm_get_clk(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ rate = rk3528_adc_get_clk(priv, clk->id);
+ break;
+ case CCLK_SRC_EMMC:
+ rate = rk3528_emmc_get_clk(priv);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ rate = rk3528_sdmmc_get_clk(priv, clk->id);
+ break;
+ case SCLK_SFC:
+ rate = rk3528_sfc_get_clk(priv);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ rate = rk3528_dclk_vop_get_clk(priv, clk->id);
+ break;
+ case DCLK_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1) / 4;
+ break;
+ case DCLK_4X_CVBS:
+ rate = rk3528_dclk_vop_get_clk(priv, DCLK_VOP1);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ rate = rk3528_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ rate = rk3528_cgpll_matrix_get_rate(priv, clk->id);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ rate = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3528_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz) {
+ printf("%s gpll=%lu\n", __func__, priv->gpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ if (priv->armclk_hz)
+ rk3528_armclk_set_clk(priv, rate);
+ priv->armclk_hz = rate;
+ break;
+ case PLL_CPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, rate);
+ priv->cpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[CPLL],
+ priv->cru, CPLL);
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_PPLL:
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, rate);
+ priv->ppll_hz = rockchip_pll_get_rate(&rk3528_pll_clks[PPLL],
+ priv->cru, PPLL);
+ break;
+ case TCLK_WDT_NS:
+ return (rate == OSC_HZ) ? 0 : -EINVAL;
+ case CLK_I2C0:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ case CLK_I2C6:
+ case CLK_I2C7:
+ ret = rk3528_i2c_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SPI0:
+ case CLK_SPI1:
+ ret = rk3528_spi_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_PWM0:
+ case CLK_PWM1:
+ ret = rk3528_pwm_set_clk(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ ret = rk3528_adc_set_clk(priv, clk->id, rate);
+ break;
+ case HCLK_SDMMC0:
+ case CCLK_SRC_SDMMC0:
+ ret = rk3528_sdmmc_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_SFC:
+ ret = rk3528_sfc_set_clk(priv, rate);
+ break;
+ case CCLK_SRC_EMMC:
+ ret = rk3528_emmc_set_clk(priv, rate);
+ break;
+ case DCLK_VOP0:
+ case DCLK_VOP1:
+ ret = rk3528_dclk_vop_set_clk(priv, clk->id, rate);
+ break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ ret = rk3528_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_MATRIX_50M_SRC:
+ case CLK_MATRIX_100M_SRC:
+ case CLK_MATRIX_150M_SRC:
+ case CLK_MATRIX_200M_SRC:
+ case CLK_MATRIX_250M_SRC:
+ case CLK_MATRIX_300M_SRC:
+ case CLK_MATRIX_339M_SRC:
+ case CLK_MATRIX_400M_SRC:
+ case CLK_MATRIX_500M_SRC:
+ case CLK_MATRIX_600M_SRC:
+ case ACLK_BUS_VOPGL_BIU:
+ ret = rk3528_cgpll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PPLL_50M_MATRIX:
+ case CLK_PPLL_100M_MATRIX:
+ case CLK_PPLL_125M_MATRIX:
+ case CLK_GMAC1_VPU_25M:
+ ret = rk3528_ppll_matrix_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_GMAC1_RMII_VPU:
+ case CLK_GMAC1_SRC_VPU:
+ /* dummy set */
+ ret = rk3528_ppll_matrix_get_rate(priv, clk->id);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rk3528_clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+ const char *clock_dev_name = parent->dev->name;
+
+ switch (clk->id) {
+ case DCLK_VOP0:
+ if (!strcmp(clock_dev_name, "inno_hdmi_pll_clk"))
+ /* clk_hdmiphy_pixel_io */
+ rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 1);
+ else
+ rk_clrsetreg(&priv->cru->clksel_con[84], 0x1, 0);
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+}
+#endif
+
+static struct clk_ops rk3528_clk_ops = {
+ .get_rate = rk3528_clk_get_rate,
+ .set_rate = rk3528_clk_set_rate,
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .set_parent = rk3528_clk_set_parent,
+#endif
+};
+
+static ulong rk3528_grfclk_get_rate(struct clk *clk)
+{
+ struct rk3528_clk_priv *priv;
+ struct udevice *cru_dev;
+ ulong rate = 0;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3528_cru),
+ &cru_dev);
+ if (ret) {
+ printf("%s: could not find cru device\n", __func__);
+ return ret;
+ }
+ priv = dev_get_priv(cru_dev);
+
+ switch (clk->id) {
+ case SCLK_SDMMC_SAMPLE:
+ rate = rk3528_sdmmc_get_clk(priv, CCLK_SRC_SDMMC0) / 2;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+#define ROCKCHIP_MMC_DELAY_SEL BIT(11)
+#define ROCKCHIP_MMC_DEGREE_MASK 0x3
+#define ROCKCHIP_MMC_DELAYNUM_OFFSET 3
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_OFFSET)
+#define PSECS_PER_SEC 1000000000000LL
+/*
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+int rk3528_mmc_get_phase(struct clk *clk)
+{
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev);
+ u32 raw_value = 0, delay_num;
+ u16 degrees = 0;
+ ulong rate;
+
+ rate = rk3528_grfclk_get_rate(clk);
+ if (rate < 0)
+ return rate;
+
+ if (clk->id == SCLK_SDMMC_SAMPLE)
+ raw_value = readl(&priv->grf->sdmmc_con1);
+ else
+ return -ENONET;
+
+ raw_value >>= 1;
+ degrees = (raw_value & ROCKCHIP_MMC_DEGREE_MASK) * 90;
+
+ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
+ /* degrees/delaynum * 10000 */
+ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+ 36 * (rate / 1000000);
+
+ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+ delay_num >>= ROCKCHIP_MMC_DELAYNUM_OFFSET;
+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
+ }
+
+ return degrees % 360;
+}
+
+int rk3528_mmc_set_phase(struct clk *clk, u32 degrees)
+{
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(clk->dev);
+ u8 nineties, remainder, delay_num;
+ u32 raw_value, delay;
+ ulong rate;
+
+ rate = rk3528_grfclk_get_rate(clk);
+ if (rate < 0)
+ return rate;
+
+ nineties = degrees / 90;
+ remainder = (degrees % 90);
+
+ /*
+ * Convert to delay; do a little extra work to make sure we
+ * don't overflow 32-bit / 64-bit numbers.
+ */
+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
+ delay *= remainder;
+ delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
+
+ delay_num = (u8)min_t(u32, delay, 255);
+
+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_OFFSET;
+ raw_value |= nineties;
+
+ raw_value <<= 1;
+ if (clk->id == SCLK_SDMMC_SAMPLE)
+ writel(raw_value | 0xffff0000, &priv->grf->sdmmc_con1);
+ else
+ return -ENONET;
+
+ debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
+ degrees, delay_num, raw_value, rk3528_mmc_get_phase(clk));
+
+ return 0;
+}
+
+static int rk3528_grfclk_get_phase(struct clk *clk)
+{
+ int ret;
+
+ debug("%s %ld\n", __func__, clk->id);
+ switch (clk->id) {
+ case SCLK_SDMMC_SAMPLE:
+ ret = rk3528_mmc_get_phase(clk);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static int rk3528_grfclk_set_phase(struct clk *clk, int degrees)
+{
+ int ret;
+
+ debug("%s %ld\n", __func__, clk->id);
+ switch (clk->id) {
+ case SCLK_SDMMC_SAMPLE:
+ ret = rk3528_mmc_set_phase(clk, degrees);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static struct clk_ops rk3528_grfclk_ops = {
+ .get_rate = rk3528_grfclk_get_rate,
+ .get_phase = rk3528_grfclk_get_phase,
+ .set_phase = rk3528_grfclk_set_phase,
+};
+
+#ifndef CONFIG_SPL_BUILD
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ const struct rk3528_clk_info *clk_dump;
+ struct rk3528_clk_priv *priv;
+ struct udevice *cru_dev;
+ struct clk clk;
+ ulong clk_count = ARRAY_SIZE(clks_dump);
+ ulong rate;
+ int i, ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3528_cru),
+ &cru_dev);
+ if (ret) {
+ printf("%s failed to get cru device\n", __func__);
+ return ret;
+ }
+
+ priv = dev_get_priv(cru_dev);
+ printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
+ priv->sync_kernel ? "sync kernel" : "uboot",
+ priv->armclk_enter_hz / 1000,
+ priv->armclk_init_hz / 1000,
+ priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
+ priv->set_armclk_rate ? " KHz" : "N/A");
+ for (i = 0; i < clk_count; i++) {
+ clk_dump = &clks_dump[i];
+ if (clk_dump->name) {
+ clk.id = clk_dump->id;
+ ret = clk_request(cru_dev, &clk);
+ if (ret < 0)
+ return ret;
+
+ rate = clk_get_rate(&clk);
+ clk_free(&clk);
+ if (i == 0) {
+ if (rate < 0)
+ printf(" %s %s\n", clk_dump->name,
+ "unknown");
+ else
+ printf(" %s %lu KHz\n", clk_dump->name,
+ rate / 1000);
+ } else {
+ if (rate < 0)
+ printf(" %s %s\n", clk_dump->name,
+ "unknown");
+ else
+ printf(" %s %lu KHz\n", clk_dump->name,
+ rate / 1000);
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+
+static int rk3528_grfclk_probe(struct udevice *dev)
+{
+ struct rk3528_grf_clk_priv *priv = dev_get_priv(dev);
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+
+ return 0;
+}
+
+static const struct udevice_id rk3528_grf_cru_ids[] = {
+ { .compatible = "rockchip,rk3528-grf-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_grf_cru) = {
+ .name = "rockchip_rk3528_grf_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3528_grf_cru_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3528_grf_clk_priv),
+ .ops = &rk3528_grfclk_ops,
+ .probe = rk3528_grfclk_probe,
+};
+
+static int rk3528_clk_init(struct rk3528_clk_priv *priv)
+{
+ int ret;
+
+ priv->sync_kernel = false;
+
+#ifdef CONFIG_SPL_BUILD
+ /*
+ * BOOTROM:
+ * CPU 1902/2(postdiv1)=546M
+ * CPLL 996/2(postdiv1)=498M
+ * GPLL 1188/2(postdiv1)=594M
+ * |-- clk_matrix_200m_src_div=1 => rate: 300M
+ * |-- clk_matrix_300m_src_div=2 => rate: 200M
+ *
+ * Avoid overclocking when change GPLL rate:
+ * Change clk_matrix_200m_src_div to 5.
+ * Change clk_matrix_300m_src_div to 3.
+ */
+ writel(0x01200120, &priv->cru->clksel_con[1]);
+ writel(0x00030003, &priv->cru->clksel_con[2]);
+
+ if (!priv->armclk_enter_hz) {
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL);
+ priv->armclk_init_hz = priv->armclk_enter_hz;
+ }
+
+ if (priv->armclk_init_hz != APLL_HZ) {
+ ret = rk3528_armclk_set_clk(priv, APLL_HZ);
+ if (!ret)
+ priv->armclk_init_hz = APLL_HZ;
+ }
+#else
+ if (!priv->armclk_enter_hz) {
+ struct clk clk;
+
+ ret = rockchip_get_scmi_clk(&clk.dev);
+ if (ret) {
+ printf("Failed to get scmi clk dev\n");
+ return ret;
+ }
+
+ clk.id = SCMI_CLK_CPU;
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
+ if (ret < 0) {
+ printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ);
+ return ret;
+ } else {
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3528_pll_clks[APLL],
+ priv->cru, APLL);
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
+ }
+ }
+#endif
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+ if (priv->ppll_hz != PPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3528_pll_clks[PPLL], priv->cru,
+ PPLL, PPLL_HZ);
+ if (!ret)
+ priv->ppll_hz = PPLL_HZ;
+ }
+
+#ifdef CONFIG_SPL_BUILD
+ /* Init to override bootrom config */
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_50M_SRC, 50000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_100M_SRC, 100000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_150M_SRC, 150000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_200M_SRC, 200000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_250M_SRC, 250000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_300M_SRC, 300000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_339M_SRC, 340000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_400M_SRC, 400000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_500M_SRC, 500000000);
+ rk3528_cgpll_matrix_set_rate(priv, CLK_MATRIX_600M_SRC, 600000000);
+ rk3528_cgpll_matrix_set_rate(priv, ACLK_BUS_VOPGL_BIU, 500000000);
+
+ /* The default rate is 100Mhz, it's not friendly for remote IR module */
+ rk3528_pwm_set_clk(priv, CLK_PWM0, 24000000);
+ rk3528_pwm_set_clk(priv, CLK_PWM1, 24000000);
+#endif
+ return 0;
+}
+
+static int rk3528_clk_probe(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ if (IS_ERR(priv->grf))
+ return PTR_ERR(priv->grf);
+
+ ret = rk3528_clk_init(priv);
+ if (ret)
+ return ret;
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3528_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3528_clk_bind(struct udevice *dev)
+{
+ struct udevice *sys_child, *sf_child;
+ struct softreset_reg *sf_priv;
+ struct sysreset_reg *priv;
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3528_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3528_cru,
+ glb_srst_snd);
+ sys_child->priv = priv;
+ }
+
+ ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
+ dev_ofnode(dev), &sf_child);
+ if (ret) {
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+ } else {
+ sf_priv = malloc(sizeof(struct softreset_reg));
+ sf_priv->sf_reset_offset = offsetof(struct rk3528_cru,
+ softrst_con[0]);
+ sf_priv->sf_reset_num = 47;
+ sf_child->priv = sf_priv;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id rk3528_clk_ids[] = {
+ { .compatible = "rockchip,rk3528-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3528_cru) = {
+ .name = "rockchip_rk3528_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3528_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv),
+ .ofdata_to_platdata = rk3528_clk_ofdata_to_platdata,
+ .ops = &rk3528_clk_ops,
+ .bind = rk3528_clk_bind,
+ .probe = rk3528_clk_probe,
+};
+
+/* spl scmi clk */
+#ifdef CONFIG_SPL_BUILD
+
+static ulong rk3528_crypto_get_rate(struct rk3528_clk_priv *priv, struct clk *clk)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, con, mask, shift;
+ ulong rate;
+
+ switch (clk->id) {
+ case SCMI_CORE_CRYPTO:
+ id = 43;
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
+ break;
+
+ case SCMI_PKA_CRYPTO:
+ id = 44;
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->clksel_con[id]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC)
+ rate = 300 * MHz;
+ else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC)
+ rate = 200 * MHz;
+ else if (sel == CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3528_crypto_set_rate(struct rk3528_clk_priv *priv,
+ struct clk *clk, ulong rate)
+{
+ struct rk3528_cru *cru = priv->cru;
+ u32 id, sel, mask, shift;
+
+ if (rate == 300 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC;
+ else if (rate == 200 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC;
+ else if (rate == 100 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC;
+ else
+ sel = CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC;
+
+ switch (clk->id) {
+ case SCMI_CORE_CRYPTO:
+ id = 43;
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
+ break;
+
+ case SCMI_PKA_CRYPTO:
+ id = 44;
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
+ break;
+
+ default:
+ return -ENOENT;
+ }
+
+ rk_clrsetreg(&cru->clksel_con[id], mask, sel << shift);
+
+ return rk3528_crypto_get_rate(priv, clk);
+}
+
+static ulong rk3528_clk_scmi_get_rate(struct clk *clk)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCMI_CORE_CRYPTO:
+ case SCMI_PKA_CRYPTO:
+ return rk3528_crypto_get_rate(priv, clk);
+ default:
+ return -ENOENT;
+ }
+};
+
+static ulong rk3528_clk_scmi_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case SCMI_CORE_CRYPTO:
+ case SCMI_PKA_CRYPTO:
+ return rk3528_crypto_set_rate(priv, clk, rate);
+ default:
+ return -ENOENT;
+ }
+
+ return 0;
+};
+
+static int rk3528_scmi_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3528_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3528_cru *)0xff4a0000;
+
+ return 0;
+}
+
+/* A fake scmi driver for SPL/TPL where smccc agent is not available. */
+static const struct clk_ops scmi_clk_ops = {
+ .get_rate = rk3528_clk_scmi_get_rate,
+ .set_rate = rk3528_clk_scmi_set_rate,
+};
+
+U_BOOT_DRIVER(scmi_clock) = {
+ .name = "scmi_clk",
+ .id = UCLASS_CLK,
+ .ops = &scmi_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct rk3528_clk_priv),
+ .ofdata_to_platdata = rk3528_scmi_clk_ofdata_to_platdata,
+};
+#endif
diff --git a/u-boot/drivers/clk/rockchip/clk_rk3562.c b/u-boot/drivers/clk/rockchip/clk_rk3562.c
new file mode 100644
index 0000000..36d8c44
--- /dev/null
+++ b/u-boot/drivers/clk/rockchip/clk_rk3562.c
@@ -0,0 +1,2046 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/cru_rk3562.h>
+#include <asm/arch/hardware.h>
+#include <asm/io.h>
+#include <dm/lists.h>
+#include <dt-bindings/clock/rk3562-cru.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
+
+static struct rockchip_pll_rate_table rk3562_pll_rates[] = {
+ /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
+ RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
+ RK3036_PLL_RATE(1416000000, 1, 118, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1296000000, 1, 108, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1104000000, 1, 92, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
+ RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0),
+ RK3036_PLL_RATE(912000000, 1, 76, 2, 1, 1, 0),
+ RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0),
+ RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0),
+ RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0),
+ RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0),
+ RK3036_PLL_RATE(408000000, 1, 68, 2, 2, 1, 0),
+ RK3036_PLL_RATE(312000000, 1, 78, 6, 1, 1, 0),
+ RK3036_PLL_RATE(216000000, 1, 72, 4, 2, 1, 0),
+ RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
+ { /* sentinel */ },
+};
+
+static struct rockchip_pll_clock rk3562_pll_clks[] = {
+ [APLL] = PLL(pll_rk3328, PLL_APLL, RK3562_PLL_CON(0),
+ RK3562_MODE_CON, 0, 10, 0, rk3562_pll_rates),
+ [GPLL] = PLL(pll_rk3328, PLL_GPLL, RK3562_PLL_CON(24),
+ RK3562_MODE_CON, 2, 10, 0, rk3562_pll_rates),
+ [VPLL] = PLL(pll_rk3328, PLL_VPLL, RK3562_PLL_CON(32),
+ RK3562_MODE_CON, 6, 10, 0, rk3562_pll_rates),
+ [HPLL] = PLL(pll_rk3328, PLL_HPLL, RK3562_PLL_CON(40),
+ RK3562_MODE_CON, 8, 10, 0, rk3562_pll_rates),
+ [CPLL] = PLL(pll_rk3328, PLL_CPLL, RK3562_PMU1_PLL_CON(0),
+ RK3562_PMU1_MODE_CON, 0, 10, 0, rk3562_pll_rates),
+ [DPLL] = PLL(pll_rk3328, PLL_DPLL, RK3562_SUBDDR_PLL_CON(0),
+ RK3562_SUBDDR_MODE_CON, 0, 10, 0, NULL),
+};
+
+#define RK3562_CPUCLK_RATE(_rate, _aclk_m_core, _pclk_dbg) \
+{ \
+ .rate = _rate##U, \
+ .aclk_div = _aclk_m_core, \
+ .pclk_div = _pclk_dbg, \
+}
+
+static struct rockchip_cpu_rate_table rk3562_cpu_rates[] = {
+ RK3562_CPUCLK_RATE(1416000000, 1, 8),
+ RK3562_CPUCLK_RATE(1296000000, 1, 8),
+ RK3562_CPUCLK_RATE(1200000000, 1, 8),
+ RK3562_CPUCLK_RATE(1104000000, 1, 8),
+ RK3562_CPUCLK_RATE(1008000000, 1, 8),
+ RK3562_CPUCLK_RATE(912000000, 1, 6),
+ RK3562_CPUCLK_RATE(816000000, 1, 6),
+ RK3562_CPUCLK_RATE(600000000, 1, 6),
+ RK3562_CPUCLK_RATE(408000000, 1, 4),
+ { /* sentinel */ },
+};
+
+#ifndef CONFIG_SPL_BUILD
+#define RK3562_CLK_DUMP(_id, _name) \
+{ \
+ .id = _id, \
+ .name = _name, \
+}
+
+static const struct rk3562_clk_info clks_dump[] = {
+ RK3562_CLK_DUMP(PLL_APLL, "apll"),
+ RK3562_CLK_DUMP(PLL_GPLL, "gpll"),
+ RK3562_CLK_DUMP(PLL_VPLL, "vpll"),
+ RK3562_CLK_DUMP(PLL_HPLL, "hpll"),
+ RK3562_CLK_DUMP(PLL_CPLL, "cpll"),
+ RK3562_CLK_DUMP(PLL_DPLL, "dpll"),
+ RK3562_CLK_DUMP(ACLK_BUS, "aclk_bus"),
+ RK3562_CLK_DUMP(HCLK_BUS, "hclk_bus"),
+ RK3562_CLK_DUMP(PCLK_BUS, "pclk_bus"),
+ RK3562_CLK_DUMP(ACLK_PERI, "aclk_peri"),
+ RK3562_CLK_DUMP(HCLK_PERI, "hclk_peri"),
+ RK3562_CLK_DUMP(PCLK_PERI, "pclk_peri"),
+};
+#endif
+
+/*
+ *
+ * rational_best_approximation(31415, 10000,
+ * (1 << 8) - 1, (1 << 5) - 1, &n, &d);
+ *
+ * you may look at given_numerator as a fixed point number,
+ * with the fractional part size described in given_denominator.
+ *
+ * for theoretical background, see:
+ * http://en.wikipedia.org/wiki/Continued_fraction
+ */
+static void rational_best_approximation(unsigned long given_numerator,
+ unsigned long given_denominator,
+ unsigned long max_numerator,
+ unsigned long max_denominator,
+ unsigned long *best_numerator,
+ unsigned long *best_denominator)
+{
+ unsigned long n, d, n0, d0, n1, d1;
+
+ n = given_numerator;
+ d = given_denominator;
+ n0 = 0;
+ d1 = 0;
+ n1 = 1;
+ d0 = 1;
+ for (;;) {
+ unsigned long t, a;
+
+ if (n1 > max_numerator || d1 > max_denominator) {
+ n1 = n0;
+ d1 = d0;
+ break;
+ }
+ if (d == 0)
+ break;
+ t = d;
+ a = n / d;
+ d = n % d;
+ n = t;
+ t = n0 + a * n1;
+ n0 = n1;
+ n1 = t;
+ t = d0 + a * d1;
+ d0 = d1;
+ d1 = t;
+ }
+ *best_numerator = n1;
+ *best_denominator = d1;
+}
+
+static int rk3562_armclk_set_rate(struct rk3562_clk_priv *priv, ulong new_rate)
+{
+ const struct rockchip_cpu_rate_table *rate;
+ struct rk3562_cru *cru = priv->cru;
+ ulong old_rate;
+
+ rate = rockchip_get_cpu_settings(rk3562_cpu_rates, new_rate);
+ if (!rate) {
+ printf("%s unsupported rate\n", __func__);
+ return -EINVAL;
+ }
+
+ /*
+ * set up dependent divisors for DBG and ACLK clocks.
+ */
+ old_rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,
+ APLL);
+ if (old_rate == new_rate) {
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
+ } else if (old_rate > new_rate) {
+ if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
+ } else if (old_rate < new_rate) {
+ rk_clrsetreg(&cru->clksel_con[11], ACLK_CORE_PRE_DIV_MASK,
+ rate->aclk_div << ACLK_CORE_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[12], PCLK_DBG_PRE_DIV_MASK,
+ rate->pclk_div << PCLK_DBG_PRE_DIV_SHIFT);
+ rk_clrsetreg(&cru->clksel_con[10], CLK_CORE_PRE_DIV_MASK, 0);
+
+ if (rockchip_pll_set_rate(&rk3562_pll_clks[APLL],
+ priv->cru, APLL, new_rate))
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ulong rk3562_bus_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con, div;
+ ulong rate;
+
+ switch (clk_id) {
+ case ACLK_BUS:
+ con = readl(&cru->clksel_con[40]);
+ sel = (con & ACLK_BUS_SEL_MASK) >> ACLK_BUS_SEL_SHIFT;
+ div = (con & ACLK_BUS_DIV_MASK) >> ACLK_BUS_DIV_SHIFT;
+ break;
+ case HCLK_BUS:
+ con = readl(&cru->clksel_con[40]);
+ sel = (con & HCLK_BUS_SEL_MASK) >> HCLK_BUS_SEL_SHIFT;
+ div = (con & HCLK_BUS_DIV_MASK) >> HCLK_BUS_DIV_SHIFT;
+ break;
+ case PCLK_BUS:
+ con = readl(&cru->clksel_con[41]);
+ sel = (con & PCLK_BUS_SEL_MASK) >> PCLK_BUS_SEL_SHIFT;
+ div = (con & PCLK_BUS_DIV_MASK) >> PCLK_BUS_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == ACLK_BUS_SEL_CPLL)
+ rate = priv->cpll_hz;
+ else
+ rate = priv->gpll_hz;
+
+ return DIV_TO_RATE(rate, div);
+}
+
+static ulong rk3562_bus_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div;
+
+ if (priv->cpll_hz % rate == 0) {
+ sel = ACLK_BUS_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ sel= ACLK_BUS_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+
+ switch (clk_id) {
+ case ACLK_BUS:
+ rk_clrsetreg(&cru->clksel_con[40],
+ ACLK_BUS_SEL_MASK | ACLK_BUS_DIV_MASK,
+ (sel << ACLK_BUS_SEL_SHIFT) |
+ ((div - 1) << ACLK_BUS_DIV_SHIFT));
+ break;
+ case HCLK_BUS:
+ rk_clrsetreg(&cru->clksel_con[40],
+ HCLK_BUS_SEL_MASK | HCLK_BUS_DIV_MASK,
+ (sel << HCLK_BUS_SEL_SHIFT) |
+ ((div - 1) << HCLK_BUS_DIV_SHIFT));
+ break;
+ case PCLK_BUS:
+ rk_clrsetreg(&cru->clksel_con[41],
+ PCLK_BUS_SEL_MASK | PCLK_BUS_DIV_MASK,
+ (sel << PCLK_BUS_SEL_SHIFT) |
+ ((div - 1) << PCLK_BUS_DIV_SHIFT));
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_bus_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_peri_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con, div;
+ ulong rate;
+
+ switch (clk_id) {
+ case ACLK_PERI:
+ con = readl(&cru->periclksel_con[0]);
+ sel = (con & ACLK_PERI_SEL_MASK) >> ACLK_PERI_SEL_SHIFT;
+ div = (con & ACLK_PERI_DIV_MASK) >> ACLK_PERI_DIV_SHIFT;
+ break;
+ case HCLK_PERI:
+ con = readl(&cru->periclksel_con[0]);
+ sel = (con & HCLK_PERI_SEL_MASK) >> HCLK_PERI_SEL_SHIFT;
+ div = (con & HCLK_PERI_DIV_MASK) >> HCLK_PERI_DIV_SHIFT;
+ break;
+ case PCLK_PERI:
+ con = readl(&cru->periclksel_con[1]);
+ sel = (con & PCLK_PERI_SEL_MASK) >> PCLK_PERI_SEL_SHIFT;
+ div = (con & PCLK_PERI_DIV_MASK) >> PCLK_PERI_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == ACLK_PERI_SEL_CPLL)
+ rate = priv->cpll_hz;
+ else
+ rate = priv->gpll_hz;
+
+ return DIV_TO_RATE(rate, div);
+}
+
+static ulong rk3562_peri_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div;
+
+ if (priv->cpll_hz % rate == 0) {
+ sel = ACLK_PERI_SEL_CPLL;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ sel= ACLK_PERI_SEL_GPLL;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
+
+ switch (clk_id) {
+ case ACLK_PERI:
+ rk_clrsetreg(&cru->periclksel_con[0],
+ ACLK_PERI_SEL_MASK | ACLK_PERI_DIV_MASK,
+ (sel << ACLK_PERI_SEL_SHIFT) |
+ ((div - 1) << ACLK_PERI_DIV_SHIFT));
+ break;
+ case HCLK_PERI:
+ rk_clrsetreg(&cru->periclksel_con[0],
+ HCLK_PERI_SEL_MASK | HCLK_PERI_DIV_MASK,
+ (sel << HCLK_PERI_SEL_SHIFT) |
+ ((div - 1) << HCLK_PERI_DIV_SHIFT));
+ break;
+ case PCLK_PERI:
+ rk_clrsetreg(&cru->periclksel_con[1],
+ PCLK_PERI_SEL_MASK | PCLK_PERI_DIV_MASK,
+ (sel << PCLK_PERI_SEL_SHIFT) |
+ ((div - 1) << PCLK_PERI_DIV_SHIFT));
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_peri_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_i2c_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con, div;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PMU0_I2C0:
+ con = readl(&cru->pmu0clksel_con[3]);
+ sel = (con & CLK_PMU0_I2C0_SEL_MASK) >> CLK_PMU0_I2C0_SEL_SHIFT;
+ if (sel == CLK_PMU0_I2C0_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_PMU0_I2C0_SEL_24M)
+ rate = OSC_HZ;
+ else
+ rate = 32768;
+ div = (con & CLK_PMU0_I2C0_DIV_MASK) >> CLK_PMU0_I2C0_DIV_SHIFT;
+
+ return DIV_TO_RATE(rate, div);
+ case CLK_I2C:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ con = readl(&cru->clksel_con[41]);
+ sel = (con & CLK_I2C_SEL_MASK) >> CLK_I2C_SEL_SHIFT;
+ if (sel == CLK_I2C_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_I2C_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_I2C_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3562_i2c_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div;
+
+ switch (clk_id) {
+ case CLK_PMU0_I2C0:
+ if (rate == 200 * MHz) {
+ sel = CLK_PMU0_I2C0_SEL_200M;
+ div = 1;
+ } else if (rate == OSC_HZ) {
+ sel = CLK_PMU0_I2C0_SEL_24M;
+ div = 1;
+ } else if (rate == 32768) {
+ sel = CLK_PMU0_I2C0_SEL_32K;
+ div = 1;
+ } else {
+ sel = CLK_PMU0_I2C0_SEL_200M;
+ div = DIV_ROUND_UP(200 * MHz, rate);
+ assert(div - 1 <= 31);
+ }
+ rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_DIV_MASK,
+ (div - 1) << CLK_PMU0_I2C0_DIV_SHIFT);
+ rk_clrsetreg(&cru->pmu0clksel_con[3], CLK_PMU0_I2C0_SEL_MASK,
+ sel << CLK_PMU0_I2C0_SEL_SHIFT);
+ break;
+ case CLK_I2C:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ if (rate == 200 * MHz)
+ sel = CLK_I2C_SEL_200M;
+ else if (rate == 100 * MHz)
+ sel = CLK_I2C_SEL_100M;
+ else if (rate == 50 * MHz)
+ sel = CLK_I2C_SEL_50M;
+ else
+ sel = CLK_I2C_SEL_24M;
+ rk_clrsetreg(&cru->clksel_con[41], CLK_I2C_SEL_MASK,
+ sel << CLK_I2C_SEL_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+
+ return rk3562_i2c_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_uart_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 reg, con, fracdiv, div, src, p_src, p_rate;
+ unsigned long m, n;
+
+ switch (clk_id) {
+ case SCLK_PMU1_UART0:
+ con = readl(&cru->pmu1clksel_con[2]);
+ src = (con & CLK_PMU1_UART0_SEL_MASK) >>
+ CLK_PMU1_UART0_SEL_SHIFT;
+ div = (con & CLK_PMU1_UART0_SRC_DIV_MASK) >>
+ CLK_PMU1_UART0_SRC_DIV_SHIFT;
+ if (src == CLK_UART_SEL_SRC) {
+ return DIV_TO_RATE(priv->cpll_hz, div);
+ } else if (src == CLK_UART_SEL_FRAC) {
+ fracdiv = readl(&cru->pmu1clksel_con[3]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return DIV_TO_RATE(priv->cpll_hz, div) * n / m;
+ } else {
+ return OSC_HZ;
+ }
+ case SCLK_UART1:
+ reg = 21;
+ break;
+ case SCLK_UART2:
+ reg = 23;
+ break;
+ case SCLK_UART3:
+ reg = 25;
+ break;
+ case SCLK_UART4:
+ reg = 27;
+ break;
+ case SCLK_UART5:
+ reg = 29;
+ break;
+ case SCLK_UART6:
+ reg = 31;
+ break;
+ case SCLK_UART7:
+ reg = 33;
+ break;
+ case SCLK_UART8:
+ reg = 35;
+ break;
+ case SCLK_UART9:
+ reg = 37;
+ break;
+ default:
+ return -ENOENT;
+ }
+ con = readl(&cru->periclksel_con[reg]);
+ src = (con & CLK_UART_SEL_MASK) >> CLK_UART_SEL_SHIFT;
+ div = (con & CLK_UART_SRC_DIV_MASK) >> CLK_UART_SRC_DIV_SHIFT;
+ p_src = (con & CLK_UART_SRC_SEL_MASK) >> CLK_UART_SRC_SEL_SHIFT;
+ if (p_src == CLK_UART_SRC_SEL_GPLL)
+ p_rate = priv->gpll_hz;
+ else
+ p_rate = priv->cpll_hz;
+ if (src == CLK_UART_SEL_SRC) {
+ return DIV_TO_RATE(p_rate, div);
+ } else if (src == CLK_UART_SEL_FRAC) {
+ fracdiv = readl(&cru->periclksel_con[reg + 1]);
+ n = fracdiv & CLK_UART_FRAC_NUMERATOR_MASK;
+ n >>= CLK_UART_FRAC_NUMERATOR_SHIFT;
+ m = fracdiv & CLK_UART_FRAC_DENOMINATOR_MASK;
+ m >>= CLK_UART_FRAC_DENOMINATOR_SHIFT;
+ return DIV_TO_RATE(p_rate, div) * n / m;
+ } else {
+ return OSC_HZ;
+ }
+}
+
+static ulong rk3562_uart_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 reg, clk_src, uart_src, div;
+ unsigned long m = 0, n = 0, val;
+
+ switch (clk_id) {
+ case SCLK_PMU1_UART0:
+ if (priv->cpll_hz % rate == 0) {
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else if (rate == OSC_HZ) {
+ uart_src = CLK_UART_SEL_XIN24M;
+ div = 2;
+ } else {
+ uart_src = CLK_UART_SEL_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->cpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &n, &m);
+ }
+
+ rk_clrsetreg(&cru->pmu1clksel_con[2],
+ CLK_PMU1_UART0_SEL_MASK |
+ CLK_PMU1_UART0_SRC_DIV_MASK,
+ (uart_src << CLK_PMU1_UART0_SEL_SHIFT) |
+ ((div - 1) << CLK_PMU1_UART0_SRC_DIV_SHIFT));
+ if (m && n) {
+ val = n << CLK_UART_FRAC_NUMERATOR_SHIFT | m;
+ writel(val, &cru->pmu1clksel_con[3]);
+ }
+
+ return rk3562_uart_get_rate(priv, clk_id);
+ case SCLK_UART1:
+ reg = 21;
+ break;
+ case SCLK_UART2:
+ reg = 23;
+ break;
+ case SCLK_UART3:
+ reg = 25;
+ break;
+ case SCLK_UART4:
+ reg = 27;
+ break;
+ case SCLK_UART5:
+ reg = 29;
+ break;
+ case SCLK_UART6:
+ reg = 31;
+ break;
+ case SCLK_UART7:
+ reg = 33;
+ break;
+ case SCLK_UART8:
+ reg = 35;
+ break;
+ case SCLK_UART9:
+ reg = 37;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (priv->gpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ } else if (priv->cpll_hz % rate == 0) {
+ clk_src = CLK_UART_SRC_SEL_CPLL;
+ uart_src = CLK_UART_SEL_SRC;
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else if (rate == OSC_HZ) {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_XIN24M;
+ div = 2;
+ } else {
+ clk_src = CLK_UART_SRC_SEL_GPLL;
+ uart_src = CLK_UART_SEL_FRAC;
+ div = 2;
+ rational_best_approximation(rate, priv->gpll_hz / div,
+ GENMASK(16 - 1, 0),
+ GENMASK(16 - 1, 0),
+ &n, &m);
+ }
+
+ rk_clrsetreg(&cru->periclksel_con[reg],
+ CLK_UART_SEL_MASK | CLK_UART_SRC_SEL_MASK |
+ CLK_UART_SRC_DIV_MASK,
+ (clk_src << CLK_UART_SRC_SEL_SHIFT) |
+ (uart_src << CLK_UART_SEL_SHIFT) |
+ ((div - 1) << CLK_UART_SRC_DIV_SHIFT));
+ if (m && n) {
+ val = n << CLK_UART_FRAC_NUMERATOR_SHIFT | m;
+ writel(val, &cru->periclksel_con[reg + 1]);
+ }
+
+ return rk3562_uart_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_pwm_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con, div, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PMU1_PWM0:
+ con = readl(&cru->pmu1clksel_con[4]);
+ sel = (con & CLK_PMU1_PWM0_SEL_MASK) >> CLK_PMU1_PWM0_SEL_SHIFT;
+ if (sel == CLK_PMU1_PWM0_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_PMU1_PWM0_SEL_24M)
+ rate = OSC_HZ;
+ else
+ rate = 32768;
+ div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT;
+
+ return DIV_TO_RATE(rate, div);
+ case CLK_PWM1_PERI:
+ mask = CLK_PWM1_PERI_SEL_MASK;
+ shift = CLK_PWM1_PERI_SEL_SHIFT;
+ break;
+ case CLK_PWM2_PERI:
+ mask = CLK_PWM2_PERI_SEL_MASK;
+ shift = CLK_PWM2_PERI_SEL_SHIFT;
+ break;
+ case CLK_PWM3_PERI:
+ mask = CLK_PWM3_PERI_SEL_MASK;
+ shift = CLK_PWM3_PERI_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->periclksel_con[40]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_PWM_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_PWM_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3562_pwm_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_PMU1_PWM0:
+ if (rate == 200 * MHz) {
+ sel = CLK_PMU1_PWM0_SEL_200M;
+ div = 1;
+ } else if (rate == OSC_HZ) {
+ sel = CLK_PMU1_PWM0_SEL_24M;
+ div = 1;
+ } else if (rate == 32768) {
+ sel = CLK_PMU1_PWM0_SEL_32K;
+ div = 1;
+ } else {
+ sel = CLK_PMU1_PWM0_SEL_200M;
+ div = DIV_ROUND_UP(200 * MHz, rate);
+ assert(div - 1 <= 3);
+ }
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_DIV_MASK,
+ (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT);
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_SEL_MASK,
+ sel << CLK_PMU1_PWM0_SEL_SHIFT);
+
+ return rk3562_pwm_get_rate(priv, clk_id);
+ case CLK_PWM1_PERI:
+ mask = CLK_PWM1_PERI_SEL_MASK;
+ shift = CLK_PWM1_PERI_SEL_SHIFT;
+ break;
+ case CLK_PWM2_PERI:
+ mask = CLK_PWM2_PERI_SEL_MASK;
+ shift = CLK_PWM2_PERI_SEL_SHIFT;
+ break;
+ case CLK_PWM3_PERI:
+ mask = CLK_PWM3_PERI_SEL_MASK;
+ shift = CLK_PWM3_PERI_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (rate == 100 * MHz)
+ sel = CLK_PWM_SEL_100M;
+ else if (rate == 50 * MHz)
+ sel = CLK_PWM_SEL_50M;
+ else
+ sel = CLK_PWM_SEL_24M;
+ rk_clrsetreg(&cru->periclksel_con[40], mask, sel << shift);
+
+ return rk3562_pwm_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_spi_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con, div, mask, shift;
+ ulong rate;
+
+ switch (clk_id) {
+ case CLK_PMU1_SPI0:
+ con = readl(&cru->pmu1clksel_con[4]);
+ sel = (con & CLK_PMU1_SPI0_SEL_MASK) >> CLK_PMU1_SPI0_SEL_SHIFT;
+ if (sel == CLK_PMU1_SPI0_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_PMU1_SPI0_SEL_24M)
+ rate = OSC_HZ;
+ else
+ rate = 32768;
+ div = (con & CLK_PMU1_SPI0_DIV_MASK) >> CLK_PMU1_SPI0_DIV_SHIFT;
+
+ return DIV_TO_RATE(rate, div);
+ case CLK_SPI1:
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ case CLK_SPI2:
+ mask = CLK_SPI2_SEL_MASK;
+ shift = CLK_SPI2_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ con = readl(&cru->periclksel_con[20]);
+ sel = (con & mask) >> shift;
+ if (sel == CLK_SPI_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_SPI_SEL_100M)
+ rate = 100 * MHz;
+ else if (sel == CLK_SPI_SEL_50M)
+ rate = 50 * MHz;
+ else
+ rate = OSC_HZ;
+
+ return rate;
+}
+
+static ulong rk3562_spi_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_PMU1_SPI0:
+ if (rate == 200 * MHz) {
+ sel = CLK_PMU1_SPI0_SEL_200M;
+ div = 1;
+ } else if (rate == OSC_HZ) {
+ sel = CLK_PMU1_SPI0_SEL_24M;
+ div = 1;
+ } else if (rate == 32768) {
+ sel = CLK_PMU1_SPI0_SEL_32K;
+ div = 1;
+ } else {
+ sel = CLK_PMU1_SPI0_SEL_200M;
+ div = DIV_ROUND_UP(200 * MHz, rate);
+ assert(div - 1 <= 3);
+ }
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_DIV_MASK,
+ (div - 1) << CLK_PMU1_SPI0_DIV_SHIFT);
+ rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_SPI0_SEL_MASK,
+ sel << CLK_PMU1_SPI0_SEL_SHIFT);
+
+ return rk3562_spi_get_rate(priv, clk_id);
+ case CLK_SPI1:
+ mask = CLK_SPI1_SEL_MASK;
+ shift = CLK_SPI1_SEL_SHIFT;
+ break;
+ case CLK_SPI2:
+ mask = CLK_SPI2_SEL_MASK;
+ shift = CLK_SPI2_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (rate == 200 * MHz)
+ sel = CLK_SPI_SEL_200M;
+ else if (rate == 100 * MHz)
+ sel = CLK_SPI_SEL_100M;
+ else if (rate == 50 * MHz)
+ sel = CLK_SPI_SEL_50M;
+ else
+ sel = CLK_SPI_SEL_24M;
+ rk_clrsetreg(&cru->periclksel_con[20], mask, sel << shift);
+
+ return rk3562_spi_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_tsadc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, con;
+
+ con = readl(&cru->clksel_con[43]);
+ switch (clk_id) {
+ case CLK_TSADC_TSEN:
+ div = (con & CLK_TSADC_TSEN_DIV_MASK) >>
+ CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+ case CLK_TSADC:
+ div = (con & CLK_TSADC_DIV_MASK) >> CLK_TSADC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3562_tsadc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, mask, shift;
+
+ switch (clk_id) {
+ case CLK_TSADC_TSEN:
+ mask = CLK_TSADC_TSEN_DIV_MASK;
+ shift = CLK_TSADC_TSEN_DIV_SHIFT;
+ break;
+ case CLK_TSADC:
+ mask = CLK_TSADC_DIV_MASK;
+ shift = CLK_TSADC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[43], mask, (div - 1) << shift);
+
+ return rk3562_tsadc_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_saradc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, con;
+
+ switch (clk_id) {
+ case CLK_SARADC_VCCIO156:
+ con = readl(&cru->clksel_con[44]);
+ div = (con & CLK_SARADC_VCCIO156_DIV_MASK) >>
+ CLK_SARADC_VCCIO156_DIV_SHIFT;
+ break;
+ case CLK_SARADC:
+ con = readl(&cru->periclksel_con[46]);
+ div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(OSC_HZ, div);
+}
+
+static ulong rk3562_saradc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div;
+
+ switch (clk_id) {
+ case CLK_SARADC_VCCIO156:
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->clksel_con[44], CLK_SARADC_VCCIO156_DIV_MASK,
+ (div - 1) << CLK_SARADC_VCCIO156_DIV_SHIFT);
+ break;
+ case CLK_SARADC:
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ rk_clrsetreg(&cru->periclksel_con[46], CLK_SARADC_DIV_MASK,
+ (div - 1) << CLK_SARADC_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_saradc_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_sfc_get_rate(struct rk3562_clk_priv *priv)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ con = readl(&cru->periclksel_con[20]);
+ div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT;
+ sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT;
+ if (sel == SCLK_SFC_SRC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == SCLK_SFC_SRC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else
+ parent = OSC_HZ;
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3562_sfc_set_rate(struct rk3562_clk_priv *priv, ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ int div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = SCLK_SFC_SRC_SEL_24M;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = SCLK_SFC_SRC_SEL_CPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = SCLK_SFC_SRC_SEL_GPLL;
+ }
+
+ assert(div - 1 <= 255);
+ rk_clrsetreg(&cru->periclksel_con[20],
+ SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK,
+ sel << SCLK_SFC_SEL_SHIFT |
+ (div - 1) << SCLK_SFC_DIV_SHIFT);
+
+ return rk3562_sfc_get_rate(priv);
+}
+
+static ulong rk3562_emmc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, sel, con, parent;
+
+ switch (clk_id) {
+ case CCLK_EMMC:
+ con = readl(&cru->periclksel_con[18]);
+ div = (con & CCLK_EMMC_DIV_MASK) >> CCLK_EMMC_DIV_SHIFT;
+ sel = (con & CCLK_EMMC_SEL_MASK) >> CCLK_EMMC_SEL_SHIFT;
+ if (sel == CCLK_EMMC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else if (sel == CCLK_EMMC_SEL_CPLL)
+ parent = priv->cpll_hz;
+ else if (sel == CCLK_EMMC_SEL_HPLL)
+ parent = priv->hpll_hz;
+ else
+ parent = OSC_HZ;
+ break;
+ case BCLK_EMMC:
+ con = readl(&cru->periclksel_con[19]);
+ div = (con & BCLK_EMMC_DIV_MASK) >> BCLK_EMMC_DIV_SHIFT;
+ sel = (con & BCLK_EMMC_SEL_MASK) >> BCLK_EMMC_SEL_SHIFT;
+ if (sel == BCLK_EMMC_SEL_GPLL)
+ parent = priv->gpll_hz;
+ else
+ parent = priv->cpll_hz;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
+static ulong rk3562_emmc_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ int div, sel;
+
+ switch (clk_id) {
+ case CCLK_EMMC:
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_EMMC_SEL_24M;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_EMMC_SEL_CPLL;
+ } else if ((priv->hpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
+ sel = CCLK_EMMC_SEL_HPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_EMMC_SEL_GPLL;
+ }
+ rk_clrsetreg(&cru->periclksel_con[18],
+ CCLK_EMMC_SEL_MASK | CCLK_EMMC_DIV_MASK,
+ sel << CCLK_EMMC_SEL_SHIFT |
+ (div - 1) << CCLK_EMMC_DIV_SHIFT);
+ break;
+ case BCLK_EMMC:
+ if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = BCLK_EMMC_SEL_CPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = BCLK_EMMC_SEL_GPLL;
+ }
+ rk_clrsetreg(&cru->periclksel_con[19],
+ BCLK_EMMC_SEL_MASK | BCLK_EMMC_DIV_MASK,
+ sel << BCLK_EMMC_SEL_SHIFT |
+ (div - 1) << BCLK_EMMC_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_emmc_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_sdmmc_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, sel, con;
+ ulong prate;
+
+ switch (clk_id) {
+ case HCLK_SDMMC0:
+ case CCLK_SDMMC0:
+ case SCLK_SDMMC0_SAMPLE:
+ con = readl(&cru->periclksel_con[16]);
+ div = (con & CCLK_SDMMC0_DIV_MASK) >> CCLK_SDMMC0_DIV_SHIFT;
+ sel = (con & CCLK_SDMMC0_SEL_MASK) >> CCLK_SDMMC0_SEL_SHIFT;
+ break;
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC1:
+ case SCLK_SDMMC1_SAMPLE:
+ con = readl(&cru->periclksel_con[17]);
+ div = (con & CCLK_SDMMC1_DIV_MASK) >> CCLK_SDMMC1_DIV_SHIFT;
+ sel = (con & CCLK_SDMMC1_SEL_MASK) >> CCLK_SDMMC1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == CCLK_SDMMC_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == CCLK_SDMMC_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else if (sel == CCLK_SDMMC_SEL_HPLL)
+ prate = priv->hpll_hz;
+ else
+ prate = OSC_HZ;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3562_sdmmc_set_rate(struct rk3562_clk_priv *priv,
+ ulong clk_id, ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 div, sel;
+
+ if (OSC_HZ % rate == 0) {
+ div = DIV_ROUND_UP(OSC_HZ, rate);
+ sel = CCLK_SDMMC_SEL_24M;
+ } else if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CCLK_SDMMC_SEL_CPLL;
+ } else if ((priv->hpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
+ sel = CCLK_SDMMC_SEL_HPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CCLK_SDMMC_SEL_CPLL;
+ }
+
+ switch (clk_id) {
+ case HCLK_SDMMC0:
+ case CCLK_SDMMC0:
+ rk_clrsetreg(&cru->periclksel_con[16],
+ CCLK_SDMMC0_SEL_MASK | CCLK_SDMMC0_DIV_MASK,
+ sel << CCLK_SDMMC0_SEL_SHIFT |
+ (div - 1) << CCLK_SDMMC0_DIV_SHIFT);
+ break;
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC1:
+ rk_clrsetreg(&cru->periclksel_con[17],
+ CCLK_SDMMC1_SEL_MASK | CCLK_SDMMC1_DIV_MASK,
+ sel << CCLK_SDMMC1_SEL_SHIFT |
+ (div - 1) << CCLK_SDMMC1_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_sdmmc_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_vop_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 con, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case ACLK_VOP:
+ con = readl(&cru->clksel_con[28]);
+ div = (con & ACLK_VOP_DIV_MASK) >> ACLK_VOP_DIV_SHIFT;
+ sel = (con & ACLK_VOP_SEL_MASK) >> ACLK_VOP_SEL_SHIFT;
+ if (sel == ACLK_VOP_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == ACLK_VOP_SEL_CPLL)
+ prate = priv->cpll_hz;
+ else if (sel == ACLK_VOP_SEL_HPLL)
+ prate = priv->hpll_hz;
+ else if (sel == ACLK_VOP_SEL_VPLL)
+ prate = priv->vpll_hz;
+ else
+ return -ENOENT;
+
+ return DIV_TO_RATE(prate, div);
+ case DCLK_VOP:
+ con = readl(&cru->clksel_con[30]);
+ div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT;
+ sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT;
+ if (sel == DCLK_VOP_SEL_VPLL)
+ priv->vpll_hz =
+ rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],
+ priv->cru, VPLL);
+ break;
+ case DCLK_VOP1:
+ con = readl(&cru->clksel_con[31]);
+ div = (con & DCLK_VOP1_DIV_MASK) >> DCLK_VOP1_DIV_SHIFT;
+ sel = (con & DCLK_VOP1_SEL_MASK) >> DCLK_VOP1_SEL_SHIFT;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ if (sel == DCLK_VOP_SEL_GPLL)
+ prate = priv->gpll_hz;
+ else if (sel == DCLK_VOP_SEL_HPLL)
+ prate = priv->hpll_hz;
+ else if (sel == DCLK_VOP_SEL_VPLL)
+ prate = priv->vpll_hz;
+ else
+ return -ENOENT;
+
+ return DIV_TO_RATE(prate, div);
+}
+
+#define RK3562_VOP_PLL_LIMIT_FREQ 600000000
+
+static ulong rk3562_vop_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 i, div, sel, best_div = 0, best_sel = 0;
+ ulong pll_rate, now, best_rate = 0;
+
+ switch (clk_id) {
+ case ACLK_VOP:
+ if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = ACLK_VOP_SEL_CPLL;
+ } else if ((priv->hpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->hpll_hz, rate);
+ sel = ACLK_VOP_SEL_HPLL;
+ } else if ((priv->vpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->vpll_hz, rate);
+ sel = ACLK_VOP_SEL_VPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = ACLK_VOP_SEL_GPLL;
+ }
+ rk_clrsetreg(&cru->clksel_con[28],
+ ACLK_VOP_SEL_MASK | ACLK_VOP_DIV_MASK,
+ sel << ACLK_VOP_SEL_SHIFT |
+ ((div - 1) << ACLK_VOP_DIV_SHIFT));
+
+ return rk3562_vop_get_rate(priv, clk_id);
+ case DCLK_VOP:
+ div = DIV_ROUND_UP(RK3562_VOP_PLL_LIMIT_FREQ, rate);
+ rk_clrsetreg(&cru->clksel_con[30],
+ DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK,
+ DCLK_VOP_SEL_VPLL << DCLK_VOP_SEL_SHIFT |
+ ((div - 1) << DCLK_VOP_DIV_SHIFT));
+ rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,
+ VPLL, div * rate);
+ break;
+ case DCLK_VOP1:
+ for (i = 0; i <= DCLK_VOP_SEL_APLL; i++) {
+ switch (i) {
+ case DCLK_VOP_SEL_GPLL:
+ pll_rate = priv->gpll_hz;
+ break;
+ case DCLK_VOP_SEL_HPLL:
+ pll_rate = priv->hpll_hz;
+ break;
+ case DCLK_VOP_SEL_VPLL:
+ case DCLK_VOP_SEL_APLL:
+ continue;
+ default:
+ printf("do not support this vop pll sel\n");
+ return -EINVAL;
+ }
+
+ div = DIV_ROUND_UP(pll_rate, rate);
+ if (div > 255)
+ continue;
+ now = pll_rate / div;
+ if (abs(rate - now) < abs(rate - best_rate)) {
+ best_rate = now;
+ best_div = div;
+ best_sel = i;
+ }
+ debug("p_rate=%lu, best_rate=%lu, div=%u, sel=%u\n",
+ pll_rate, best_rate, best_div, best_sel);
+ }
+ if (best_rate) {
+ rk_clrsetreg(&cru->clksel_con[31],
+ DCLK_VOP1_SEL_MASK | DCLK_VOP1_DIV_MASK,
+ best_sel << DCLK_VOP1_SEL_SHIFT |
+ (best_div - 1) << DCLK_VOP1_DIV_SHIFT);
+ } else {
+ printf("do not support this vop freq %lu\n", rate);
+ return -EINVAL;
+ }
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_vop_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_gmac_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 con, sel, div;
+ ulong prate;
+
+ switch (clk_id) {
+ case CLK_GMAC_125M_CRU_I:
+ con = readl(&cru->clksel_con[45]);
+ sel = (con & CLK_GMAC_125M_SEL_MASK) >> CLK_GMAC_125M_SEL_SHIFT;
+ if (sel == CLK_GMAC_125M)
+ return 125000000;
+ else
+ return OSC_HZ;
+ case CLK_GMAC_50M_CRU_I:
+ con = readl(&cru->clksel_con[45]);
+ sel = (con & CLK_GMAC_50M_SEL_MASK) >> CLK_GMAC_50M_SEL_SHIFT;
+ if (sel == CLK_GMAC_50M)
+ return 50000000;
+ else
+ return OSC_HZ;
+ case CLK_MAC100_50M_MATRIX:
+ con = readl(&cru->clksel_con[47]);
+ sel = (con & CLK_GMAC_50M_SEL_MASK) >> CLK_GMAC_50M_SEL_SHIFT;
+ if (sel == CLK_GMAC_50M)
+ return 50000000;
+ else
+ return OSC_HZ;
+ case CLK_GMAC_ETH_OUT2IO:
+ con = readl(&cru->clksel_con[46]);
+ sel = (con & CLK_GMAC_ETH_OUT2IO_SEL_MASK) >> CLK_GMAC_ETH_OUT2IO_SEL_SHIFT;
+ div = (con & CLK_GMAC_ETH_OUT2IO_DIV_MASK) >> CLK_GMAC_ETH_OUT2IO_DIV_SHIFT;
+ if (sel == CLK_GMAC_ETH_OUT2IO_GPLL)
+ prate = priv->gpll_hz;
+ else
+ prate = priv->cpll_hz;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return DIV_TO_RATE(prate, div);
+}
+
+static ulong rk3562_gmac_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, div;
+
+ switch (clk_id) {
+ case CLK_GMAC_125M_CRU_I:
+ if (rate == 125000000)
+ sel = CLK_GMAC_125M;
+ else
+ sel = CLK_GMAC_24M;
+ rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_125M_SEL_MASK,
+ sel << CLK_GMAC_125M_SEL_SHIFT);
+ break;
+ case CLK_GMAC_50M_CRU_I:
+ if (rate == 50000000)
+ sel = CLK_GMAC_50M;
+ else
+ sel = CLK_GMAC_24M;
+ rk_clrsetreg(&cru->clksel_con[45], CLK_GMAC_50M_SEL_MASK,
+ sel << CLK_GMAC_50M_SEL_SHIFT);
+ break;
+ case CLK_MAC100_50M_MATRIX:
+ if (rate == 50000000)
+ sel = CLK_GMAC_50M;
+ else
+ sel = CLK_GMAC_24M;
+ rk_clrsetreg(&cru->clksel_con[47], CLK_GMAC_50M_SEL_MASK,
+ sel << CLK_GMAC_50M_SEL_SHIFT);
+ break;
+ case CLK_GMAC_ETH_OUT2IO:
+ if ((priv->cpll_hz % rate) == 0) {
+ div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ sel = CLK_GMAC_ETH_OUT2IO_CPLL;
+ } else {
+ div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ sel = CLK_GMAC_ETH_OUT2IO_GPLL;
+ }
+ rk_clrsetreg(&cru->clksel_con[46],
+ CLK_GMAC_ETH_OUT2IO_SEL_MASK | CLK_GMAC_ETH_OUT2IO_DIV_MASK,
+ sel << CLK_GMAC_ETH_OUT2IO_SEL_SHIFT |
+ (div - 1) << CLK_GMAC_ETH_OUT2IO_DIV_SHIFT);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rk3562_gmac_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_clk_get_rate(struct clk *clk)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong rate = 0;
+
+ if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) {
+ printf("%s: gpll=%lu, cpll=%lu, hpll=%lu\n",
+ __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz);
+ return -ENOENT;
+ }
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[APLL], priv->cru,
+ APLL);
+ break;
+ case PLL_GPLL:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL], priv->cru,
+ GPLL);
+ break;
+
+ case PLL_VPLL:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL], priv->cru,
+ VPLL);
+ break;
+ case PLL_HPLL:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL], priv->cru,
+ HPLL);
+ break;
+ case PLL_CPLL:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[CPLL], priv->cru,
+ CPLL);
+ break;
+ case PLL_DPLL:
+ rate = rockchip_pll_get_rate(&rk3562_pll_clks[DPLL], priv->cru,
+ DPLL);
+ break;
+ case ACLK_BUS:
+ case HCLK_BUS:
+ case PCLK_BUS:
+ rate = rk3562_bus_get_rate(priv, clk->id);
+ break;
+ case ACLK_PERI:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ rate = rk3562_peri_get_rate(priv, clk->id);
+ break;
+ case CLK_PMU0_I2C0:
+ case CLK_I2C:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ rate = rk3562_i2c_get_rate(priv, clk->id);
+ break;
+ case SCLK_PMU1_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ rate = rk3562_uart_get_rate(priv, clk->id);
+ break;
+ case CLK_PMU1_PWM0:
+ case CLK_PWM1_PERI:
+ case CLK_PWM2_PERI:
+ case CLK_PWM3_PERI:
+ rate = rk3562_pwm_get_rate(priv, clk->id);
+ break;
+ case CLK_PMU1_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ rate = rk3562_spi_get_rate(priv, clk->id);
+ break;
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ rate = rk3562_tsadc_get_rate(priv, clk->id);
+ break;
+ case CLK_SARADC:
+ case CLK_SARADC_VCCIO156:
+ rate = rk3562_saradc_get_rate(priv, clk->id);
+ break;
+ case SCLK_SFC:
+ rate = rk3562_sfc_get_rate(priv);
+ break;
+ case CCLK_EMMC:
+ case BCLK_EMMC:
+ rate = rk3562_emmc_get_rate(priv, clk->id);
+ break;
+ case HCLK_SDMMC0:
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC0:
+ case CCLK_SDMMC1:
+ case SCLK_SDMMC0_SAMPLE:
+ case SCLK_SDMMC1_SAMPLE:
+ rate = rk3562_sdmmc_get_rate(priv, clk->id);
+ break;
+ case ACLK_VOP:
+ case DCLK_VOP:
+ case DCLK_VOP1:
+ rate = rk3562_vop_get_rate(priv, clk->id);
+ break;
+ case CLK_GMAC_125M_CRU_I:
+ case CLK_GMAC_50M_CRU_I:
+ case CLK_GMAC_ETH_OUT2IO:
+ case CLK_MAC100_50M_MATRIX:
+ rate = rk3562_gmac_get_rate(priv, clk->id);
+ break;
+ case CLK_WDTNS:
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+};
+
+static ulong rk3562_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+ ulong ret = 0;
+
+ if (!priv->gpll_hz || !priv->cpll_hz || !priv->hpll_hz) {
+ printf("%s: gpll=%lu, cpll=%lu, hpll=%lu\n",
+ __func__, priv->gpll_hz, priv->cpll_hz, priv->hpll_hz);
+ return -ENOENT;
+ }
+
+ debug("%s: id=%ld, rate=%ld\n", __func__, clk->id, rate);
+
+ switch (clk->id) {
+ case PLL_APLL:
+ case ARMCLK:
+ if (priv->armclk_hz)
+ rk3562_armclk_set_rate(priv, rate);
+ priv->armclk_hz = rate;
+ break;
+ case PLL_GPLL:
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru,
+ GPLL, rate);
+ priv->gpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[GPLL],
+ priv->cru, GPLL);
+ break;
+ case PLL_VPLL:
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[VPLL], priv->cru,
+ VPLL, rate);
+ priv->vpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[VPLL],
+ priv->cru, VPLL);
+ break;
+ case PLL_HPLL:
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru,
+ HPLL, rate);
+ priv->hpll_hz = rockchip_pll_get_rate(&rk3562_pll_clks[HPLL],
+ priv->cru, HPLL);
+ break;
+ case ACLK_BUS:
+ case HCLK_BUS:
+ case PCLK_BUS:
+ ret = rk3562_bus_set_rate(priv, clk->id, rate);
+ break;
+ case ACLK_PERI:
+ case HCLK_PERI:
+ case PCLK_PERI:
+ ret = rk3562_peri_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PMU0_I2C0:
+ case CLK_I2C:
+ case CLK_I2C1:
+ case CLK_I2C2:
+ case CLK_I2C3:
+ case CLK_I2C4:
+ case CLK_I2C5:
+ ret = rk3562_i2c_set_rate(priv, clk->id, rate);
+ break;
+ case SCLK_PMU1_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ case SCLK_UART5:
+ case SCLK_UART6:
+ case SCLK_UART7:
+ case SCLK_UART8:
+ case SCLK_UART9:
+ ret = rk3562_uart_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PMU1_PWM0:
+ case CLK_PWM1_PERI:
+ case CLK_PWM2_PERI:
+ case CLK_PWM3_PERI:
+ ret = rk3562_pwm_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_PMU1_SPI0:
+ case CLK_SPI1:
+ case CLK_SPI2:
+ ret = rk3562_spi_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_TSADC:
+ case CLK_TSADC_TSEN:
+ ret = rk3562_tsadc_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_SARADC:
+ case CLK_SARADC_VCCIO156:
+ ret = rk3562_saradc_set_rate(priv, clk->id, rate);
+ break;
+ case SCLK_SFC:
+ ret = rk3562_sfc_set_rate(priv, rate);
+ break;
+ case CCLK_EMMC:
+ case BCLK_EMMC:
+ ret = rk3562_emmc_set_rate(priv, clk->id, rate);
+ break;
+ case HCLK_SDMMC0:
+ case HCLK_SDMMC1:
+ case CCLK_SDMMC0:
+ case CCLK_SDMMC1:
+ ret = rk3562_sdmmc_set_rate(priv, clk->id, rate);
+ break;
+ case ACLK_VOP:
+ case DCLK_VOP:
+ case DCLK_VOP1:
+ ret = rk3562_vop_set_rate(priv, clk->id, rate);
+ break;
+ case CLK_GMAC_125M_CRU_I:
+ case CLK_GMAC_50M_CRU_I:
+ case CLK_GMAC_ETH_OUT2IO:
+ case CLK_MAC100_50M_MATRIX:
+ ret = rk3562_gmac_set_rate(priv, clk->id, rate);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+};
+
+#define ROCKCHIP_MMC_DELAY_SEL BIT(11)
+#define ROCKCHIP_MMC_DEGREE_SHIFT 1
+#define ROCKCHIP_MMC_DEGREE_MASK (0x3 << ROCKCHIP_MMC_DEGREE_SHIFT)
+#define ROCKCHIP_MMC_DELAYNUM_SHIFT 3
+#define ROCKCHIP_MMC_DELAYNUM_MASK (0xff << ROCKCHIP_MMC_DELAYNUM_SHIFT)
+#define PSECS_PER_SEC 1000000000000LL
+
+/*
+ * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
+ * simplify calculations. So 45degs could be anywhere between 33deg and 57.8deg.
+ */
+#define ROCKCHIP_MMC_DELAY_ELEMENT_PSEC 60
+
+int rk3562_mmc_get_phase(struct clk *clk)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3562_cru *cru = priv->cru;
+ u32 raw_value, delay_num;
+ u16 degrees = 0;
+ ulong rate;
+
+ rate = rk3562_clk_get_rate(clk);
+ if (rate < 0)
+ return rate;
+
+ if (clk->id == SCLK_SDMMC0_SAMPLE)
+ raw_value = readl(&cru->sdmmc0_con[1]);
+ else if (clk->id == SCLK_SDMMC0_SAMPLE)
+ raw_value = readl(&cru->sdmmc1_con[1]);
+ else
+ return -ENONET;
+
+ raw_value &= ROCKCHIP_MMC_DEGREE_MASK;
+ degrees = (raw_value >> ROCKCHIP_MMC_DEGREE_SHIFT) * 90;
+
+ if (raw_value & ROCKCHIP_MMC_DELAY_SEL) {
+ /* degrees/delaynum * 10000 */
+ unsigned long factor = (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10) *
+ 36 * (rate / 1000000);
+
+ delay_num = (raw_value & ROCKCHIP_MMC_DELAYNUM_MASK);
+ delay_num >>= ROCKCHIP_MMC_DELAYNUM_SHIFT;
+ degrees += DIV_ROUND_CLOSEST(delay_num * factor, 10000);
+ }
+
+ return degrees % 360;
+}
+
+int rk3562_mmc_set_phase(struct clk *clk, u32 degrees)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3562_cru *cru = priv->cru;
+ u8 nineties, remainder, delay_num;
+ u32 raw_value, delay;
+ ulong rate;
+
+ rate = rk3562_clk_get_rate(clk);
+ if (rate < 0)
+ return rate;
+
+ nineties = degrees / 90;
+ remainder = (degrees % 90);
+
+ /*
+ * Convert to delay; do a little extra work to make sure we
+ * don't overflow 32-bit / 64-bit numbers.
+ */
+ delay = 10000000; /* PSECS_PER_SEC / 10000 / 10 */
+ delay *= remainder;
+ delay = DIV_ROUND_CLOSEST(delay, (rate / 1000) * 36 *
+ (ROCKCHIP_MMC_DELAY_ELEMENT_PSEC / 10));
+
+ delay_num = (u8)min_t(u32, delay, 255);
+
+ raw_value = delay_num ? ROCKCHIP_MMC_DELAY_SEL : 0;
+ raw_value |= delay_num << ROCKCHIP_MMC_DELAYNUM_SHIFT;
+ raw_value |= nineties << ROCKCHIP_MMC_DEGREE_SHIFT;
+
+ if (clk->id == SCLK_SDMMC0_SAMPLE)
+ writel(raw_value | 0xffff0000, &cru->sdmmc0_con[1]);
+ else
+ writel(raw_value | 0xffff0000, &cru->sdmmc1_con[1]);
+
+ debug("mmc set_phase(%d) delay_nums=%u reg=%#x actual_degrees=%d\n",
+ degrees, delay_num, raw_value, rk3562_mmc_get_phase(clk));
+
+ return 0;
+}
+
+static int rk3562_clk_get_phase(struct clk *clk)
+{
+ int ret;
+
+ switch (clk->id) {
+ case SCLK_SDMMC0_SAMPLE:
+ case SCLK_SDMMC1_SAMPLE:
+ ret = rk3562_mmc_get_phase(clk);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static int rk3562_clk_set_phase(struct clk *clk, int degrees)
+{
+ int ret;
+
+ switch (clk->id) {
+ case SCLK_SDMMC0_SAMPLE:
+ case SCLK_SDMMC1_SAMPLE:
+ ret = rk3562_mmc_set_phase(clk, degrees);
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return ret;
+}
+
+static struct clk_ops rk3562_clk_ops = {
+ .get_rate = rk3562_clk_get_rate,
+ .set_rate = rk3562_clk_set_rate,
+ .get_phase = rk3562_clk_get_phase,
+ .set_phase = rk3562_clk_set_phase,
+};
+
+#ifndef CONFIG_SPL_BUILD
+/**
+ * soc_clk_dump() - Print clock frequencies
+ * Returns zero on success
+ *
+ * Implementation for the clk dump command.
+ */
+int soc_clk_dump(void)
+{
+ const struct rk3562_clk_info *clk_dump;
+ struct rk3562_clk_priv *priv;
+ struct udevice *cru_dev;
+ struct clk clk;
+ ulong clk_count = ARRAY_SIZE(clks_dump);
+ ulong rate;
+ int i, ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_GET_DRIVER(rockchip_rk3562_cru),
+ &cru_dev);
+ if (ret) {
+ printf("%s failed to get cru device\n", __func__);
+ return ret;
+ }
+
+ priv = dev_get_priv(cru_dev);
+ printf("CLK: (%s. arm: enter %lu KHz, init %lu KHz, kernel %lu%s)\n",
+ priv->sync_kernel ? "sync kernel" : "uboot",
+ priv->armclk_enter_hz / 1000,
+ priv->armclk_init_hz / 1000,
+ priv->set_armclk_rate ? priv->armclk_hz / 1000 : 0,
+ priv->set_armclk_rate ? " KHz" : "N/A");
+ for (i = 0; i < clk_count; i++) {
+ clk_dump = &clks_dump[i];
+ if (clk_dump->name) {
+ clk.id = clk_dump->id;
+ ret = clk_request(cru_dev, &clk);
+ if (ret < 0)
+ return ret;
+
+ rate = clk_get_rate(&clk);
+ clk_free(&clk);
+ if (i == 0) {
+ if (rate < 0)
+ printf(" %s %s\n", clk_dump->name,
+ "unknown");
+ else
+ printf(" %s %lu KHz\n", clk_dump->name,
+ rate / 1000);
+ } else {
+ if (rate < 0)
+ printf(" %s %s\n", clk_dump->name,
+ "unknown");
+ else
+ printf(" %s %lu KHz\n", clk_dump->name,
+ rate / 1000);
+ }
+ }
+ }
+
+ return 0;
+}
+#endif
+
+static void rk3562_clk_init(struct rk3562_clk_priv *priv)
+{
+ int ret;
+
+ priv->sync_kernel = false;
+ if (!priv->armclk_enter_hz)
+ priv->armclk_enter_hz =
+ rockchip_pll_get_rate(&rk3562_pll_clks[APLL],
+ priv->cru, APLL);
+
+ if (!priv->armclk_init_hz) {
+#ifdef CONFIG_SPL_BUILD
+ ret = rk3562_armclk_set_rate(priv, APLL_HZ);
+ if (!ret)
+ priv->armclk_init_hz = APLL_HZ;
+
+#else
+ struct clk clk;
+
+ ret = rockchip_get_scmi_clk(&clk.dev);
+ if (ret) {
+ printf("Failed to get scmi clk dev\n");
+ return;
+ }
+
+ clk.id = ARMCLK;
+ ret = clk_set_rate(&clk, CPU_PVTPLL_HZ);
+ if (ret < 0) {
+ printf("Failed to set scmi cpu %dhz\n", CPU_PVTPLL_HZ);
+ return;
+ } else {
+ priv->armclk_init_hz = CPU_PVTPLL_HZ;
+ }
+#endif
+ }
+ if (priv->cpll_hz != CPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[CPLL], priv->cru,
+ CPLL, CPLL_HZ);
+ if (!ret)
+ priv->cpll_hz = CPLL_HZ;
+ }
+
+ if (priv->gpll_hz != GPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[GPLL], priv->cru,
+ GPLL, GPLL_HZ);
+ if (!ret)
+ priv->gpll_hz = GPLL_HZ;
+ }
+
+ if (priv->hpll_hz != HPLL_HZ) {
+ ret = rockchip_pll_set_rate(&rk3562_pll_clks[HPLL], priv->cru,
+ HPLL, HPLL_HZ);
+ if (!ret)
+ priv->hpll_hz = HPLL_HZ;
+ }
+}
+
+static int rk3562_clk_probe(struct udevice *dev)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ rk3562_clk_init(priv);
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev);
+ if (ret)
+ debug("%s clk_set_defaults failed %d\n", __func__, ret);
+ else
+ priv->sync_kernel = true;
+
+ return 0;
+}
+
+static int rk3562_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = dev_read_addr_ptr(dev);
+
+ return 0;
+}
+
+static int rk3562_clk_bind(struct udevice *dev)
+{
+ struct udevice *sys_child, *sf_child;
+ struct softreset_reg *sf_priv;
+ struct sysreset_reg *priv;
+ int ret;
+
+ /* The reset driver does not have a device node, so bind it here */
+ ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
+ &sys_child);
+ if (ret) {
+ debug("Warning: No sysreset driver: ret=%d\n", ret);
+ } else {
+ priv = malloc(sizeof(struct sysreset_reg));
+ priv->glb_srst_fst_value = offsetof(struct rk3562_cru,
+ glb_srst_fst);
+ priv->glb_srst_snd_value = offsetof(struct rk3562_cru,
+ glb_srst_snd);
+ sys_child->priv = priv;
+ }
+
+ ret = device_bind_driver_to_node(dev, "rockchip_reset", "reset",
+ dev_ofnode(dev), &sf_child);
+ if (ret) {
+ debug("Warning: No rockchip reset driver: ret=%d\n", ret);
+ } else {
+ sf_priv = malloc(sizeof(struct softreset_reg));
+ sf_priv->sf_reset_offset = offsetof(struct rk3562_cru,
+ softrst_con[0]);
+ /* (0x30444 - 0x400) / 4 + 1 = 49170 */
+ sf_priv->sf_reset_num = 49170;
+ sf_child->priv = sf_priv;
+ }
+
+ return 0;
+}
+
+static const struct udevice_id rk3562_clk_ids[] = {
+ { .compatible = "rockchip,rk3562-cru" },
+ { }
+};
+
+U_BOOT_DRIVER(rockchip_rk3562_cru) = {
+ .name = "rockchip_rk3562_cru",
+ .id = UCLASS_CLK,
+ .of_match = rk3562_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct rk3562_clk_priv),
+ .ofdata_to_platdata = rk3562_clk_ofdata_to_platdata,
+ .ops = &rk3562_clk_ops,
+ .bind = rk3562_clk_bind,
+ .probe = rk3562_clk_probe,
+};
+
+/* spl scmi clk */
+#ifdef CONFIG_SPL_BUILD
+
+static ulong rk3562_crypto_get_rate(struct rk3562_clk_priv *priv, ulong clk_id)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 sel, con;
+ ulong rate;
+
+ con = readl(&cru->periclksel_con[43]);
+ switch (clk_id) {
+ case CLK_CORE_CRYPTO:
+ sel = (con & CLK_CORE_CRYPTO_SEL_MASK) >>
+ CLK_CORE_CRYPTO_SEL_SHIFT;
+ if (sel == CLK_CORE_CRYPTO_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_CORE_CRYPTO_SEL_100M)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ case CLK_PKA_CRYPTO:
+ sel = (con & CLK_PKA_CRYPTO_SEL_MASK) >>
+ CLK_PKA_CRYPTO_SEL_SHIFT;
+ if (sel == CLK_PKA_CRYPTO_SEL_300M)
+ rate = 300 * MHz;
+ else if (sel == CLK_PKA_CRYPTO_SEL_200M)
+ rate = 200 * MHz;
+ else if (sel == CLK_PKA_CRYPTO_SEL_100M)
+ rate = 100 * MHz;
+ else
+ rate = OSC_HZ;
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ return rate;
+}
+
+static ulong rk3562_crypto_set_rate(struct rk3562_clk_priv *priv, ulong clk_id,
+ ulong rate)
+{
+ struct rk3562_cru *cru = priv->cru;
+ u32 mask, shift, sel;
+
+ switch (clk_id) {
+ case CLK_CORE_CRYPTO:
+ mask = CLK_CORE_CRYPTO_SEL_MASK;
+ shift = CLK_CORE_CRYPTO_SEL_SHIFT;
+ if (rate == 200 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_200M;
+ else if (rate == 100 * MHz)
+ sel = CLK_CORE_CRYPTO_SEL_100M;
+ else
+ sel = CLK_CORE_CRYPTO_SEL_24M;
+ break;
+ case CLK_PKA_CRYPTO:
+ mask = CLK_PKA_CRYPTO_SEL_MASK;
+ shift = CLK_PKA_CRYPTO_SEL_SHIFT;
+ if (rate == 300 * MHz)
+ sel = CLK_PKA_CRYPTO_SEL_300M;
+ else if (rate == 200 * MHz)
+ sel = CLK_PKA_CRYPTO_SEL_200M;
+ else if (rate == 100 * MHz)
+ sel = CLK_PKA_CRYPTO_SEL_100M;
+ else
+ sel = CLK_PKA_CRYPTO_SEL_24M;
+ break;
+ default:
+ return -ENOENT;
+ }
+ rk_clrsetreg(&cru->periclksel_con[43], mask, sel << shift);
+
+ return rk3562_crypto_get_rate(priv, clk_id);
+}
+
+static ulong rk3562_clk_scmi_get_rate(struct clk *clk)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLK_CORE_CRYPTO:
+ case CLK_PKA_CRYPTO:
+ return rk3562_crypto_get_rate(priv, clk->id);
+ default:
+ return -ENOENT;
+ }
+};
+
+static ulong rk3562_clk_scmi_set_rate(struct clk *clk, ulong rate)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLK_CORE_CRYPTO:
+ case CLK_PKA_CRYPTO:
+ return rk3562_crypto_set_rate(priv, clk->id, rate);
+ default:
+ return -ENOENT;
+ }
+ return 0;
+};
+
+static int rk3562_scmi_clk_ofdata_to_platdata(struct udevice *dev)
+{
+ struct rk3562_clk_priv *priv = dev_get_priv(dev);
+
+ priv->cru = (struct rk3562_cru *)0xff100000;
+
+ return 0;
+}
+
+/* A fake scmi driver for SPL/TPL where smccc agent is not available. */
+static const struct clk_ops scmi_clk_ops = {
+ .get_rate = rk3562_clk_scmi_get_rate,
+ .set_rate = rk3562_clk_scmi_set_rate,
+};
+
+U_BOOT_DRIVER(scmi_clock) = {
+ .name = "scmi_clk",
+ .id = UCLASS_CLK,
+ .ops = &scmi_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct rk3562_clk_priv),
+ .ofdata_to_platdata = rk3562_scmi_clk_ofdata_to_platdata,
+};
+#endif
diff --git a/u-boot/drivers/clk/rockchip/clk_rk3568.c b/u-boot/drivers/clk/rockchip/clk_rk3568.c
index 18b8e9d..f6a60d5 100644
--- a/u-boot/drivers/clk/rockchip/clk_rk3568.c
+++ b/u-boot/drivers/clk/rockchip/clk_rk3568.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
- * Author: Elaine Zhang <zhangqing@rock-chips.com>
+ * Author: Joseph Chen <chenjh@rock-chips.com>
*/
#include <common.h>
@@ -1160,7 +1160,7 @@
switch (clk_id) {
case CLK_PWM1:
- sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM3_SEL_SHIFT;
+ sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT;
break;
case CLK_PWM2:
sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT;
@@ -1850,7 +1850,7 @@
rockchip_pll_set_rate(&rk3568_pll_clks[VPLL],
priv->cru, VPLL, div * rate);
} else {
- for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) {
+ for (i = sel; i <= DCLK_VOP_SEL_CPLL; i++) {
switch (i) {
case DCLK_VOP_SEL_GPLL:
pll_rate = priv->gpll_hz;
@@ -3107,9 +3107,15 @@
if (parent->id == PLL_VPLL) {
rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
DCLK_VOP_SEL_VPLL << DCLK0_VOP_SEL_SHIFT);
- } else {
+ } else if (parent->id == PLL_HPLL) {
rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
DCLK_VOP_SEL_HPLL << DCLK0_VOP_SEL_SHIFT);
+ } else if (parent->id == PLL_CPLL) {
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+ DCLK_VOP_SEL_CPLL << DCLK0_VOP_SEL_SHIFT);
+ } else {
+ rk_clrsetreg(&cru->clksel_con[con_id], DCLK0_VOP_SEL_MASK,
+ DCLK_VOP_SEL_GPLL << DCLK0_VOP_SEL_SHIFT);
}
return 0;
diff --git a/u-boot/drivers/clk/rockchip/clk_rk3588.c b/u-boot/drivers/clk/rockchip/clk_rk3588.c
index 598d744..715ea04 100644
--- a/u-boot/drivers/clk/rockchip/clk_rk3588.c
+++ b/u-boot/drivers/clk/rockchip/clk_rk3588.c
@@ -332,12 +332,18 @@
switch (clk_id) {
case ACLK_TOP_ROOT:
- src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ if (!(priv->cpll_hz % rate)) {
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_CPLL;
+ src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate);
+ } else {
+ src_clk = ACLK_TOP_ROOT_SRC_SEL_GPLL;
+ src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate);
+ }
assert(src_clk_div - 1 <= 31);
rk_clrsetreg(&cru->clksel_con[8],
ACLK_TOP_ROOT_DIV_MASK |
ACLK_TOP_ROOT_SRC_SEL_MASK,
- (ACLK_TOP_ROOT_SRC_SEL_GPLL <<
+ (src_clk <<
ACLK_TOP_ROOT_SRC_SEL_SHIFT) |
(src_clk_div - 1) << ACLK_TOP_ROOT_DIV_SHIFT);
break;
@@ -1148,13 +1154,23 @@
}
if (sel == DCLK_VOP_SRC_SEL_V0PLL) {
- div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
- rk_clrsetreg(&cru->clksel_con[conid],
- mask,
- DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
- ((div - 1) << div_shift));
- rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
- priv->cru, V0PLL, div * rate);
+ pll_rate = rockchip_pll_get_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL);
+ if (pll_rate >= RK3588_VOP_PLL_LIMIT_FREQ && pll_rate % rate == 0) {
+ div = DIV_ROUND_UP(pll_rate, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
+ ((div - 1) << div_shift));
+ } else {
+ div = DIV_ROUND_UP(RK3588_VOP_PLL_LIMIT_FREQ, rate);
+ rk_clrsetreg(&cru->clksel_con[conid],
+ mask,
+ DCLK_VOP_SRC_SEL_V0PLL << sel_shift |
+ ((div - 1) << div_shift));
+ rockchip_pll_set_rate(&rk3588_pll_clks[V0PLL],
+ priv->cru, V0PLL, div * rate);
+ }
} else {
for (i = 0; i <= DCLK_VOP_SRC_SEL_AUPLL; i++) {
switch (i) {
diff --git a/u-boot/drivers/core/device.c b/u-boot/drivers/core/device.c
index e0e9ca1..a8803ee 100644
--- a/u-boot/drivers/core/device.c
+++ b/u-boot/drivers/core/device.c
@@ -97,8 +97,6 @@
debug("%s do not delete uboot dev: %s\n",
__func__, dev->name);
return 0;
- } else if (drv->id == UCLASS_REGULATOR) {
- /* stay in dm tree, in order to handle exclusion */
} else {
list_del_init(&dev->uclass_node);
}
diff --git a/u-boot/drivers/core/fdtaddr.c b/u-boot/drivers/core/fdtaddr.c
index 3847dd8..2b25c8d 100644
--- a/u-boot/drivers/core/fdtaddr.c
+++ b/u-boot/drivers/core/fdtaddr.c
@@ -127,6 +127,16 @@
return devfdt_get_addr_index(dev, 0);
}
+void *devfdt_remap_addr_index(struct udevice *dev, int index)
+{
+ fdt_addr_t addr = devfdt_get_addr_index(dev, index);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_physmem(addr, 0, MAP_NOCACHE);
+}
+
void *devfdt_get_addr_ptr(struct udevice *dev)
{
return (void *)(uintptr_t)devfdt_get_addr_index(dev, 0);
diff --git a/u-boot/drivers/core/read.c b/u-boot/drivers/core/read.c
index a7f77e9..a7ce6a4 100644
--- a/u-boot/drivers/core/read.c
+++ b/u-boot/drivers/core/read.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <dm.h>
#include <mapmem.h>
+#include <asm/io.h>
#include <dm/of_access.h>
int dev_read_u32_default(struct udevice *dev, const char *propname, int def)
@@ -63,6 +64,16 @@
return dev_read_addr_index(dev, 0);
}
+void *dev_remap_addr_index(struct udevice *dev, int index)
+{
+ fdt_addr_t addr = dev_read_addr_index(dev, index);
+
+ if (addr == FDT_ADDR_T_NONE)
+ return NULL;
+
+ return map_physmem(addr, 0, MAP_NOCACHE);
+}
+
void *dev_read_addr_ptr(struct udevice *dev)
{
fdt_addr_t addr = dev_read_addr(dev);
diff --git a/u-boot/drivers/core/root.c b/u-boot/drivers/core/root.c
index c928256..0eb2fa9 100644
--- a/u-boot/drivers/core/root.c
+++ b/u-boot/drivers/core/root.c
@@ -224,12 +224,8 @@
for (np = node_parent->child; np; np = np->sibling) {
if (pre_reloc_only &&
-#ifdef CONFIG_USING_KERNEL_DTB
- (!of_find_property(np, "u-boot,dm-pre-reloc", NULL) &&
- !of_find_property(np, "u-boot,dm-spl", NULL)))
-#else
- !of_find_property(np, "u-boot,dm-pre-reloc", NULL))
-#endif
+ (!of_find_property(np, "u-boot,dm-pre-reloc", NULL) &&
+ !of_find_property(np, "u-boot,dm-spl", NULL)))
continue;
if (!of_device_is_available(np)) {
pr_debug(" - ignoring disabled device\n");
@@ -272,7 +268,6 @@
int offset, bool pre_reloc_only)
{
int ret = 0, err;
- const char *name;
for (offset = fdt_first_subnode(blob, offset);
offset > 0;
@@ -291,11 +286,15 @@
ret);
}
+#if CONFIG_IS_ENABLED(SCMI_FIRMWARE)
+ const char *name;
+
/* There is no compatible in "/firmware", bind it by default. */
name = fdt_get_name(blob, offset, NULL);
if (name && !strcmp(name, "firmware"))
ret = device_bind_driver_to_node(parent, "firmware",
name, offset_to_ofnode(offset), NULL);
+#endif
}
if (ret)
diff --git a/u-boot/drivers/cpu/amp.its b/u-boot/drivers/cpu/amp.its
index 26ed969..e1d3ed0 100644
--- a/u-boot/drivers/cpu/amp.its
+++ b/u-boot/drivers/cpu/amp.its
@@ -1,20 +1,22 @@
/*
* Copyright (C) 2021 Fuzhou Rockchip Electronics Co., Ltd
+ *
* SPDX-License-Identifier: GPL-2.0
*/
/dts-v1/;
/ {
- description = "FIT source file for rockchip AMP";
+ description = "Rockchip AMP FIT Image";
#address-cells = <1>;
images {
+ /* ARM cortex-A core */
amp1 {
description = "bare-mental-core1";
data = /incbin/("./amp1.bin");
- type = "firmware";
+ type = "firmware"; // must be "firmware"
compression = "none";
- arch = "arm"; // "arm64" or "arm"
+ arch = "arm"; // "arm64" or "arm", the same as U-Boot state
cpu = <0x100>; // mpidr
thumb = <0>; // 0: arm or thumb2; 1: thumb
hyp = <0>; // 0: el1/svc; 1: el2/hyp
@@ -56,6 +58,20 @@
algo = "sha256";
};
};
+
+ /* Other core */
+ amp4 {
+ description = "standalone-mcu1";
+ data = /incbin/("./mcu1.bin");
+ type = "standalone"; // must be "standalone"
+ compression = "none";
+ arch = "arm"; // "arm64" or "arm", the same as U-Boot state
+ load = <0x06800000>;
+ udelay = <1000000>;
+ hash {
+ algo = "sha256";
+ };
+ };
};
configurations {
@@ -63,7 +79,7 @@
conf {
description = "Rockchip AMP images";
rollback-index = <0x0>;
- loadables = "amp1", "amp2", "amp3";
+ loadables = "amp1", "amp2", "amp3", "amp4";
signature {
algo = "sha256,rsa2048";
diff --git a/u-boot/drivers/cpu/rockchip_amp.c b/u-boot/drivers/cpu/rockchip_amp.c
index 6cf9c35..f17ddf5 100644
--- a/u-boot/drivers/cpu/rockchip_amp.c
+++ b/u-boot/drivers/cpu/rockchip_amp.c
@@ -134,7 +134,7 @@
flush_dcache_all();
/* fixup: ramdisk/fdt/entry depend on U-Boot */
- *entry = env_get_ulong("kernel_addr_r", 16, 0);
+ *entry = (u32)images.ep;
return 0;
}
@@ -206,6 +206,31 @@
return 0;
}
+__weak int fit_standalone_release(char *id, uintptr_t entry_point)
+{
+ return 0;
+}
+
+static int standalone_handler(const char *id, u32 entry_point, int data_size)
+{
+ int ret;
+
+ if (!sysmem_alloc_base_by_name(id,
+ (phys_addr_t)entry_point, data_size))
+ return -ENXIO;
+
+ printf("Handle standalone: '%s' at 0x%08x ...", id, entry_point);
+
+ ret = fit_standalone_release((char *)id, entry_point);
+ if (ret) {
+ printf("failed, ret=%d\n", ret);
+ return ret;
+ }
+ printf("OK\n");
+
+ return 0;
+}
+
static int brought_up_amp(void *fit, int noffset,
boot_cpu_t *bootcpu, int is_linux)
{
@@ -217,27 +242,38 @@
int boot_on;
int data_size;
int i, ret;
- u8 arch = -ENODATA;
+ u8 type = -ENODATA;
+ u8 arch = -ENODATA;
desc = fdt_getprop(fit, noffset, "description", NULL);
cpu = fit_get_u32_default(fit, noffset, "cpu", -ENODATA);
hyp = fit_get_u32_default(fit, noffset, "hyp", 0);
thumb = fit_get_u32_default(fit, noffset, "thumb", 0);
- load = fit_get_u32_default(fit, noffset, "load", -ENODATA);
+ entry = load = fit_get_u32_default(fit, noffset, "load", -ENODATA);
us = fit_get_u32_default(fit, noffset, "udelay", 0);
boot_on = fit_get_u32_default(fit, noffset, "boot-on", 1);
fit_image_get_arch(fit, noffset, &arch);
+ fit_image_get_type(fit, noffset, &type);
fit_image_get_data_size(fit, noffset, &data_size);
memset(&args, 0, sizeof(args));
- if (!desc || cpu == -ENODATA || arch == -ENODATA ||
+ /* standalone is simple, just handle it and then exit. Allow failure */
+ if (type == IH_TYPE_STANDALONE) {
+ if (!desc || load == -ENODATA) {
+ AMP_E("standalone: \"desc\" or \"load\" property missing!\n");
+ goto exit;
+ }
+ standalone_handler(desc, load, data_size);
+ goto exit;
+ }
+
+ if (!desc || cpu == -ENODATA || arch == -ENODATA || type == -ENODATA ||
(load == -ENODATA && !is_linux)) {
AMP_E("Property missing!\n");
return -EINVAL;
}
aarch64 = (arch == IH_ARCH_ARM) ? 0 : 1;
pe_state = PE_STATE(aarch64, hyp, thumb, 0);
- entry = load;
#ifdef DEBUG
AMP_I(" desc: %s\n", desc);
@@ -245,7 +281,7 @@
AMP_I(" aarch64: %d\n", aarch64);
AMP_I(" hyp: %d\n", hyp);
AMP_I(" thumb: %d\n", thumb);
- AMP_I(" entry: 0x%08x\n", entry);
+ AMP_I(" load: 0x%08x\n", load);
AMP_I(" pe_state: 0x%08x\n", pe_state);
AMP_I(" linux-os: %d\n\n", is_linux);
#endif
@@ -294,7 +330,7 @@
ret = smc_cpu_on(cpu, pe_state, entry, &args, is_linux);
if (ret)
return ret;
-
+exit:
if (us)
udelay(us);
@@ -336,7 +372,7 @@
/* === only boot cpu can reach here === */
- if (!g_bootcpu.linux_os) {
+ if (!g_bootcpu.linux_os && g_bootcpu.entry) {
flush_dcache_all();
AMP_I("Brought up cpu[%x, self] with state 0x%x, entry 0x%08x ...",
(u32)read_mpidr() & 0x0fff, g_bootcpu.state, g_bootcpu.entry);
diff --git a/u-boot/drivers/crypto/rockchip/crypto_v2.c b/u-boot/drivers/crypto/rockchip/crypto_v2.c
index 86226fe..e2135a7 100644
--- a/u-boot/drivers/crypto/rockchip/crypto_v2.c
+++ b/u-boot/drivers/crypto/rockchip/crypto_v2.c
@@ -8,6 +8,7 @@
#include <crypto.h>
#include <dm.h>
#include <asm/io.h>
+#include <clk-uclass.h>
#include <asm/arch/hardware.h>
#include <asm/arch/clock.h>
#include <rockchip/crypto_hash_cache.h>
@@ -54,6 +55,7 @@
char *clocks;
u32 *frequencies;
u32 nclocks;
+ u32 freq_nclocks;
u32 length;
struct rk_hash_ctx *hw_ctx;
struct rk_crypto_soc_data *soc_data;
@@ -217,6 +219,43 @@
for (i = 0; i < tag_len / 4; i++, chn_base += 4)
word2byte_be(crypto_read(chn_base), tag + 4 * i);
+}
+
+static int rk_crypto_do_enable_clk(struct udevice *dev, int enable)
+{
+ struct rockchip_crypto_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ int i, ret;
+
+ for (i = 0; i < priv->nclocks; i++) {
+ ret = clk_get_by_index(dev, i, &clk);
+ if (ret < 0) {
+ printf("Failed to get clk index %d, ret=%d\n", i, ret);
+ return ret;
+ }
+
+ if (enable)
+ ret = clk_enable(&clk);
+ else
+ ret = clk_disable(&clk);
+ if (ret < 0 && ret != -ENOSYS) {
+ printf("Failed to enable(%d) clk(%ld): ret=%d\n",
+ enable, clk.id, ret);
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int rk_crypto_enable_clk(struct udevice *dev)
+{
+ return rk_crypto_do_enable_clk(dev, 1);
+}
+
+static int rk_crypto_disable_clk(struct udevice *dev)
+{
+ return rk_crypto_do_enable_clk(dev, 0);
}
static u32 crypto_v3_dynamic_cap(void)
@@ -397,7 +436,7 @@
if (!(*started_flag)) {
lli->user_define |=
- (LLI_USER_STRING_START | LLI_USER_CPIHER_START);
+ (LLI_USER_STRING_START | LLI_USER_CIPHER_START);
crypto_write((u32)virt_to_phys(lli), CRYPTO_DMA_LLI_ADDR);
crypto_write((CRYPTO_HASH_ENABLE << CRYPTO_WRITE_MASK_SHIFT) |
CRYPTO_HASH_ENABLE, CRYPTO_HASH_CTL);
@@ -520,6 +559,7 @@
{
struct rockchip_crypto_priv *priv = dev_get_priv(dev);
struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
+ int ret = 0;
if (!ctx)
return -EINVAL;
@@ -535,7 +575,12 @@
if (!hash_ctx->hash_cache)
return -EFAULT;
- return rk_hash_init(hash_ctx, ctx->algo);
+ rk_crypto_enable_clk(dev);
+ ret = rk_hash_init(hash_ctx, ctx->algo);
+ if (ret)
+ rk_crypto_disable_clk(dev);
+
+ return ret;
}
static int rockchip_crypto_sha_update(struct udevice *dev,
@@ -545,8 +590,10 @@
int ret, i;
u8 *p;
- if (!len)
- return -EINVAL;
+ if (!len) {
+ ret = -EINVAL;
+ goto exit;
+ }
p = (u8 *)input;
@@ -560,6 +607,9 @@
ret = rk_hash_update(priv->hw_ctx, p, len % HASH_UPDATE_LIMIT);
exit:
+ if (ret)
+ rk_crypto_disable_clk(dev);
+
return ret;
}
@@ -583,6 +633,8 @@
exit:
hw_hash_clean_ctx(priv->hw_ctx);
+ rk_crypto_disable_clk(dev);
+
return ret;
}
@@ -614,6 +666,7 @@
{
struct rockchip_crypto_priv *priv = dev_get_priv(dev);
struct rk_hash_ctx *hash_ctx = priv->hw_ctx;
+ int ret = 0;
if (!ctx)
return -EINVAL;
@@ -629,7 +682,12 @@
if (!hash_ctx->hash_cache)
return -EFAULT;
- return rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
+ rk_crypto_enable_clk(dev);
+ ret = rk_hmac_init(priv->hw_ctx, ctx->algo, key, key_len);
+ if (ret)
+ rk_crypto_disable_clk(dev);
+
+ return ret;
}
static int rockchip_crypto_hmac_update(struct udevice *dev,
@@ -763,6 +821,11 @@
{
u32 i;
+ if (aad_len == 0) {
+ *padding_size = 0;
+ return;
+ }
+
i = aad_len < (0x10000 - 0x100) ? 2 : 6;
if (i == 2) {
@@ -779,7 +842,7 @@
*padding_size = i;
}
-static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 tag_size)
+static int ccm_compose_aad_iv(u8 *aad_iv, u32 data_len, u32 aad_len, u32 tag_size)
{
aad_iv[0] |= ((u8)(((tag_size - 2) / 2) & 7) << 3);
@@ -788,7 +851,8 @@
aad_iv[14] = (u8)(data_len >> 8);
aad_iv[15] = (u8)data_len;
- aad_iv[0] |= 0x40; //set aad flag
+ if (aad_len)
+ aad_iv[0] |= 0x40; //set aad flag
return 0;
}
@@ -925,12 +989,14 @@
data_desc->dma_ctrl |= LLI_DMA_CTRL_DST_DONE;
}
+ data_desc->user_define = LLI_USER_CIPHER_START |
+ LLI_USER_STRING_START |
+ LLI_USER_STRING_LAST |
+ (key_chn << 4);
+ crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
+
if (rk_mode == RK_MODE_CCM || rk_mode == RK_MODE_GCM) {
u32 aad_tmp_len = 0;
-
- data_desc->user_define = LLI_USER_STRING_START |
- LLI_USER_STRING_LAST |
- (key_chn << 4);
aad_desc = align_malloc(sizeof(*aad_desc), LLI_ADDR_ALIGN_SIZE);
if (!aad_desc)
@@ -938,7 +1004,7 @@
memset(aad_desc, 0x00, sizeof(*aad_desc));
aad_desc->next_addr = (u32)virt_to_phys(data_desc);
- aad_desc->user_define = LLI_USER_CPIHER_START |
+ aad_desc->user_define = LLI_USER_CIPHER_START |
LLI_USER_STRING_START |
LLI_USER_STRING_LAST |
LLI_USER_STRING_AAD |
@@ -958,12 +1024,15 @@
if (!aad_tmp)
goto exit;
- /* read iv data from reg */
- get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
- ccm_compose_aad_iv(aad_tmp, tmp_len, tag_len);
- memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
+ /* clear last block */
memset(aad_tmp + aad_tmp_len - AES_BLOCK_SIZE,
0x00, AES_BLOCK_SIZE);
+
+ /* read iv data from reg */
+ get_iv_reg(key_chn, aad_tmp, AES_BLOCK_SIZE);
+ ccm_compose_aad_iv(aad_tmp, tmp_len, aad_len, tag_len);
+ memcpy(aad_tmp + AES_BLOCK_SIZE, padding, padding_size);
+
memcpy(aad_tmp + AES_BLOCK_SIZE + padding_size,
aad, aad_len);
} else {
@@ -985,15 +1054,15 @@
aad_desc->src_addr = (u32)virt_to_phys(aad_tmp);
aad_desc->src_len = aad_tmp_len;
- crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
- cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
- cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
- } else {
- data_desc->user_define = LLI_USER_CPIHER_START |
- LLI_USER_STRING_START |
- LLI_USER_STRING_LAST |
- (key_chn << 4);
- crypto_write((u32)virt_to_phys(data_desc), CRYPTO_DMA_LLI_ADDR);
+
+ if (aad_tmp_len) {
+ data_desc->user_define = LLI_USER_STRING_START |
+ LLI_USER_STRING_LAST |
+ (key_chn << 4);
+ crypto_write((u32)virt_to_phys(aad_desc), CRYPTO_DMA_LLI_ADDR);
+ cache_op_inner(DCACHE_AREA_CLEAN, aad_tmp, aad_tmp_len);
+ cache_op_inner(DCACHE_AREA_CLEAN, aad_desc, sizeof(*aad_desc));
+ }
}
cache_op_inner(DCACHE_AREA_CLEAN, data_desc, sizeof(*data_desc));
@@ -1175,21 +1244,29 @@
int rockchip_crypto_cipher(struct udevice *dev, cipher_context *ctx,
const u8 *in, u8 *out, u32 len, bool enc)
{
+ int ret;
+
+ rk_crypto_enable_clk(dev);
+
switch (ctx->algo) {
case CRYPTO_DES:
- return rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
- ctx->iv, in, out, len, enc);
+ ret = rk_crypto_des(dev, ctx->mode, ctx->key, ctx->key_len,
+ ctx->iv, in, out, len, enc);
case CRYPTO_AES:
- return rk_crypto_aes(dev, ctx->mode,
- ctx->key, ctx->twk_key, ctx->key_len,
- ctx->iv, ctx->iv_len, in, out, len, enc);
+ ret = rk_crypto_aes(dev, ctx->mode,
+ ctx->key, ctx->twk_key, ctx->key_len,
+ ctx->iv, ctx->iv_len, in, out, len, enc);
case CRYPTO_SM4:
- return rk_crypto_sm4(dev, ctx->mode,
- ctx->key, ctx->twk_key, ctx->key_len,
- ctx->iv, ctx->iv_len, in, out, len, enc);
+ ret = rk_crypto_sm4(dev, ctx->mode,
+ ctx->key, ctx->twk_key, ctx->key_len,
+ ctx->iv, ctx->iv_len, in, out, len, enc);
default:
- return -EINVAL;
+ ret = -EINVAL;
}
+
+ rk_crypto_disable_clk(dev);
+
+ return ret;
}
int rk_crypto_mac(struct udevice *dev, u32 algo, u32 mode,
@@ -1223,8 +1300,16 @@
int rockchip_crypto_mac(struct udevice *dev, cipher_context *ctx,
const u8 *in, u32 len, u8 *tag)
{
- return rk_crypto_mac(dev, ctx->algo, ctx->mode,
- ctx->key, ctx->key_len, in, len, tag);
+ int ret = 0;
+
+ rk_crypto_enable_clk(dev);
+
+ ret = rk_crypto_mac(dev, ctx->algo, ctx->mode,
+ ctx->key, ctx->key_len, in, len, tag);
+
+ rk_crypto_disable_clk(dev);
+
+ return ret;
}
int rk_crypto_ae(struct udevice *dev, u32 algo, u32 mode,
@@ -1236,6 +1321,9 @@
int ret;
if (!IS_AE_MODE(rk_mode))
+ return -EINVAL;
+
+ if (len == 0)
return -EINVAL;
if (algo != CRYPTO_AES && algo != CRYPTO_SM4)
@@ -1261,9 +1349,17 @@
u8 *out, u8 *tag)
{
- return rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
- ctx->iv, ctx->iv_len, in, len,
- aad, aad_len, out, tag);
+ int ret = 0;
+
+ rk_crypto_enable_clk(dev);
+
+ ret = rk_crypto_ae(dev, ctx->algo, ctx->mode, ctx->key, ctx->key_len,
+ ctx->iv, ctx->iv_len, in, len,
+ aad, aad_len, out, tag);
+
+ rk_crypto_disable_clk(dev);
+
+ return ret;
}
#endif
@@ -1312,9 +1408,11 @@
if (ret)
goto exit;
+ rk_crypto_enable_clk(dev);
ret = rk_exptmod_np(mpa_m, mpa_e, mpa_n, mpa_c, mpa_result);
if (!ret)
memcpy(output, mpa_result->d, BITS2BYTE(n_bits));
+ rk_crypto_disable_clk(dev);
exit:
rk_mpa_free(&mpa_m);
@@ -1378,7 +1476,7 @@
if (!priv->clocks)
return -ENOMEM;
- priv->nclocks = len / sizeof(u32);
+ priv->nclocks = len / (2 * sizeof(u32));
if (dev_read_u32_array(dev, "clocks", (u32 *)priv->clocks,
priv->nclocks)) {
printf("Can't read \"clocks\" property\n");
@@ -1386,24 +1484,19 @@
goto exit;
}
- if (!dev_read_prop(dev, "clock-frequency", &len)) {
- printf("Can't find \"clock-frequency\" property\n");
- ret = -EINVAL;
- goto exit;
- }
-
- priv->frequencies = malloc(len);
- if (!priv->frequencies) {
- ret = -ENOMEM;
- goto exit;
- }
-
- priv->nclocks = len / sizeof(u32);
- if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
- priv->nclocks)) {
- printf("Can't read \"clock-frequency\" property\n");
- ret = -EINVAL;
- goto exit;
+ if (dev_read_prop(dev, "clock-frequency", &len)) {
+ priv->frequencies = malloc(len);
+ if (!priv->frequencies) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+ priv->freq_nclocks = len / sizeof(u32);
+ if (dev_read_u32_array(dev, "clock-frequency", priv->frequencies,
+ priv->freq_nclocks)) {
+ printf("Can't read \"clock-frequency\" property\n");
+ ret = -EINVAL;
+ goto exit;
+ }
}
return 0;
@@ -1423,10 +1516,15 @@
struct clk clk;
int i, ret;
- if (!priv->clocks && priv->nclocks == 0)
+ /* use standard "assigned-clock-rates" props */
+ if (dev_read_size(dev, "assigned-clock-rates") > 0)
+ return clk_set_defaults(dev);
+
+ /* use "clock-frequency" props */
+ if (priv->freq_nclocks == 0)
return 0;
- for (i = 0; i < priv->nclocks; i++) {
+ for (i = 0; i < priv->freq_nclocks; i++) {
ret = clk_get_by_index(dev, i, &clk);
if (ret < 0) {
printf("Failed to get clk index %d, ret=%d\n", i, ret);
@@ -1465,7 +1563,11 @@
if (ret)
return ret;
+ rk_crypto_enable_clk(dev);
+
hw_crypto_reset();
+
+ rk_crypto_disable_clk(dev);
return 0;
}
@@ -1557,6 +1659,10 @@
.compatible = "rockchip,crypto-v3",
.data = (ulong)&soc_data_cryptov3
},
+ {
+ .compatible = "rockchip,crypto-v4",
+ .data = (ulong)&soc_data_cryptov3 /* reuse crypto v3 config */
+ },
{ }
};
diff --git a/u-boot/drivers/gpio/Kconfig b/u-boot/drivers/gpio/Kconfig
index f059ea7..412df72 100644
--- a/u-boot/drivers/gpio/Kconfig
+++ b/u-boot/drivers/gpio/Kconfig
@@ -24,6 +24,15 @@
is a mechanism providing automatic GPIO request and config-
uration as part of the gpio-controller's driver probe function.
+config GPIO_NO_UC_FLAG_SEQ_ALIAS
+ bool "Disable GPIO uclass sequence themselves with aliases"
+ depends on USING_KERNEL_DTB
+ default n
+ help
+ Disable GPIO uclass sequence, this is a workaround when kernel
+ dtb feature is enabled. Avoid gpio device probe failed when
+ alloc req_seq both for gpio devices from U-Boot and kernel dtb.
+
config ALTERA_PIO
bool "Altera PIO driver"
depends on DM_GPIO
@@ -211,12 +220,6 @@
Support for the GPIO controller contained in NVIDIA Tegra186. This
covers both the "main" and "AON" controller instances, even though
they have slightly different register layout.
-
-config GPIO_MAX96752F
- bool "Maxim MAX96752F GPIO"
- depends on DM_GPIO && I2C_MUX_MAX96752F
- help
- Say yes here to support Maxim MAX96752F GPIOs.
config GPIO_UNIPHIER
bool "UniPhier GPIO"
diff --git a/u-boot/drivers/gpio/Makefile b/u-boot/drivers/gpio/Makefile
index 451032a..1396467 100644
--- a/u-boot/drivers/gpio/Makefile
+++ b/u-boot/drivers/gpio/Makefile
@@ -8,7 +8,6 @@
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_DWAPB_GPIO) += dwapb_gpio.o
obj-$(CONFIG_AXP_GPIO) += axp_gpio.o
-obj-$(CONFIG_GPIO_MAX96752F) += gpio-max96752f.o
endif
obj-$(CONFIG_DM_GPIO) += gpio-uclass.o
diff --git a/u-boot/drivers/gpio/gpio-max96752f.c b/u-boot/drivers/gpio/gpio-max96752f.c
deleted file mode 100644
index 426b30e..0000000
--- a/u-boot/drivers/gpio/gpio-max96752f.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#include <asm-generic/gpio.h>
-#include <common.h>
-#include <dm.h>
-#include <i2c.h>
-#include <max96752f.h>
-
-static int max96752f_gpio_direction_output(struct udevice *dev, unsigned offset,
- int value)
-{
- int ret;
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(offset),
- GPIO_OUT_DIS | GPIO_OUT,
- FIELD_PREP(GPIO_OUT_DIS, 0) |
- FIELD_PREP(GPIO_OUT, value));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int max96752f_gpio_get_value(struct udevice *dev, unsigned offset)
-{
- int ret;
-
- ret = dm_i2c_reg_read(dev->parent, GPIO_A_REG(offset));
- if (ret < 0)
- return ret;
-
- return FIELD_GET(GPIO_OUT, ret);
-}
-
-static int max96752f_gpio_set_value(struct udevice *dev, unsigned offset,
- int value)
-{
- int ret;
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(offset), GPIO_OUT,
- FIELD_PREP(GPIO_OUT, value));
- if (ret < 0)
- return ret;
-
- return 0;
-}
-
-static int max96752f_gpio_get_function(struct udevice *dev, unsigned offset)
-{
- int ret;
-
- ret = dm_i2c_reg_read(dev->parent, GPIO_A_REG(offset));
- if (ret < 0)
- return ret;
-
- return FIELD_GET(GPIO_OUT_DIS, ret) ? GPIOF_INPUT : GPIOF_OUTPUT;
-}
-
-static const struct dm_gpio_ops max96752f_gpio_ops = {
- .direction_output = max96752f_gpio_direction_output,
- .get_value = max96752f_gpio_get_value,
- .set_value = max96752f_gpio_set_value,
- .get_function = max96752f_gpio_get_function,
-};
-
-static int max96752f_gpio_probe(struct udevice *dev)
-{
- struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-
- uc_priv->gpio_count = 16;
- uc_priv->bank_name = of_node_full_name(dev_np(dev));
-
- return 0;
-}
-
-static const struct udevice_id max96752f_gpio_match[] = {
- { .compatible = "maxim,max96752f-gpio" },
- { }
-};
-
-U_BOOT_DRIVER(max96752f_gpio) = {
- .name = "max96752f_gpio",
- .id = UCLASS_GPIO,
- .of_match = max96752f_gpio_match,
- .probe = max96752f_gpio_probe,
- .ops = &max96752f_gpio_ops,
-};
diff --git a/u-boot/drivers/gpio/gpio-uclass.c b/u-boot/drivers/gpio/gpio-uclass.c
index 5868dd4..a8479b0 100644
--- a/u-boot/drivers/gpio/gpio-uclass.c
+++ b/u-boot/drivers/gpio/gpio-uclass.c
@@ -1058,7 +1058,9 @@
UCLASS_DRIVER(gpio) = {
.id = UCLASS_GPIO,
.name = "gpio",
+#ifndef CONFIG_GPIO_NO_UC_FLAG_SEQ_ALIAS
.flags = DM_UC_FLAG_SEQ_ALIAS,
+#endif
.post_probe = gpio_post_probe,
.post_bind = gpio_post_bind,
.pre_remove = gpio_pre_remove,
diff --git a/u-boot/drivers/gpio/rk_gpio.c b/u-boot/drivers/gpio/rk_gpio.c
index 593701b..d1c7889 100644
--- a/u-boot/drivers/gpio/rk_gpio.c
+++ b/u-boot/drivers/gpio/rk_gpio.c
@@ -130,7 +130,6 @@
struct rockchip_pinctrl_priv *pctrl_priv;
struct rockchip_pin_bank *bank;
char *end = NULL;
- static int gpio;
int id = -1, ret;
priv->regs = dev_read_addr_ptr(dev);
@@ -152,14 +151,12 @@
end = strrchr(dev->name, '@');
if (end)
id = trailing_strtoln(dev->name, end);
- else
+ if (id < 0)
dev_read_alias_seq(dev, &id);
- if (id < 0)
- id = gpio++;
-
- if (id >= pctrl_priv->ctrl->nr_banks) {
- dev_err(dev, "bank id invalid\n");
+ if (id < 0 || id >= pctrl_priv->ctrl->nr_banks) {
+ dev_err(dev, "nr_banks=%d, bank id=%d invalid\n",
+ pctrl_priv->ctrl->nr_banks, id);
return -EINVAL;
}
diff --git a/u-boot/drivers/i2c/muxes/Kconfig b/u-boot/drivers/i2c/muxes/Kconfig
index d87dee7..a98c33c 100644
--- a/u-boot/drivers/i2c/muxes/Kconfig
+++ b/u-boot/drivers/i2c/muxes/Kconfig
@@ -51,13 +51,6 @@
If you say yes here you get support for the Maxim MAX96745
I2C multiplexer.
-config I2C_MUX_MAX96752F
- tristate "Maxim MAX96752F I2C multiplexer"
- depends on I2C_MUX
- help
- If you say yes here you get support for the Maxim MAX96752F
- I2C multiplexer.
-
config I2C_MUX_MAX96755F
tristate "Maxim MAX96755F I2C multiplexer"
depends on I2C_MUX
diff --git a/u-boot/drivers/i2c/muxes/Makefile b/u-boot/drivers/i2c/muxes/Makefile
index d41ccb2..959fd9f 100644
--- a/u-boot/drivers/i2c/muxes/Makefile
+++ b/u-boot/drivers/i2c/muxes/Makefile
@@ -8,6 +8,5 @@
obj-$(CONFIG_I2C_MUX_PCA954x) += pca954x.o
obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
obj-$(CONFIG_I2C_MUX_MAX96745) += max96745.o
-obj-$(CONFIG_I2C_MUX_MAX96752F) += max96752f.o
obj-$(CONFIG_I2C_MUX_MAX96755F) += max96755f.o
diff --git a/u-boot/drivers/i2c/muxes/max96745.c b/u-boot/drivers/i2c/muxes/max96745.c
index 1a76c3f..5c85cb5 100644
--- a/u-boot/drivers/i2c/muxes/max96745.c
+++ b/u-boot/drivers/i2c/muxes/max96745.c
@@ -13,11 +13,18 @@
struct max96745_priv {
struct udevice *dev;
struct gpio_desc enable_gpio;
+ struct gpio_desc pwdnb_gpio;
+ bool idle_disc;
};
static int max96745_select(struct udevice *mux, struct udevice *bus,
uint channel)
{
+ struct max96745_priv *priv = dev_get_priv(mux);
+
+ if (!priv->idle_disc)
+ return 0;
+
if (channel == 1)
dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
FIELD_PREP(DIS_REM_CC, 0));
@@ -31,6 +38,11 @@
static int max96745_deselect(struct udevice *mux, struct udevice *bus,
uint channel)
{
+ struct max96745_priv *priv = dev_get_priv(mux);
+
+ if (!priv->idle_disc)
+ return 0;
+
if (channel == 1)
dm_i2c_reg_clrset(mux, 0x0086, DIS_REM_CC,
FIELD_PREP(DIS_REM_CC, 1));
@@ -55,15 +67,27 @@
mdelay(200);
}
- ret = dm_i2c_reg_clrset(priv->dev, 0x0076, DIS_REM_CC,
- FIELD_PREP(DIS_REM_CC, 1));
+ if (dm_gpio_is_valid(&priv->pwdnb_gpio)) {
+ dm_gpio_set_value(&priv->pwdnb_gpio, 0);
+ mdelay(30);
+ }
+
+ /* Set for I2C Fast-mode speed */
+ ret = dm_i2c_reg_write(priv->dev, 0x0070, 0x16);
if (ret < 0)
return ret;
- ret = dm_i2c_reg_clrset(priv->dev, 0x0086, DIS_REM_CC,
- FIELD_PREP(DIS_REM_CC, 1));
- if (ret < 0)
- return ret;
+ if (priv->idle_disc) {
+ ret = dm_i2c_reg_clrset(priv->dev, 0x0076, DIS_REM_CC,
+ FIELD_PREP(DIS_REM_CC, 1));
+ if (ret < 0)
+ return ret;
+
+ ret = dm_i2c_reg_clrset(priv->dev, 0x0086, DIS_REM_CC,
+ FIELD_PREP(DIS_REM_CC, 1));
+ if (ret < 0)
+ return ret;
+ }
return 0;
}
@@ -78,6 +102,7 @@
return ret;
priv->dev = dev;
+ priv->idle_disc = dev_read_bool(dev, "i2c-mux-idle-disconnect");
ret = gpio_request_by_name(dev, "enable-gpios", 0,
&priv->enable_gpio, GPIOD_IS_OUT);
@@ -86,6 +111,13 @@
return ret;
}
+ ret = gpio_request_by_name(dev, "pwdnb-gpios", 0,
+ &priv->pwdnb_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "%s: failed to get pwdnb GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+
max96745_power_on(priv);
return 0;
diff --git a/u-boot/drivers/i2c/muxes/max96752f.c b/u-boot/drivers/i2c/muxes/max96752f.c
deleted file mode 100644
index b979859..0000000
--- a/u-boot/drivers/i2c/muxes/max96752f.c
+++ /dev/null
@@ -1,100 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <i2c.h>
-#include <max96752f.h>
-
-#include <asm-generic/gpio.h>
-
-static int max96752f_select(struct udevice *mux, struct udevice *bus,
- uint channel)
-{
- return 0;
-}
-
-static int max96752f_deselect(struct udevice *mux, struct udevice *bus,
- uint channel)
-{
- return 0;
-}
-
-static const struct i2c_mux_ops max96752f_ops = {
- .select = max96752f_select,
- .deselect = max96752f_deselect,
-};
-
-static uint addr_list[] = {
- 0x48, 0x68, 0x6a, 0x4a, 0x4c, 0x6c, 0x28, 0x2a
-};
-
-void max96752f_init(struct udevice *dev)
-{
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
- u32 stream_id = dev_read_u32_default(dev->parent, "reg", 0);
- uint addr = chip->chip_addr;
- int i, ret;
-
- for (i = 0; i < ARRAY_SIZE(addr_list); i++) {
- chip->chip_addr = addr_list[i];
-
- ret = dm_i2c_reg_read(dev, 0x000d);
- if (ret < 0)
- continue;
-
- if (ret == 0x82) {
- dm_i2c_reg_write(dev, 0x0000, addr << 1);
- break;
- }
- }
-
- chip->chip_addr = addr;
-
- dm_i2c_reg_clrset(dev, 0x0050, STR_SEL,
- FIELD_PREP(STR_SEL, stream_id));
- dm_i2c_reg_clrset(dev, 0x0073, TX_SRC_ID,
- FIELD_PREP(TX_SRC_ID, stream_id));
-}
-
-static int max96752f_probe(struct udevice *dev)
-{
- struct gpio_desc enable_gpio;
- int ret;
-
- ret = i2c_set_chip_offset_len(dev, 2);
- if (ret)
- return ret;
-
- ret = gpio_request_by_name(dev, "enable-gpios", 0, &enable_gpio,
- GPIOD_IS_OUT);
- if (ret && ret != -ENOENT) {
- dev_err(dev, "%s: failed to get enable GPIO: %d\n",
- __func__, ret);
- return ret;
- }
-
- if (dm_gpio_is_valid(&enable_gpio)) {
- dm_gpio_set_value(&enable_gpio, 1);
- mdelay(200);
- }
-
- return 0;
-}
-
-static const struct udevice_id max96752f_of_match[] = {
- { .compatible = "maxim,max96752f" },
- {}
-};
-
-U_BOOT_DRIVER(max96752f) = {
- .name = "max96752f",
- .id = UCLASS_I2C_MUX,
- .of_match = max96752f_of_match,
- .bind = dm_scan_fdt_dev,
- .probe = max96752f_probe,
- .ops = &max96752f_ops,
-};
diff --git a/u-boot/drivers/input/adc_key.c b/u-boot/drivers/input/adc_key.c
index 391e324..32e63d0 100644
--- a/u-boot/drivers/input/adc_key.c
+++ b/u-boot/drivers/input/adc_key.c
@@ -11,13 +11,10 @@
static int adc_key_ofdata_to_platdata(struct udevice *dev)
{
struct dm_key_uclass_platdata *uc_key;
- u32 chn[2], mV;
- int vref, ret;
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
- int range = 4096; /* 12-bit adc */
-#else
- int range = 1024; /* 10-bit adc */
-#endif
+ int t, down_threshold = -1, up_threshold;
+ int ret, num = 0, volt_margin = 150000; /* will be div 2 */
+ u32 voltage, chn[2];
+ ofnode node;
uc_key = dev_get_uclass_platdata(dev);
if (!uc_key)
@@ -33,29 +30,50 @@
return -EINVAL;
}
- vref = dev_read_u32_default(dev_get_parent(dev),
+ up_threshold = dev_read_u32_default(dev_get_parent(dev),
"keyup-threshold-microvolt", -ENODATA);
- if (vref < 0) {
- printf("%s: read 'keyup-threshold-microvolt' failed, ret=%d\n",
- uc_key->name, vref);
- return -EINVAL;
- }
+ if (up_threshold < 0)
+ return -ENODATA;
uc_key->code = dev_read_u32_default(dev, "linux,code", -ENODATA);
- if (uc_key->code < 0) {
- printf("%s: read 'linux,code' failed\n", uc_key->name);
- return -EINVAL;
+ if (uc_key->code < 0)
+ return -ENODATA;
+
+ voltage = dev_read_u32_default(dev, "press-threshold-microvolt", -ENODATA);
+ if (voltage < 0)
+ return -ENODATA;
+
+ dev_for_each_subnode(node, dev->parent) {
+ ret = ofnode_read_s32(node, "press-threshold-microvolt", &t);
+ if (ret)
+ return ret;
+
+ if (t > voltage && t < up_threshold)
+ up_threshold = t;
+ else if (t < voltage && t > down_threshold)
+ down_threshold = t;
+ num++;
}
- mV = dev_read_u32_default(dev, "press-threshold-microvolt", -ENODATA);
- if (mV < 0) {
- printf("%s: read 'press-threshold-microvolt' failed\n",
- uc_key->name);
- return -EINVAL;
+ /* although one node only, it doesn't mean only one key on hardware */
+ if (num == 1) {
+ down_threshold = voltage - volt_margin;
+ up_threshold = voltage + volt_margin;
}
+ uc_key->in_volt = 1;
uc_key->channel = chn[1];
- uc_key->adcval = mV / (vref / range);
+ uc_key->center = voltage;
+ /*
+ * Define the voltage range such that the button is only pressed
+ * when the voltage is closest to its own press-threshold-microvolt
+ */
+ if (down_threshold < 0)
+ uc_key->min = 0;
+ else
+ uc_key->min = down_threshold + (voltage - down_threshold) / 2;
+
+ uc_key->max = voltage + (up_threshold - voltage) / 2;
return 0;
}
diff --git a/u-boot/drivers/input/key-uclass.c b/u-boot/drivers/input/key-uclass.c
index f28869a..c4f85da 100644
--- a/u-boot/drivers/input/key-uclass.c
+++ b/u-boot/drivers/input/key-uclass.c
@@ -6,6 +6,7 @@
#include <common.h>
#include <adc.h>
+#include <div64.h>
#include <dm.h>
#include <irq-generic.h>
#include <key.h>
@@ -37,11 +38,42 @@
return (cntpct > base) ? (cntpct - base) : 0;
}
-static int key_adc_event(struct dm_key_uclass_platdata *uc_key, int adcval)
+#ifdef CONFIG_ADC
+static int adc_raw_to_mV(struct udevice *dev, unsigned int raw, int *mV)
{
- return (adcval <= uc_key->max && adcval >= uc_key->min) ?
+ unsigned int data_mask;
+ int ret, vref = 1800000;
+ u64 raw64 = raw;
+
+ ret = adc_data_mask(dev, &data_mask);
+ if (ret)
+ return ret;
+
+ raw64 *= vref;
+ do_div(raw64, data_mask);
+ *mV = raw64;
+
+ return 0;
+}
+
+static int key_adc_event(struct udevice *dev,
+ struct dm_key_uclass_platdata *uc_key, int adcval)
+{
+ int val = adcval;
+
+ if (uc_key->in_volt) {
+ if (adc_raw_to_mV(dev, adcval, &val))
+ return KEY_PRESS_NONE;
+ }
+
+ debug("[%s] <%d, %d, %d>: adcval=%d -> mV=%d\n",
+ uc_key->name, uc_key->min, uc_key->center, uc_key->max,
+ adcval, val);
+
+ return (val <= uc_key->max && val >= uc_key->min) ?
KEY_PRESS_DOWN : KEY_PRESS_NONE;
}
+#endif
static int key_gpio_event(struct dm_key_uclass_platdata *uc_key)
{
@@ -108,16 +140,34 @@
static int key_core_read(struct dm_key_uclass_platdata *uc_key)
{
- unsigned int adcval;
-
if (uc_key->type == ADC_KEY) {
- if (adc_channel_single_shot("saradc",
- uc_key->channel, &adcval)) {
- KEY_ERR("%s failed to read saradc\n", uc_key->name);
+#ifdef CONFIG_ADC
+ struct udevice *dev;
+ unsigned int adcval;
+ int ret;
+
+ ret = uclass_get_device_by_name(UCLASS_ADC, "saradc", &dev);
+ if (ret) {
+ KEY_ERR("%s: No saradc\n", uc_key->name);
return KEY_NOT_EXIST;
}
- return key_adc_event(uc_key, adcval);
+ ret = adc_start_channel(dev, uc_key->channel);
+ if (ret) {
+ KEY_ERR("%s: Failed to start saradc\n", uc_key->name);
+ return KEY_NOT_EXIST;
+ }
+
+ ret = adc_channel_data(dev, uc_key->channel, &adcval);
+ if (ret) {
+ KEY_ERR("%s: Failed to read saradc, %d\n", uc_key->name, ret);
+ return KEY_NOT_EXIST;
+ }
+
+ return key_adc_event(dev, uc_key, adcval);
+#else
+ return KEY_NOT_EXIST;
+#endif
}
return (uc_key->code == KEY_POWER) ?
@@ -273,11 +323,7 @@
{
struct dm_key_uclass_platdata *uc_key;
int ret;
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
- int margin = 120;
-#else
- int margin = 30;
-#endif
+
uc_key = dev_get_uclass_platdata(dev);
if (!uc_key)
return -ENXIO;
@@ -286,11 +332,7 @@
uc_key->pre_reloc = dev_read_bool(dev, "u-boot,dm-pre-reloc") ||
dev_read_bool(dev, "u-boot,dm-spl");
- if (uc_key->type == ADC_KEY) {
- uc_key->max = uc_key->adcval + margin;
- uc_key->min = uc_key->adcval > margin ?
- uc_key->adcval - margin : 0;
- } else {
+ if (uc_key->type != ADC_KEY) {
if (uc_key->code == KEY_POWER) {
#if CONFIG_IS_ENABLED(IRQ)
int irq;
@@ -337,8 +379,9 @@
dev->parent->name);
if (uc_key->type == ADC_KEY) {
- printf(" adcval: %d (%d, %d)\n", uc_key->adcval,
- uc_key->min, uc_key->max);
+ printf(" %s: %d (%d, %d)\n",
+ uc_key->in_volt ? "volt" : " adc",
+ uc_key->center, uc_key->min, uc_key->max);
printf(" channel: %d\n\n", uc_key->channel);
} else {
const char *gpio_name =
diff --git a/u-boot/drivers/input/rk_key.c b/u-boot/drivers/input/rk_key.c
index 2619a8e..4d275e9 100644
--- a/u-boot/drivers/input/rk_key.c
+++ b/u-boot/drivers/input/rk_key.c
@@ -27,9 +27,13 @@
if (dev_read_bool(dev, "rockchip,adc_value")) {
uc_key->type = ADC_KEY;
+ uc_key->in_volt = 0;
uc_key->channel = chn[1];
- uc_key->adcval =
- dev_read_u32_default(dev, "rockchip,adc_value", 0);
+ uc_key->center = dev_read_u32_default(dev, "rockchip,adc_value", 0);
+ uc_key->min = uc_key->center - 30;
+ if (uc_key->min < 0)
+ uc_key->min = 0;
+ uc_key->max = uc_key->center + 30;
} else {
uc_key->type = GPIO_KEY;
if (dev_read_u32_array(dev, "gpios",
diff --git a/u-boot/drivers/input/spl_adc_key.c b/u-boot/drivers/input/spl_adc_key.c
index 60e0394..8aceaef 100644
--- a/u-boot/drivers/input/spl_adc_key.c
+++ b/u-boot/drivers/input/spl_adc_key.c
@@ -6,28 +6,46 @@
#include <common.h>
#include <adc.h>
+#include <div64.h>
#include <fdtdec.h>
+#include <dm/uclass.h>
DECLARE_GLOBAL_DATA_PTR;
+
+static int adc_raw_to_mV(struct udevice *dev, unsigned int raw, int *mV)
+{
+ unsigned int data_mask;
+ int ret, vref = 1800000;
+ u64 raw64 = raw;
+
+ ret = adc_data_mask(dev, &data_mask);
+ if (ret)
+ return ret;
+
+ raw64 *= vref;
+ do_div(raw64, data_mask);
+ *mV = raw64;
+
+ return 0;
+}
int key_read(int code)
{
const void *fdt_blob = gd->fdt_blob;
+ struct udevice *dev;
int adc_node, offset;
- int cd, channel, adc;
- int ret, vref, mv;
+ int t, down_threshold = -1, up_threshold;
+ int ret, num = 0, volt_margin = 150000; /* will be div 2 */
+ int mV, cd, voltage = -1;
int min, max;
- int margin;
- int range;
- uint val;
- u32 chn[2];
-#ifdef CONFIG_SARADC_ROCKCHIP_V2
- range = 4096; /* 12-bit adc */
- margin = 120;
-#else
- range = 1024; /* 10-bit adc */
- margin = 30;
-#endif
+ u32 chn[2], adc;
+
+ ret = uclass_get_device_by_name(UCLASS_ADC, "saradc", &dev);
+ if (ret) {
+ debug("No saradc device, ret=%d\n", ret);
+ return 0;
+ }
+
adc_node = fdt_node_offset_by_compatible(fdt_blob, 0, "adc-keys");
if (adc_node < 0) {
debug("No 'adc-keys' node, ret=%d\n", adc_node);
@@ -41,40 +59,87 @@
return 0;
}
- vref = fdtdec_get_int(fdt_blob, adc_node,
- "keyup-threshold-microvolt", -1);
- if (vref < 0) {
+ up_threshold = fdtdec_get_int(fdt_blob, adc_node,
+ "keyup-threshold-microvolt", -ENODATA);
+ if (up_threshold < 0) {
debug("Can't read 'keyup-threshold-microvolt'\n");
return 0;
}
- channel = chn[1];
+ /* find the expected key-code */
+ for (offset = fdt_first_subnode(fdt_blob, adc_node);
+ offset >= 0;
+ offset = fdt_next_subnode(fdt_blob, offset)) {
+ cd = fdtdec_get_int(fdt_blob, offset, "linux,code", -ENODATA);
+ if (cd < 0) {
+ debug("Can't read 'linux,code', ret=%d\n", cd);
+ return 0;
+ }
+
+ if (cd == code) {
+ voltage = fdtdec_get_int(fdt_blob, offset,
+ "press-threshold-microvolt", -ENODATA);
+ if (voltage < 0) {
+ debug("Can't read 'press-threshold-microvolt'\n");
+ return 0;
+ }
+ break;
+ }
+ }
+
+ if (voltage < 0)
+ return 0;
for (offset = fdt_first_subnode(fdt_blob, adc_node);
offset >= 0;
offset = fdt_next_subnode(fdt_blob, offset)) {
- cd = fdtdec_get_int(fdt_blob, offset, "linux,code", -1);
- if (cd == code) {
- mv = fdtdec_get_int(fdt_blob, offset,
- "press-threshold-microvolt", -1);
- if (mv < 0) {
- debug("Can't read 'press-threshold-microvolt'\n");
- return 0;
- }
-
- adc = mv / (vref / range);
- max = adc + margin;
- min = adc > margin ? adc - margin : 0;
- ret = adc_channel_single_shot("saradc", channel, &val);
- if (ret) {
- debug("Failed to read adc%d, ret=%d\n",
- channel, ret);
- return 0;
- }
-
- return (val >= min && val <= max);
+ t = fdtdec_get_int(fdt_blob, offset,
+ "press-threshold-microvolt", -ENODATA);
+ if (t < 0) {
+ debug("Can't read 'press-threshold-microvolt'\n");
+ return 0;
}
+
+ if (t > voltage && t < up_threshold)
+ up_threshold = t;
+ else if (t < voltage && t > down_threshold)
+ down_threshold = t;
+ num++;
}
- return 0;
+ /* although one node only, it doesn't mean only one key on hardware */
+ if (num == 1) {
+ down_threshold = voltage - volt_margin;
+ up_threshold = voltage + volt_margin;
+ }
+
+ /*
+ * Define the voltage range such that the button is only pressed
+ * when the voltage is closest to its own press-threshold-microvolt
+ */
+ if (down_threshold < 0)
+ min = 0;
+ else
+ min = down_threshold + (voltage - down_threshold) / 2;
+
+ max = voltage + (up_threshold - voltage) / 2;
+
+ /* now, read key status */
+ ret = adc_channel_single_shot("saradc", chn[1], &adc);
+ if (ret) {
+ debug("Failed to read adc%d, ret=%d\n", chn[1], ret);
+ return 0;
+ }
+
+ ret = adc_raw_to_mV(dev, adc, &mV);
+ if (ret) {
+ debug("Failed to convert adc to mV, ret=%d\n", ret);
+ return 0;
+ }
+
+ debug("key[%d] <%d, %d, %d>: adc=%d -> mV=%d\n",
+ code, min, voltage, max, adc, mV);
+
+ return (mV <= max && mV >= min);
}
+
diff --git a/u-boot/drivers/misc/Makefile b/u-boot/drivers/misc/Makefile
index b262618..65777a5 100644
--- a/u-boot/drivers/misc/Makefile
+++ b/u-boot/drivers/misc/Makefile
@@ -83,4 +83,12 @@
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3588-secure-otp.o
endif
+ifdef CONFIG_ROCKCHIP_RK3528
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3528-secure-otp.o
+endif
+
+ifdef CONFIG_ROCKCHIP_RK3562
+obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_SECURE_OTP) += rk3562-secure-otp.o
+endif
+
obj-$(CONFIG_$(SPL_TPL_)ROCKCHIP_HW_DECOMPRESS) += rockchip_decompress.o
diff --git a/u-boot/drivers/misc/rk3528-secure-otp.S b/u-boot/drivers/misc/rk3528-secure-otp.S
new file mode 100644
index 0000000..12b91f3
--- /dev/null
+++ b/u-boot/drivers/misc/rk3528-secure-otp.S
@@ -0,0 +1,15901 @@
+ .arch armv8-a+nosimd
+ .file "rk3528-secure-otp.c"
+ .text
+.Ltext0:
+ .cfi_sections .debug_frame
+ .section .text.rk3528_spl_rockchip_otp_stop,"ax",@progbits
+ .align 2
+ .type rk3528_spl_rockchip_otp_stop, %function
+rk3528_spl_rockchip_otp_stop:
+.LFB263:
+ .file 1 "drivers/misc/rk3528-secure-otp.c"
+ .loc 1 81 0
+ .cfi_startproc
+.LVL0:
+.LBB22:
+ .loc 1 82 0
+#APP
+// 82 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w1, 16777216
+.LVL1:
+ str w1, [x0]
+ ret
+.LBE22:
+ .cfi_endproc
+.LFE263:
+ .size rk3528_spl_rockchip_otp_stop, .-rk3528_spl_rockchip_otp_stop
+ .section .text.secure_otp_ioctl,"ax",@progbits
+ .align 2
+ .type secure_otp_ioctl, %function
+secure_otp_ioctl:
+.LFB276:
+ .loc 1 697 0
+ .cfi_startproc
+.LVL2:
+ .loc 1 700 0
+ mov x0, 27908
+.LVL3:
+ cmp x1, x0
+ bne .L6
+.LVL4:
+.LBB23:
+.LBB24:
+ .loc 1 689 0
+ mov w0, 8
+ str w0, [x2]
+.LVL5:
+.LBE24:
+.LBE23:
+ .loc 1 702 0
+ mov w0, 0
+ .loc 1 703 0
+ ret
+.LVL6:
+.L6:
+ .loc 1 698 0
+ mov w0, -22
+ .loc 1 709 0
+ ret
+ .cfi_endproc
+.LFE276:
+ .size secure_otp_ioctl, .-secure_otp_ioctl
+ .section .text.secure_otp_write,"ax",@progbits
+ .align 2
+ .type secure_otp_write, %function
+secure_otp_write:
+.LFB274:
+ .loc 1 681 0
+ .cfi_startproc
+.LVL7:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov x19, x0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -16
+ .cfi_offset 22, -8
+ .loc 1 681 0
+ mov w20, w1
+ mov x21, x2
+ mov w22, w3
+ .loc 1 682 0
+ bl dev_get_driver_data
+.LVL8:
+ .loc 1 684 0
+ ldr x4, [x0, 8]
+ mov w3, w22
+ mov x2, x21
+ mov w1, w20
+ mov x0, x19
+.LVL9:
+ .loc 1 685 0
+ ldp x21, x22, [sp, 32]
+.LVL10:
+ ldp x19, x20, [sp, 16]
+.LVL11:
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ .loc 1 684 0
+ br x4
+.LVL12:
+ .cfi_endproc
+.LFE274:
+ .size secure_otp_write, .-secure_otp_write
+ .section .text.secure_otp_read,"ax",@progbits
+ .align 2
+ .type secure_otp_read, %function
+secure_otp_read:
+.LFB273:
+ .loc 1 673 0
+ .cfi_startproc
+.LVL13:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov x19, x0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -16
+ .cfi_offset 22, -8
+ .loc 1 673 0
+ mov w20, w1
+ mov x21, x2
+ mov w22, w3
+ .loc 1 674 0
+ bl dev_get_driver_data
+.LVL14:
+ .loc 1 676 0
+ ldr x4, [x0]
+ mov w3, w22
+ mov x2, x21
+ mov w1, w20
+ mov x0, x19
+.LVL15:
+ .loc 1 677 0
+ ldp x21, x22, [sp, 32]
+.LVL16:
+ ldp x19, x20, [sp, 16]
+.LVL17:
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ .loc 1 676 0
+ br x4
+.LVL18:
+ .cfi_endproc
+.LFE273:
+ .size secure_otp_read, .-secure_otp_read
+ .section .text.rockchip_secure_otp_ofdata_to_platdata,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_ofdata_to_platdata, %function
+rockchip_secure_otp_ofdata_to_platdata:
+.LFB277:
+ .loc 1 718 0
+ .cfi_startproc
+.LVL19:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 718 0
+ mov x20, x0
+ .loc 1 719 0
+ bl dev_get_platdata
+.LVL20:
+ mov x19, x0
+.LVL21:
+ .loc 1 721 0
+ mov x0, x20
+.LVL22:
+ bl dev_read_addr_ptr
+.LVL23:
+ .loc 1 722 0
+ mov w2, 0
+ adrp x1, .LC0
+ .loc 1 721 0
+ str x0, [x19]
+ .loc 1 722 0
+ add x1, x1, :lo12:.LC0
+ mov x0, x20
+ bl dev_read_u32_default
+.LVL24:
+ .loc 1 723 0
+ uxtw x0, w0
+ str x0, [x19, 8]
+ .loc 1 724 0
+ mov w2, 0
+ mov x0, x20
+ adrp x1, .LC1
+ add x1, x1, :lo12:.LC1
+ bl dev_read_u32_default
+.LVL25:
+ .loc 1 725 0
+ uxtw x0, w0
+ str x0, [x19, 16]
+ .loc 1 726 0
+ mov w2, 0
+ mov x0, x20
+ adrp x1, .LC2
+ add x1, x1, :lo12:.LC2
+ bl dev_read_u32_default
+.LVL26:
+ .loc 1 727 0
+ uxtw x0, w0
+ str x0, [x19, 24]
+ .loc 1 730 0
+ mov w0, 0
+ ldp x19, x20, [sp, 16]
+.LVL27:
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE277:
+ .size rockchip_secure_otp_ofdata_to_platdata, .-rockchip_secure_otp_ofdata_to_platdata
+ .section .text.rk3528_spl_rockchip_otp_start,"ax",@progbits
+ .align 2
+ .type rk3528_spl_rockchip_otp_start, %function
+rk3528_spl_rockchip_otp_start:
+.LFB262:
+ .loc 1 69 0
+ .cfi_startproc
+.LVL28:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ .loc 1 69 0
+ mov x19, x1
+.LBB25:
+ .loc 1 71 0
+#APP
+// 71 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w1, 16777472
+.LVL29:
+ str w1, [x0]
+.LVL30:
+.LBE25:
+.LBB26:
+ .loc 1 72 0
+#APP
+// 72 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w0, 131074
+.LVL31:
+ str w0, [x19]
+.LBE26:
+ .loc 1 73 0
+ mov x0, 2
+ bl udelay
+.LVL32:
+.LBB27:
+ .loc 1 74 0
+#APP
+// 74 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w0, 131072
+ str w0, [x19]
+.LBE27:
+ .loc 1 76 0
+ ldr x19, [sp, 16]
+.LVL33:
+ .loc 1 75 0
+ mov x0, 1
+ .loc 1 76 0
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+ .loc 1 75 0
+ b udelay
+.LVL34:
+ .cfi_endproc
+.LFE262:
+ .size rk3528_spl_rockchip_otp_start, .-rk3528_spl_rockchip_otp_start
+ .section .text.rockchip_secure_otp_check_flag.isra.0,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_check_flag.isra.0, %function
+rockchip_secure_otp_check_flag.isra.0:
+.LFB278:
+ .loc 1 129 0
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 129 0
+ mov w19, 34465
+ mov x20, x0
+ movk w19, 0x1, lsl 16
+.L17:
+.LVL35:
+.LBB28:
+ .loc 1 136 0
+ ldr x0, [x20]
+ ldr w1, [x0, 44]
+.LVL36:
+#APP
+// 136 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL37:
+#NO_APP
+.LBE28:
+ .loc 1 137 0
+ and w0, w1, 16
+ tbz x1, 4, .L15
+ .loc 1 140 0
+ subs w19, w19, #1
+.LVL38:
+ beq .L18
+.LVL39:
+ .loc 1 146 0
+ mov x0, 1
+ bl udelay
+.LVL40:
+ b .L17
+.LVL41:
+.L18:
+ .loc 1 141 0
+ mov w0, -1
+.LVL42:
+.L15:
+ .loc 1 150 0
+ ldp x19, x20, [sp, 16]
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE278:
+ .size rockchip_secure_otp_check_flag.isra.0, .-rockchip_secure_otp_check_flag.isra.0
+ .section .text.rockchip_secure_otp_wait_flag.isra.1,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_wait_flag.isra.1, %function
+rockchip_secure_otp_wait_flag.isra.1:
+.LFB279:
+ .loc 1 106 0
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 106 0
+ mov x20, x0
+ mov w19, 20001
+.L25:
+.LVL43:
+.LBB29:
+ .loc 1 113 0
+ ldr x0, [x20]
+ ldr w0, [x0, 44]
+.LVL44:
+#APP
+// 113 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL45:
+#NO_APP
+.LBE29:
+ .loc 1 114 0
+ tbnz x0, 4, .L26
+ .loc 1 117 0
+ subs w19, w19, #1
+.LVL46:
+ beq .L27
+ .loc 1 122 0
+ mov x0, 1
+.LVL47:
+ bl udelay
+.LVL48:
+ b .L25
+.LVL49:
+.L26:
+ .loc 1 110 0
+ mov w0, 0
+.LVL50:
+.L23:
+ .loc 1 127 0
+ ldp x19, x20, [sp, 16]
+ ldp x29, x30, [sp], 32
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL51:
+.L27:
+ .cfi_restore_state
+ .loc 1 118 0
+ mov w0, -1
+.LVL52:
+ b .L23
+ .cfi_endproc
+.LFE279:
+ .size rockchip_secure_otp_wait_flag.isra.1, .-rockchip_secure_otp_wait_flag.isra.1
+ .section .text.rockchip_secure_otp_wait_status.isra.2,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_wait_status.isra.2, %function
+rockchip_secure_otp_wait_status.isra.2:
+.LFB280:
+ .loc 1 86 0
+ .cfi_startproc
+.LVL53:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov w19, w1
+ str x21, [sp, 32]
+ .cfi_offset 21, -16
+ .loc 1 86 0
+ mov x21, x0
+ mov w20, 10000
+.LVL54:
+.L30:
+.LBB36:
+ .loc 1 91 0
+ ldr x0, [x21]
+ ldr w0, [x0, 772]
+.LVL55:
+#APP
+// 91 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+.LBE36:
+ tst w0, w19
+ beq .L32
+.LBB37:
+ .loc 1 101 0
+ orr w19, w19, -65536
+.LVL56:
+#APP
+// 101 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x21]
+.LVL57:
+ str w19, [x0, 772]
+.LBE37:
+ .loc 1 103 0
+ mov w0, 0
+ b .L29
+.LVL58:
+.L32:
+ .loc 1 92 0
+ mov x0, 1
+.LVL59:
+ bl udelay
+.LVL60:
+ .loc 1 94 0
+ subs w20, w20, #1
+.LVL61:
+ bne .L30
+.LVL62:
+.LBB38:
+.LBB39:
+ .loc 1 95 0
+ adrp x1, .LANCHOR0
+ adrp x0, .LC3
+ add x1, x1, :lo12:.LANCHOR0
+ add x0, x0, :lo12:.LC3
+ bl printf
+.LVL63:
+ mov w0, -110
+.LVL64:
+.L29:
+.LBE39:
+.LBE38:
+ .loc 1 104 0
+ ldp x19, x20, [sp, 16]
+.LVL65:
+ ldr x21, [sp, 32]
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE280:
+ .size rockchip_secure_otp_wait_status.isra.2, .-rockchip_secure_otp_wait_status.isra.2
+ .section .text.rk3528_secure_otp_write_2_bytes_noecc,"ax",@progbits
+ .align 2
+ .type rk3528_secure_otp_write_2_bytes_noecc, %function
+rk3528_secure_otp_write_2_bytes_noecc:
+.LFB269:
+ .loc 1 240 0
+ .cfi_startproc
+.LVL66:
+ stp x29, x30, [sp, -96]!
+ .cfi_def_cfa_offset 96
+ .cfi_offset 29, -96
+ .cfi_offset 30, -88
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -48
+ .cfi_offset 24, -40
+ mov w24, w2
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -80
+ .cfi_offset 20, -72
+ .loc 1 244 0
+ asr w20, w24, 1
+ .loc 1 240 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -64
+ .cfi_offset 22, -56
+ and w21, w3, 65535
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -32
+ .cfi_offset 26, -24
+ mov x26, x1
+ stp x27, x28, [sp, 80]
+ .cfi_offset 27, -16
+ .cfi_offset 28, -8
+ .loc 1 242 0
+ bl dev_get_driver_data
+.LVL67:
+ .loc 1 245 0
+ cmp w20, 447
+ bgt .L43
+ mov x23, x0
+ .loc 1 249 0
+ sub w0, w20, #416
+.LVL68:
+ cmp w0, 15
+ ccmp w20, 16, 4, hi
+ beq .L37
+ .loc 1 252 0
+ adrp x0, .LC4
+ and w1, w24, -2
+ add x0, x0, :lo12:.LC4
+ bl printf
+.LVL69:
+.L43:
+ .loc 1 246 0
+ mov w0, -1
+.LVL70:
+.L35:
+ .loc 1 446 0
+ ldp x19, x20, [sp, 16]
+.LVL71:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+ ldp x25, x26, [sp, 64]
+.LVL72:
+ ldp x27, x28, [sp, 80]
+ ldp x29, x30, [sp], 96
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 28
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL73:
+.L37:
+ .cfi_restore_state
+ .loc 1 256 0
+ cbz w21, .L44
+ .loc 1 259 0
+ ldr x6, [x23, 16]
+ mov w3, w20
+ ldp x0, x2, [x26, 8]
+ ldr x1, [x26, 24]
+ blr x6
+.LVL74:
+.LBB40:
+ .loc 1 262 0
+#APP
+// 262 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 65536
+ str w1, [x0, 256]
+.LVL75:
+.LBE40:
+.LBB41:
+ .loc 1 263 0
+#APP
+// 263 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 262148
+ str w1, [x0, 32]
+.LVL76:
+.LBE41:
+.LBB42:
+ .loc 1 264 0
+#APP
+// 264 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, -65536
+ str w1, [x0, 40]
+.LVL77:
+.LBE42:
+.LBB43:
+ .loc 1 265 0
+#APP
+// 265 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL78:
+.LBE43:
+.LBB44:
+ .loc 1 266 0
+#APP
+// 266 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w22, -65534
+ str w22, [x0, 36]
+.LVL79:
+.LBE44:
+.LBB45:
+ .loc 1 267 0
+#APP
+// 267 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 252
+ str w1, [x0, 4096]
+.LVL80:
+.LBE45:
+.LBB46:
+ .loc 1 268 0
+#APP
+// 268 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL81:
+.LBE46:
+.LBB47:
+ .loc 1 269 0
+#APP
+// 269 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4104]
+.LVL82:
+.LBE47:
+.LBB48:
+ .loc 1 270 0
+#APP
+// 270 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w19, 65537
+.LBE48:
+ .loc 1 271 0
+ mov w1, 2
+.LBB49:
+ .loc 1 270 0
+ str w19, [x0, 32]
+.LBE49:
+ .loc 1 271 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL83:
+ .loc 1 272 0
+ tbz w0, #31, .L38
+.L40:
+ .loc 1 273 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC5
+.LVL84:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC5
+.L46:
+ .loc 1 406 0
+ bl printf
+.LVL85:
+.L39:
+ .loc 1 442 0
+ ldr x5, [x23, 24]
+ mov w3, w20
+ ldp x0, x2, [x26, 8]
+ ldr x1, [x26, 24]
+ blr x5
+.LVL86:
+.L44:
+ .loc 1 257 0
+ mov w0, 0
+ b .L35
+.LVL87:
+.L38:
+.LBB50:
+ .loc 1 277 0
+#APP
+// 277 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL88:
+ mov w28, -65522
+ str w28, [x0, 36]
+.LVL89:
+.LBE50:
+.LBB51:
+ .loc 1 278 0
+#APP
+// 278 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w27, 240
+ str w27, [x0, 4096]
+.LVL90:
+.LBE51:
+.LBB52:
+ .loc 1 279 0
+#APP
+// 279 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL91:
+.LBE52:
+.LBB53:
+ .loc 1 280 0
+#APP
+// 280 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w25, 122
+ str w25, [x0, 4104]
+.LVL92:
+.LBE53:
+.LBB54:
+ .loc 1 281 0
+#APP
+// 281 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 37
+ str w1, [x0, 4108]
+.LVL93:
+.LBE54:
+.LBB55:
+ .loc 1 282 0
+#APP
+// 282 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4112]
+.LVL94:
+.LBE55:
+.LBB56:
+ .loc 1 283 0
+#APP
+// 283 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4116]
+.LVL95:
+.LBE56:
+.LBB57:
+ .loc 1 284 0
+#APP
+// 284 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4120]
+.LVL96:
+.LBE57:
+.LBB58:
+ .loc 1 285 0
+#APP
+// 285 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 31
+ str w1, [x0, 4124]
+.LVL97:
+.LBE58:
+.LBB59:
+ .loc 1 286 0
+#APP
+// 286 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 11
+ str w1, [x0, 4128]
+.LVL98:
+.LBE59:
+.LBB60:
+ .loc 1 287 0
+#APP
+// 287 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 8
+ str w1, [x0, 4132]
+.LVL99:
+.LBE60:
+.LBB61:
+ .loc 1 288 0
+#APP
+// 288 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4136]
+.LVL100:
+.LBE61:
+.LBB62:
+ .loc 1 289 0
+#APP
+// 289 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4140]
+.LVL101:
+.LBE62:
+.LBB63:
+ .loc 1 290 0
+#APP
+// 290 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4144]
+.LBE63:
+.LBB64:
+ .loc 1 291 0
+ and w0, w20, 255
+#APP
+// 291 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x26]
+.LBE64:
+.LBB65:
+ .loc 1 292 0
+ ubfx x5, x24, 9, 8
+.LVL102:
+.LBE65:
+.LBB66:
+ .loc 1 291 0
+ str w0, [x1, 4148]
+.LBE66:
+.LBB67:
+ .loc 1 292 0
+#APP
+// 292 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w5, [x0, 4152]
+.LVL103:
+.LBE67:
+.LBB68:
+ .loc 1 293 0
+#APP
+// 293 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE68:
+ .loc 1 294 0
+ mov w1, 2
+.LBB69:
+ .loc 1 293 0
+ str w19, [x0, 32]
+.LBE69:
+ .loc 1 294 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL104:
+ .loc 1 295 0
+ tbnz w0, #31, .L40
+.LVL105:
+.LBB70:
+ .loc 1 300 0
+#APP
+// 300 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL106:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL107:
+.LBE70:
+.LBB71:
+ .loc 1 301 0
+#APP
+// 301 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 250
+ str w1, [x0, 4096]
+.LVL108:
+.LBE71:
+.LBB72:
+ .loc 1 302 0
+#APP
+// 302 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 9
+ str w1, [x0, 4100]
+.LVL109:
+.LBE72:
+.LBB73:
+ .loc 1 303 0
+#APP
+// 303 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE73:
+ .loc 1 304 0
+ mov w1, 2
+.LBB74:
+ .loc 1 303 0
+ str w19, [x0, 32]
+.LBE74:
+ .loc 1 304 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL110:
+ .loc 1 305 0
+ tbnz w0, #31, .L40
+.LVL111:
+.LBB75:
+ .loc 1 310 0
+#APP
+// 310 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL112:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL113:
+.LBE75:
+.LBB76:
+ .loc 1 311 0
+#APP
+// 311 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w28, [x0, 36]
+.LVL114:
+.LBE76:
+.LBB77:
+ .loc 1 312 0
+#APP
+// 312 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w27, [x0, 4096]
+.LVL115:
+.LBE77:
+.LBB78:
+ .loc 1 313 0
+#APP
+// 313 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL116:
+.LBE78:
+.LBB79:
+ .loc 1 314 0
+#APP
+// 314 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w25, [x0, 4104]
+.LVL117:
+.LBE79:
+.LBB80:
+ .loc 1 315 0
+#APP
+// 315 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 21
+ str w1, [x0, 4108]
+.LVL118:
+.LBE80:
+.LBB81:
+ .loc 1 316 0
+#APP
+// 316 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 220
+ str w1, [x0, 4112]
+.LVL119:
+.LBE81:
+.LBB82:
+ .loc 1 317 0
+#APP
+// 317 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 146
+ str w1, [x0, 4116]
+.LVL120:
+.LBE82:
+.LBB83:
+ .loc 1 318 0
+#APP
+// 318 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 121
+ str w1, [x0, 4120]
+.LVL121:
+.LBE83:
+.LBB84:
+ .loc 1 319 0
+#APP
+// 319 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 129
+ str w1, [x0, 4124]
+.LVL122:
+.LBE84:
+.LBB85:
+ .loc 1 320 0
+#APP
+// 320 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 126
+ str w1, [x0, 4128]
+.LVL123:
+.LBE85:
+.LBB86:
+ .loc 1 321 0
+#APP
+// 321 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 33
+ str w1, [x0, 4132]
+.LVL124:
+.LBE86:
+.LBB87:
+ .loc 1 322 0
+#APP
+// 322 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 17
+ str w1, [x0, 4136]
+.LVL125:
+.LBE87:
+.LBB88:
+ .loc 1 323 0
+#APP
+// 323 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 157
+ str w1, [x0, 4140]
+.LVL126:
+.LBE88:
+.LBB89:
+ .loc 1 324 0
+#APP
+// 324 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w25, 2
+ str w25, [x0, 4144]
+.LVL127:
+.LBE89:
+.LBB90:
+ .loc 1 325 0
+#APP
+// 325 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4148]
+.LVL128:
+.LBE90:
+.LBB91:
+ .loc 1 326 0
+#APP
+// 326 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 64
+ str w1, [x0, 4152]
+.LVL129:
+.LBE91:
+.LBB92:
+ .loc 1 327 0
+#APP
+// 327 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE92:
+ .loc 1 328 0
+ mov w1, w25
+.LBB93:
+ .loc 1 327 0
+ str w19, [x0, 32]
+.LBE93:
+ .loc 1 328 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL130:
+ .loc 1 329 0
+ tbnz w0, #31, .L40
+.LVL131:
+.LBB94:
+ .loc 1 334 0
+#APP
+// 334 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL132:
+ str w22, [x0, 36]
+.LVL133:
+.LBE94:
+.LBB95:
+ .loc 1 335 0
+#APP
+// 335 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 252
+ str w1, [x0, 4096]
+.LVL134:
+.LBE95:
+.LBB96:
+ .loc 1 336 0
+#APP
+// 336 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL135:
+.LBE96:
+.LBB97:
+ .loc 1 337 0
+#APP
+// 337 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 112
+ str w1, [x0, 4104]
+.LVL136:
+.LBE97:
+.LBB98:
+ .loc 1 338 0
+#APP
+// 338 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE98:
+ .loc 1 339 0
+ mov w1, w25
+.LBB99:
+ .loc 1 338 0
+ str w19, [x0, 32]
+.LBE99:
+ .loc 1 339 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL137:
+ .loc 1 340 0
+ tbnz w0, #31, .L40
+.LVL138:
+.LBB100:
+ .loc 1 345 0
+#APP
+// 345 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL139:
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL140:
+.LBE100:
+.LBB101:
+ .loc 1 346 0
+#APP
+// 346 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w22, [x0, 36]
+.LVL141:
+.LBE101:
+.LBB102:
+ .loc 1 347 0
+#APP
+// 347 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 192
+ str w1, [x0, 4096]
+.LBE102:
+.LBB103:
+ .loc 1 348 0
+ and w1, w21, 255
+.LVL142:
+#APP
+// 348 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE103:
+.LBB104:
+ .loc 1 349 0
+ lsr w21, w21, 8
+.LVL143:
+.LBE104:
+.LBB105:
+ .loc 1 348 0
+ str w1, [x0, 4100]
+.LBE105:
+.LBB106:
+ .loc 1 349 0
+#APP
+// 349 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w21, [x0, 4104]
+.LVL144:
+.LBE106:
+.LBB107:
+ .loc 1 350 0
+#APP
+// 350 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE107:
+ .loc 1 351 0
+ mov w1, w25
+.LVL145:
+.LBB108:
+ .loc 1 350 0
+ str w19, [x0, 32]
+.LBE108:
+ .loc 1 351 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL146:
+ .loc 1 352 0
+ tbnz w0, #31, .L40
+.LVL147:
+.LBB109:
+ .loc 1 357 0
+#APP
+// 357 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL148:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL149:
+.LBE109:
+.LBB110:
+ .loc 1 358 0
+#APP
+// 358 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 224
+ str w1, [x0, 4096]
+.LVL150:
+.LBE110:
+.LBB111:
+ .loc 1 359 0
+#APP
+// 359 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL151:
+.LBE111:
+.LBB112:
+ .loc 1 360 0
+#APP
+// 360 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE112:
+ .loc 1 361 0
+ mov w1, w25
+.LBB113:
+ .loc 1 360 0
+ str w19, [x0, 32]
+.LBE113:
+ .loc 1 361 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL152:
+ .loc 1 362 0
+ tbnz w0, #31, .L40
+.LVL153:
+.LBB114:
+ .loc 1 367 0
+#APP
+// 367 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL154:
+ mov w22, -65535
+ str w22, [x0, 36]
+.LVL155:
+.LBE114:
+.LBB115:
+ .loc 1 368 0
+#APP
+// 368 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL156:
+.LBE115:
+.LBB116:
+ .loc 1 369 0
+#APP
+// 369 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 255
+ str w1, [x0, 4096]
+.LVL157:
+.LBE116:
+.LBB117:
+ .loc 1 370 0
+#APP
+// 370 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL158:
+.LBE117:
+.LBB118:
+ .loc 1 371 0
+#APP
+// 371 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w21, 65537
+.LVL159:
+.LBE118:
+ .loc 1 372 0
+ mov w1, w25
+.LBB119:
+ .loc 1 371 0
+ str w21, [x0, 32]
+.LBE119:
+ .loc 1 372 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL160:
+ .loc 1 373 0
+ tbnz w0, #31, .L40
+.LVL161:
+.LBB120:
+ .loc 1 378 0
+#APP
+// 378 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL162:
+ str w22, [x0, 36]
+.LVL163:
+.LBE120:
+.LBB121:
+ .loc 1 379 0
+#APP
+// 379 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4096]
+.LVL164:
+.LBE121:
+.LBB122:
+ .loc 1 380 0
+#APP
+// 380 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w24, 191
+.LVL165:
+ str w24, [x0, 4100]
+.LVL166:
+.LBE122:
+.LBB123:
+ .loc 1 381 0
+#APP
+// 381 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE123:
+ .loc 1 382 0
+ mov w1, w25
+.LBB124:
+ .loc 1 381 0
+ str w21, [x0, 32]
+.LBE124:
+ .loc 1 382 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL167:
+ .loc 1 383 0
+ tbnz w0, #31, .L40
+ .loc 1 388 0
+ mov x0, x26
+.LVL168:
+ bl rockchip_secure_otp_check_flag.isra.0
+.LVL169:
+ .loc 1 389 0
+ tbz w0, #31, .L41
+ .loc 1 390 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC6
+.LVL170:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC6
+ b .L46
+.LVL171:
+.L41:
+.LBB125:
+ .loc 1 394 0
+#APP
+// 394 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL172:
+ str w22, [x0, 36]
+.LVL173:
+.LBE125:
+.LBB126:
+ .loc 1 395 0
+#APP
+// 395 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w19, 2
+ str w19, [x0, 4096]
+.LVL174:
+.LBE126:
+.LBB127:
+ .loc 1 396 0
+#APP
+// 396 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w24, [x0, 4100]
+.LVL175:
+.LBE127:
+.LBB128:
+ .loc 1 397 0
+#APP
+// 397 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE128:
+ .loc 1 398 0
+ mov w1, w19
+.LBB129:
+ .loc 1 397 0
+ str w21, [x0, 32]
+.LBE129:
+ .loc 1 398 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL176:
+ .loc 1 399 0
+ tbnz w0, #31, .L40
+ .loc 1 404 0
+ mov x0, x26
+.LVL177:
+ bl rockchip_secure_otp_wait_flag.isra.1
+.LVL178:
+ .loc 1 405 0
+ tbz w0, #31, .L42
+ .loc 1 406 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC7
+.LVL179:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC7
+ b .L46
+.LVL180:
+.L42:
+.LBB130:
+ .loc 1 410 0
+#APP
+// 410 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL181:
+ mov w1, -65533
+ str w1, [x0, 772]
+.LVL182:
+.LBE130:
+.LBB131:
+ .loc 1 411 0
+#APP
+// 411 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL183:
+.LBE131:
+.LBB132:
+ .loc 1 412 0
+#APP
+// 412 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w22, [x0, 36]
+.LVL184:
+.LBE132:
+.LBB133:
+ .loc 1 413 0
+#APP
+// 413 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w19, [x0, 4096]
+.LVL185:
+.LBE133:
+.LBB134:
+ .loc 1 414 0
+#APP
+// 414 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 128
+ str w1, [x0, 4100]
+.LVL186:
+.LBE134:
+.LBB135:
+ .loc 1 415 0
+#APP
+// 415 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE135:
+ .loc 1 416 0
+ mov w1, w19
+.LBB136:
+ .loc 1 415 0
+ str w21, [x0, 32]
+.LBE136:
+ .loc 1 416 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL187:
+ .loc 1 417 0
+ tbnz w0, #31, .L40
+.LVL188:
+.LBB137:
+ .loc 1 422 0
+#APP
+// 422 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL189:
+ str w22, [x0, 36]
+.LVL190:
+.LBE137:
+.LBB138:
+ .loc 1 423 0
+#APP
+// 423 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 160
+ str w1, [x0, 4096]
+.LVL191:
+.LBE138:
+.LBB139:
+ .loc 1 424 0
+#APP
+// 424 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL192:
+.LBE139:
+.LBB140:
+ .loc 1 425 0
+#APP
+// 425 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE140:
+ .loc 1 426 0
+ mov w1, w19
+.LBB141:
+ .loc 1 425 0
+ str w21, [x0, 32]
+.LBE141:
+ .loc 1 426 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL193:
+ .loc 1 427 0
+ tbnz w0, #31, .L40
+.LVL194:
+.LBB142:
+ .loc 1 432 0
+#APP
+// 432 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL195:
+ mov w1, 250
+ str w1, [x0, 4096]
+.LVL196:
+.LBE142:
+.LBB143:
+ .loc 1 433 0
+#APP
+// 433 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 9
+ str w1, [x0, 4100]
+.LVL197:
+.LBE143:
+.LBB144:
+ .loc 1 434 0
+#APP
+// 434 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE144:
+ .loc 1 435 0
+ mov w1, w19
+.LBB145:
+ .loc 1 434 0
+ str w21, [x0, 32]
+.LBE145:
+ .loc 1 435 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL198:
+ .loc 1 436 0
+ tbz w0, #31, .L39
+ b .L40
+ .cfi_endproc
+.LFE269:
+ .size rk3528_secure_otp_write_2_bytes_noecc, .-rk3528_secure_otp_write_2_bytes_noecc
+ .section .text.rockchip_secure_otp_ecc_enable,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_ecc_enable, %function
+rockchip_secure_otp_ecc_enable:
+.LFB267:
+ .loc 1 154 0
+ .cfi_startproc
+.LVL199:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ and w1, w1, 255
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+.LBB160:
+ .loc 1 157 0
+#APP
+// 157 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, 512
+ movk w3, 0xff00, lsl 16
+ str w3, [x2, 32]
+.LVL200:
+.LBE160:
+.LBB161:
+ .loc 1 158 0
+#APP
+// 158 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, -65535
+ str w3, [x2, 36]
+.LVL201:
+.LBE161:
+.LBB162:
+ .loc 1 159 0
+#APP
+// 159 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, 250
+ str w3, [x2, 4096]
+.LBE162:
+ .loc 1 160 0
+ cbz w1, .L48
+.LVL202:
+.LBB163:
+ .loc 1 161 0
+#APP
+// 161 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+.LVL203:
+ str wzr, [x1, 4100]
+.LVL204:
+.L49:
+.LBE163:
+.LBB164:
+ .loc 1 165 0
+#APP
+// 165 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+ mov w2, 65537
+ str w2, [x1, 32]
+.LBE164:
+ .loc 1 167 0
+ mov w1, 2
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL205:
+ mov w19, w0
+.LVL206:
+ .loc 1 168 0
+ tbz w0, #31, .L47
+.LVL207:
+.LBB165:
+.LBB166:
+ .loc 1 169 0
+ adrp x1, .LANCHOR2
+ adrp x0, .LC8
+.LVL208:
+ add x1, x1, :lo12:.LANCHOR2
+ add x0, x0, :lo12:.LC8
+ bl printf
+.LVL209:
+.L47:
+.LBE166:
+.LBE165:
+ .loc 1 172 0
+ mov w0, w19
+ ldr x19, [sp, 16]
+.LVL210:
+ ldp x29, x30, [sp], 32
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+ ret
+.LVL211:
+.L48:
+ .cfi_restore_state
+.LBB167:
+ .loc 1 163 0
+#APP
+// 163 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+ mov w2, 9
+ str w2, [x1, 4100]
+ b .L49
+.LBE167:
+ .cfi_endproc
+.LFE267:
+ .size rockchip_secure_otp_ecc_enable, .-rockchip_secure_otp_ecc_enable
+ .section .text.rk3528_secure_otp_read,"ax",@progbits
+ .align 2
+ .type rk3528_secure_otp_read, %function
+rk3528_secure_otp_read:
+.LFB268:
+ .loc 1 176 0
+ .cfi_startproc
+.LVL212:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .loc 1 183 0
+ asr w19, w1, 1
+ .loc 1 176 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ mov x21, x2
+ stp x23, x24, [sp, 48]
+ mov x22, x0
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ mov w23, w3
+ str x25, [sp, 64]
+ .cfi_offset 25, -16
+ .loc 1 177 0
+ bl dev_get_platdata
+.LVL213:
+ mov x20, x0
+.LVL214:
+ .loc 1 178 0
+ mov x0, x22
+.LVL215:
+ bl dev_get_driver_data
+.LVL216:
+ .loc 1 184 0
+ ldr x4, [x0, 16]
+ .loc 1 178 0
+ mov x24, x0
+.LVL217:
+ .loc 1 184 0
+ ldr x1, [x20, 24]
+ mov w3, w19
+ ldp x0, x2, [x20, 8]
+.LVL218:
+ blr x4
+.LVL219:
+ .loc 1 187 0
+ sub w1, w19, #16
+ sub w0, w19, #416
+ cmp w1, 15
+ ccmp w0, 31, 0, hi
+ bhi .L53
+ .loc 1 188 0
+ mov w1, 0
+.L65:
+ .loc 1 190 0
+ mov x0, x20
+ bl rockchip_secure_otp_ecc_enable
+.LVL220:
+.LBB168:
+ .loc 1 192 0
+#APP
+// 192 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+ mov w25, 65537
+.LBE168:
+ .loc 1 181 0
+ mov w22, 0
+.LVL221:
+.LBB169:
+ .loc 1 192 0
+ str w25, [x0, 256]
+.LBE169:
+ .loc 1 193 0
+ mov x0, 50
+ bl udelay
+.LVL222:
+.L55:
+ .loc 1 194 0
+ cbz w23, .L60
+ .loc 1 196 0
+ cmp w19, 447
+ ble .L56
+ .loc 1 197 0
+ adrp x0, .LC9
+ mov w1, w19
+ add x0, x0, :lo12:.LC9
+.L66:
+ .loc 1 205 0
+ mov w22, -1
+.LVL223:
+ .loc 1 204 0
+ bl printf
+.LVL224:
+.L52:
+ .loc 1 235 0
+ mov w0, w22
+ ldr x25, [sp, 64]
+ ldp x19, x20, [sp, 16]
+.LVL225:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL226:
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL227:
+.L53:
+ .cfi_restore_state
+ .loc 1 190 0
+ mov w1, 1
+ b .L65
+.LVL228:
+.L56:
+ .loc 1 201 0
+ sub w0, w19, #192
+ cmp w0, 31
+ ccmp w19, 16, 4, hi
+ beq .L58
+ .loc 1 201 0 is_stmt 0 discriminator 1
+ sub w0, w19, #416
+ cmp w0, 15
+ bls .L58
+ .loc 1 204 0 is_stmt 1
+ adrp x0, .LC10
+ lsl w1, w19, 1
+ add x0, x0, :lo12:.LC10
+ b .L66
+.L58:
+.LBB170:
+ .loc 1 208 0
+ orr w1, w19, -65536
+.LVL229:
+#APP
+// 208 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+.LBE170:
+ .loc 1 209 0
+ add w19, w19, 1
+.LVL230:
+.LBB171:
+ .loc 1 208 0
+ str w1, [x0, 260]
+.LBE171:
+.LBB172:
+ .loc 1 210 0
+#APP
+// 210 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+.LBE172:
+ .loc 1 212 0
+ mov w1, 4
+.LVL231:
+.LBB173:
+ .loc 1 210 0
+ str w25, [x0, 264]
+.LVL232:
+.LBE173:
+ .loc 1 212 0
+ mov x0, x20
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL233:
+ mov w22, w0
+.LVL234:
+ .loc 1 213 0
+ tbz w0, #31, .L59
+ .loc 1 214 0
+ adrp x1, .LANCHOR3
+ adrp x0, .LC11
+.LVL235:
+ add x1, x1, :lo12:.LANCHOR3
+ add x0, x0, :lo12:.LC11
+ bl printf
+.LVL236:
+.L60:
+.LBB174:
+ .loc 1 228 0
+#APP
+// 228 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+ mov w1, 65536
+.LBE174:
+ .loc 1 230 0
+ ldr x2, [x20, 16]
+ mov w3, w19
+ ldr x4, [x24, 24]
+.LBB175:
+ .loc 1 228 0
+ str w1, [x0, 256]
+.LBE175:
+ .loc 1 230 0
+ ldr x0, [x20, 8]
+ ldr x1, [x20, 24]
+ blr x4
+.LVL237:
+ .loc 1 234 0
+ b .L52
+.LVL238:
+.L59:
+.LBB176:
+ .loc 1 218 0
+ ldr x0, [x20]
+.LVL239:
+ ldrh w0, [x0, 292]
+ and w0, w0, 65535
+.LVL240:
+#APP
+// 218 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL241:
+#NO_APP
+.LBE176:
+ .loc 1 220 0
+ strb w0, [x21]
+ .loc 1 221 0
+ cmp w23, 1
+ beq .L60
+.LVL242:
+ .loc 1 222 0
+ lsr w0, w0, 8
+.LVL243:
+ .loc 1 223 0
+ sub w23, w23, #2
+.LVL244:
+ .loc 1 222 0
+ strb w0, [x21, 1]
+ add x21, x21, 2
+.LVL245:
+ b .L55
+ .cfi_endproc
+.LFE268:
+ .size rk3528_secure_otp_read, .-rk3528_secure_otp_read
+ .section .text.rk3528_secure_otp_write,"ax",@progbits
+ .align 2
+ .type rk3528_secure_otp_write, %function
+rk3528_secure_otp_write:
+.LFB272:
+ .loc 1 621 0
+ .cfi_startproc
+.LVL246:
+ stp x29, x30, [sp, -144]!
+ .cfi_def_cfa_offset 144
+ .cfi_offset 29, -144
+ .cfi_offset 30, -136
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -128
+ .cfi_offset 20, -120
+ mov w20, w1
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -112
+ .cfi_offset 22, -104
+ mov w21, w3
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -96
+ .cfi_offset 24, -88
+ mov x24, x0
+ stp x27, x28, [sp, 80]
+ stp x25, x26, [sp, 64]
+ .cfi_offset 27, -64
+ .cfi_offset 28, -56
+ .cfi_offset 25, -80
+ .cfi_offset 26, -72
+ .loc 1 621 0
+ str x2, [x29, 112]
+ .loc 1 622 0
+ bl dev_get_platdata
+.LVL247:
+ mov x28, x0
+.LVL248:
+ .loc 1 625 0
+ sxtw x0, w21
+.LVL249:
+ bl malloc_simple
+.LVL250:
+ .loc 1 628 0
+ cbnz x0, .L68
+.LVL251:
+.L115:
+ .loc 1 643 0
+ mov w27, -1
+.LVL252:
+.L67:
+ .loc 1 669 0
+ mov w0, w27
+ ldp x19, x20, [sp, 16]
+.LVL253:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL254:
+ ldp x25, x26, [sp, 64]
+ ldp x27, x28, [sp, 80]
+.LVL255:
+ ldp x29, x30, [sp], 144
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 28
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+.LVL256:
+ ret
+.LVL257:
+.L68:
+ .cfi_restore_state
+ mov x19, x0
+ .loc 1 631 0
+ sub w0, w20, #384
+.LVL258:
+ cmp w0, 63
+ bls .L70
+.LVL259:
+.L77:
+ .loc 1 649 0
+ sub w1, w20, #832
+ sub w0, w20, #32
+ cmp w1, 63
+ ccmp w0, 31, 0, hi
+ bls .L71
+ .loc 1 659 0
+ mov w0, 2
+.LBB244:
+.LBB245:
+ .loc 1 607 0
+ adrp x19, .LANCHOR4
+.LVL260:
+ add x19, x19, :lo12:.LANCHOR4
+.LBE245:
+.LBE244:
+ .loc 1 659 0
+ mov x23, 0
+ sdiv w0, w21, w0
+ str w0, [x29, 108]
+.LVL261:
+.L78:
+ .loc 1 659 0 is_stmt 0 discriminator 1
+ ldr w0, [x29, 108]
+ cmp w0, w23
+ ble .L97
+ .loc 1 660 0 is_stmt 1
+ ldr x0, [x29, 112]
+ add w21, w20, w23, lsl 1
+.LBB324:
+.LBB320:
+ .loc 1 477 0
+ asr w25, w21, 1
+.LBE320:
+.LBE324:
+ .loc 1 660 0
+ ldrh w26, [x0, x23, lsl 1]
+.LVL262:
+.LBB325:
+.LBB321:
+ .loc 1 475 0
+ mov x0, x24
+ bl dev_get_driver_data
+.LVL263:
+ str x0, [x29, 120]
+.LVL264:
+ .loc 1 478 0
+ cmp w25, 447
+ bgt .L99
+ .loc 1 482 0
+ sub w0, w25, #192
+.LVL265:
+ cmp w0, 31
+ bls .L85
+ .loc 1 485 0
+ adrp x0, .LC4
+ and w1, w21, -2
+ add x0, x0, :lo12:.LC4
+ bl printf
+.LVL266:
+.L99:
+ .loc 1 478 0
+ mov w27, -1
+ b .L84
+.LVL267:
+.L70:
+.LBE321:
+.LBE325:
+ .loc 1 633 0
+ mov w3, w21
+ mov x2, x19
+ mov w1, w20
+ mov x0, x24
+ bl rk3528_secure_otp_read
+.LVL268:
+ .loc 1 634 0
+ cbnz w0, .L115
+ mov x0, 0
+.LVL269:
+.L75:
+ .loc 1 639 0 discriminator 1
+ cmp w21, w0
+ ble .L77
+ add x0, x0, 1
+.LVL270:
+ .loc 1 640 0
+ add x1, x19, x0
+ ldrb w1, [x1, -1]
+ cbz w1, .L75
+ .loc 1 641 0
+ adrp x0, .LC12
+ add x0, x0, :lo12:.LC12
+ bl printf
+.LVL271:
+ b .L115
+.LVL272:
+.L83:
+.LBB326:
+.LBB327:
+ .loc 1 455 0
+ adds w25, w20, w19
+.LBE327:
+.LBE326:
+ .loc 1 652 0
+ ldr x0, [x29, 112]
+.LBB332:
+.LBB328:
+ .loc 1 455 0
+ and w26, w25, 1
+ mov w3, 2
+ csneg w22, w26, w26, pl
+ add x2, x29, 142
+ sub w22, w25, w22
+.LBE328:
+.LBE332:
+ .loc 1 652 0
+ ldrb w23, [x0, x19]
+.LVL273:
+.LBB333:
+.LBB329:
+ .loc 1 455 0
+ mov w1, w22
+ mov x0, x24
+ bl rk3528_secure_otp_read
+.LVL274:
+ .loc 1 456 0
+ cbnz w0, .L79
+ ldrh w3, [x29, 142]
+ .loc 1 459 0
+ cbnz w26, .L80
+.LVL275:
+ .loc 1 461 0
+ bic w3, w23, w3
+ mov w2, w25
+.LVL276:
+.L112:
+ .loc 1 464 0
+ mov x1, x28
+ mov x0, x24
+.LVL277:
+ add x19, x19, 1
+.LVL278:
+ bl rk3528_secure_otp_write_2_bytes_noecc
+.LVL279:
+ mov w27, w0
+.LVL280:
+.LBE329:
+.LBE333:
+ .loc 1 653 0
+ cbz w0, .L82
+.L98:
+ .loc 1 654 0
+ adrp x0, .LC13
+ add x0, x0, :lo12:.LC13
+.LVL281:
+.L114:
+ .loc 1 662 0
+ bl printf
+.LVL282:
+ .loc 1 663 0
+ b .L67
+.LVL283:
+.L80:
+.LBB334:
+.LBB330:
+ .loc 1 463 0
+ lsl w23, w23, 8
+.LVL284:
+ .loc 1 464 0
+ mov w2, w22
+ bic w3, w23, w3
+ b .L112
+.LVL285:
+.L71:
+.LBE330:
+.LBE334:
+ mov x19, 0
+.LVL286:
+.L82:
+ .loc 1 651 0 discriminator 1
+ cmp w21, w19
+ bgt .L83
+.LVL287:
+.L97:
+ .loc 1 629 0
+ mov w27, 0
+ b .L67
+.LVL288:
+.L85:
+.LBB335:
+.LBB322:
+ .loc 1 489 0
+ cbz w26, .L86
+ .loc 1 492 0
+ ldr x0, [x29, 120]
+ mov w3, w25
+ ldp x2, x1, [x28, 16]
+ ldr x5, [x0, 16]
+ ldr x0, [x28, 8]
+ blr x5
+.LVL289:
+.LBB246:
+ .loc 1 495 0
+#APP
+// 495 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 65536
+ str w1, [x0, 256]
+.LVL290:
+.LBE246:
+.LBB247:
+ .loc 1 496 0
+#APP
+// 496 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 262148
+ str w1, [x0, 32]
+.LVL291:
+.LBE247:
+.LBB248:
+ .loc 1 497 0
+#APP
+// 497 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65536
+ str w1, [x0, 40]
+.LVL292:
+.LBE248:
+.LBB249:
+ .loc 1 498 0
+#APP
+// 498 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL293:
+.LBE249:
+.LBB250:
+ .loc 1 499 0
+#APP
+// 499 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65522
+ str w1, [x0, 36]
+.LVL294:
+.LBE250:
+.LBB251:
+ .loc 1 500 0
+#APP
+// 500 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w3, 240
+ str w3, [x29, 100]
+.LVL295:
+ str w3, [x0, 4096]
+.LBE251:
+.LBB252:
+ .loc 1 501 0
+#APP
+// 501 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL296:
+.LBE252:
+.LBB253:
+ .loc 1 502 0
+#APP
+// 502 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 122
+ str w2, [x29, 104]
+.LVL297:
+ str w2, [x0, 4104]
+.LBE253:
+.LBB254:
+ .loc 1 503 0
+#APP
+// 503 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 37
+ str w1, [x0, 4108]
+.LVL298:
+.LBE254:
+.LBB255:
+ .loc 1 504 0
+#APP
+// 504 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4112]
+.LVL299:
+.LBE255:
+.LBB256:
+ .loc 1 505 0
+#APP
+// 505 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4116]
+.LVL300:
+.LBE256:
+.LBB257:
+ .loc 1 506 0
+#APP
+// 506 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4120]
+.LVL301:
+.LBE257:
+.LBB258:
+ .loc 1 507 0
+#APP
+// 507 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 31
+ str w1, [x0, 4124]
+.LVL302:
+.LBE258:
+.LBB259:
+ .loc 1 508 0
+#APP
+// 508 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 11
+ str w1, [x0, 4128]
+.LVL303:
+.LBE259:
+.LBB260:
+ .loc 1 509 0
+#APP
+// 509 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 8
+ str w1, [x0, 4132]
+.LVL304:
+.LBE260:
+.LBB261:
+ .loc 1 510 0
+#APP
+// 510 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4136]
+.LVL305:
+.LBE261:
+.LBB262:
+ .loc 1 511 0
+#APP
+// 511 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4140]
+.LVL306:
+.LBE262:
+.LBB263:
+ .loc 1 512 0
+#APP
+// 512 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4144]
+.LVL307:
+.LBE263:
+.LBB264:
+ .loc 1 513 0
+#APP
+// 513 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE264:
+.LBB265:
+ .loc 1 514 0
+ ubfx x21, x21, 9, 8
+.LVL308:
+.LBE265:
+.LBB266:
+ .loc 1 513 0
+ str w25, [x0, 4148]
+.LBE266:
+.LBB267:
+ .loc 1 514 0
+#APP
+// 514 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w21, [x0, 4152]
+.LVL309:
+.LBE267:
+.LBB268:
+ .loc 1 515 0
+#APP
+// 515 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w22, 65537
+.LBE268:
+ .loc 1 516 0
+ mov w1, 2
+.LBB269:
+ .loc 1 515 0
+ str w22, [x0, 32]
+.LBE269:
+ .loc 1 516 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL310:
+ mov w27, w0
+.LVL311:
+ .loc 1 517 0
+ ldp w3, w2, [x29, 100]
+ tbz w0, #31, .L87
+ .loc 1 518 0
+ adrp x0, .LC5
+.LVL312:
+ mov x1, x19
+ add x0, x0, :lo12:.LC5
+.LVL313:
+.L113:
+ .loc 1 607 0
+ bl printf
+.LVL314:
+.L88:
+.LBB270:
+ .loc 1 612 0
+#APP
+// 612 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65533
+.LBE270:
+ .loc 1 613 0
+ ldr x2, [x28, 16]
+ mov w3, w25
+.LBB271:
+ .loc 1 612 0
+ str w1, [x0, 772]
+.LBE271:
+ .loc 1 613 0
+ ldr x0, [x29, 120]
+ ldr x1, [x28, 24]
+ ldr x6, [x0, 24]
+ ldr x0, [x28, 8]
+ blr x6
+.LVL315:
+.LBE322:
+.LBE335:
+ .loc 1 661 0
+ cbz w27, .L86
+.LVL316:
+.L84:
+ .loc 1 662 0
+ adrp x0, .LC20
+ add x0, x0, :lo12:.LC20
+ b .L114
+.LVL317:
+.L87:
+.LBB336:
+.LBB323:
+.LBB272:
+ .loc 1 522 0
+#APP
+// 522 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL318:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL319:
+.LBE272:
+.LBB273:
+ .loc 1 523 0
+#APP
+// 523 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w3, [x0, 4096]
+.LVL320:
+.LBE273:
+.LBB274:
+ .loc 1 524 0
+#APP
+// 524 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL321:
+.LBE274:
+.LBB275:
+ .loc 1 525 0
+#APP
+// 525 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w2, [x0, 4104]
+.LVL322:
+.LBE275:
+.LBB276:
+ .loc 1 526 0
+#APP
+// 526 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 21
+ str w1, [x0, 4108]
+.LVL323:
+.LBE276:
+.LBB277:
+ .loc 1 527 0
+#APP
+// 527 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 220
+ str w1, [x0, 4112]
+.LVL324:
+.LBE277:
+.LBB278:
+ .loc 1 528 0
+#APP
+// 528 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 146
+ str w1, [x0, 4116]
+.LVL325:
+.LBE278:
+.LBB279:
+ .loc 1 529 0
+#APP
+// 529 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 121
+ str w1, [x0, 4120]
+.LVL326:
+.LBE279:
+.LBB280:
+ .loc 1 530 0
+#APP
+// 530 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 129
+ str w1, [x0, 4124]
+.LVL327:
+.LBE280:
+.LBB281:
+ .loc 1 531 0
+#APP
+// 531 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 126
+ str w1, [x0, 4128]
+.LVL328:
+.LBE281:
+.LBB282:
+ .loc 1 532 0
+#APP
+// 532 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 33
+ str w1, [x0, 4132]
+.LVL329:
+.LBE282:
+.LBB283:
+ .loc 1 533 0
+#APP
+// 533 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 17
+ str w1, [x0, 4136]
+.LVL330:
+.LBE283:
+.LBB284:
+ .loc 1 534 0
+#APP
+// 534 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 157
+ str w1, [x0, 4140]
+.LVL331:
+.LBE284:
+.LBB285:
+ .loc 1 535 0
+#APP
+// 535 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w21, 2
+.LVL332:
+ str w21, [x0, 4144]
+.LVL333:
+.LBE285:
+.LBB286:
+ .loc 1 536 0
+#APP
+// 536 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4148]
+.LVL334:
+.LBE286:
+.LBB287:
+ .loc 1 537 0
+#APP
+// 537 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4152]
+.LVL335:
+.LBE287:
+.LBB288:
+ .loc 1 538 0
+#APP
+// 538 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE288:
+ .loc 1 539 0
+ mov w1, w21
+.LBB289:
+ .loc 1 538 0
+ str w22, [x0, 32]
+.LBE289:
+ .loc 1 539 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL336:
+ mov w27, w0
+.LVL337:
+ .loc 1 540 0
+ tbz w0, #31, .L89
+ .loc 1 541 0
+ adrp x0, .LC14
+.LVL338:
+ mov x1, x19
+ add x0, x0, :lo12:.LC14
+ b .L113
+.LVL339:
+.L89:
+.LBB290:
+ .loc 1 545 0
+#APP
+// 545 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL340:
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL341:
+.LBE290:
+.LBB291:
+ .loc 1 546 0
+#APP
+// 546 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL342:
+.LBE291:
+.LBB292:
+ .loc 1 547 0
+#APP
+// 547 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 251
+ str w1, [x0, 4096]
+.LVL343:
+.LBE292:
+.LBB293:
+ .loc 1 548 0
+#APP
+// 548 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4100]
+.LVL344:
+.LBE293:
+.LBB294:
+ .loc 1 549 0
+#APP
+// 549 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE294:
+ .loc 1 550 0
+ mov w1, w21
+.LBB295:
+ .loc 1 549 0
+ str w22, [x0, 32]
+.LBE295:
+ .loc 1 550 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL345:
+ mov w27, w0
+.LVL346:
+ .loc 1 551 0
+ tbz w0, #31, .L90
+ .loc 1 552 0
+ adrp x0, .LC15
+.LVL347:
+ mov x1, x19
+ add x0, x0, :lo12:.LC15
+ b .L113
+.LVL348:
+.L90:
+.LBB296:
+ .loc 1 556 0
+#APP
+// 556 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL349:
+ mov w1, -65534
+ str w1, [x0, 36]
+.LVL350:
+.LBE296:
+.LBB297:
+ .loc 1 557 0
+#APP
+// 557 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 192
+ str w1, [x0, 4096]
+.LBE297:
+.LBB298:
+ .loc 1 558 0
+ and w1, w26, 255
+.LVL351:
+#APP
+// 558 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE298:
+.LBB299:
+ .loc 1 559 0
+ lsr w26, w26, 8
+.LVL352:
+.LBE299:
+.LBB300:
+ .loc 1 558 0
+ str w1, [x0, 4100]
+.LBE300:
+.LBB301:
+ .loc 1 559 0
+#APP
+// 559 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w26, [x0, 4104]
+.LVL353:
+.LBE301:
+.LBB302:
+ .loc 1 560 0
+#APP
+// 560 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE302:
+ .loc 1 561 0
+ mov w1, w21
+.LVL354:
+.LBB303:
+ .loc 1 560 0
+ str w22, [x0, 32]
+.LBE303:
+ .loc 1 561 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL355:
+ mov w27, w0
+.LVL356:
+ .loc 1 562 0
+ tbz w0, #31, .L91
+ .loc 1 563 0
+ adrp x0, .LC16
+.LVL357:
+ mov x1, x19
+ add x0, x0, :lo12:.LC16
+ b .L113
+.LVL358:
+.L91:
+.LBB304:
+ .loc 1 567 0
+#APP
+// 567 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL359:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL360:
+.LBE304:
+.LBB305:
+ .loc 1 568 0
+#APP
+// 568 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL361:
+.LBE305:
+.LBB306:
+ .loc 1 569 0
+#APP
+// 569 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 255
+ str w1, [x0, 4096]
+.LVL362:
+.LBE306:
+.LBB307:
+ .loc 1 570 0
+#APP
+// 570 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL363:
+.LBE307:
+.LBB308:
+ .loc 1 571 0
+#APP
+// 571 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE308:
+ .loc 1 572 0
+ mov w1, w21
+.LBB309:
+ .loc 1 571 0
+ str w22, [x0, 32]
+.LBE309:
+ .loc 1 572 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL364:
+ mov w27, w0
+.LVL365:
+ .loc 1 573 0
+ tbz w0, #31, .L92
+ .loc 1 574 0
+ adrp x0, .LC17
+.LVL366:
+ mov x1, x19
+ add x0, x0, :lo12:.LC17
+ b .L113
+.LVL367:
+.L92:
+.LBB310:
+ .loc 1 578 0
+#APP
+// 578 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL368:
+ mov w1, -65534
+ str w1, [x0, 36]
+.LVL369:
+.LBE310:
+.LBB311:
+ .loc 1 579 0
+#APP
+// 579 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4096]
+.LVL370:
+.LBE311:
+.LBB312:
+ .loc 1 580 0
+#APP
+// 580 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 191
+ str w1, [x0, 4100]
+.LVL371:
+.LBE312:
+.LBB313:
+ .loc 1 581 0
+#APP
+// 581 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4104]
+.LVL372:
+.LBE313:
+.LBB314:
+ .loc 1 582 0
+#APP
+// 582 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE314:
+ .loc 1 583 0
+ mov w1, w21
+.LBB315:
+ .loc 1 582 0
+ str w22, [x0, 32]
+.LBE315:
+ .loc 1 583 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL373:
+ mov w27, w0
+.LVL374:
+ .loc 1 584 0
+ tbz w0, #31, .L93
+ .loc 1 585 0
+ adrp x0, .LC18
+.LVL375:
+ mov x1, x19
+ add x0, x0, :lo12:.LC18
+ b .L113
+.LVL376:
+.L93:
+ .loc 1 589 0
+ mov x0, x28
+.LVL377:
+ bl rockchip_secure_otp_check_flag.isra.0
+.LVL378:
+ mov w27, w0
+.LVL379:
+ .loc 1 590 0
+ tbz w0, #31, .L94
+ .loc 1 591 0
+ adrp x0, .LC6
+.LVL380:
+ mov x1, x19
+ add x0, x0, :lo12:.LC6
+ b .L113
+.LVL381:
+.L94:
+.LBB316:
+ .loc 1 595 0
+#APP
+// 595 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL382:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL383:
+.LBE316:
+.LBB317:
+ .loc 1 596 0
+#APP
+// 596 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 2
+ str w1, [x0, 4096]
+.LVL384:
+.LBE317:
+.LBB318:
+ .loc 1 597 0
+#APP
+// 597 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 191
+ str w2, [x0, 4100]
+.LVL385:
+.LBE318:
+.LBB319:
+ .loc 1 598 0
+#APP
+// 598 "drivers/misc/rk3528-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 65537
+ str w2, [x0, 32]
+.LBE319:
+ .loc 1 599 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL386:
+ mov w27, w0
+.LVL387:
+ .loc 1 600 0
+ tbz w0, #31, .L95
+ .loc 1 601 0
+ adrp x0, .LC19
+.LVL388:
+ mov x1, x19
+ add x0, x0, :lo12:.LC19
+ b .L113
+.LVL389:
+.L95:
+ .loc 1 605 0
+ mov x0, x28
+.LVL390:
+ bl rockchip_secure_otp_wait_flag.isra.1
+.LVL391:
+ mov w27, w0
+.LVL392:
+ .loc 1 606 0
+ tbz w0, #31, .L88
+ .loc 1 607 0
+ adrp x0, .LC7
+.LVL393:
+ mov x1, x19
+ add x0, x0, :lo12:.LC7
+ b .L113
+.LVL394:
+.L86:
+ add x23, x23, 1
+.LVL395:
+ b .L78
+.LVL396:
+.L79:
+.LBE323:
+.LBE336:
+.LBB337:
+.LBB331:
+ .loc 1 457 0
+ mov w27, -1
+ b .L98
+.LBE331:
+.LBE337:
+ .cfi_endproc
+.LFE272:
+ .size rk3528_secure_otp_write, .-rk3528_secure_otp_write
+ .global _u_boot_list_2_driver_2_rockchip_secure_otp
+ .section .rodata.__func__.7575,"a",@progbits
+ .align 3
+ .set .LANCHOR0,. + 0
+ .type __func__.7575, %object
+ .size __func__.7575, 32
+__func__.7575:
+ .string "rockchip_secure_otp_wait_status"
+ .section .rodata.__func__.7618,"a",@progbits
+ .align 3
+ .set .LANCHOR2,. + 0
+ .type __func__.7618, %object
+ .size __func__.7618, 31
+__func__.7618:
+ .string "rockchip_secure_otp_ecc_enable"
+ .section .rodata.__func__.7636,"a",@progbits
+ .align 3
+ .set .LANCHOR3,. + 0
+ .type __func__.7636, %object
+ .size __func__.7636, 23
+__func__.7636:
+ .string "rk3528_secure_otp_read"
+ .section .rodata.__func__.7671,"a",@progbits
+ .align 3
+ .set .LANCHOR1,. + 0
+ .type __func__.7671, %object
+ .size __func__.7671, 38
+__func__.7671:
+ .string "rk3528_secure_otp_write_2_bytes_noecc"
+ .section .rodata.__func__.7892,"a",@progbits
+ .align 3
+ .set .LANCHOR4,. + 0
+ .type __func__.7892, %object
+ .size __func__.7892, 32
+__func__.7892:
+ .string "rk3528_secure_otp_write_2_bytes"
+ .section .rodata.rk3528_data,"a",@progbits
+ .align 3
+ .type rk3528_data, %object
+ .size rk3528_data, 32
+rk3528_data:
+ .xword rk3528_secure_otp_read
+ .xword rk3528_secure_otp_write
+ .xword rk3528_spl_rockchip_otp_start
+ .xword rk3528_spl_rockchip_otp_stop
+ .section .rodata.rk3528_secure_otp_read.str1.1,"aMS",@progbits,1
+.LC9:
+ .string "do not access non secure area, half word offset = %d\n"
+.LC10:
+ .string "Please input correct addr, offset(bytes) is 0x%x\n"
+.LC11:
+ .string "%s timeout during read setup\n"
+ .section .rodata.rk3528_secure_otp_write.str1.1,"aMS",@progbits,1
+.LC12:
+ .string "The zone is written.\n"
+.LC13:
+ .string "rk3528_secure_otp_write_byte_noecc error\n"
+.LC14:
+ .string "%s timeout during write setup 2\n"
+.LC15:
+ .string "%s timeout during write setup 3\n"
+.LC16:
+ .string "%s timeout during write setup 4\n"
+.LC17:
+ .string "%s timeout during write setup 5\n"
+.LC18:
+ .string "%s timeout during write setup 6\n"
+.LC19:
+ .string "%s timeout during write setup 8\n"
+.LC20:
+ .string "rk3528_secure_otp_write_2_bytes error\n"
+ .section .rodata.rk3528_secure_otp_write_2_bytes_noecc.str1.1,"aMS",@progbits,1
+.LC4:
+ .string "Please input correct addr, offset is 0x%x\n"
+.LC5:
+ .string "%s timeout during write setup 1\n"
+.LC6:
+ .string "%s timeout during write setup 7\n"
+.LC7:
+ .string "%s timeout during write setup 9\n"
+ .section .rodata.rockchip_otp_ids,"a",@progbits
+ .align 3
+ .type rockchip_otp_ids, %object
+ .size rockchip_otp_ids, 32
+rockchip_otp_ids:
+ .xword .LC22
+ .xword rk3528_data
+ .zero 16
+ .section .rodata.rockchip_secure_otp_ecc_enable.str1.1,"aMS",@progbits,1
+.LC8:
+ .string "%s timeout during ecc_enable\n"
+ .section .rodata.rockchip_secure_otp_ofdata_to_platdata.str1.1,"aMS",@progbits,1
+.LC0:
+ .string "secure_conf"
+.LC1:
+ .string "mask_addr"
+.LC2:
+ .string "cru_rst_addr"
+ .section .rodata.rockchip_secure_otp_ops,"a",@progbits
+ .align 3
+ .type rockchip_secure_otp_ops, %object
+ .size rockchip_secure_otp_ops, 32
+rockchip_secure_otp_ops:
+ .xword secure_otp_read
+ .xword secure_otp_write
+ .xword secure_otp_ioctl
+ .zero 8
+ .section .rodata.rockchip_secure_otp_wait_status.isra.2.str1.1,"aMS",@progbits,1
+.LC3:
+ .string "%s: wait init status timeout\n"
+ .section .rodata.str1.1,"aMS",@progbits,1
+.LC21:
+ .string "rockchip_secure_otp"
+.LC22:
+ .string "rockchip,rk3528-secure-otp"
+ .section .u_boot_list_2_driver_2_rockchip_secure_otp,"aw",@progbits
+ .align 2
+ .type _u_boot_list_2_driver_2_rockchip_secure_otp, %object
+ .size _u_boot_list_2_driver_2_rockchip_secure_otp, 120
+_u_boot_list_2_driver_2_rockchip_secure_otp:
+ .8byte .LC21
+ .word 36
+ .zero 4
+ .8byte rockchip_otp_ids
+ .zero 32
+ .8byte rockchip_secure_otp_ofdata_to_platdata
+ .zero 28
+ .word 32
+ .zero 8
+ .8byte rockchip_secure_otp_ops
+ .zero 8
+ .text
+.Letext0:
+ .file 2 "include/common.h"
+ .file 3 "./arch/arm/include/asm/types.h"
+ .file 4 "include/linux/types.h"
+ .file 5 "include/errno.h"
+ .file 6 "include/linux/string.h"
+ .file 7 "include/efi.h"
+ .file 8 "include/dm/device.h"
+ .file 9 "include/ide.h"
+ .file 10 "include/linux/list.h"
+ .file 11 "include/part.h"
+ .file 12 "include/flash.h"
+ .file 13 "include/lmb.h"
+ .file 14 "include/asm-generic/u-boot.h"
+ .file 15 "./arch/arm/include/asm/u-boot-arm.h"
+ .file 16 "include/linux/libfdt_env.h"
+ .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h"
+ .file 18 "include/linux/libfdt.h"
+ .file 19 "include/image.h"
+ .file 20 "./arch/arm/include/asm/global_data.h"
+ .file 21 "include/asm-generic/global_data.h"
+ .file 22 "include/dm/of.h"
+ .file 23 "include/net.h"
+ .file 24 "include/dm/uclass-id.h"
+ .file 25 "include/dm/ofnode.h"
+ .file 26 "include/malloc.h"
+ .file 27 "include/linux/compat.h"
+ .file 28 "include/dm/uclass.h"
+ .file 29 "include/asm-generic/ioctl.h"
+ .file 30 "include/misc.h"
+ .file 31 "include/rockchip-otp.h"
+ .file 32 "include/dm/read.h"
+ .file 33 "include/stdio.h"
+ .file 34 "include/linux/delay.h"
+ .file 35 "include/log.h"
+ .section .debug_info,"",@progbits
+.Ldebug_info0:
+ .4byte 0x42d0
+ .2byte 0x4
+ .4byte .Ldebug_abbrev0
+ .byte 0x8
+ .uleb128 0x1
+ .4byte .LASF458
+ .byte 0xc
+ .4byte .LASF459
+ .4byte .LASF460
+ .4byte .Ldebug_ranges0+0x6c0
+ .8byte 0
+ .4byte .Ldebug_line0
+ .uleb128 0x2
+ .4byte .LASF4
+ .byte 0x2
+ .byte 0xd
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF0
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF1
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x7
+ .4byte .LASF2
+ .uleb128 0x4
+ .4byte .LASF21
+ .byte 0x5
+ .byte 0xc
+ .4byte 0x54
+ .uleb128 0x5
+ .byte 0x4
+ .byte 0x5
+ .string "int"
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x6
+ .4byte .LASF3
+ .uleb128 0x2
+ .4byte .LASF5
+ .byte 0x3
+ .byte 0xc
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x5
+ .4byte .LASF6
+ .uleb128 0x2
+ .4byte .LASF7
+ .byte 0x3
+ .byte 0x12
+ .4byte 0x7f
+ .uleb128 0x3
+ .byte 0x4
+ .byte 0x7
+ .4byte .LASF8
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF9
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF10
+ .uleb128 0x6
+ .string "u8"
+ .byte 0x3
+ .byte 0x1f
+ .4byte 0x34
+ .uleb128 0x7
+ .4byte 0x94
+ .uleb128 0x6
+ .string "u16"
+ .byte 0x3
+ .byte 0x22
+ .4byte 0x42
+ .uleb128 0x6
+ .string "u32"
+ .byte 0x3
+ .byte 0x25
+ .4byte 0x7f
+ .uleb128 0x6
+ .string "u64"
+ .byte 0x3
+ .byte 0x28
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF11
+ .byte 0x3
+ .byte 0x31
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF12
+ .byte 0x3
+ .byte 0x32
+ .4byte 0x8d
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF13
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xee
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF14
+ .uleb128 0x7
+ .4byte 0xe7
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF15
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe7
+ .uleb128 0x2
+ .4byte .LASF16
+ .byte 0x4
+ .byte 0x59
+ .4byte 0x42
+ .uleb128 0x2
+ .4byte .LASF17
+ .byte 0x4
+ .byte 0x5b
+ .4byte 0x3b
+ .uleb128 0x2
+ .4byte .LASF18
+ .byte 0x4
+ .byte 0x69
+ .4byte 0x62
+ .uleb128 0x2
+ .4byte .LASF19
+ .byte 0x4
+ .byte 0x6b
+ .4byte 0x74
+ .uleb128 0x2
+ .4byte .LASF20
+ .byte 0x4
+ .byte 0x97
+ .4byte 0x74
+ .uleb128 0x9
+ .byte 0x8
+ .uleb128 0x4
+ .4byte .LASF22
+ .byte 0x6
+ .byte 0xb
+ .4byte 0xfa
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x2
+ .4byte .LASF23
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x156
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF24
+ .byte 0x7
+ .2byte 0x140
+ .4byte 0x14b
+ .uleb128 0xc
+ .4byte .LASF25
+ .byte 0x7
+ .2byte 0x143
+ .4byte 0x14b
+ .uleb128 0xc
+ .4byte .LASF26
+ .byte 0x7
+ .2byte 0x143
+ .4byte 0x14b
+ .uleb128 0xd
+ .4byte .LASF45
+ .byte 0xa0
+ .byte 0x8
+ .byte 0x83
+ .4byte 0x25f
+ .uleb128 0xe
+ .4byte .LASF27
+ .byte 0x8
+ .byte 0x84
+ .4byte 0x1397
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x8
+ .byte 0x85
+ .4byte 0xe1
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF29
+ .byte 0x8
+ .byte 0x86
+ .4byte 0x137
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF30
+ .byte 0x8
+ .byte 0x87
+ .4byte 0x137
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF31
+ .byte 0x8
+ .byte 0x88
+ .4byte 0x137
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF32
+ .byte 0x8
+ .byte 0x89
+ .4byte 0x133e
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF33
+ .byte 0x8
+ .byte 0x8a
+ .4byte 0x10b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF34
+ .byte 0x8
+ .byte 0x8b
+ .4byte 0x25f
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF35
+ .byte 0x8
+ .byte 0x8c
+ .4byte 0x137
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF36
+ .byte 0x8
+ .byte 0x8d
+ .4byte 0x13e6
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF37
+ .byte 0x8
+ .byte 0x8e
+ .4byte 0x137
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF38
+ .byte 0x8
+ .byte 0x8f
+ .4byte 0x137
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF39
+ .byte 0x8
+ .byte 0x90
+ .4byte 0x292
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF40
+ .byte 0x8
+ .byte 0x91
+ .4byte 0x292
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF41
+ .byte 0x8
+ .byte 0x92
+ .4byte 0x292
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x8
+ .byte 0x93
+ .4byte 0x121
+ .byte 0x90
+ .uleb128 0xe
+ .4byte .LASF43
+ .byte 0x8
+ .byte 0x94
+ .4byte 0x54
+ .byte 0x94
+ .uleb128 0xf
+ .string "seq"
+ .byte 0x8
+ .byte 0x95
+ .4byte 0x54
+ .byte 0x98
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x17a
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x26b
+ .uleb128 0x10
+ .uleb128 0xa
+ .4byte 0x10b
+ .4byte 0x277
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF44
+ .byte 0x9
+ .byte 0x10
+ .4byte 0x26c
+ .uleb128 0xa
+ .4byte 0x34
+ .4byte 0x292
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF46
+ .byte 0x10
+ .byte 0xa
+ .byte 0x16
+ .4byte 0x2b7
+ .uleb128 0xe
+ .4byte .LASF47
+ .byte 0xa
+ .byte 0x17
+ .4byte 0x2b7
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF48
+ .byte 0xa
+ .byte 0x17
+ .4byte 0x2b7
+ .byte 0x8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x292
+ .uleb128 0xd
+ .4byte .LASF49
+ .byte 0x10
+ .byte 0xb
+ .byte 0xf
+ .4byte 0x2e2
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0xb
+ .byte 0x10
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF50
+ .byte 0xb
+ .byte 0x11
+ .4byte 0x2fb
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x2bd
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x2fb
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x2e7
+ .uleb128 0xa
+ .4byte 0x2e2
+ .4byte 0x30c
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x301
+ .uleb128 0x4
+ .4byte .LASF49
+ .byte 0xb
+ .byte 0xe1
+ .4byte 0x30c
+ .uleb128 0x14
+ .2byte 0x1220
+ .byte 0xc
+ .byte 0x13
+ .4byte 0x370
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xc
+ .byte 0x14
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF52
+ .byte 0xc
+ .byte 0x15
+ .4byte 0x100
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF53
+ .byte 0xc
+ .byte 0x16
+ .4byte 0x10b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF54
+ .byte 0xc
+ .byte 0x17
+ .4byte 0x370
+ .byte 0x18
+ .uleb128 0x15
+ .4byte .LASF55
+ .byte 0xc
+ .byte 0x18
+ .4byte 0x381
+ .2byte 0x1018
+ .uleb128 0x16
+ .string "mtd"
+ .byte 0xc
+ .byte 0x31
+ .4byte 0x397
+ .2byte 0x1218
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x10b
+ .4byte 0x381
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x29
+ .4byte 0x392
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0x18
+ .4byte .LASF317
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x392
+ .uleb128 0x2
+ .4byte .LASF56
+ .byte 0xc
+ .byte 0x37
+ .4byte 0x31c
+ .uleb128 0xa
+ .4byte 0x39d
+ .4byte 0x3b3
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF57
+ .byte 0xc
+ .byte 0x39
+ .4byte 0x3a8
+ .uleb128 0x3
+ .byte 0x10
+ .byte 0x4
+ .4byte .LASF58
+ .uleb128 0xd
+ .4byte .LASF59
+ .byte 0x10
+ .byte 0xd
+ .byte 0x10
+ .4byte 0x3ea
+ .uleb128 0xe
+ .4byte .LASF60
+ .byte 0xd
+ .byte 0x11
+ .4byte 0xc4
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xd
+ .byte 0x12
+ .4byte 0xcf
+ .byte 0x8
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF61
+ .2byte 0x120
+ .byte 0xd
+ .byte 0x15
+ .4byte 0x41c
+ .uleb128 0xf
+ .string "cnt"
+ .byte 0xd
+ .byte 0x16
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xd
+ .byte 0x17
+ .4byte 0xcf
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF62
+ .byte 0xd
+ .byte 0x18
+ .4byte 0x41c
+ .byte 0x10
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x3c5
+ .4byte 0x42c
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x10
+ .byte 0
+ .uleb128 0x1a
+ .string "lmb"
+ .2byte 0x240
+ .byte 0xd
+ .byte 0x1b
+ .4byte 0x453
+ .uleb128 0xe
+ .4byte .LASF63
+ .byte 0xd
+ .byte 0x1c
+ .4byte 0x3ea
+ .byte 0
+ .uleb128 0x15
+ .4byte .LASF64
+ .byte 0xd
+ .byte 0x1d
+ .4byte 0x3ea
+ .2byte 0x120
+ .byte 0
+ .uleb128 0x1b
+ .string "lmb"
+ .byte 0xd
+ .byte 0x20
+ .4byte 0x42c
+ .uleb128 0x1c
+ .byte 0x10
+ .byte 0xe
+ .byte 0x5d
+ .4byte 0x47f
+ .uleb128 0xe
+ .4byte .LASF54
+ .byte 0xe
+ .byte 0x5e
+ .4byte 0xb9
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xe
+ .byte 0x5f
+ .4byte 0xb9
+ .byte 0x8
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF65
+ .byte 0xb0
+ .byte 0xe
+ .byte 0x1b
+ .4byte 0x57c
+ .uleb128 0xe
+ .4byte .LASF66
+ .byte 0xe
+ .byte 0x1c
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF67
+ .byte 0xe
+ .byte 0x1d
+ .4byte 0xcf
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF68
+ .byte 0xe
+ .byte 0x1e
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF69
+ .byte 0xe
+ .byte 0x1f
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF70
+ .byte 0xe
+ .byte 0x20
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF71
+ .byte 0xe
+ .byte 0x21
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF72
+ .byte 0xe
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF73
+ .byte 0xe
+ .byte 0x24
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF74
+ .byte 0xe
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF75
+ .byte 0xe
+ .byte 0x26
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF76
+ .byte 0xe
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF77
+ .byte 0xe
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF78
+ .byte 0xe
+ .byte 0x33
+ .4byte 0x282
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF79
+ .byte 0xe
+ .byte 0x34
+ .4byte 0x42
+ .byte 0x66
+ .uleb128 0xe
+ .4byte .LASF80
+ .byte 0xe
+ .byte 0x35
+ .4byte 0x3b
+ .byte 0x68
+ .uleb128 0xe
+ .4byte .LASF81
+ .byte 0xe
+ .byte 0x36
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF82
+ .byte 0xe
+ .byte 0x57
+ .4byte 0x10b
+ .byte 0x78
+ .uleb128 0xe
+ .4byte .LASF83
+ .byte 0xe
+ .byte 0x58
+ .4byte 0x10b
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF84
+ .byte 0xe
+ .byte 0x5b
+ .4byte 0x7f
+ .byte 0x88
+ .uleb128 0xe
+ .4byte .LASF85
+ .byte 0xe
+ .byte 0x60
+ .4byte 0x57c
+ .byte 0x90
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x45e
+ .4byte 0x58c
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF86
+ .byte 0xe
+ .byte 0x62
+ .4byte 0x47f
+ .uleb128 0x4
+ .4byte .LASF87
+ .byte 0xf
+ .byte 0x13
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF88
+ .byte 0xf
+ .byte 0x14
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF89
+ .byte 0xf
+ .byte 0x15
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF90
+ .byte 0xf
+ .byte 0x16
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF91
+ .byte 0xf
+ .byte 0x17
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF92
+ .byte 0xf
+ .byte 0x18
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF93
+ .byte 0xf
+ .byte 0x19
+ .4byte 0x10b
+ .uleb128 0x2
+ .4byte .LASF94
+ .byte 0x10
+ .byte 0x11
+ .4byte 0x12c
+ .uleb128 0xd
+ .4byte .LASF95
+ .byte 0x28
+ .byte 0x11
+ .byte 0x39
+ .4byte 0x674
+ .uleb128 0xe
+ .4byte .LASF96
+ .byte 0x11
+ .byte 0x3a
+ .4byte 0x5e4
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF97
+ .byte 0x11
+ .byte 0x3b
+ .4byte 0x5e4
+ .byte 0x4
+ .uleb128 0xe
+ .4byte .LASF98
+ .byte 0x11
+ .byte 0x3c
+ .4byte 0x5e4
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF99
+ .byte 0x11
+ .byte 0x3d
+ .4byte 0x5e4
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF100
+ .byte 0x11
+ .byte 0x3e
+ .4byte 0x5e4
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF101
+ .byte 0x11
+ .byte 0x3f
+ .4byte 0x5e4
+ .byte 0x14
+ .uleb128 0xe
+ .4byte .LASF102
+ .byte 0x11
+ .byte 0x40
+ .4byte 0x5e4
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF103
+ .byte 0x11
+ .byte 0x43
+ .4byte 0x5e4
+ .byte 0x1c
+ .uleb128 0xe
+ .4byte .LASF104
+ .byte 0x11
+ .byte 0x46
+ .4byte 0x5e4
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF105
+ .byte 0x11
+ .byte 0x49
+ .4byte 0x5e4
+ .byte 0x24
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF106
+ .byte 0x12
+ .2byte 0x136
+ .4byte 0x680
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x5ef
+ .uleb128 0x1d
+ .4byte .LASF107
+ .byte 0x40
+ .byte 0x13
+ .2byte 0x137
+ .4byte 0x730
+ .uleb128 0x1e
+ .4byte .LASF108
+ .byte 0x13
+ .2byte 0x138
+ .4byte 0x12c
+ .byte 0
+ .uleb128 0x1e
+ .4byte .LASF109
+ .byte 0x13
+ .2byte 0x139
+ .4byte 0x12c
+ .byte 0x4
+ .uleb128 0x1e
+ .4byte .LASF110
+ .byte 0x13
+ .2byte 0x13a
+ .4byte 0x12c
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF111
+ .byte 0x13
+ .2byte 0x13b
+ .4byte 0x12c
+ .byte 0xc
+ .uleb128 0x1e
+ .4byte .LASF112
+ .byte 0x13
+ .2byte 0x13c
+ .4byte 0x12c
+ .byte 0x10
+ .uleb128 0x1e
+ .4byte .LASF113
+ .byte 0x13
+ .2byte 0x13d
+ .4byte 0x12c
+ .byte 0x14
+ .uleb128 0x1e
+ .4byte .LASF114
+ .byte 0x13
+ .2byte 0x13e
+ .4byte 0x12c
+ .byte 0x18
+ .uleb128 0x1e
+ .4byte .LASF115
+ .byte 0x13
+ .2byte 0x13f
+ .4byte 0x116
+ .byte 0x1c
+ .uleb128 0x1e
+ .4byte .LASF116
+ .byte 0x13
+ .2byte 0x140
+ .4byte 0x116
+ .byte 0x1d
+ .uleb128 0x1e
+ .4byte .LASF117
+ .byte 0x13
+ .2byte 0x141
+ .4byte 0x116
+ .byte 0x1e
+ .uleb128 0x1e
+ .4byte .LASF118
+ .byte 0x13
+ .2byte 0x142
+ .4byte 0x116
+ .byte 0x1f
+ .uleb128 0x1e
+ .4byte .LASF119
+ .byte 0x13
+ .2byte 0x143
+ .4byte 0x730
+ .byte 0x20
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x116
+ .4byte 0x740
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF120
+ .byte 0x13
+ .2byte 0x144
+ .4byte 0x686
+ .uleb128 0x1d
+ .4byte .LASF121
+ .byte 0x30
+ .byte 0x13
+ .2byte 0x146
+ .4byte 0x7ce
+ .uleb128 0x1e
+ .4byte .LASF54
+ .byte 0x13
+ .2byte 0x147
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0x20
+ .string "end"
+ .byte 0x13
+ .2byte 0x147
+ .4byte 0x10b
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF122
+ .byte 0x13
+ .2byte 0x148
+ .4byte 0x10b
+ .byte 0x10
+ .uleb128 0x1e
+ .4byte .LASF123
+ .byte 0x13
+ .2byte 0x148
+ .4byte 0x10b
+ .byte 0x18
+ .uleb128 0x1e
+ .4byte .LASF124
+ .byte 0x13
+ .2byte 0x149
+ .4byte 0x10b
+ .byte 0x20
+ .uleb128 0x1e
+ .4byte .LASF125
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x28
+ .uleb128 0x1e
+ .4byte .LASF126
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x29
+ .uleb128 0x20
+ .string "os"
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x2a
+ .uleb128 0x1e
+ .4byte .LASF127
+ .byte 0x13
+ .2byte 0x14b
+ .4byte 0x116
+ .byte 0x2b
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF128
+ .byte 0x13
+ .2byte 0x14c
+ .4byte 0x74c
+ .uleb128 0x21
+ .4byte .LASF129
+ .2byte 0x380
+ .byte 0x13
+ .2byte 0x152
+ .4byte 0x977
+ .uleb128 0x1e
+ .4byte .LASF130
+ .byte 0x13
+ .2byte 0x158
+ .4byte 0x977
+ .byte 0
+ .uleb128 0x1e
+ .4byte .LASF131
+ .byte 0x13
+ .2byte 0x159
+ .4byte 0x740
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF132
+ .byte 0x13
+ .2byte 0x15a
+ .4byte 0x10b
+ .byte 0x48
+ .uleb128 0x1e
+ .4byte .LASF133
+ .byte 0x13
+ .2byte 0x15d
+ .4byte 0xe1
+ .byte 0x50
+ .uleb128 0x1e
+ .4byte .LASF134
+ .byte 0x13
+ .2byte 0x15f
+ .4byte 0x137
+ .byte 0x58
+ .uleb128 0x1e
+ .4byte .LASF135
+ .byte 0x13
+ .2byte 0x160
+ .4byte 0xe1
+ .byte 0x60
+ .uleb128 0x1e
+ .4byte .LASF136
+ .byte 0x13
+ .2byte 0x161
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0x1e
+ .4byte .LASF137
+ .byte 0x13
+ .2byte 0x163
+ .4byte 0x137
+ .byte 0x70
+ .uleb128 0x1e
+ .4byte .LASF138
+ .byte 0x13
+ .2byte 0x164
+ .4byte 0xe1
+ .byte 0x78
+ .uleb128 0x1e
+ .4byte .LASF139
+ .byte 0x13
+ .2byte 0x165
+ .4byte 0x54
+ .byte 0x80
+ .uleb128 0x1e
+ .4byte .LASF140
+ .byte 0x13
+ .2byte 0x167
+ .4byte 0x137
+ .byte 0x88
+ .uleb128 0x1e
+ .4byte .LASF141
+ .byte 0x13
+ .2byte 0x168
+ .4byte 0xe1
+ .byte 0x90
+ .uleb128 0x1e
+ .4byte .LASF142
+ .byte 0x13
+ .2byte 0x169
+ .4byte 0x54
+ .byte 0x98
+ .uleb128 0x1e
+ .4byte .LASF143
+ .byte 0x13
+ .2byte 0x16b
+ .4byte 0x137
+ .byte 0xa0
+ .uleb128 0x1e
+ .4byte .LASF144
+ .byte 0x13
+ .2byte 0x16c
+ .4byte 0xe1
+ .byte 0xa8
+ .uleb128 0x1e
+ .4byte .LASF145
+ .byte 0x13
+ .2byte 0x16d
+ .4byte 0x54
+ .byte 0xb0
+ .uleb128 0x20
+ .string "os"
+ .byte 0x13
+ .2byte 0x171
+ .4byte 0x7ce
+ .byte 0xb8
+ .uleb128 0x20
+ .string "ep"
+ .byte 0x13
+ .2byte 0x172
+ .4byte 0x10b
+ .byte 0xe8
+ .uleb128 0x1e
+ .4byte .LASF146
+ .byte 0x13
+ .2byte 0x174
+ .4byte 0x10b
+ .byte 0xf0
+ .uleb128 0x1e
+ .4byte .LASF147
+ .byte 0x13
+ .2byte 0x174
+ .4byte 0x10b
+ .byte 0xf8
+ .uleb128 0x22
+ .4byte .LASF148
+ .byte 0x13
+ .2byte 0x176
+ .4byte 0xfa
+ .2byte 0x100
+ .uleb128 0x22
+ .4byte .LASF149
+ .byte 0x13
+ .2byte 0x177
+ .4byte 0x10b
+ .2byte 0x108
+ .uleb128 0x22
+ .4byte .LASF150
+ .byte 0x13
+ .2byte 0x179
+ .4byte 0x10b
+ .2byte 0x110
+ .uleb128 0x22
+ .4byte .LASF151
+ .byte 0x13
+ .2byte 0x17a
+ .4byte 0x10b
+ .2byte 0x118
+ .uleb128 0x22
+ .4byte .LASF152
+ .byte 0x13
+ .2byte 0x17b
+ .4byte 0x10b
+ .2byte 0x120
+ .uleb128 0x22
+ .4byte .LASF153
+ .byte 0x13
+ .2byte 0x17c
+ .4byte 0x10b
+ .2byte 0x128
+ .uleb128 0x23
+ .string "kbd"
+ .byte 0x13
+ .2byte 0x17d
+ .4byte 0x97d
+ .2byte 0x130
+ .uleb128 0x22
+ .4byte .LASF154
+ .byte 0x13
+ .2byte 0x180
+ .4byte 0x54
+ .2byte 0x138
+ .uleb128 0x22
+ .4byte .LASF155
+ .byte 0x13
+ .2byte 0x18d
+ .4byte 0x54
+ .2byte 0x13c
+ .uleb128 0x23
+ .string "lmb"
+ .byte 0x13
+ .2byte 0x190
+ .4byte 0x42c
+ .2byte 0x140
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x740
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x58c
+ .uleb128 0x1f
+ .4byte .LASF156
+ .byte 0x13
+ .2byte 0x196
+ .4byte 0x7da
+ .uleb128 0xc
+ .4byte .LASF157
+ .byte 0x13
+ .2byte 0x198
+ .4byte 0x983
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x9ac
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x3ff
+ .byte 0
+ .uleb128 0x24
+ .4byte .LASF351
+ .byte 0x4
+ .4byte 0x54
+ .byte 0x18
+ .byte 0xe
+ .4byte 0xc0f
+ .uleb128 0x25
+ .4byte .LASF158
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF159
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF160
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF161
+ .byte 0x3
+ .uleb128 0x25
+ .4byte .LASF162
+ .byte 0x4
+ .uleb128 0x25
+ .4byte .LASF163
+ .byte 0x5
+ .uleb128 0x25
+ .4byte .LASF164
+ .byte 0x6
+ .uleb128 0x25
+ .4byte .LASF165
+ .byte 0x7
+ .uleb128 0x25
+ .4byte .LASF166
+ .byte 0x8
+ .uleb128 0x25
+ .4byte .LASF167
+ .byte 0x9
+ .uleb128 0x25
+ .4byte .LASF168
+ .byte 0xa
+ .uleb128 0x25
+ .4byte .LASF169
+ .byte 0xb
+ .uleb128 0x25
+ .4byte .LASF170
+ .byte 0xc
+ .uleb128 0x25
+ .4byte .LASF171
+ .byte 0xd
+ .uleb128 0x25
+ .4byte .LASF172
+ .byte 0xe
+ .uleb128 0x25
+ .4byte .LASF173
+ .byte 0xf
+ .uleb128 0x25
+ .4byte .LASF174
+ .byte 0x10
+ .uleb128 0x25
+ .4byte .LASF175
+ .byte 0x11
+ .uleb128 0x25
+ .4byte .LASF176
+ .byte 0x12
+ .uleb128 0x25
+ .4byte .LASF177
+ .byte 0x13
+ .uleb128 0x25
+ .4byte .LASF178
+ .byte 0x14
+ .uleb128 0x25
+ .4byte .LASF179
+ .byte 0x15
+ .uleb128 0x25
+ .4byte .LASF180
+ .byte 0x16
+ .uleb128 0x25
+ .4byte .LASF181
+ .byte 0x17
+ .uleb128 0x25
+ .4byte .LASF182
+ .byte 0x18
+ .uleb128 0x25
+ .4byte .LASF183
+ .byte 0x19
+ .uleb128 0x25
+ .4byte .LASF184
+ .byte 0x1a
+ .uleb128 0x25
+ .4byte .LASF185
+ .byte 0x1b
+ .uleb128 0x25
+ .4byte .LASF186
+ .byte 0x1c
+ .uleb128 0x25
+ .4byte .LASF187
+ .byte 0x1d
+ .uleb128 0x25
+ .4byte .LASF188
+ .byte 0x1e
+ .uleb128 0x25
+ .4byte .LASF189
+ .byte 0x1f
+ .uleb128 0x25
+ .4byte .LASF190
+ .byte 0x20
+ .uleb128 0x25
+ .4byte .LASF191
+ .byte 0x21
+ .uleb128 0x25
+ .4byte .LASF192
+ .byte 0x22
+ .uleb128 0x25
+ .4byte .LASF193
+ .byte 0x23
+ .uleb128 0x25
+ .4byte .LASF194
+ .byte 0x24
+ .uleb128 0x25
+ .4byte .LASF195
+ .byte 0x25
+ .uleb128 0x25
+ .4byte .LASF196
+ .byte 0x26
+ .uleb128 0x25
+ .4byte .LASF197
+ .byte 0x27
+ .uleb128 0x25
+ .4byte .LASF198
+ .byte 0x28
+ .uleb128 0x25
+ .4byte .LASF199
+ .byte 0x29
+ .uleb128 0x25
+ .4byte .LASF200
+ .byte 0x2a
+ .uleb128 0x25
+ .4byte .LASF201
+ .byte 0x2b
+ .uleb128 0x25
+ .4byte .LASF202
+ .byte 0x2c
+ .uleb128 0x25
+ .4byte .LASF203
+ .byte 0x2d
+ .uleb128 0x25
+ .4byte .LASF204
+ .byte 0x2e
+ .uleb128 0x25
+ .4byte .LASF205
+ .byte 0x2f
+ .uleb128 0x25
+ .4byte .LASF206
+ .byte 0x30
+ .uleb128 0x25
+ .4byte .LASF207
+ .byte 0x31
+ .uleb128 0x25
+ .4byte .LASF208
+ .byte 0x32
+ .uleb128 0x25
+ .4byte .LASF209
+ .byte 0x33
+ .uleb128 0x25
+ .4byte .LASF210
+ .byte 0x34
+ .uleb128 0x25
+ .4byte .LASF211
+ .byte 0x35
+ .uleb128 0x25
+ .4byte .LASF212
+ .byte 0x36
+ .uleb128 0x25
+ .4byte .LASF213
+ .byte 0x37
+ .uleb128 0x25
+ .4byte .LASF214
+ .byte 0x38
+ .uleb128 0x25
+ .4byte .LASF215
+ .byte 0x39
+ .uleb128 0x25
+ .4byte .LASF216
+ .byte 0x3a
+ .uleb128 0x25
+ .4byte .LASF217
+ .byte 0x3b
+ .uleb128 0x25
+ .4byte .LASF218
+ .byte 0x3c
+ .uleb128 0x25
+ .4byte .LASF219
+ .byte 0x3d
+ .uleb128 0x25
+ .4byte .LASF220
+ .byte 0x3e
+ .uleb128 0x25
+ .4byte .LASF221
+ .byte 0x3f
+ .uleb128 0x25
+ .4byte .LASF222
+ .byte 0x40
+ .uleb128 0x25
+ .4byte .LASF223
+ .byte 0x41
+ .uleb128 0x25
+ .4byte .LASF224
+ .byte 0x42
+ .uleb128 0x25
+ .4byte .LASF225
+ .byte 0x43
+ .uleb128 0x25
+ .4byte .LASF226
+ .byte 0x44
+ .uleb128 0x25
+ .4byte .LASF227
+ .byte 0x45
+ .uleb128 0x25
+ .4byte .LASF228
+ .byte 0x46
+ .uleb128 0x25
+ .4byte .LASF229
+ .byte 0x47
+ .uleb128 0x25
+ .4byte .LASF230
+ .byte 0x48
+ .uleb128 0x25
+ .4byte .LASF231
+ .byte 0x49
+ .uleb128 0x25
+ .4byte .LASF232
+ .byte 0x4a
+ .uleb128 0x25
+ .4byte .LASF233
+ .byte 0x4b
+ .uleb128 0x25
+ .4byte .LASF234
+ .byte 0x4c
+ .uleb128 0x25
+ .4byte .LASF235
+ .byte 0x4d
+ .uleb128 0x25
+ .4byte .LASF236
+ .byte 0x4e
+ .uleb128 0x25
+ .4byte .LASF237
+ .byte 0x4f
+ .uleb128 0x25
+ .4byte .LASF238
+ .byte 0x50
+ .uleb128 0x25
+ .4byte .LASF239
+ .byte 0x51
+ .uleb128 0x25
+ .4byte .LASF240
+ .byte 0x52
+ .uleb128 0x25
+ .4byte .LASF241
+ .byte 0x53
+ .uleb128 0x25
+ .4byte .LASF242
+ .byte 0x54
+ .uleb128 0x25
+ .4byte .LASF243
+ .byte 0x55
+ .uleb128 0x25
+ .4byte .LASF244
+ .byte 0x56
+ .uleb128 0x25
+ .4byte .LASF245
+ .byte 0x57
+ .uleb128 0x25
+ .4byte .LASF246
+ .byte 0x58
+ .uleb128 0x25
+ .4byte .LASF247
+ .byte 0x59
+ .uleb128 0x25
+ .4byte .LASF248
+ .byte 0x5a
+ .uleb128 0x25
+ .4byte .LASF249
+ .byte 0x5b
+ .uleb128 0x25
+ .4byte .LASF250
+ .byte 0x5c
+ .uleb128 0x25
+ .4byte .LASF251
+ .byte 0x5d
+ .uleb128 0x25
+ .4byte .LASF252
+ .byte 0x5e
+ .uleb128 0x25
+ .4byte .LASF253
+ .byte 0x5f
+ .uleb128 0x25
+ .4byte .LASF254
+ .byte 0x60
+ .uleb128 0x25
+ .4byte .LASF255
+ .byte 0x61
+ .uleb128 0x26
+ .4byte .LASF256
+ .sleb128 -1
+ .byte 0
+ .uleb128 0x27
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x23
+ .byte 0xf6
+ .4byte 0xc22
+ .uleb128 0x25
+ .4byte .LASF257
+ .byte 0x5
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF258
+ .byte 0x40
+ .byte 0x14
+ .byte 0xc
+ .4byte 0xc9b
+ .uleb128 0xe
+ .4byte .LASF259
+ .byte 0x14
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xf
+ .string "tbu"
+ .byte 0x14
+ .byte 0x23
+ .4byte 0x7f
+ .byte 0x8
+ .uleb128 0xf
+ .string "tbl"
+ .byte 0x14
+ .byte 0x24
+ .4byte 0x7f
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF260
+ .byte 0x14
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF261
+ .byte 0x14
+ .byte 0x26
+ .4byte 0x8d
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF262
+ .byte 0x14
+ .byte 0x29
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF263
+ .byte 0x14
+ .byte 0x2a
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF264
+ .byte 0x14
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF265
+ .byte 0x14
+ .byte 0x2d
+ .4byte 0x3b
+ .byte 0x38
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF266
+ .byte 0x18
+ .byte 0x15
+ .byte 0x22
+ .4byte 0xce3
+ .uleb128 0xe
+ .4byte .LASF267
+ .byte 0x15
+ .byte 0x23
+ .4byte 0xae
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF268
+ .byte 0x15
+ .byte 0x24
+ .4byte 0xae
+ .byte 0x4
+ .uleb128 0xf
+ .string "id"
+ .byte 0x15
+ .byte 0x25
+ .4byte 0xae
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF269
+ .byte 0x15
+ .byte 0x26
+ .4byte 0xae
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF270
+ .byte 0x15
+ .byte 0x27
+ .4byte 0x10b
+ .byte 0x10
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF271
+ .2byte 0x1c0
+ .byte 0x15
+ .byte 0x2a
+ .4byte 0xf0c
+ .uleb128 0xf
+ .string "bd"
+ .byte 0x15
+ .byte 0x2b
+ .4byte 0x97d
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x15
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF269
+ .byte 0x15
+ .byte 0x2d
+ .4byte 0x7f
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF272
+ .byte 0x15
+ .byte 0x2e
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF273
+ .byte 0x15
+ .byte 0x2f
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF274
+ .byte 0x15
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF275
+ .byte 0x15
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF276
+ .byte 0x15
+ .byte 0x3e
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF277
+ .byte 0x15
+ .byte 0x42
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF278
+ .byte 0x15
+ .byte 0x43
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF279
+ .byte 0x15
+ .byte 0x45
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF280
+ .byte 0x15
+ .byte 0x46
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF281
+ .byte 0x15
+ .byte 0x47
+ .4byte 0x3b
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF282
+ .byte 0x15
+ .byte 0x48
+ .4byte 0xcf
+ .byte 0x68
+ .uleb128 0xe
+ .4byte .LASF283
+ .byte 0x15
+ .byte 0x49
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF284
+ .byte 0x15
+ .byte 0x4a
+ .4byte 0x3b
+ .byte 0x78
+ .uleb128 0xe
+ .4byte .LASF285
+ .byte 0x15
+ .byte 0x4b
+ .4byte 0x3b
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF286
+ .byte 0x15
+ .byte 0x4c
+ .4byte 0x3b
+ .byte 0x88
+ .uleb128 0xe
+ .4byte .LASF287
+ .byte 0x15
+ .byte 0x4d
+ .4byte 0xf0c
+ .byte 0x90
+ .uleb128 0xe
+ .4byte .LASF288
+ .byte 0x15
+ .byte 0x50
+ .4byte 0x25f
+ .byte 0x98
+ .uleb128 0xe
+ .4byte .LASF289
+ .byte 0x15
+ .byte 0x51
+ .4byte 0x25f
+ .byte 0xa0
+ .uleb128 0xe
+ .4byte .LASF290
+ .byte 0x15
+ .byte 0x52
+ .4byte 0x292
+ .byte 0xa8
+ .uleb128 0xe
+ .4byte .LASF291
+ .byte 0x15
+ .byte 0x57
+ .4byte 0x265
+ .byte 0xb8
+ .uleb128 0xe
+ .4byte .LASF292
+ .byte 0x15
+ .byte 0x58
+ .4byte 0x137
+ .byte 0xc0
+ .uleb128 0xe
+ .4byte .LASF293
+ .byte 0x15
+ .byte 0x59
+ .4byte 0x3b
+ .byte 0xc8
+ .uleb128 0xe
+ .4byte .LASF294
+ .byte 0x15
+ .byte 0x5b
+ .4byte 0xf84
+ .byte 0xd0
+ .uleb128 0xe
+ .4byte .LASF295
+ .byte 0x15
+ .byte 0x5c
+ .4byte 0xf84
+ .byte 0xd8
+ .uleb128 0xe
+ .4byte .LASF296
+ .byte 0x15
+ .byte 0x5e
+ .4byte 0x265
+ .byte 0xe0
+ .uleb128 0xe
+ .4byte .LASF297
+ .byte 0x15
+ .byte 0x5f
+ .4byte 0x265
+ .byte 0xe8
+ .uleb128 0xf
+ .string "jt"
+ .byte 0x15
+ .byte 0x60
+ .4byte 0xf8f
+ .byte 0xf0
+ .uleb128 0xe
+ .4byte .LASF298
+ .byte 0x15
+ .byte 0x61
+ .4byte 0xf95
+ .byte 0xf8
+ .uleb128 0x15
+ .4byte .LASF299
+ .byte 0x15
+ .byte 0x6b
+ .4byte 0x7f
+ .2byte 0x118
+ .uleb128 0x15
+ .4byte .LASF300
+ .byte 0x15
+ .byte 0x6c
+ .4byte 0x7f
+ .2byte 0x11c
+ .uleb128 0x15
+ .4byte .LASF301
+ .byte 0x15
+ .byte 0x6e
+ .4byte 0x3b
+ .2byte 0x120
+ .uleb128 0x15
+ .4byte .LASF302
+ .byte 0x15
+ .byte 0x6f
+ .4byte 0x3b
+ .2byte 0x128
+ .uleb128 0x15
+ .4byte .LASF303
+ .byte 0x15
+ .byte 0x70
+ .4byte 0x3b
+ .2byte 0x130
+ .uleb128 0x15
+ .4byte .LASF304
+ .byte 0x15
+ .byte 0x79
+ .4byte 0x25f
+ .2byte 0x138
+ .uleb128 0x15
+ .4byte .LASF127
+ .byte 0x15
+ .byte 0x7a
+ .4byte 0xc22
+ .2byte 0x140
+ .uleb128 0x15
+ .4byte .LASF305
+ .byte 0x15
+ .byte 0x80
+ .4byte 0x10b
+ .2byte 0x180
+ .uleb128 0x15
+ .4byte .LASF306
+ .byte 0x15
+ .byte 0x81
+ .4byte 0x10b
+ .2byte 0x188
+ .uleb128 0x15
+ .4byte .LASF307
+ .byte 0x15
+ .byte 0x87
+ .4byte 0xc4
+ .2byte 0x190
+ .uleb128 0x15
+ .4byte .LASF308
+ .byte 0x15
+ .byte 0x8c
+ .4byte 0xc9b
+ .2byte 0x198
+ .uleb128 0x15
+ .4byte .LASF309
+ .byte 0x15
+ .byte 0x8d
+ .4byte 0x10b
+ .2byte 0x1b0
+ .uleb128 0x15
+ .4byte .LASF310
+ .byte 0x15
+ .byte 0x8e
+ .4byte 0x54
+ .2byte 0x1b8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xce3
+ .uleb128 0xd
+ .4byte .LASF311
+ .byte 0x40
+ .byte 0x16
+ .byte 0x2c
+ .4byte 0xf7f
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x16
+ .byte 0x2d
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF126
+ .byte 0x16
+ .byte 0x2e
+ .4byte 0xe1
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF312
+ .byte 0x16
+ .byte 0x2f
+ .4byte 0x12b8
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF313
+ .byte 0x16
+ .byte 0x30
+ .4byte 0xe1
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF314
+ .byte 0x16
+ .byte 0x32
+ .4byte 0x1300
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF34
+ .byte 0x16
+ .byte 0x33
+ .4byte 0xf84
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF315
+ .byte 0x16
+ .byte 0x34
+ .4byte 0xf84
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF316
+ .byte 0x16
+ .byte 0x35
+ .4byte 0xf84
+ .byte 0x38
+ .byte 0
+ .uleb128 0x7
+ .4byte 0xf12
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf12
+ .uleb128 0x18
+ .4byte .LASF318
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf8a
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0xfa5
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF319
+ .byte 0x15
+ .byte 0x9b
+ .4byte 0xce3
+ .uleb128 0x28
+ .4byte 0xfa5
+ .uleb128 0x4
+ .4byte .LASF320
+ .byte 0x2
+ .byte 0xad
+ .4byte 0x10b
+ .uleb128 0xa
+ .4byte 0x94
+ .4byte 0xfcb
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF321
+ .byte 0x2
+ .byte 0xaf
+ .4byte 0xfc0
+ .uleb128 0x4
+ .4byte .LASF322
+ .byte 0x2
+ .byte 0xb0
+ .4byte 0xfc0
+ .uleb128 0x4
+ .4byte .LASF323
+ .byte 0x2
+ .byte 0xfe
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF324
+ .byte 0x2
+ .byte 0xff
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF325
+ .byte 0x2
+ .2byte 0x100
+ .4byte 0x10b
+ .uleb128 0xd
+ .4byte .LASF326
+ .byte 0x4
+ .byte 0x17
+ .byte 0x2e
+ .4byte 0x101c
+ .uleb128 0xe
+ .4byte .LASF327
+ .byte 0x17
+ .byte 0x2f
+ .4byte 0x12c
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x29
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x1031
+ .uleb128 0x13
+ .4byte 0x25f
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1022
+ .uleb128 0xa
+ .4byte 0x94
+ .4byte 0x1047
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF328
+ .byte 0x17
+ .2byte 0x1fd
+ .4byte 0x1003
+ .uleb128 0xc
+ .4byte .LASF329
+ .byte 0x17
+ .2byte 0x1fe
+ .4byte 0x1003
+ .uleb128 0xc
+ .4byte .LASF330
+ .byte 0x17
+ .2byte 0x200
+ .4byte 0x1003
+ .uleb128 0xc
+ .4byte .LASF331
+ .byte 0x17
+ .2byte 0x205
+ .4byte 0xf95
+ .uleb128 0xc
+ .4byte .LASF332
+ .byte 0x17
+ .2byte 0x206
+ .4byte 0xf95
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x1093
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x3f
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF333
+ .byte 0x17
+ .2byte 0x207
+ .4byte 0x1083
+ .uleb128 0xc
+ .4byte .LASF334
+ .byte 0x17
+ .2byte 0x209
+ .4byte 0x1037
+ .uleb128 0xc
+ .4byte .LASF335
+ .byte 0x17
+ .2byte 0x20a
+ .4byte 0x1037
+ .uleb128 0xc
+ .4byte .LASF336
+ .byte 0x17
+ .2byte 0x20b
+ .4byte 0x1003
+ .uleb128 0xc
+ .4byte .LASF337
+ .byte 0x17
+ .2byte 0x20c
+ .4byte 0x1003
+ .uleb128 0xc
+ .4byte .LASF338
+ .byte 0x17
+ .2byte 0x20d
+ .4byte 0x101c
+ .uleb128 0xa
+ .4byte 0x101c
+ .4byte 0x10eb
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x3
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF339
+ .byte 0x17
+ .2byte 0x20e
+ .4byte 0x10db
+ .uleb128 0xc
+ .4byte .LASF340
+ .byte 0x17
+ .2byte 0x20f
+ .4byte 0x101c
+ .uleb128 0xc
+ .4byte .LASF341
+ .byte 0x17
+ .2byte 0x210
+ .4byte 0x54
+ .uleb128 0xa
+ .4byte 0x9e
+ .4byte 0x111f
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x110f
+ .uleb128 0xc
+ .4byte .LASF342
+ .byte 0x17
+ .2byte 0x211
+ .4byte 0x111f
+ .uleb128 0xc
+ .4byte .LASF343
+ .byte 0x17
+ .2byte 0x212
+ .4byte 0x111f
+ .uleb128 0xc
+ .4byte .LASF344
+ .byte 0x17
+ .2byte 0x216
+ .4byte 0x100
+ .uleb128 0xc
+ .4byte .LASF345
+ .byte 0x17
+ .2byte 0x217
+ .4byte 0x100
+ .uleb128 0xc
+ .4byte .LASF346
+ .byte 0x17
+ .2byte 0x219
+ .4byte 0x54
+ .uleb128 0xc
+ .4byte .LASF347
+ .byte 0x17
+ .2byte 0x220
+ .4byte 0x99b
+ .uleb128 0xc
+ .4byte .LASF348
+ .byte 0x17
+ .2byte 0x222
+ .4byte 0xae
+ .uleb128 0xc
+ .4byte .LASF349
+ .byte 0x17
+ .2byte 0x224
+ .4byte 0xae
+ .uleb128 0xc
+ .4byte .LASF350
+ .byte 0x17
+ .2byte 0x230
+ .4byte 0x1003
+ .uleb128 0x29
+ .4byte .LASF352
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x17
+ .2byte 0x286
+ .4byte 0x11ba
+ .uleb128 0x25
+ .4byte .LASF353
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF354
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF355
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF356
+ .byte 0x3
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF357
+ .byte 0x17
+ .2byte 0x28c
+ .4byte 0x1190
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x94
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xa3
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xae
+ .uleb128 0xd
+ .4byte .LASF27
+ .byte 0x78
+ .byte 0x8
+ .byte 0xf1
+ .4byte 0x12b3
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x8
+ .byte 0xf2
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xf
+ .string "id"
+ .byte 0x8
+ .byte 0xf3
+ .4byte 0x9ac
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF358
+ .byte 0x8
+ .byte 0xf4
+ .4byte 0x1416
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF359
+ .byte 0x8
+ .byte 0xf5
+ .4byte 0x1031
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF360
+ .byte 0x8
+ .byte 0xf6
+ .4byte 0x1031
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF361
+ .byte 0x8
+ .byte 0xf7
+ .4byte 0x1031
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF362
+ .byte 0x8
+ .byte 0xf8
+ .4byte 0x1031
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF363
+ .byte 0x8
+ .byte 0xf9
+ .4byte 0x1031
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF364
+ .byte 0x8
+ .byte 0xfa
+ .4byte 0x1031
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF365
+ .byte 0x8
+ .byte 0xfb
+ .4byte 0x1031
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF366
+ .byte 0x8
+ .byte 0xfc
+ .4byte 0x1031
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF367
+ .byte 0x8
+ .byte 0xfd
+ .4byte 0x54
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF368
+ .byte 0x8
+ .byte 0xfe
+ .4byte 0x54
+ .byte 0x5c
+ .uleb128 0xe
+ .4byte .LASF369
+ .byte 0x8
+ .byte 0xff
+ .4byte 0x54
+ .byte 0x60
+ .uleb128 0x1e
+ .4byte .LASF370
+ .byte 0x8
+ .2byte 0x100
+ .4byte 0x54
+ .byte 0x64
+ .uleb128 0x20
+ .string "ops"
+ .byte 0x8
+ .2byte 0x101
+ .4byte 0x265
+ .byte 0x68
+ .uleb128 0x1e
+ .4byte .LASF42
+ .byte 0x8
+ .2byte 0x102
+ .4byte 0x121
+ .byte 0x70
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x11d8
+ .uleb128 0x2
+ .4byte .LASF312
+ .byte 0x16
+ .byte 0xf
+ .4byte 0xae
+ .uleb128 0xd
+ .4byte .LASF371
+ .byte 0x20
+ .byte 0x16
+ .byte 0x19
+ .4byte 0x1300
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x16
+ .byte 0x1a
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF372
+ .byte 0x16
+ .byte 0x1b
+ .4byte 0x54
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF373
+ .byte 0x16
+ .byte 0x1c
+ .4byte 0x137
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF47
+ .byte 0x16
+ .byte 0x1d
+ .4byte 0x1300
+ .byte 0x18
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12c3
+ .uleb128 0x2a
+ .string "gd"
+ .byte 0x16
+ .byte 0x57
+ .4byte 0x1310
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xfb0
+ .uleb128 0x2b
+ .4byte .LASF461
+ .byte 0x8
+ .byte 0x19
+ .byte 0x33
+ .4byte 0x1338
+ .uleb128 0x2c
+ .string "np"
+ .byte 0x19
+ .byte 0x34
+ .4byte 0x1338
+ .uleb128 0x2d
+ .4byte .LASF374
+ .byte 0x19
+ .byte 0x35
+ .4byte 0xf3
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf7f
+ .uleb128 0x2
+ .4byte .LASF375
+ .byte 0x19
+ .byte 0x36
+ .4byte 0x1316
+ .uleb128 0xc
+ .4byte .LASF376
+ .byte 0x1a
+ .2byte 0x3ba
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF377
+ .byte 0x1a
+ .2byte 0x3bb
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF378
+ .byte 0x1a
+ .2byte 0x3bc
+ .4byte 0x10b
+ .uleb128 0xd
+ .4byte .LASF379
+ .byte 0x4
+ .byte 0x1b
+ .byte 0xd
+ .4byte 0x1386
+ .uleb128 0xf
+ .string "pid"
+ .byte 0x1b
+ .byte 0xe
+ .4byte 0x54
+ .byte 0
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF380
+ .byte 0x1b
+ .byte 0x11
+ .4byte 0x1391
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x136d
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12b3
+ .uleb128 0xd
+ .4byte .LASF36
+ .byte 0x38
+ .byte 0x1c
+ .byte 0x23
+ .4byte 0x13e6
+ .uleb128 0xe
+ .4byte .LASF35
+ .byte 0x1c
+ .byte 0x24
+ .4byte 0x137
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF381
+ .byte 0x1c
+ .byte 0x25
+ .4byte 0x1500
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF382
+ .byte 0x1c
+ .byte 0x26
+ .4byte 0x292
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF41
+ .byte 0x1c
+ .byte 0x27
+ .4byte 0x292
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF383
+ .byte 0x1c
+ .byte 0x29
+ .4byte 0x2b7
+ .byte 0x30
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x139d
+ .uleb128 0xd
+ .4byte .LASF384
+ .byte 0x10
+ .byte 0x8
+ .byte 0xb8
+ .4byte 0x1411
+ .uleb128 0xe
+ .4byte .LASF385
+ .byte 0x8
+ .byte 0xb9
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF386
+ .byte 0x8
+ .byte 0xba
+ .4byte 0x10b
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x13ec
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1411
+ .uleb128 0xd
+ .4byte .LASF387
+ .byte 0x80
+ .byte 0x1c
+ .byte 0x57
+ .4byte 0x1500
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x1c
+ .byte 0x58
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xf
+ .string "id"
+ .byte 0x1c
+ .byte 0x59
+ .4byte 0x9ac
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF388
+ .byte 0x1c
+ .byte 0x5a
+ .4byte 0x1031
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF389
+ .byte 0x1c
+ .byte 0x5b
+ .4byte 0x1031
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF390
+ .byte 0x1c
+ .byte 0x5c
+ .4byte 0x1031
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF391
+ .byte 0x1c
+ .byte 0x5d
+ .4byte 0x1031
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF392
+ .byte 0x1c
+ .byte 0x5e
+ .4byte 0x1031
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF364
+ .byte 0x1c
+ .byte 0x5f
+ .4byte 0x1031
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF365
+ .byte 0x1c
+ .byte 0x60
+ .4byte 0x1031
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF393
+ .byte 0x1c
+ .byte 0x61
+ .4byte 0x1515
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF394
+ .byte 0x1c
+ .byte 0x62
+ .4byte 0x1515
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF367
+ .byte 0x1c
+ .byte 0x63
+ .4byte 0x54
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF395
+ .byte 0x1c
+ .byte 0x64
+ .4byte 0x54
+ .byte 0x5c
+ .uleb128 0xe
+ .4byte .LASF396
+ .byte 0x1c
+ .byte 0x65
+ .4byte 0x54
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF369
+ .byte 0x1c
+ .byte 0x66
+ .4byte 0x54
+ .byte 0x64
+ .uleb128 0xe
+ .4byte .LASF370
+ .byte 0x1c
+ .byte 0x67
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0xf
+ .string "ops"
+ .byte 0x1c
+ .byte 0x68
+ .4byte 0x265
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x1c
+ .byte 0x69
+ .4byte 0x121
+ .byte 0x78
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x141c
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x1515
+ .uleb128 0x13
+ .4byte 0x13e6
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1506
+ .uleb128 0x4
+ .4byte .LASF397
+ .byte 0x1d
+ .byte 0x49
+ .4byte 0x7f
+ .uleb128 0x24
+ .4byte .LASF398
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1e
+ .byte 0x15
+ .4byte 0x1555
+ .uleb128 0x25
+ .4byte .LASF399
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF400
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF401
+ .byte 0x4
+ .uleb128 0x25
+ .4byte .LASF402
+ .byte 0x8
+ .uleb128 0x25
+ .4byte .LASF403
+ .byte 0x10
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF404
+ .byte 0x20
+ .byte 0x1e
+ .byte 0x61
+ .4byte 0x1592
+ .uleb128 0xe
+ .4byte .LASF405
+ .byte 0x1e
+ .byte 0x6b
+ .4byte 0x15b5
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF406
+ .byte 0x1e
+ .byte 0x75
+ .4byte 0x15d9
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF407
+ .byte 0x1e
+ .byte 0x7f
+ .4byte 0x15f8
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF408
+ .byte 0x1e
+ .byte 0x8c
+ .4byte 0x1626
+ .byte 0x18
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x1555
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15b5
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1597
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15d9
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x265
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x15bb
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15f8
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x3b
+ .uleb128 0x13
+ .4byte 0x137
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x15df
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x1626
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x15fe
+ .uleb128 0xd
+ .4byte .LASF409
+ .byte 0x20
+ .byte 0x1f
+ .byte 0x5e
+ .4byte 0x1669
+ .uleb128 0xe
+ .4byte .LASF60
+ .byte 0x1f
+ .byte 0x5f
+ .4byte 0x137
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF410
+ .byte 0x1f
+ .byte 0x60
+ .4byte 0x3b
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF411
+ .byte 0x1f
+ .byte 0x61
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF412
+ .byte 0x1f
+ .byte 0x62
+ .4byte 0x3b
+ .byte 0x18
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF413
+ .byte 0x20
+ .byte 0x1
+ .byte 0xf
+ .4byte 0x16a6
+ .uleb128 0xe
+ .4byte .LASF405
+ .byte 0x1
+ .byte 0x10
+ .4byte 0x15b5
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF406
+ .byte 0x1
+ .byte 0x11
+ .4byte 0x15d9
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF414
+ .byte 0x1
+ .byte 0x12
+ .4byte 0x16c5
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF415
+ .byte 0x1
+ .byte 0x15
+ .4byte 0x16c5
+ .byte 0x18
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x1669
+ .uleb128 0x2e
+ .4byte 0x16c5
+ .uleb128 0x13
+ .4byte 0x11d2
+ .uleb128 0x13
+ .4byte 0x11d2
+ .uleb128 0x13
+ .4byte 0x3b
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x16ab
+ .uleb128 0x2f
+ .4byte .LASF416
+ .byte 0x1
+ .2byte 0x2c7
+ .4byte 0x1592
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rockchip_secure_otp_ops
+ .uleb128 0x2f
+ .4byte .LASF417
+ .byte 0x1
+ .2byte 0x2dc
+ .4byte 0x16a6
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rk3528_data
+ .uleb128 0xa
+ .4byte 0x1411
+ .4byte 0x1707
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x16f7
+ .uleb128 0x2f
+ .4byte .LASF418
+ .byte 0x1
+ .2byte 0x2e3
+ .4byte 0x1707
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rockchip_otp_ids
+ .uleb128 0x30
+ .4byte .LASF419
+ .byte 0x1
+ .2byte 0x2eb
+ .4byte 0x11d8
+ .uleb128 0x9
+ .byte 0x3
+ .8byte _u_boot_list_2_driver_2_rockchip_secure_otp
+ .uleb128 0x31
+ .4byte .LASF420
+ .byte 0x1
+ .2byte 0x2cd
+ .4byte 0x54
+ .8byte .LFB277
+ .8byte .LFE277-.LFB277
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1825
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2cd
+ .4byte 0x25f
+ .4byte .LLST14
+ .uleb128 0x33
+ .string "otp"
+ .byte 0x1
+ .2byte 0x2cf
+ .4byte 0x1825
+ .4byte .LLST15
+ .uleb128 0x34
+ .8byte .LVL20
+ .4byte 0x4283
+ .4byte 0x1792
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL23
+ .4byte 0x428f
+ .4byte 0x17aa
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL24
+ .4byte 0x429a
+ .4byte 0x17d4
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL25
+ .4byte 0x429a
+ .4byte 0x17fe
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC1
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL26
+ .4byte 0x429a
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC2
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x162c
+ .uleb128 0x31
+ .4byte .LASF421
+ .byte 0x1
+ .2byte 0x2b6
+ .4byte 0x54
+ .8byte .LFB276
+ .8byte .LFE276-.LFB276
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x18ac
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2b6
+ .4byte 0x25f
+ .4byte .LLST1
+ .uleb128 0x37
+ .4byte .LASF422
+ .byte 0x1
+ .2byte 0x2b7
+ .4byte 0x3b
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x38
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2b8
+ .4byte 0x137
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x33
+ .string "ret"
+ .byte 0x1
+ .2byte 0x2ba
+ .4byte 0x54
+ .4byte .LLST2
+ .uleb128 0x39
+ .4byte 0x18ac
+ .8byte .LBB23
+ .8byte .LBE23-.LBB23
+ .byte 0x1
+ .2byte 0x2be
+ .uleb128 0x3a
+ .4byte 0x18bd
+ .4byte .LLST3
+ .byte 0
+ .byte 0
+ .uleb128 0x3b
+ .4byte .LASF430
+ .byte 0x1
+ .2byte 0x2af
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x18ca
+ .uleb128 0x3c
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2af
+ .4byte 0x11d2
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF423
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x54
+ .8byte .LFB274
+ .8byte .LFE274-.LFB274
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x197b
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x25f
+ .4byte .LLST4
+ .uleb128 0x3d
+ .4byte .LASF424
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x54
+ .4byte .LLST5
+ .uleb128 0x32
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2a8
+ .4byte 0x265
+ .4byte .LLST6
+ .uleb128 0x3d
+ .4byte .LASF51
+ .byte 0x1
+ .2byte 0x2a8
+ .4byte 0x54
+ .4byte .LLST7
+ .uleb128 0x3e
+ .4byte .LASF425
+ .byte 0x1
+ .2byte 0x2aa
+ .4byte 0x197b
+ .4byte .LLST8
+ .uleb128 0x34
+ .8byte .LVL8
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+ .byte 0
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+ .uleb128 0x1
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+ .uleb128 0x1
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+ .uleb128 0x1
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+ .uleb128 0x3
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+ .uleb128 0x1
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+ .byte 0
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+ .byte 0x1
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+ .8byte .LFE273-.LFB273
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1a32
+ .uleb128 0x32
+ .string "dev"
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+ .2byte 0x29f
+ .4byte 0x25f
+ .4byte .LLST9
+ .uleb128 0x3d
+ .4byte .LASF424
+ .byte 0x1
+ .2byte 0x29f
+ .4byte 0x54
+ .4byte .LLST10
+ .uleb128 0x32
+ .string "buf"
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+ .2byte 0x2a0
+ .4byte 0x137
+ .4byte .LLST11
+ .uleb128 0x3d
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+ .byte 0x1
+ .2byte 0x2a0
+ .4byte 0x54
+ .4byte .LLST12
+ .uleb128 0x3e
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+ .byte 0x1
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+ .4byte 0x1a0b
+ .uleb128 0x35
+ .uleb128 0x1
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+ .string "dev"
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+ .4byte 0x25f
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+ .uleb128 0x3d
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+ .byte 0x1
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+ .4byte 0x54
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+ .uleb128 0x32
+ .string "buf"
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+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x54
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+ .uleb128 0x33
+ .string "otp"
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+ .byte 0x1
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+ .byte 0x1
+ .2byte 0x271
+ .4byte 0xfa
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+ .uleb128 0x33
+ .string "i"
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+ .2byte 0x272
+ .4byte 0x54
+ .4byte .LLST77
+ .uleb128 0x33
+ .string "ret"
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+ .2byte 0x272
+ .4byte 0x54
+ .4byte .LLST78
+ .uleb128 0x40
+ .4byte 0x255e
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+ .4byte .Ldebug_ranges0+0x3f0
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+ .4byte 0x2430
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+ .uleb128 0x3a
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+ .4byte .LLST88
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+ .4byte 0x27ed
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+ .uleb128 0x1
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+ .byte 0
+ .uleb128 0x34
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+ .4byte .LASF429
+ .byte 0x1
+ .2byte 0x1c4
+ .4byte 0xa3
+ .uleb128 0x4c
+ .string "ret"
+ .byte 0x1
+ .2byte 0x1c5
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x52
+ .4byte .LASF435
+ .byte 0x1
+ .byte 0xed
+ .4byte 0x54
+ .8byte .LFB269
+ .8byte .LFE269-.LFB269
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x39ba
+ .uleb128 0x53
+ .string "dev"
+ .byte 0x1
+ .byte 0xed
+ .4byte 0x25f
+ .4byte .LLST30
+ .uleb128 0x53
+ .string "otp"
+ .byte 0x1
+ .byte 0xee
+ .4byte 0x1825
+ .4byte .LLST31
+ .uleb128 0x54
+ .4byte .LASF424
+ .byte 0x1
+ .byte 0xef
+ .4byte 0x54
+ .4byte .LLST32
+ .uleb128 0x54
+ .4byte .LASF386
+ .byte 0x1
+ .byte 0xef
+ .4byte 0xa3
+ .4byte .LLST33
+ .uleb128 0x55
+ .string "ret"
+ .byte 0x1
+ .byte 0xf1
+ .4byte 0x54
+ .4byte .LLST34
+ .uleb128 0x56
+ .4byte .LASF425
+ .byte 0x1
+ .byte 0xf2
+ .4byte 0x197b
+ .4byte .LLST35
+ .uleb128 0x57
+ .4byte .LASF432
+ .4byte 0x39ca
+ .uleb128 0x9
+ .byte 0x3
+ .8byte __func__.7671
+ .uleb128 0x58
+ .4byte .LASF438
+ .byte 0x1
+ .2byte 0x1b9
+ .8byte .L39
+ .uleb128 0x45
+ .8byte .LBB40
+ .8byte .LBE40-.LBB40
+ .4byte 0x2b76
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x106
+ .4byte 0xae
+ .4byte .LLST36
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB41
+ .8byte .LBE41-.LBB41
+ .4byte 0x2b9c
+ .uleb128 0x33
+ .string "__v"
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+ .2byte 0x107
+ .4byte 0xae
+ .4byte .LLST37
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB42
+ .8byte .LBE42-.LBB42
+ .4byte 0x2bc2
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x108
+ .4byte 0xae
+ .4byte .LLST38
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB43
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+ .4byte 0x2be8
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x109
+ .4byte 0xae
+ .4byte .LLST39
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB44
+ .8byte .LBE44-.LBB44
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+ .uleb128 0x33
+ .string "__v"
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+ .2byte 0x10a
+ .4byte 0xae
+ .4byte .LLST40
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB45
+ .8byte .LBE45-.LBB45
+ .4byte 0x2c34
+ .uleb128 0x33
+ .string "__v"
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+ .2byte 0x10b
+ .4byte 0xae
+ .4byte .LLST41
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB46
+ .8byte .LBE46-.LBB46
+ .4byte 0x2c5a
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x10c
+ .4byte 0xae
+ .4byte .LLST42
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB47
+ .8byte .LBE47-.LBB47
+ .4byte 0x2c80
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x10d
+ .4byte 0xae
+ .4byte .LLST43
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0
+ .4byte 0x2c9a
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x10e
+ .4byte 0xae
+ .4byte .LLST44
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB50
+ .8byte .LBE50-.LBB50
+ .4byte 0x2cbf
+ .uleb128 0x59
+ .string "__v"
+ .byte 0x1
+ .2byte 0x115
+ .4byte 0xae
+ .sleb128 -65522
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB51
+ .8byte .LBE51-.LBB51
+ .4byte 0x2ce2
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x116
+ .4byte 0xae
+ .byte 0xf0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB52
+ .8byte .LBE52-.LBB52
+ .4byte 0x2d05
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x117
+ .4byte 0xae
+ .byte 0x1
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB53
+ .8byte .LBE53-.LBB53
+ .4byte 0x2d28
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x118
+ .4byte 0xae
+ .byte 0x7a
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB54
+ .8byte .LBE54-.LBB54
+ .4byte 0x2d4b
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x119
+ .4byte 0xae
+ .byte 0x25
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB55
+ .8byte .LBE55-.LBB55
+ .4byte 0x2d6e
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11a
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB56
+ .8byte .LBE56-.LBB56
+ .4byte 0x2d91
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11b
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB57
+ .8byte .LBE57-.LBB57
+ .4byte 0x2db4
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11c
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB58
+ .8byte .LBE58-.LBB58
+ .4byte 0x2dd7
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11d
+ .4byte 0xae
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB59
+ .8byte .LBE59-.LBB59
+ .4byte 0x2dfa
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11e
+ .4byte 0xae
+ .byte 0xb
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB60
+ .8byte .LBE60-.LBB60
+ .4byte 0x2e1d
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x11f
+ .4byte 0xae
+ .byte 0x8
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB61
+ .8byte .LBE61-.LBB61
+ .4byte 0x2e40
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x120
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB62
+ .8byte .LBE62-.LBB62
+ .4byte 0x2e63
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x121
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB63
+ .8byte .LBE63-.LBB63
+ .4byte 0x2e86
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x122
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x30
+ .4byte 0x2e9e
+ .uleb128 0x5b
+ .string "__v"
+ .byte 0x1
+ .2byte 0x123
+ .4byte 0xae
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x60
+ .4byte 0x2eb8
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x124
+ .4byte 0xae
+ .4byte .LLST45
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x90
+ .4byte 0x2ed2
+ .uleb128 0x5c
+ .string "__v"
+ .byte 0x1
+ .2byte 0x125
+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB70
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+ .4byte 0x2ef7
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x12c
+ .4byte 0xae
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB71
+ .8byte .LBE71-.LBB71
+ .4byte 0x2f1a
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x12d
+ .4byte 0xae
+ .byte 0xfa
+ .byte 0
+ .uleb128 0x45
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x12e
+ .4byte 0xae
+ .byte 0x9
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0xc0
+ .4byte 0x2f57
+ .uleb128 0x5c
+ .string "__v"
+ .byte 0x1
+ .2byte 0x12f
+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB75
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+ .4byte 0x2f7d
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x136
+ .4byte 0xae
+ .sleb128 -16762368
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB76
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+ .4byte 0x2fa2
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x137
+ .4byte 0xae
+ .sleb128 -65522
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB77
+ .8byte .LBE77-.LBB77
+ .4byte 0x2fc5
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x138
+ .4byte 0xae
+ .byte 0xf0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB78
+ .8byte .LBE78-.LBB78
+ .4byte 0x2fe8
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
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+ .4byte 0xae
+ .byte 0x1
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB79
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+ .4byte 0x300b
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x13a
+ .4byte 0xae
+ .byte 0x7a
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE80-.LBB80
+ .4byte 0x302e
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x13b
+ .4byte 0xae
+ .byte 0x15
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE81-.LBB81
+ .4byte 0x3051
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x13c
+ .4byte 0xae
+ .byte 0xdc
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE82-.LBB82
+ .4byte 0x3074
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x13d
+ .4byte 0xae
+ .byte 0x92
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB83
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+ .4byte 0x3097
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x13e
+ .4byte 0xae
+ .byte 0x79
+ .byte 0
+ .uleb128 0x45
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+ .4byte 0x30ba
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x13f
+ .4byte 0xae
+ .byte 0x81
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE85-.LBB85
+ .4byte 0x30dd
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x140
+ .4byte 0xae
+ .byte 0x7e
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE86-.LBB86
+ .4byte 0x3100
+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0x21
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB87
+ .8byte .LBE87-.LBB87
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x142
+ .4byte 0xae
+ .byte 0x11
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE88-.LBB88
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x143
+ .4byte 0xae
+ .byte 0x9d
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE89-.LBB89
+ .4byte 0x3169
+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0x2
+ .byte 0
+ .uleb128 0x45
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+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0
+ .byte 0
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+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0x40
+ .byte 0
+ .uleb128 0x46
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+ .4byte 0x31c9
+ .uleb128 0x5c
+ .string "__v"
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+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
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+ .uleb128 0x59
+ .string "__v"
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+ .4byte 0xae
+ .sleb128 -65534
+ .byte 0
+ .uleb128 0x45
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+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0xfc
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE96-.LBB96
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x150
+ .4byte 0xae
+ .byte 0xa
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE97-.LBB97
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x151
+ .4byte 0xae
+ .byte 0x70
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x120
+ .4byte 0x3271
+ .uleb128 0x5c
+ .string "__v"
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+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE100-.LBB100
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+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x159
+ .4byte 0xae
+ .sleb128 -16776704
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB101
+ .8byte .LBE101-.LBB101
+ .4byte 0x32bc
+ .uleb128 0x59
+ .string "__v"
+ .byte 0x1
+ .2byte 0x15a
+ .4byte 0xae
+ .sleb128 -65534
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB102
+ .8byte .LBE102-.LBB102
+ .4byte 0x32df
+ .uleb128 0x5a
+ .string "__v"
+ .byte 0x1
+ .2byte 0x15b
+ .4byte 0xae
+ .byte 0xc0
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x150
+ .4byte 0x32f9
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x15c
+ .4byte 0xae
+ .4byte .LLST46
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x180
+ .4byte 0x3313
+ .uleb128 0x33
+ .string "__v"
+ .byte 0x1
+ .2byte 0x15d
+ .4byte 0xae
+ .4byte .LLST47
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x1b0
+ .4byte 0x332d
+ .uleb128 0x5c
+ .string "__v"
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+ .2byte 0x15e
+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE109-.LBB109
+ .4byte 0x3352
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x165
+ .4byte 0xae
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB110
+ .8byte .LBE110-.LBB110
+ .4byte 0x3375
+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0xe0
+ .byte 0
+ .uleb128 0x45
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+ .4byte 0x3398
+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x167
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x1e0
+ .4byte 0x33b2
+ .uleb128 0x5c
+ .string "__v"
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+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE114-.LBB114
+ .4byte 0x33d7
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x16f
+ .4byte 0xae
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB115
+ .8byte .LBE115-.LBB115
+ .4byte 0x33fd
+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x170
+ .4byte 0xae
+ .sleb128 -16762368
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB116
+ .8byte .LBE116-.LBB116
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+ .uleb128 0x5a
+ .string "__v"
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+ .4byte 0xae
+ .byte 0xff
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE117-.LBB117
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x172
+ .4byte 0xae
+ .byte 0xa
+ .byte 0
+ .uleb128 0x46
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+ .uleb128 0x5c
+ .string "__v"
+ .byte 0x1
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+ .4byte 0xae
+ .4byte 0x10001
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE120-.LBB120
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+ .uleb128 0x59
+ .string "__v"
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+ .2byte 0x17a
+ .4byte 0xae
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB121
+ .8byte .LBE121-.LBB121
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x17b
+ .4byte 0xae
+ .byte 0x1
+ .byte 0
+ .uleb128 0x45
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+ .8byte .LBE122-.LBB122
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+ .uleb128 0x5a
+ .string "__v"
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+ .2byte 0x17c
+ .4byte 0xae
+ .byte 0xbf
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x240
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+ .uleb128 0x5c
+ .string "__v"
+ .byte 0x1
+ .2byte 0x17d
+ .4byte 0xae
+ .4byte 0x10001
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+ .byte 0x1
+ .byte 0xa3
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0xa5
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .4byte 0xee
+ .4byte 0x3ccb
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1e
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x3cbb
+ .uleb128 0x5f
+ .4byte .LASF441
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3d1a
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x1825
+ .uleb128 0x63
+ .4byte .LASF442
+ .byte 0x1
+ .byte 0x83
+ .4byte 0x54
+ .uleb128 0x63
+ .4byte .LASF429
+ .byte 0x1
+ .byte 0x84
+ .4byte 0x54
+ .uleb128 0x62
+ .string "ret"
+ .byte 0x1
+ .byte 0x85
+ .4byte 0x54
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x88
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .4byte .LASF443
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3d64
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x1825
+ .uleb128 0x63
+ .4byte .LASF442
+ .byte 0x1
+ .byte 0x6c
+ .4byte 0x54
+ .uleb128 0x63
+ .4byte .LASF429
+ .byte 0x1
+ .byte 0x6d
+ .4byte 0x54
+ .uleb128 0x62
+ .string "ret"
+ .byte 0x1
+ .byte 0x6e
+ .4byte 0x54
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x71
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .4byte .LASF444
+ .byte 0x1
+ .byte 0x56
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3dc1
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x56
+ .4byte 0x1825
+ .uleb128 0x61
+ .4byte .LASF445
+ .byte 0x1
+ .byte 0x57
+ .4byte 0xae
+ .uleb128 0x63
+ .4byte .LASF442
+ .byte 0x1
+ .byte 0x59
+ .4byte 0x54
+ .uleb128 0x4e
+ .4byte .LASF432
+ .4byte 0x2a47
+ .4byte .LASF444
+ .uleb128 0x50
+ .4byte 0x3db3
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x5b
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x65
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .4byte .LASF449
+ .byte 0x1
+ .byte 0x4e
+ .8byte .LFB263
+ .8byte .LFE263-.LFB263
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3e36
+ .uleb128 0x65
+ .4byte .LASF446
+ .byte 0x1
+ .byte 0x4e
+ .4byte 0x11d2
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x54
+ .4byte .LASF447
+ .byte 0x1
+ .byte 0x4f
+ .4byte 0x11d2
+ .4byte .LLST0
+ .uleb128 0x65
+ .4byte .LASF448
+ .byte 0x1
+ .byte 0x50
+ .4byte 0x3b
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x65
+ .4byte .LASF424
+ .byte 0x1
+ .byte 0x50
+ .4byte 0x54
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x66
+ .8byte .LBB22
+ .8byte .LBE22-.LBB22
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x52
+ .4byte 0xae
+ .4byte 0x1000000
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .4byte .LASF450
+ .byte 0x1
+ .byte 0x42
+ .8byte .LFB262
+ .8byte .LFE262-.LFB262
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3f29
+ .uleb128 0x54
+ .4byte .LASF446
+ .byte 0x1
+ .byte 0x42
+ .4byte 0x11d2
+ .4byte .LLST16
+ .uleb128 0x54
+ .4byte .LASF447
+ .byte 0x1
+ .byte 0x43
+ .4byte 0x11d2
+ .4byte .LLST17
+ .uleb128 0x54
+ .4byte .LASF448
+ .byte 0x1
+ .byte 0x44
+ .4byte 0x3b
+ .4byte .LLST18
+ .uleb128 0x54
+ .4byte .LASF424
+ .byte 0x1
+ .byte 0x44
+ .4byte 0x54
+ .4byte .LLST19
+ .uleb128 0x45
+ .8byte .LBB25
+ .8byte .LBE25-.LBB25
+ .4byte 0x3eb4
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x47
+ .4byte 0xae
+ .4byte 0x1000100
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB26
+ .8byte .LBE26-.LBB26
+ .4byte 0x3ed9
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x48
+ .4byte 0xae
+ .4byte 0x20002
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB27
+ .8byte .LBE27-.LBB27
+ .4byte 0x3efe
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x4a
+ .4byte 0xae
+ .4byte 0x20000
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL32
+ .4byte 0x42c8
+ .4byte 0x3f15
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x32
+ .byte 0
+ .uleb128 0x68
+ .8byte .LVL34
+ .4byte 0x42c8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x69
+ .4byte .LASF462
+ .byte 0x1a
+ .2byte 0x36f
+ .byte 0x3
+ .4byte 0x3f43
+ .uleb128 0x3c
+ .string "ptr"
+ .byte 0x1a
+ .2byte 0x36f
+ .4byte 0x137
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3cd0
+ .8byte .LFB278
+ .8byte .LFE278-.LFB278
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3fad
+ .uleb128 0x6b
+ .4byte 0x3ce0
+ .uleb128 0x42
+ .4byte 0x3ceb
+ .4byte .LLST20
+ .uleb128 0x42
+ .4byte 0x3cf6
+ .4byte .LLST21
+ .uleb128 0x44
+ .4byte 0x3d01
+ .uleb128 0x45
+ .8byte .LBB28
+ .8byte .LBE28-.LBB28
+ .4byte 0x3f99
+ .uleb128 0x42
+ .4byte 0x3d0d
+ .4byte .LLST22
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL40
+ .4byte 0x42c8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3d1a
+ .8byte .LFB279
+ .8byte .LFE279-.LFB279
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x4018
+ .uleb128 0x6b
+ .4byte 0x3d2a
+ .uleb128 0x42
+ .4byte 0x3d35
+ .4byte .LLST23
+ .uleb128 0x42
+ .4byte 0x3d40
+ .4byte .LLST24
+ .uleb128 0x6c
+ .4byte 0x3d4b
+ .sleb128 -1
+ .uleb128 0x45
+ .8byte .LBB29
+ .8byte .LBE29-.LBB29
+ .4byte 0x4004
+ .uleb128 0x42
+ .4byte 0x3d57
+ .4byte .LLST25
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL48
+ .4byte 0x42c8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3d64
+ .8byte .LFB280
+ .8byte .LFE280-.LFB280
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x4105
+ .uleb128 0x3a
+ .4byte 0x3d7f
+ .4byte .LLST26
+ .uleb128 0x6b
+ .4byte 0x3d74
+ .uleb128 0x42
+ .4byte 0x3d8a
+ .4byte .LLST27
+ .uleb128 0x44
+ .4byte 0x3d95
+ .uleb128 0x45
+ .8byte .LBB36
+ .8byte .LBE36-.LBB36
+ .4byte 0x406e
+ .uleb128 0x42
+ .4byte 0x3da7
+ .4byte .LLST28
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB37
+ .8byte .LBE37-.LBB37
+ .4byte 0x408d
+ .uleb128 0x42
+ .4byte 0x3db4
+ .4byte .LLST29
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB38
+ .8byte .LBE38-.LBB38
+ .4byte 0x40f1
+ .uleb128 0x6b
+ .4byte 0x3d7f
+ .uleb128 0x6b
+ .4byte 0x3d74
+ .uleb128 0x66
+ .8byte .LBB39
+ .8byte .LBE39-.LBB39
+ .uleb128 0x44
+ .4byte 0x3d8a
+ .uleb128 0x44
+ .4byte 0x3d95
+ .uleb128 0x36
+ .8byte .LVL63
+ .4byte 0x42b1
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC3
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL60
+ .4byte 0x42c8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3c1a
+ .8byte .LFB267
+ .8byte .LFE267-.LFB267
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x4283
+ .uleb128 0x3a
+ .4byte 0x3c2a
+ .4byte .LLST48
+ .uleb128 0x3a
+ .4byte 0x3c35
+ .4byte .LLST49
+ .uleb128 0x42
+ .4byte 0x3c40
+ .4byte .LLST50
+ .uleb128 0x44
+ .4byte 0x3c4b
+ .uleb128 0x45
+ .8byte .LBB160
+ .8byte .LBE160-.LBB160
+ .4byte 0x415f
+ .uleb128 0x6c
+ .4byte 0x3c5d
+ .sleb128 -16776704
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB161
+ .8byte .LBE161-.LBB161
+ .4byte 0x417d
+ .uleb128 0x6c
+ .4byte 0x3c6e
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB162
+ .8byte .LBE162-.LBB162
+ .4byte 0x4199
+ .uleb128 0x6d
+ .4byte 0x3c7f
+ .byte 0xfa
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB163
+ .8byte .LBE163-.LBB163
+ .4byte 0x41b8
+ .uleb128 0x42
+ .4byte 0x3c90
+ .4byte .LLST51
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB164
+ .8byte .LBE164-.LBB164
+ .4byte 0x41d7
+ .uleb128 0x42
+ .4byte 0x3cae
+ .4byte .LLST52
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB165
+ .8byte .LBE165-.LBB165
+ .4byte 0x4243
+ .uleb128 0x3a
+ .4byte 0x3c2a
+ .4byte .LLST53
+ .uleb128 0x3a
+ .4byte 0x3c35
+ .4byte .LLST54
+ .uleb128 0x66
+ .8byte .LBB166
+ .8byte .LBE166-.LBB166
+ .uleb128 0x44
+ .4byte 0x4132
+ .uleb128 0x44
+ .4byte 0x413b
+ .uleb128 0x36
+ .8byte .LVL209
+ .4byte 0x42b1
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR2
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB167
+ .8byte .LBE167-.LBB167
+ .4byte 0x425f
+ .uleb128 0x6d
+ .4byte 0x3ca1
+ .byte 0x9
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL205
+ .4byte 0x4018
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x32
+ .uleb128 0x48
+ .4byte 0x3d74
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0
+ .byte 0
+ .uleb128 0x6e
+ .4byte .LASF451
+ .4byte .LASF451
+ .byte 0x8
+ .2byte 0x115
+ .uleb128 0x6f
+ .4byte .LASF452
+ .4byte .LASF452
+ .byte 0x20
+ .byte 0x85
+ .uleb128 0x6f
+ .4byte .LASF453
+ .4byte .LASF453
+ .byte 0x20
+ .byte 0x38
+ .uleb128 0x6e
+ .4byte .LASF454
+ .4byte .LASF454
+ .byte 0x8
+ .2byte 0x16e
+ .uleb128 0x6f
+ .4byte .LASF455
+ .4byte .LASF455
+ .byte 0x21
+ .byte 0x13
+ .uleb128 0x6e
+ .4byte .LASF456
+ .4byte .LASF456
+ .byte 0x1a
+ .2byte 0x393
+ .uleb128 0x6f
+ .4byte .LASF457
+ .4byte .LASF457
+ .byte 0x22
+ .byte 0xb
+ .byte 0
+ .section .debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+ .uleb128 0x1
+ .uleb128 0x11
+ .byte 0x1
+ .uleb128 0x25
+ .uleb128 0xe
+ .uleb128 0x13
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1b
+ .uleb128 0xe
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x10
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x2
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x4
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x5
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0x8
+ .byte 0
+ .byte 0
+ .uleb128 0x6
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x7
+ .uleb128 0x26
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x9
+ .uleb128 0xf
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .uleb128 0x1
+ .byte 0x1
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0x21
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0xc
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0xd
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0xe
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0xf
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x10
+ .uleb128 0x26
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x11
+ .uleb128 0x21
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2f
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x12
+ .uleb128 0x15
+ .byte 0x1
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x13
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x14
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x15
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x16
+ .uleb128 0xd
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x38
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x17
+ .uleb128 0x21
+ .byte 0
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2f
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x18
+ .uleb128 0x13
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3c
+ .uleb128 0x19
+ .byte 0
+ .byte 0
+ .uleb128 0x19
+ .uleb128 0x13
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0xb
+ .uleb128 0x5
+ .uleb128 0x3a
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+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x11
+ .uleb128 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x60
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x61
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x62
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x63
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x65
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x66
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .byte 0
+ .byte 0
+ .uleb128 0x67
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0x6
+ .byte 0
+ .byte 0
+ .uleb128 0x68
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x2115
+ .uleb128 0x19
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x69
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6b
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xd
+ .byte 0
+ .byte 0
+ .uleb128 0x6d
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x6e
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x6f
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .byte 0
+ .section .debug_loc,"",@progbits
+.Ldebug_loc0:
+.LLST14:
+ .8byte .LVL19
+ .8byte .LVL20-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL20-1
+ .8byte .LVL27
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL27
+ .8byte .LFE277
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST15:
+ .8byte .LVL21
+ .8byte .LVL22
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL22
+ .8byte .LVL27
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST1:
+ .8byte .LVL2
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL3
+ .8byte .LFE276
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST2:
+ .8byte .LVL2
+ .8byte .LVL5
+ .2byte 0x3
+ .byte 0x9
+ .byte 0xea
+ .byte 0x9f
+ .8byte .LVL6
+ .8byte .LFE276
+ .2byte 0x3
+ .byte 0x9
+ .byte 0xea
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST3:
+ .8byte .LVL4
+ .8byte .LVL5
+ .2byte 0x1
+ .byte 0x52
+ .8byte 0
+ .8byte 0
+.LLST4:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL8-1
+ .8byte .LVL11
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL11
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST5:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL8-1
+ .8byte .LVL11
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL11
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST6:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL8-1
+ .8byte .LVL10
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL10
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST7:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL8-1
+ .8byte .LVL10
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL10
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST8:
+ .8byte .LVL8
+ .8byte .LVL9
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST9:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL14-1
+ .8byte .LVL17
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL17
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST10:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL14-1
+ .8byte .LVL17
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL17
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST11:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL14-1
+ .8byte .LVL16
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL16
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST12:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL14-1
+ .8byte .LVL16
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL16
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST13:
+ .8byte .LVL14
+ .8byte .LVL15
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST69:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL247-1
+ .8byte .LVL254
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL254
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST70:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL247-1
+ .8byte .LVL253
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL253
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST71:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL247-1
+ .8byte .LVL256
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte .LVL256
+ .8byte .LVL257
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 80
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte 0
+ .8byte 0
+.LLST72:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL247-1
+ .8byte .LVL252
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL252
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LVL261
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL261
+ .8byte .LVL267
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL267
+ .8byte .LVL281
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL281
+ .8byte .LVL283
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL287
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL287
+ .8byte .LVL396
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL396
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST73:
+ .8byte .LVL248
+ .8byte .LVL249
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL249
+ .8byte .LVL255
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST74:
+ .8byte .LVL248
+ .8byte .LVL256
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte .LVL256
+ .8byte .LVL257
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 80
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte 0
+ .8byte 0
+.LLST76:
+ .8byte .LVL250
+ .8byte .LVL251
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL257
+ .8byte .LVL258
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL258
+ .8byte .LVL260
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL267
+ .8byte .LVL272
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL285
+ .8byte .LVL286
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST77:
+ .8byte .LVL261
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL269
+ .8byte .LVL270
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL272
+ .8byte .LVL278
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL286
+ .8byte .LVL287
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL288
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL394
+ .8byte .LVL395
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 1
+ .byte 0x9f
+ .8byte .LVL396
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST78:
+ .8byte .LVL250
+ .8byte .LVL251
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LVL268
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL268
+ .8byte .LVL269
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL272
+ .8byte .LVL280
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL315
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST79:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL288
+ .8byte .LVL313
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL317
+ .8byte .LVL352
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST80:
+ .8byte .LVL262
+ .8byte .LVL264
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL264
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST81:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST82:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST83:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL288
+ .8byte .LVL311
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL311
+ .8byte .LVL312
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL312
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL317
+ .8byte .LVL318
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL318
+ .8byte .LVL337
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL337
+ .8byte .LVL338
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL338
+ .8byte .LVL339
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL339
+ .8byte .LVL340
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL340
+ .8byte .LVL346
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL346
+ .8byte .LVL347
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL347
+ .8byte .LVL348
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL348
+ .8byte .LVL349
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL349
+ .8byte .LVL356
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL356
+ .8byte .LVL357
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL357
+ .8byte .LVL358
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL358
+ .8byte .LVL359
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL359
+ .8byte .LVL365
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL365
+ .8byte .LVL366
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL366
+ .8byte .LVL367
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL367
+ .8byte .LVL368
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL368
+ .8byte .LVL374
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL374
+ .8byte .LVL375
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL375
+ .8byte .LVL376
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL376
+ .8byte .LVL377
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL377
+ .8byte .LVL379
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL379
+ .8byte .LVL380
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL380
+ .8byte .LVL381
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL381
+ .8byte .LVL382
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL382
+ .8byte .LVL387
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL387
+ .8byte .LVL388
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL388
+ .8byte .LVL389
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL389
+ .8byte .LVL390
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL390
+ .8byte .LVL392
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL392
+ .8byte .LVL393
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL393
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6b
+ .8byte 0
+ .8byte 0
+.LLST84:
+ .8byte .LVL264
+ .8byte .LVL265
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL265
+ .8byte .LVL267
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte 0
+ .8byte 0
+.LLST85:
+ .8byte .LVL289
+ .8byte .LVL316
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST86:
+ .8byte .LVL290
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST87:
+ .8byte .LVL291
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST88:
+ .8byte .LVL292
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST89:
+ .8byte .LVL293
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65522
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65522
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST90:
+ .8byte .LVL294
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST91:
+ .8byte .LVL295
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST92:
+ .8byte .LVL296
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST93:
+ .8byte .LVL297
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x25
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x25
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST94:
+ .8byte .LVL298
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST95:
+ .8byte .LVL299
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST96:
+ .8byte .LVL300
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST97:
+ .8byte .LVL301
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x4f
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x4f
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST98:
+ .8byte .LVL302
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x3b
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x3b
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST99:
+ .8byte .LVL303
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x38
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x38
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST100:
+ .8byte .LVL304
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST101:
+ .8byte .LVL305
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST102:
+ .8byte .LVL306
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST103:
+ .8byte .LVL307
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST104:
+ .8byte .LVL308
+ .8byte .LVL313
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL317
+ .8byte .LVL332
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST105:
+ .8byte .LVL309
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST106:
+ .8byte .LVL314
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65533
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST107:
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16762368
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST108:
+ .8byte .LVL319
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST109:
+ .8byte .LVL320
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST110:
+ .8byte .LVL321
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST111:
+ .8byte .LVL322
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x45
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST112:
+ .8byte .LVL323
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xdc
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST113:
+ .8byte .LVL324
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x92
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST114:
+ .8byte .LVL325
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x79
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST115:
+ .8byte .LVL326
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x81
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST116:
+ .8byte .LVL327
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7e
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST117:
+ .8byte .LVL328
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x21
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST118:
+ .8byte .LVL329
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x41
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST119:
+ .8byte .LVL330
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x9d
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST120:
+ .8byte .LVL331
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x32
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST121:
+ .8byte .LVL333
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST122:
+ .8byte .LVL334
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST123:
+ .8byte .LVL335
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST124:
+ .8byte .LVL339
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST125:
+ .8byte .LVL341
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST126:
+ .8byte .LVL342
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfb
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST127:
+ .8byte .LVL343
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST128:
+ .8byte .LVL344
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST129:
+ .8byte .LVL348
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST130:
+ .8byte .LVL350
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xc0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST131:
+ .8byte .LVL351
+ .8byte .LVL354
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST132:
+ .8byte .LVL352
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST133:
+ .8byte .LVL353
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST134:
+ .8byte .LVL358
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16762368
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST135:
+ .8byte .LVL360
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST136:
+ .8byte .LVL361
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xff
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST137:
+ .8byte .LVL362
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x3a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST138:
+ .8byte .LVL363
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST139:
+ .8byte .LVL367
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST140:
+ .8byte .LVL369
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST141:
+ .8byte .LVL370
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xbf
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST142:
+ .8byte .LVL371
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST143:
+ .8byte .LVL372
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST144:
+ .8byte .LVL381
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST145:
+ .8byte .LVL383
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x32
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST146:
+ .8byte .LVL384
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xbf
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST147:
+ .8byte .LVL385
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST148:
+ .8byte .LVL273
+ .8byte .LVL276
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL283
+ .8byte .LVL284
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST149:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST150:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST151:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST152:
+ .8byte .LVL275
+ .8byte .LVL276
+ .2byte 0xd
+ .byte 0x8f
+ .sleb128 254
+ .byte 0x94
+ .byte 0x2
+ .byte 0x20
+ .byte 0x87
+ .sleb128 0
+ .byte 0x8
+ .byte 0xff
+ .byte 0x1a
+ .byte 0x1a
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL284
+ .2byte 0xf
+ .byte 0x8f
+ .sleb128 254
+ .byte 0x94
+ .byte 0x2
+ .byte 0x20
+ .byte 0x87
+ .sleb128 0
+ .byte 0x8
+ .byte 0xff
+ .byte 0x1a
+ .byte 0x38
+ .byte 0x24
+ .byte 0x1a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST153:
+ .8byte .LVL274
+ .8byte .LVL277
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST30:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL67-1
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST31:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL67-1
+ .8byte .LVL72
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL72
+ .8byte .LVL73
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST32:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL67-1
+ .8byte .LVL67
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL67
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL71
+ .8byte .LVL73
+ .2byte 0x6
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x31
+ .byte 0x26
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST33:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL67-1
+ .8byte .LVL70
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL70
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST34:
+ .8byte .LVL66
+ .8byte .LVL70
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LVL83
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL83
+ .8byte .LVL84
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL87
+ .8byte .LVL88
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL104
+ .8byte .LVL106
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL110
+ .8byte .LVL112
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL130
+ .8byte .LVL132
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL137
+ .8byte .LVL139
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL146
+ .8byte .LVL148
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL152
+ .8byte .LVL154
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL160
+ .8byte .LVL162
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL167
+ .8byte .LVL168
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL169
+ .8byte .LVL170
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL171
+ .8byte .LVL172
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL176
+ .8byte .LVL177
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL178
+ .8byte .LVL179
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL180
+ .8byte .LVL181
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL187
+ .8byte .LVL189
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL193
+ .8byte .LVL195
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL198
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST35:
+ .8byte .LVL67
+ .8byte .LVL68
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL68
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST36:
+ .8byte .LVL74
+ .8byte .LVL86
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST37:
+ .8byte .LVL75
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST38:
+ .8byte .LVL76
+ .8byte .LVL86
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST39:
+ .8byte .LVL77
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST40:
+ .8byte .LVL78
+ .8byte .LVL86
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST41:
+ .8byte .LVL79
+ .8byte .LVL86
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfc
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfc
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST42:
+ .8byte .LVL80
+ .8byte .LVL86
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST43:
+ .8byte .LVL81
+ .8byte .LVL86
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST44:
+ .8byte .LVL82
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST45:
+ .8byte .LVL102
+ .8byte .LVL104-1
+ .2byte 0x1
+ .byte 0x55
+ .8byte .LVL104-1
+ .8byte .LVL165
+ .2byte 0x6
+ .byte 0x88
+ .sleb128 0
+ .byte 0x9
+ .byte 0xf7
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST46:
+ .8byte .LVL142
+ .8byte .LVL145
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST47:
+ .8byte .LVL143
+ .8byte .LVL159
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL159
+ .8byte .LFE269
+ .2byte 0xa
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0xa
+ .2byte 0xffff
+ .byte 0x1a
+ .byte 0x38
+ .byte 0x25
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST55:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL213-1
+ .8byte .LVL221
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL221
+ .8byte .LVL227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST56:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL213-1
+ .8byte .LVL217
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL217
+ .8byte .LVL225
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST57:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL213-1
+ .8byte .LVL222
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL222
+ .8byte .LVL227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST58:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL213-1
+ .8byte .LVL222
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL222
+ .8byte .LVL226
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL228
+ .8byte .LVL244
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL244
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST59:
+ .8byte .LVL214
+ .8byte .LVL215
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL215
+ .8byte .LVL225
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST60:
+ .8byte .LVL217
+ .8byte .LVL218
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL218
+ .8byte .LVL226
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST61:
+ .8byte .LVL217
+ .8byte .LVL224
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL227
+ .8byte .LVL236
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL238
+ .8byte .LVL241
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL241
+ .8byte .LVL242
+ .2byte 0x3
+ .byte 0x85
+ .sleb128 1
+ .byte 0x9f
+ .8byte .LVL242
+ .8byte .LVL245
+ .2byte 0x3
+ .byte 0x85
+ .sleb128 2
+ .byte 0x9f
+ .8byte .LVL245
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST62:
+ .8byte .LVL241
+ .8byte .LVL243
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST63:
+ .8byte .LVL217
+ .8byte .LVL222
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL222
+ .8byte .LVL223
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL228
+ .8byte .LVL234
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL234
+ .8byte .LVL235
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL235
+ .8byte .LVL238
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL238
+ .8byte .LVL239
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL239
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST64:
+ .8byte .LVL220
+ .8byte .LVL227
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST65:
+ .8byte .LVL229
+ .8byte .LVL231
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL231
+ .8byte .LVL232
+ .2byte 0x6
+ .byte 0x84
+ .sleb128 0
+ .byte 0x6
+ .byte 0x23
+ .uleb128 0x104
+ .8byte .LVL232
+ .8byte .LVL236
+ .2byte 0x8
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x21
+ .byte 0x9f
+ .8byte .LVL238
+ .8byte .LFE268
+ .2byte 0x8
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x21
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST66:
+ .8byte .LVL230
+ .8byte .LVL236
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL238
+ .8byte .LFE268
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST68:
+ .8byte .LVL240
+ .8byte .LVL243
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST67:
+ .8byte .LVL236
+ .8byte .LVL238
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST0:
+ .8byte .LVL0
+ .8byte .LVL1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL1
+ .8byte .LFE263
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST16:
+ .8byte .LVL28
+ .8byte .LVL31
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL31
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST17:
+ .8byte .LVL28
+ .8byte .LVL29
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL29
+ .8byte .LVL33
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL33
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST18:
+ .8byte .LVL28
+ .8byte .LVL32-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL32-1
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST19:
+ .8byte .LVL28
+ .8byte .LVL32-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL32-1
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST20:
+ .8byte .LVL35
+ .8byte .LVL38
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL41
+ .8byte .LVL42
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST21:
+ .8byte .LVL37
+ .8byte .LVL40-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL41
+ .8byte .LFE278
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST22:
+ .8byte .LVL36
+ .8byte .LVL40-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL41
+ .8byte .LFE278
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST23:
+ .8byte .LVL43
+ .8byte .LVL46
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL46
+ .8byte .LVL48
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL48
+ .8byte .LVL50
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL51
+ .8byte .LFE279
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST24:
+ .8byte .LVL45
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL49
+ .8byte .LVL50
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL51
+ .8byte .LVL52
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST25:
+ .8byte .LVL44
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL49
+ .8byte .LVL50
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL51
+ .8byte .LVL52
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST26:
+ .8byte .LVL53
+ .8byte .LVL54
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL54
+ .8byte .LVL56
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL56
+ .8byte .LVL58
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL58
+ .8byte .LVL64
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL64
+ .8byte .LFE280
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST27:
+ .8byte .LVL54
+ .8byte .LVL60
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL60
+ .8byte .LVL61
+ .2byte 0x3
+ .byte 0x84
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL61
+ .8byte .LVL65
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST28:
+ .8byte .LVL55
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL58
+ .8byte .LVL59
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST29:
+ .8byte .LVL56
+ .8byte .LVL58
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST48:
+ .8byte .LVL199
+ .8byte .LVL205-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL205-1
+ .8byte .LVL211
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL211
+ .8byte .LFE267
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST49:
+ .8byte .LVL199
+ .8byte .LVL203
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL203
+ .8byte .LFE267
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST50:
+ .8byte .LVL199
+ .8byte .LVL206
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL206
+ .8byte .LVL208
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL208
+ .8byte .LVL210
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL210
+ .8byte .LVL211
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL211
+ .8byte .LFE267
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST51:
+ .8byte .LVL202
+ .8byte .LVL204
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST52:
+ .8byte .LVL204
+ .8byte .LVL211
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST53:
+ .8byte .LVL207
+ .8byte .LVL209
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST54:
+ .8byte .LVL207
+ .8byte .LVL209
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+ .section .debug_aranges,"",@progbits
+ .4byte 0xec
+ .2byte 0x2
+ .4byte .Ldebug_info0
+ .byte 0x8
+ .byte 0
+ .2byte 0
+ .2byte 0
+ .8byte .LFB263
+ .8byte .LFE263-.LFB263
+ .8byte .LFB276
+ .8byte .LFE276-.LFB276
+ .8byte .LFB274
+ .8byte .LFE274-.LFB274
+ .8byte .LFB273
+ .8byte .LFE273-.LFB273
+ .8byte .LFB277
+ .8byte .LFE277-.LFB277
+ .8byte .LFB262
+ .8byte .LFE262-.LFB262
+ .8byte .LFB278
+ .8byte .LFE278-.LFB278
+ .8byte .LFB279
+ .8byte .LFE279-.LFB279
+ .8byte .LFB280
+ .8byte .LFE280-.LFB280
+ .8byte .LFB269
+ .8byte .LFE269-.LFB269
+ .8byte .LFB267
+ .8byte .LFE267-.LFB267
+ .8byte .LFB268
+ .8byte .LFE268-.LFB268
+ .8byte .LFB272
+ .8byte .LFE272-.LFB272
+ .8byte 0
+ .8byte 0
+ .section .debug_ranges,"",@progbits
+.Ldebug_ranges0:
+ .8byte .LBB48
+ .8byte .LBE48
+ .8byte .LBB49
+ .8byte .LBE49
+ .8byte 0
+ .8byte 0
+ .8byte .LBB64
+ .8byte .LBE64
+ .8byte .LBB66
+ .8byte .LBE66
+ .8byte 0
+ .8byte 0
+ .8byte .LBB65
+ .8byte .LBE65
+ .8byte .LBB67
+ .8byte .LBE67
+ .8byte 0
+ .8byte 0
+ .8byte .LBB68
+ .8byte .LBE68
+ .8byte .LBB69
+ .8byte .LBE69
+ .8byte 0
+ .8byte 0
+ .8byte .LBB73
+ .8byte .LBE73
+ .8byte .LBB74
+ .8byte .LBE74
+ .8byte 0
+ .8byte 0
+ .8byte .LBB92
+ .8byte .LBE92
+ .8byte .LBB93
+ .8byte .LBE93
+ .8byte 0
+ .8byte 0
+ .8byte .LBB98
+ .8byte .LBE98
+ .8byte .LBB99
+ .8byte .LBE99
+ .8byte 0
+ .8byte 0
+ .8byte .LBB103
+ .8byte .LBE103
+ .8byte .LBB105
+ .8byte .LBE105
+ .8byte 0
+ .8byte 0
+ .8byte .LBB104
+ .8byte .LBE104
+ .8byte .LBB106
+ .8byte .LBE106
+ .8byte 0
+ .8byte 0
+ .8byte .LBB107
+ .8byte .LBE107
+ .8byte .LBB108
+ .8byte .LBE108
+ .8byte 0
+ .8byte 0
+ .8byte .LBB112
+ .8byte .LBE112
+ .8byte .LBB113
+ .8byte .LBE113
+ .8byte 0
+ .8byte 0
+ .8byte .LBB118
+ .8byte .LBE118
+ .8byte .LBB119
+ .8byte .LBE119
+ .8byte 0
+ .8byte 0
+ .8byte .LBB123
+ .8byte .LBE123
+ .8byte .LBB124
+ .8byte .LBE124
+ .8byte 0
+ .8byte 0
+ .8byte .LBB128
+ .8byte .LBE128
+ .8byte .LBB129
+ .8byte .LBE129
+ .8byte 0
+ .8byte 0
+ .8byte .LBB135
+ .8byte .LBE135
+ .8byte .LBB136
+ .8byte .LBE136
+ .8byte 0
+ .8byte 0
+ .8byte .LBB140
+ .8byte .LBE140
+ .8byte .LBB141
+ .8byte .LBE141
+ .8byte 0
+ .8byte 0
+ .8byte .LBB144
+ .8byte .LBE144
+ .8byte .LBB145
+ .8byte .LBE145
+ .8byte 0
+ .8byte 0
+ .8byte .LBB168
+ .8byte .LBE168
+ .8byte .LBB169
+ .8byte .LBE169
+ .8byte 0
+ .8byte 0
+ .8byte .LBB170
+ .8byte .LBE170
+ .8byte .LBB171
+ .8byte .LBE171
+ .8byte 0
+ .8byte 0
+ .8byte .LBB172
+ .8byte .LBE172
+ .8byte .LBB173
+ .8byte .LBE173
+ .8byte 0
+ .8byte 0
+ .8byte .LBB174
+ .8byte .LBE174
+ .8byte .LBB175
+ .8byte .LBE175
+ .8byte 0
+ .8byte 0
+ .8byte .LBB244
+ .8byte .LBE244
+ .8byte .LBB324
+ .8byte .LBE324
+ .8byte .LBB325
+ .8byte .LBE325
+ .8byte .LBB335
+ .8byte .LBE335
+ .8byte .LBB336
+ .8byte .LBE336
+ .8byte 0
+ .8byte 0
+ .8byte .LBB264
+ .8byte .LBE264
+ .8byte .LBB266
+ .8byte .LBE266
+ .8byte 0
+ .8byte 0
+ .8byte .LBB265
+ .8byte .LBE265
+ .8byte .LBB267
+ .8byte .LBE267
+ .8byte 0
+ .8byte 0
+ .8byte .LBB268
+ .8byte .LBE268
+ .8byte .LBB269
+ .8byte .LBE269
+ .8byte 0
+ .8byte 0
+ .8byte .LBB270
+ .8byte .LBE270
+ .8byte .LBB271
+ .8byte .LBE271
+ .8byte 0
+ .8byte 0
+ .8byte .LBB288
+ .8byte .LBE288
+ .8byte .LBB289
+ .8byte .LBE289
+ .8byte 0
+ .8byte 0
+ .8byte .LBB294
+ .8byte .LBE294
+ .8byte .LBB295
+ .8byte .LBE295
+ .8byte 0
+ .8byte 0
+ .8byte .LBB298
+ .8byte .LBE298
+ .8byte .LBB300
+ .8byte .LBE300
+ .8byte 0
+ .8byte 0
+ .8byte .LBB299
+ .8byte .LBE299
+ .8byte .LBB301
+ .8byte .LBE301
+ .8byte 0
+ .8byte 0
+ .8byte .LBB302
+ .8byte .LBE302
+ .8byte .LBB303
+ .8byte .LBE303
+ .8byte 0
+ .8byte 0
+ .8byte .LBB308
+ .8byte .LBE308
+ .8byte .LBB309
+ .8byte .LBE309
+ .8byte 0
+ .8byte 0
+ .8byte .LBB314
+ .8byte .LBE314
+ .8byte .LBB315
+ .8byte .LBE315
+ .8byte 0
+ .8byte 0
+ .8byte .LBB326
+ .8byte .LBE326
+ .8byte .LBB332
+ .8byte .LBE332
+ .8byte .LBB333
+ .8byte .LBE333
+ .8byte .LBB334
+ .8byte .LBE334
+ .8byte .LBB337
+ .8byte .LBE337
+ .8byte 0
+ .8byte 0
+ .8byte .LFB263
+ .8byte .LFE263
+ .8byte .LFB276
+ .8byte .LFE276
+ .8byte .LFB274
+ .8byte .LFE274
+ .8byte .LFB273
+ .8byte .LFE273
+ .8byte .LFB277
+ .8byte .LFE277
+ .8byte .LFB262
+ .8byte .LFE262
+ .8byte .LFB278
+ .8byte .LFE278
+ .8byte .LFB279
+ .8byte .LFE279
+ .8byte .LFB280
+ .8byte .LFE280
+ .8byte .LFB269
+ .8byte .LFE269
+ .8byte .LFB267
+ .8byte .LFE267
+ .8byte .LFB268
+ .8byte .LFE268
+ .8byte .LFB272
+ .8byte .LFE272
+ .8byte 0
+ .8byte 0
+ .section .debug_line,"",@progbits
+.Ldebug_line0:
+ .section .debug_str,"MS",@progbits,1
+.LASF222:
+ .string "UCLASS_SERIAL"
+.LASF319:
+ .string "gd_t"
+.LASF15:
+ .string "long int"
+.LASF39:
+ .string "uclass_node"
+.LASF422:
+ .string "request"
+.LASF312:
+ .string "phandle"
+.LASF53:
+ .string "flash_id"
+.LASF404:
+ .string "misc_ops"
+.LASF376:
+ .string "mem_malloc_start"
+.LASF332:
+ .string "net_hostname"
+.LASF28:
+ .string "name"
+.LASF248:
+ .string "UCLASS_ETH_PHY"
+.LASF229:
+ .string "UCLASS_THERMAL"
+.LASF60:
+ .string "base"
+.LASF354:
+ .string "NETLOOP_RESTART"
+.LASF287:
+ .string "new_gd"
+.LASF348:
+ .string "net_boot_file_size"
+.LASF134:
+ .string "fit_hdr_os"
+.LASF181:
+ .string "UCLASS_FIRMWARE"
+.LASF457:
+ .string "udelay"
+.LASF142:
+ .string "fit_noffset_fdt"
+.LASF74:
+ .string "bi_dsp_freq"
+.LASF303:
+ .string "malloc_ptr"
+.LASF91:
+ .string "_datarellocal_start_ofs"
+.LASF94:
+ .string "fdt32_t"
+.LASF146:
+ .string "rd_start"
+.LASF371:
+ .string "property"
+.LASF265:
+ .string "tlb_emerg"
+.LASF78:
+ .string "bi_enetaddr"
+.LASF290:
+ .string "uclass_root"
+.LASF188:
+ .string "UCLASS_IRQ"
+.LASF420:
+ .string "rockchip_secure_otp_ofdata_to_platdata"
+.LASF437:
+ .string "buffer"
+.LASF234:
+ .string "UCLASS_USB_HUB"
+.LASF230:
+ .string "UCLASS_TIMER"
+.LASF42:
+ .string "flags"
+.LASF139:
+ .string "fit_noffset_rd"
+.LASF269:
+ .string "baudrate"
+.LASF334:
+ .string "net_ethaddr"
+.LASF300:
+ .string "timebase_l"
+.LASF21:
+ .string "errno"
+.LASF32:
+ .string "node"
+.LASF359:
+ .string "bind"
+.LASF455:
+ .string "printf"
+.LASF401:
+ .string "DECOM_ZLIB"
+.LASF8:
+ .string "unsigned int"
+.LASF47:
+ .string "next"
+.LASF101:
+ .string "version"
+.LASF396:
+ .string "per_device_platdata_auto_alloc_size"
+.LASF131:
+ .string "legacy_hdr_os_copy"
+.LASF195:
+ .string "UCLASS_MMC"
+.LASF289:
+ .string "dm_root_f"
+.LASF340:
+ .string "net_rx_packet"
+.LASF38:
+ .string "parent_priv"
+.LASF176:
+ .string "UCLASS_CROS_EC"
+.LASF310:
+ .string "console_evt"
+.LASF191:
+ .string "UCLASS_LPC"
+.LASF105:
+ .string "size_dt_struct"
+.LASF379:
+ .string "p_current"
+.LASF344:
+ .string "net_our_vlan"
+.LASF22:
+ .string "___strtok"
+.LASF67:
+ .string "bi_memsize"
+.LASF121:
+ .string "image_info"
+.LASF200:
+ .string "UCLASS_NVME"
+.LASF156:
+ .string "bootm_headers_t"
+.LASF252:
+ .string "UCLASS_RNG"
+.LASF249:
+ .string "UCLASS_MDIO"
+.LASF187:
+ .string "UCLASS_IDE"
+.LASF273:
+ .string "bus_clk"
+.LASF377:
+ .string "mem_malloc_end"
+.LASF225:
+ .string "UCLASS_SPI_FLASH"
+.LASF189:
+ .string "UCLASS_KEYBOARD"
+.LASF72:
+ .string "bi_sramsize"
+.LASF185:
+ .string "UCLASS_I2C_MUX"
+.LASF297:
+ .string "fdt_blob_kern"
+.LASF277:
+ .string "env_addr"
+.LASF48:
+ .string "prev"
+.LASF227:
+ .string "UCLASS_SYSCON"
+.LASF171:
+ .string "UCLASS_BLK"
+.LASF212:
+ .string "UCLASS_PWRSEQ"
+.LASF132:
+ .string "legacy_hdr_valid"
+.LASF264:
+ .string "tlb_fillptr"
+.LASF82:
+ .string "bi_arch_number"
+.LASF323:
+ .string "load_addr"
+.LASF291:
+ .string "fdt_blob"
+.LASF328:
+ .string "net_gateway"
+.LASF166:
+ .string "UCLASS_PCI_EMUL"
+.LASF424:
+ .string "offset"
+.LASF426:
+ .string "secure_otp_read"
+.LASF349:
+ .string "net_boot_file_expected_size_in_blocks"
+.LASF403:
+ .string "OTP_NS"
+.LASF414:
+ .string "spl_rockchip_otp_start"
+.LASF206:
+ .string "UCLASS_PHY"
+.LASF454:
+ .string "dev_get_driver_data"
+.LASF3:
+ .string "signed char"
+.LASF203:
+ .string "UCLASS_PCH"
+.LASF100:
+ .string "off_mem_rsvmap"
+.LASF163:
+ .string "UCLASS_TEST_PROBE"
+.LASF149:
+ .string "ft_len"
+.LASF19:
+ .string "uint32_t"
+.LASF384:
+ .string "udevice_id"
+.LASF325:
+ .string "save_size"
+.LASF439:
+ .string "read_end"
+.LASF378:
+ .string "mem_malloc_brk"
+.LASF124:
+ .string "load"
+.LASF143:
+ .string "fit_hdr_setup"
+.LASF299:
+ .string "timebase_h"
+.LASF160:
+ .string "UCLASS_TEST"
+.LASF87:
+ .string "IRQ_STACK_START"
+.LASF419:
+ .string "_u_boot_list_2_driver_2_rockchip_secure_otp"
+.LASF125:
+ .string "comp"
+.LASF70:
+ .string "bi_flashoffset"
+.LASF201:
+ .string "UCLASS_PANEL"
+.LASF266:
+ .string "pre_serial"
+.LASF36:
+ .string "uclass"
+.LASF162:
+ .string "UCLASS_TEST_BUS"
+.LASF460:
+ .string "/home/lxh/uboot/u-boot"
+.LASF238:
+ .string "UCLASS_VIDEO_CONSOLE"
+.LASF360:
+ .string "probe"
+.LASF10:
+ .string "long long unsigned int"
+.LASF260:
+ .string "lastinc"
+.LASF388:
+ .string "post_bind"
+.LASF284:
+ .string "irq_sp"
+.LASF449:
+ .string "rk3528_spl_rockchip_otp_stop"
+.LASF197:
+ .string "UCLASS_MTD"
+.LASF216:
+ .string "UCLASS_RESET"
+.LASF117:
+ .string "ih_type"
+.LASF80:
+ .string "bi_intfreq"
+.LASF172:
+ .string "UCLASS_CLK"
+.LASF350:
+ .string "net_ping_ip"
+.LASF79:
+ .string "bi_ethspeed"
+.LASF375:
+ .string "ofnode"
+.LASF435:
+ .string "rk3528_secure_otp_write_2_bytes_noecc"
+.LASF231:
+ .string "UCLASS_TPM"
+.LASF315:
+ .string "child"
+.LASF443:
+ .string "rockchip_secure_otp_wait_flag"
+.LASF456:
+ .string "malloc_simple"
+.LASF59:
+ .string "lmb_property"
+.LASF268:
+ .string "enable"
+.LASF262:
+ .string "tlb_addr"
+.LASF373:
+ .string "value"
+.LASF184:
+ .string "UCLASS_I2C_GENERIC"
+.LASF99:
+ .string "off_dt_strings"
+.LASF418:
+ .string "rockchip_otp_ids"
+.LASF103:
+ .string "boot_cpuid_phys"
+.LASF361:
+ .string "remove"
+.LASF133:
+ .string "fit_uname_cfg"
+.LASF106:
+ .string "working_fdt"
+.LASF316:
+ .string "sibling"
+.LASF118:
+ .string "ih_comp"
+.LASF202:
+ .string "UCLASS_PANEL_BACKLIGHT"
+.LASF81:
+ .string "bi_busfreq"
+.LASF296:
+ .string "ufdt_blob"
+.LASF279:
+ .string "ram_top"
+.LASF271:
+ .string "global_data"
+.LASF327:
+ .string "s_addr"
+.LASF127:
+ .string "arch"
+.LASF226:
+ .string "UCLASS_SPI_GENERIC"
+.LASF317:
+ .string "mtd_info"
+.LASF95:
+ .string "fdt_header"
+.LASF177:
+ .string "UCLASS_DISPLAY"
+.LASF390:
+ .string "pre_probe"
+.LASF352:
+ .string "net_loop_state"
+.LASF55:
+ .string "protect"
+.LASF306:
+ .string "video_bottom"
+.LASF438:
+ .string "write_end"
+.LASF71:
+ .string "bi_sramstart"
+.LASF224:
+ .string "UCLASS_SPMI"
+.LASF220:
+ .string "UCLASS_SCMI_AGENT"
+.LASF23:
+ .string "_Bool"
+.LASF12:
+ .string "phys_size_t"
+.LASF45:
+ .string "udevice"
+.LASF37:
+ .string "uclass_priv"
+.LASF123:
+ .string "image_len"
+.LASF318:
+ .string "jt_funcs"
+.LASF408:
+ .string "call"
+.LASF330:
+ .string "net_dns_server"
+.LASF427:
+ .string "rk3528_secure_otp_write"
+.LASF397:
+ .string "__invalid_size_argument_for_IOC"
+.LASF57:
+ .string "flash_info"
+.LASF462:
+ .string "free"
+.LASF288:
+ .string "dm_root"
+.LASF108:
+ .string "ih_magic"
+.LASF218:
+ .string "UCLASS_RAMDISK"
+.LASF450:
+ .string "rk3528_spl_rockchip_otp_start"
+.LASF26:
+ .string "_binary_u_boot_bin_end"
+.LASF141:
+ .string "fit_uname_fdt"
+.LASF190:
+ .string "UCLASS_LED"
+.LASF292:
+ .string "new_fdt"
+.LASF407:
+ .string "ioctl"
+.LASF170:
+ .string "UCLASS_AHCI"
+.LASF41:
+ .string "sibling_node"
+.LASF333:
+ .string "net_root_path"
+.LASF49:
+ .string "block_drvr"
+.LASF9:
+ .string "long long int"
+.LASF250:
+ .string "UCLASS_EBC"
+.LASF324:
+ .string "save_addr"
+.LASF35:
+ .string "priv"
+.LASF209:
+ .string "UCLASS_PMIC"
+.LASF302:
+ .string "malloc_limit"
+.LASF14:
+ .string "char"
+.LASF413:
+ .string "secure_otp_data"
+.LASF180:
+ .string "UCLASS_GPIO"
+.LASF44:
+ .string "ide_bus_offset"
+.LASF254:
+ .string "UCLASS_PD"
+.LASF52:
+ .string "sector_count"
+.LASF145:
+ .string "fit_noffset_setup"
+.LASF122:
+ .string "image_start"
+.LASF56:
+ .string "flash_info_t"
+.LASF228:
+ .string "UCLASS_SYSRESET"
+.LASF115:
+ .string "ih_os"
+.LASF31:
+ .string "uclass_platdata"
+.LASF336:
+ .string "net_ip"
+.LASF458:
+ .ascii "GNU C11 6.3.1 201"
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
+.LASF305:
+ .string "video_top"
+.LASF257:
+ .string "LOGF_MAX_CATEGORIES"
+.LASF357:
+ .string "net_state"
+.LASF459:
+ .string "drivers/misc/rk3528-secure-otp.c"
+.LASF285:
+ .string "start_addr_sp"
+.LASF135:
+ .string "fit_uname_os"
+.LASF18:
+ .string "uint8_t"
+.LASF7:
+ .string "__u32"
+.LASF362:
+ .string "unbind"
+.LASF283:
+ .string "mon_len"
+.LASF356:
+ .string "NETLOOP_FAIL"
+.LASF428:
+ .string "data_byte"
+.LASF364:
+ .string "child_post_bind"
+.LASF313:
+ .string "full_name"
+.LASF214:
+ .string "UCLASS_REGULATOR"
+.LASF183:
+ .string "UCLASS_I2C_EEPROM"
+.LASF370:
+ .string "per_child_platdata_auto_alloc_size"
+.LASF444:
+ .string "rockchip_secure_otp_wait_status"
+.LASF129:
+ .string "bootm_headers"
+.LASF275:
+ .string "mem_clk"
+.LASF358:
+ .string "of_match"
+.LASF351:
+ .string "uclass_id"
+.LASF320:
+ .string "monitor_flash_len"
+.LASF366:
+ .string "child_post_remove"
+.LASF369:
+ .string "per_child_auto_alloc_size"
+.LASF213:
+ .string "UCLASS_RAM"
+.LASF293:
+ .string "fdt_size"
+.LASF363:
+ .string "ofdata_to_platdata"
+.LASF208:
+ .string "UCLASS_PINCTRL"
+.LASF29:
+ .string "platdata"
+.LASF259:
+ .string "timer_rate_hz"
+.LASF433:
+ .string "rk3528_secure_otp_write_byte_noecc"
+.LASF434:
+ .string "data_2b"
+.LASF90:
+ .string "_datarelrolocal_start_ofs"
+.LASF164:
+ .string "UCLASS_SPI_EMUL"
+.LASF196:
+ .string "UCLASS_MOD_EXP"
+.LASF97:
+ .string "totalsize"
+.LASF387:
+ .string "uclass_driver"
+.LASF73:
+ .string "bi_arm_freq"
+.LASF199:
+ .string "UCLASS_NORTHBRIDGE"
+.LASF235:
+ .string "UCLASS_USB_GADGET_GENERIC"
+.LASF120:
+ .string "image_header_t"
+.LASF68:
+ .string "bi_flashstart"
+.LASF92:
+ .string "_datarelro_start_ofs"
+.LASF346:
+ .string "net_restart_wrap"
+.LASF385:
+ .string "compatible"
+.LASF165:
+ .string "UCLASS_I2C_EMUL"
+.LASF274:
+ .string "pci_clk"
+.LASF173:
+ .string "UCLASS_CPU"
+.LASF343:
+ .string "net_null_ethaddr"
+.LASF86:
+ .string "bd_t"
+.LASF174:
+ .string "UCLASS_AMP"
+.LASF243:
+ .string "UCLASS_RC"
+.LASF453:
+ .string "dev_read_u32_default"
+.LASF337:
+ .string "net_server_ip"
+.LASF280:
+ .string "ram_top_ext_size"
+.LASF51:
+ .string "size"
+.LASF58:
+ .string "long double"
+.LASF76:
+ .string "bi_bootflags"
+.LASF83:
+ .string "bi_boot_params"
+.LASF441:
+ .string "rockchip_secure_otp_check_flag"
+.LASF448:
+ .string "mask"
+.LASF246:
+ .string "UCLASS_IO_DOMAIN"
+.LASF25:
+ .string "_binary_u_boot_bin_start"
+.LASF159:
+ .string "UCLASS_DEMO"
+.LASF107:
+ .string "image_header"
+.LASF102:
+ .string "last_comp_version"
+.LASF321:
+ .string "__dtb_dt_begin"
+.LASF251:
+ .string "UCLASS_EINK_DISPLAY"
+.LASF309:
+ .string "sys_start_tick"
+.LASF168:
+ .string "UCLASS_SIMPLE_BUS"
+.LASF179:
+ .string "UCLASS_ETH"
+.LASF153:
+ .string "cmdline_end"
+.LASF75:
+ .string "bi_ddr_freq"
+.LASF98:
+ .string "off_dt_struct"
+.LASF440:
+ .string "rockchip_secure_otp_ecc_enable"
+.LASF301:
+ .string "malloc_base"
+.LASF308:
+ .string "serial"
+.LASF386:
+ .string "data"
+.LASF329:
+ .string "net_netmask"
+.LASF322:
+ .string "__dtb_dt_spl_begin"
+.LASF65:
+ .string "bd_info"
+.LASF152:
+ .string "cmdline_start"
+.LASF157:
+ .string "images"
+.LASF267:
+ .string "using_pre_serial"
+.LASF130:
+ .string "legacy_hdr_os"
+.LASF425:
+ .string "otp_data"
+.LASF192:
+ .string "UCLASS_MAILBOX"
+.LASF217:
+ .string "UCLASS_RKNAND"
+.LASF138:
+ .string "fit_uname_rd"
+.LASF77:
+ .string "bi_ip_addr"
+.LASF307:
+ .string "pm_ctx_phys"
+.LASF295:
+ .string "of_root_f"
+.LASF281:
+ .string "relocaddr"
+.LASF33:
+ .string "driver_data"
+.LASF0:
+ .string "unsigned char"
+.LASF11:
+ .string "phys_addr_t"
+.LASF389:
+ .string "pre_unbind"
+.LASF13:
+ .string "sizetype"
+.LASF338:
+ .string "net_tx_packet"
+.LASF395:
+ .string "per_device_auto_alloc_size"
+.LASF150:
+ .string "initrd_start"
+.LASF34:
+ .string "parent"
+.LASF380:
+ .string "current"
+.LASF6:
+ .string "short int"
+.LASF116:
+ .string "ih_arch"
+.LASF400:
+ .string "DECOM_GZIP"
+.LASF314:
+ .string "properties"
+.LASF240:
+ .string "UCLASS_WDT"
+.LASF442:
+ .string "delay"
+.LASF372:
+ .string "length"
+.LASF331:
+ .string "net_nis_domain"
+.LASF112:
+ .string "ih_load"
+.LASF298:
+ .string "env_buf"
+.LASF355:
+ .string "NETLOOP_SUCCESS"
+.LASF167:
+ .string "UCLASS_USB_EMUL"
+.LASF429:
+ .string "temp"
+.LASF161:
+ .string "UCLASS_TEST_FDT"
+.LASF415:
+ .string "spl_rockchip_otp_stop"
+.LASF445:
+ .string "flag"
+.LASF17:
+ .string "ulong"
+.LASF110:
+ .string "ih_time"
+.LASF111:
+ .string "ih_size"
+.LASF178:
+ .string "UCLASS_DMA"
+.LASF253:
+ .string "UCLASS_DMC"
+.LASF215:
+ .string "UCLASS_REMOTEPROC"
+.LASF353:
+ .string "NETLOOP_CONTINUE"
+.LASF219:
+ .string "UCLASS_RTC"
+.LASF261:
+ .string "timer_reset_value"
+.LASF294:
+ .string "of_root"
+.LASF339:
+ .string "net_rx_packets"
+.LASF194:
+ .string "UCLASS_MISC"
+.LASF62:
+ .string "region"
+.LASF148:
+ .string "ft_addr"
+.LASF416:
+ .string "rockchip_secure_otp_ops"
+.LASF405:
+ .string "read"
+.LASF54:
+ .string "start"
+.LASF144:
+ .string "fit_uname_setup"
+.LASF114:
+ .string "ih_dcrc"
+.LASF24:
+ .string "image_base"
+.LASF392:
+ .string "pre_remove"
+.LASF158:
+ .string "UCLASS_ROOT"
+.LASF96:
+ .string "magic"
+.LASF241:
+ .string "UCLASS_FG"
+.LASF137:
+ .string "fit_hdr_rd"
+.LASF140:
+ .string "fit_hdr_fdt"
+.LASF113:
+ .string "ih_ep"
+.LASF286:
+ .string "reloc_off"
+.LASF393:
+ .string "init"
+.LASF239:
+ .string "UCLASS_VIDEO_CRTC"
+.LASF236:
+ .string "UCLASS_VIDEO"
+.LASF446:
+ .string "secure_conf"
+.LASF205:
+ .string "UCLASS_PCI_GENERIC"
+.LASF1:
+ .string "long unsigned int"
+.LASF5:
+ .string "__u8"
+.LASF374:
+ .string "of_offset"
+.LASF258:
+ .string "arch_global_data"
+.LASF89:
+ .string "_datarel_start_ofs"
+.LASF311:
+ .string "device_node"
+.LASF263:
+ .string "tlb_size"
+.LASF66:
+ .string "bi_memstart"
+.LASF109:
+ .string "ih_hcrc"
+.LASF104:
+ .string "size_dt_strings"
+.LASF128:
+ .string "image_info_t"
+.LASF63:
+ .string "memory"
+.LASF27:
+ .string "driver"
+.LASF147:
+ .string "rd_end"
+.LASF193:
+ .string "UCLASS_MASS_STORAGE"
+.LASF326:
+ .string "in_addr"
+.LASF151:
+ .string "initrd_end"
+.LASF210:
+ .string "UCLASS_PWM"
+.LASF93:
+ .string "IRQ_STACK_START_IN"
+.LASF84:
+ .string "bi_andr_version"
+.LASF126:
+ .string "type"
+.LASF341:
+ .string "net_rx_packet_len"
+.LASF383:
+ .string "u_boot_dev_head"
+.LASF431:
+ .string "rk3528_secure_otp_write_2_bytes"
+.LASF221:
+ .string "UCLASS_SCSI"
+.LASF16:
+ .string "ushort"
+.LASF204:
+ .string "UCLASS_PCI"
+.LASF198:
+ .string "UCLASS_NOP"
+.LASF394:
+ .string "destroy"
+.LASF447:
+ .string "otp_cru_rst"
+.LASF247:
+ .string "UCLASS_CRYPTO"
+.LASF452:
+ .string "dev_read_addr_ptr"
+.LASF276:
+ .string "have_console"
+.LASF399:
+ .string "DECOM_LZ4"
+.LASF175:
+ .string "UCLASS_CODEC"
+.LASF381:
+ .string "uc_drv"
+.LASF232:
+ .string "UCLASS_USB"
+.LASF304:
+ .string "cur_serial_dev"
+.LASF270:
+ .string "addr"
+.LASF46:
+ .string "list_head"
+.LASF155:
+ .string "state"
+.LASF20:
+ .string "__be32"
+.LASF207:
+ .string "UCLASS_PINCONFIG"
+.LASF233:
+ .string "UCLASS_USB_DEV_GENERIC"
+.LASF342:
+ .string "net_bcast_ethaddr"
+.LASF136:
+ .string "fit_noffset_os"
+.LASF223:
+ .string "UCLASS_SPI"
+.LASF436:
+ .string "rk3528_secure_otp_read"
+.LASF335:
+ .string "net_server_ethaddr"
+.LASF255:
+ .string "UCLASS_COUNT"
+.LASF278:
+ .string "env_valid"
+.LASF245:
+ .string "UCLASS_DVFS"
+.LASF412:
+ .string "otp_cru_rst_base"
+.LASF40:
+ .string "child_head"
+.LASF50:
+ .string "select_hwpart"
+.LASF4:
+ .string "uchar"
+.LASF69:
+ .string "bi_flashsize"
+.LASF382:
+ .string "dev_head"
+.LASF409:
+ .string "rockchip_otp_platdata"
+.LASF2:
+ .string "short unsigned int"
+.LASF391:
+ .string "post_probe"
+.LASF365:
+ .string "child_pre_probe"
+.LASF421:
+ .string "secure_otp_ioctl"
+.LASF347:
+ .string "net_boot_file_name"
+.LASF406:
+ .string "write"
+.LASF244:
+ .string "UCLASS_CHARGE_DISPLAY"
+.LASF256:
+ .string "UCLASS_INVALID"
+.LASF402:
+ .string "OTP_S"
+.LASF432:
+ .string "__func__"
+.LASF64:
+ .string "reserved"
+.LASF417:
+ .string "rk3528_data"
+.LASF182:
+ .string "UCLASS_I2C"
+.LASF119:
+ .string "ih_name"
+.LASF461:
+ .string "ofnode_union"
+.LASF411:
+ .string "otp_mask_base"
+.LASF169:
+ .string "UCLASS_ADC"
+.LASF43:
+ .string "req_seq"
+.LASF282:
+ .string "ram_size"
+.LASF451:
+ .string "dev_get_platdata"
+.LASF186:
+ .string "UCLASS_I2S"
+.LASF367:
+ .string "priv_auto_alloc_size"
+.LASF30:
+ .string "parent_platdata"
+.LASF410:
+ .string "secure_conf_base"
+.LASF154:
+ .string "verify"
+.LASF88:
+ .string "FIQ_STACK_START"
+.LASF85:
+ .string "bi_dram"
+.LASF430:
+ .string "rockchip_secure_otp_capability"
+.LASF345:
+ .string "net_native_vlan"
+.LASF423:
+ .string "secure_otp_write"
+.LASF211:
+ .string "UCLASS_POWER_DOMAIN"
+.LASF398:
+ .string "misc_mode"
+.LASF272:
+ .string "cpu_clk"
+.LASF237:
+ .string "UCLASS_VIDEO_BRIDGE"
+.LASF368:
+ .string "platdata_auto_alloc_size"
+.LASF61:
+ .string "lmb_region"
+.LASF242:
+ .string "UCLASS_KEY"
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
+ .section .note.GNU-stack,"",@progbits
diff --git a/u-boot/drivers/misc/rk3562-secure-otp.S b/u-boot/drivers/misc/rk3562-secure-otp.S
new file mode 100644
index 0000000..e3b3f34
--- /dev/null
+++ b/u-boot/drivers/misc/rk3562-secure-otp.S
@@ -0,0 +1,15906 @@
+ .arch armv8-a+nosimd
+ .file "rk3562-secure-otp.c"
+ .text
+.Ltext0:
+ .cfi_sections .debug_frame
+ .section .text.rk3562_spl_rockchip_otp_stop,"ax",@progbits
+ .align 2
+ .type rk3562_spl_rockchip_otp_stop, %function
+rk3562_spl_rockchip_otp_stop:
+.LFB263:
+ .file 1 "drivers/misc/rk3562-secure-otp.c"
+ .loc 1 81 0
+ .cfi_startproc
+.LVL0:
+.LBB22:
+ .loc 1 82 0
+#APP
+// 82 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w1, 524288
+.LVL1:
+ str w1, [x0]
+ ret
+.LBE22:
+ .cfi_endproc
+.LFE263:
+ .size rk3562_spl_rockchip_otp_stop, .-rk3562_spl_rockchip_otp_stop
+ .section .text.secure_otp_ioctl,"ax",@progbits
+ .align 2
+ .type secure_otp_ioctl, %function
+secure_otp_ioctl:
+.LFB276:
+ .loc 1 697 0
+ .cfi_startproc
+.LVL2:
+ .loc 1 700 0
+ mov x0, 27908
+.LVL3:
+ cmp x1, x0
+ bne .L6
+.LVL4:
+.LBB23:
+.LBB24:
+ .loc 1 689 0
+ mov w0, 8
+ str w0, [x2]
+.LVL5:
+.LBE24:
+.LBE23:
+ .loc 1 702 0
+ mov w0, 0
+ .loc 1 703 0
+ ret
+.LVL6:
+.L6:
+ .loc 1 698 0
+ mov w0, -22
+ .loc 1 709 0
+ ret
+ .cfi_endproc
+.LFE276:
+ .size secure_otp_ioctl, .-secure_otp_ioctl
+ .section .text.secure_otp_write,"ax",@progbits
+ .align 2
+ .type secure_otp_write, %function
+secure_otp_write:
+.LFB274:
+ .loc 1 681 0
+ .cfi_startproc
+.LVL7:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov x19, x0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -16
+ .cfi_offset 22, -8
+ .loc 1 681 0
+ mov w20, w1
+ mov x21, x2
+ mov w22, w3
+ .loc 1 682 0
+ bl dev_get_driver_data
+.LVL8:
+ .loc 1 684 0
+ ldr x4, [x0, 8]
+ mov w3, w22
+ mov x2, x21
+ mov w1, w20
+ mov x0, x19
+.LVL9:
+ .loc 1 685 0
+ ldp x21, x22, [sp, 32]
+.LVL10:
+ ldp x19, x20, [sp, 16]
+.LVL11:
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ .loc 1 684 0
+ br x4
+.LVL12:
+ .cfi_endproc
+.LFE274:
+ .size secure_otp_write, .-secure_otp_write
+ .section .text.secure_otp_read,"ax",@progbits
+ .align 2
+ .type secure_otp_read, %function
+secure_otp_read:
+.LFB273:
+ .loc 1 673 0
+ .cfi_startproc
+.LVL13:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov x19, x0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -16
+ .cfi_offset 22, -8
+ .loc 1 673 0
+ mov w20, w1
+ mov x21, x2
+ mov w22, w3
+ .loc 1 674 0
+ bl dev_get_driver_data
+.LVL14:
+ .loc 1 676 0
+ ldr x4, [x0]
+ mov w3, w22
+ mov x2, x21
+ mov w1, w20
+ mov x0, x19
+.LVL15:
+ .loc 1 677 0
+ ldp x21, x22, [sp, 32]
+.LVL16:
+ ldp x19, x20, [sp, 16]
+.LVL17:
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ .loc 1 676 0
+ br x4
+.LVL18:
+ .cfi_endproc
+.LFE273:
+ .size secure_otp_read, .-secure_otp_read
+ .section .text.rockchip_secure_otp_ofdata_to_platdata,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_ofdata_to_platdata, %function
+rockchip_secure_otp_ofdata_to_platdata:
+.LFB277:
+ .loc 1 718 0
+ .cfi_startproc
+.LVL19:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 718 0
+ mov x20, x0
+ .loc 1 719 0
+ bl dev_get_platdata
+.LVL20:
+ mov x19, x0
+.LVL21:
+ .loc 1 721 0
+ mov x0, x20
+.LVL22:
+ bl dev_read_addr_ptr
+.LVL23:
+ .loc 1 722 0
+ mov w2, 0
+ adrp x1, .LC0
+ .loc 1 721 0
+ str x0, [x19]
+ .loc 1 722 0
+ add x1, x1, :lo12:.LC0
+ mov x0, x20
+ bl dev_read_u32_default
+.LVL24:
+ .loc 1 723 0
+ uxtw x0, w0
+ str x0, [x19, 8]
+ .loc 1 724 0
+ mov w2, 0
+ mov x0, x20
+ adrp x1, .LC1
+ add x1, x1, :lo12:.LC1
+ bl dev_read_u32_default
+.LVL25:
+ .loc 1 725 0
+ uxtw x0, w0
+ str x0, [x19, 16]
+ .loc 1 726 0
+ mov w2, 0
+ mov x0, x20
+ adrp x1, .LC2
+ add x1, x1, :lo12:.LC2
+ bl dev_read_u32_default
+.LVL26:
+ .loc 1 727 0
+ uxtw x0, w0
+ str x0, [x19, 24]
+ .loc 1 730 0
+ mov w0, 0
+ ldp x19, x20, [sp, 16]
+.LVL27:
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE277:
+ .size rockchip_secure_otp_ofdata_to_platdata, .-rockchip_secure_otp_ofdata_to_platdata
+ .section .text.rk3562_spl_rockchip_otp_start,"ax",@progbits
+ .align 2
+ .type rk3562_spl_rockchip_otp_start, %function
+rk3562_spl_rockchip_otp_start:
+.LFB262:
+ .loc 1 69 0
+ .cfi_startproc
+.LVL28:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+ .loc 1 69 0
+ mov x19, x1
+.LBB25:
+ .loc 1 71 0
+#APP
+// 71 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w1, 524296
+.LVL29:
+ str w1, [x0]
+.LVL30:
+.LBE25:
+.LBB26:
+ .loc 1 72 0
+#APP
+// 72 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w0, 1048592
+.LVL31:
+ str w0, [x19]
+.LBE26:
+ .loc 1 73 0
+ mov x0, 2
+ bl udelay
+.LVL32:
+.LBB27:
+ .loc 1 74 0
+#APP
+// 74 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ mov w0, 1048576
+ str w0, [x19]
+.LBE27:
+ .loc 1 76 0
+ ldr x19, [sp, 16]
+.LVL33:
+ .loc 1 75 0
+ mov x0, 1
+ .loc 1 76 0
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+ .loc 1 75 0
+ b udelay
+.LVL34:
+ .cfi_endproc
+.LFE262:
+ .size rk3562_spl_rockchip_otp_start, .-rk3562_spl_rockchip_otp_start
+ .section .text.rockchip_secure_otp_check_flag.isra.0,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_check_flag.isra.0, %function
+rockchip_secure_otp_check_flag.isra.0:
+.LFB278:
+ .loc 1 129 0
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 129 0
+ mov w19, 34465
+ mov x20, x0
+ movk w19, 0x1, lsl 16
+.L17:
+.LVL35:
+.LBB28:
+ .loc 1 136 0
+ ldr x0, [x20]
+ ldr w1, [x0, 44]
+.LVL36:
+#APP
+// 136 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL37:
+#NO_APP
+.LBE28:
+ .loc 1 137 0
+ and w0, w1, 16
+ tbz x1, 4, .L15
+ .loc 1 140 0
+ subs w19, w19, #1
+.LVL38:
+ beq .L18
+.LVL39:
+ .loc 1 146 0
+ mov x0, 1
+ bl udelay
+.LVL40:
+ b .L17
+.LVL41:
+.L18:
+ .loc 1 141 0
+ mov w0, -1
+.LVL42:
+.L15:
+ .loc 1 150 0
+ ldp x19, x20, [sp, 16]
+ ldp x29, x30, [sp], 32
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE278:
+ .size rockchip_secure_otp_check_flag.isra.0, .-rockchip_secure_otp_check_flag.isra.0
+ .section .text.rockchip_secure_otp_wait_flag.isra.1,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_wait_flag.isra.1, %function
+rockchip_secure_otp_wait_flag.isra.1:
+.LFB279:
+ .loc 1 106 0
+ .cfi_startproc
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -16
+ .cfi_offset 20, -8
+ .loc 1 106 0
+ mov x20, x0
+ mov w19, 20001
+.L25:
+.LVL43:
+.LBB29:
+ .loc 1 113 0
+ ldr x0, [x20]
+ ldr w0, [x0, 44]
+.LVL44:
+#APP
+// 113 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL45:
+#NO_APP
+.LBE29:
+ .loc 1 114 0
+ tbnz x0, 4, .L26
+ .loc 1 117 0
+ subs w19, w19, #1
+.LVL46:
+ beq .L27
+ .loc 1 122 0
+ mov x0, 1
+.LVL47:
+ bl udelay
+.LVL48:
+ b .L25
+.LVL49:
+.L26:
+ .loc 1 110 0
+ mov w0, 0
+.LVL50:
+.L23:
+ .loc 1 127 0
+ ldp x19, x20, [sp, 16]
+ ldp x29, x30, [sp], 32
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL51:
+.L27:
+ .cfi_restore_state
+ .loc 1 118 0
+ mov w0, -1
+.LVL52:
+ b .L23
+ .cfi_endproc
+.LFE279:
+ .size rockchip_secure_otp_wait_flag.isra.1, .-rockchip_secure_otp_wait_flag.isra.1
+ .section .text.rockchip_secure_otp_wait_status.isra.2,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_wait_status.isra.2, %function
+rockchip_secure_otp_wait_status.isra.2:
+.LFB280:
+ .loc 1 86 0
+ .cfi_startproc
+.LVL53:
+ stp x29, x30, [sp, -48]!
+ .cfi_def_cfa_offset 48
+ .cfi_offset 29, -48
+ .cfi_offset 30, -40
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -32
+ .cfi_offset 20, -24
+ mov w19, w1
+ str x21, [sp, 32]
+ .cfi_offset 21, -16
+ .loc 1 86 0
+ mov x21, x0
+ mov w20, 10000
+.LVL54:
+.L30:
+.LBB36:
+ .loc 1 91 0
+ ldr x0, [x21]
+ ldr w0, [x0, 772]
+.LVL55:
+#APP
+// 91 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+.LBE36:
+ tst w0, w19
+ beq .L32
+.LBB37:
+ .loc 1 101 0
+ orr w19, w19, -65536
+.LVL56:
+#APP
+// 101 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x21]
+.LVL57:
+ str w19, [x0, 772]
+.LBE37:
+ .loc 1 103 0
+ mov w0, 0
+ b .L29
+.LVL58:
+.L32:
+ .loc 1 92 0
+ mov x0, 1
+.LVL59:
+ bl udelay
+.LVL60:
+ .loc 1 94 0
+ subs w20, w20, #1
+.LVL61:
+ bne .L30
+.LVL62:
+.LBB38:
+.LBB39:
+ .loc 1 95 0
+ adrp x1, .LANCHOR0
+ adrp x0, .LC3
+ add x1, x1, :lo12:.LANCHOR0
+ add x0, x0, :lo12:.LC3
+ bl printf
+.LVL63:
+ mov w0, -110
+.LVL64:
+.L29:
+.LBE39:
+.LBE38:
+ .loc 1 104 0
+ ldp x19, x20, [sp, 16]
+.LVL65:
+ ldr x21, [sp, 32]
+ ldp x29, x30, [sp], 48
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 21
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+ .cfi_endproc
+.LFE280:
+ .size rockchip_secure_otp_wait_status.isra.2, .-rockchip_secure_otp_wait_status.isra.2
+ .section .text.rk3562_secure_otp_write_2_bytes_noecc,"ax",@progbits
+ .align 2
+ .type rk3562_secure_otp_write_2_bytes_noecc, %function
+rk3562_secure_otp_write_2_bytes_noecc:
+.LFB269:
+ .loc 1 240 0
+ .cfi_startproc
+.LVL66:
+ stp x29, x30, [sp, -96]!
+ .cfi_def_cfa_offset 96
+ .cfi_offset 29, -96
+ .cfi_offset 30, -88
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -48
+ .cfi_offset 24, -40
+ mov w24, w2
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -80
+ .cfi_offset 20, -72
+ .loc 1 244 0
+ asr w20, w24, 1
+ .loc 1 240 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -64
+ .cfi_offset 22, -56
+ and w21, w3, 65535
+ stp x25, x26, [sp, 64]
+ .cfi_offset 25, -32
+ .cfi_offset 26, -24
+ mov x26, x1
+ stp x27, x28, [sp, 80]
+ .cfi_offset 27, -16
+ .cfi_offset 28, -8
+ .loc 1 242 0
+ bl dev_get_driver_data
+.LVL67:
+ .loc 1 245 0
+ cmp w20, 447
+ bgt .L43
+ mov x23, x0
+ .loc 1 249 0
+ sub w0, w20, #416
+.LVL68:
+ cmp w0, 15
+ ccmp w20, 16, 4, hi
+ beq .L37
+ .loc 1 252 0
+ adrp x0, .LC4
+ and w1, w24, -2
+ add x0, x0, :lo12:.LC4
+ bl printf
+.LVL69:
+.L43:
+ .loc 1 246 0
+ mov w0, -1
+.LVL70:
+.L35:
+ .loc 1 446 0
+ ldp x19, x20, [sp, 16]
+.LVL71:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+ ldp x25, x26, [sp, 64]
+.LVL72:
+ ldp x27, x28, [sp, 80]
+ ldp x29, x30, [sp], 96
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 28
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL73:
+.L37:
+ .cfi_restore_state
+ .loc 1 256 0
+ cbz w21, .L44
+ .loc 1 259 0
+ ldr x6, [x23, 16]
+ mov w3, w20
+ ldp x0, x2, [x26, 8]
+ ldr x1, [x26, 24]
+ blr x6
+.LVL74:
+.LBB40:
+ .loc 1 262 0
+#APP
+// 262 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 65536
+ str w1, [x0, 256]
+.LVL75:
+.LBE40:
+.LBB41:
+ .loc 1 263 0
+#APP
+// 263 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 262148
+ str w1, [x0, 32]
+.LVL76:
+.LBE41:
+.LBB42:
+ .loc 1 264 0
+#APP
+// 264 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, -65536
+ str w1, [x0, 40]
+.LVL77:
+.LBE42:
+.LBB43:
+ .loc 1 265 0
+#APP
+// 265 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL78:
+.LBE43:
+.LBB44:
+ .loc 1 266 0
+#APP
+// 266 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w22, -65534
+ str w22, [x0, 36]
+.LVL79:
+.LBE44:
+.LBB45:
+ .loc 1 267 0
+#APP
+// 267 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 252
+ str w1, [x0, 4096]
+.LVL80:
+.LBE45:
+.LBB46:
+ .loc 1 268 0
+#APP
+// 268 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL81:
+.LBE46:
+.LBB47:
+ .loc 1 269 0
+#APP
+// 269 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4104]
+.LVL82:
+.LBE47:
+.LBB48:
+ .loc 1 270 0
+#APP
+// 270 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w19, 65537
+.LBE48:
+ .loc 1 271 0
+ mov w1, 2
+.LBB49:
+ .loc 1 270 0
+ str w19, [x0, 32]
+.LBE49:
+ .loc 1 271 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL83:
+ .loc 1 272 0
+ tbz w0, #31, .L38
+.L40:
+ .loc 1 273 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC5
+.LVL84:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC5
+.L46:
+ .loc 1 406 0
+ bl printf
+.LVL85:
+.L39:
+ .loc 1 442 0
+ ldr x5, [x23, 24]
+ mov w3, w20
+ ldp x0, x2, [x26, 8]
+ ldr x1, [x26, 24]
+ blr x5
+.LVL86:
+.L44:
+ .loc 1 257 0
+ mov w0, 0
+ b .L35
+.LVL87:
+.L38:
+.LBB50:
+ .loc 1 277 0
+#APP
+// 277 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL88:
+ mov w28, -65522
+ str w28, [x0, 36]
+.LVL89:
+.LBE50:
+.LBB51:
+ .loc 1 278 0
+#APP
+// 278 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w27, 240
+ str w27, [x0, 4096]
+.LVL90:
+.LBE51:
+.LBB52:
+ .loc 1 279 0
+#APP
+// 279 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL91:
+.LBE52:
+.LBB53:
+ .loc 1 280 0
+#APP
+// 280 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w25, 122
+ str w25, [x0, 4104]
+.LVL92:
+.LBE53:
+.LBB54:
+ .loc 1 281 0
+#APP
+// 281 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 37
+ str w1, [x0, 4108]
+.LVL93:
+.LBE54:
+.LBB55:
+ .loc 1 282 0
+#APP
+// 282 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4112]
+.LVL94:
+.LBE55:
+.LBB56:
+ .loc 1 283 0
+#APP
+// 283 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4116]
+.LVL95:
+.LBE56:
+.LBB57:
+ .loc 1 284 0
+#APP
+// 284 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4120]
+.LVL96:
+.LBE57:
+.LBB58:
+ .loc 1 285 0
+#APP
+// 285 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 31
+ str w1, [x0, 4124]
+.LVL97:
+.LBE58:
+.LBB59:
+ .loc 1 286 0
+#APP
+// 286 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 11
+ str w1, [x0, 4128]
+.LVL98:
+.LBE59:
+.LBB60:
+ .loc 1 287 0
+#APP
+// 287 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 8
+ str w1, [x0, 4132]
+.LVL99:
+.LBE60:
+.LBB61:
+ .loc 1 288 0
+#APP
+// 288 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4136]
+.LVL100:
+.LBE61:
+.LBB62:
+ .loc 1 289 0
+#APP
+// 289 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4140]
+.LVL101:
+.LBE62:
+.LBB63:
+ .loc 1 290 0
+#APP
+// 290 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4144]
+.LBE63:
+.LBB64:
+ .loc 1 291 0
+ and w0, w20, 255
+#APP
+// 291 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x26]
+.LBE64:
+.LBB65:
+ .loc 1 292 0
+ ubfx x5, x24, 9, 8
+.LVL102:
+.LBE65:
+.LBB66:
+ .loc 1 291 0
+ str w0, [x1, 4148]
+.LBE66:
+.LBB67:
+ .loc 1 292 0
+#APP
+// 292 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w5, [x0, 4152]
+.LVL103:
+.LBE67:
+.LBB68:
+ .loc 1 293 0
+#APP
+// 293 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE68:
+ .loc 1 294 0
+ mov w1, 2
+.LBB69:
+ .loc 1 293 0
+ str w19, [x0, 32]
+.LBE69:
+ .loc 1 294 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL104:
+ .loc 1 295 0
+ tbnz w0, #31, .L40
+.LVL105:
+.LBB70:
+ .loc 1 300 0
+#APP
+// 300 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL106:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL107:
+.LBE70:
+.LBB71:
+ .loc 1 301 0
+#APP
+// 301 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 250
+ str w1, [x0, 4096]
+.LVL108:
+.LBE71:
+.LBB72:
+ .loc 1 302 0
+#APP
+// 302 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 9
+ str w1, [x0, 4100]
+.LVL109:
+.LBE72:
+.LBB73:
+ .loc 1 303 0
+#APP
+// 303 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE73:
+ .loc 1 304 0
+ mov w1, 2
+.LBB74:
+ .loc 1 303 0
+ str w19, [x0, 32]
+.LBE74:
+ .loc 1 304 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL110:
+ .loc 1 305 0
+ tbnz w0, #31, .L40
+.LVL111:
+.LBB75:
+ .loc 1 310 0
+#APP
+// 310 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL112:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL113:
+.LBE75:
+.LBB76:
+ .loc 1 311 0
+#APP
+// 311 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w28, [x0, 36]
+.LVL114:
+.LBE76:
+.LBB77:
+ .loc 1 312 0
+#APP
+// 312 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w27, [x0, 4096]
+.LVL115:
+.LBE77:
+.LBB78:
+ .loc 1 313 0
+#APP
+// 313 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL116:
+.LBE78:
+.LBB79:
+ .loc 1 314 0
+#APP
+// 314 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w25, [x0, 4104]
+.LVL117:
+.LBE79:
+.LBB80:
+ .loc 1 315 0
+#APP
+// 315 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 21
+ str w1, [x0, 4108]
+.LVL118:
+.LBE80:
+.LBB81:
+ .loc 1 316 0
+#APP
+// 316 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 220
+ str w1, [x0, 4112]
+.LVL119:
+.LBE81:
+.LBB82:
+ .loc 1 317 0
+#APP
+// 317 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 146
+ str w1, [x0, 4116]
+.LVL120:
+.LBE82:
+.LBB83:
+ .loc 1 318 0
+#APP
+// 318 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 121
+ str w1, [x0, 4120]
+.LVL121:
+.LBE83:
+.LBB84:
+ .loc 1 319 0
+#APP
+// 319 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 129
+ str w1, [x0, 4124]
+.LVL122:
+.LBE84:
+.LBB85:
+ .loc 1 320 0
+#APP
+// 320 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 126
+ str w1, [x0, 4128]
+.LVL123:
+.LBE85:
+.LBB86:
+ .loc 1 321 0
+#APP
+// 321 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 33
+ str w1, [x0, 4132]
+.LVL124:
+.LBE86:
+.LBB87:
+ .loc 1 322 0
+#APP
+// 322 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 17
+ str w1, [x0, 4136]
+.LVL125:
+.LBE87:
+.LBB88:
+ .loc 1 323 0
+#APP
+// 323 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 157
+ str w1, [x0, 4140]
+.LVL126:
+.LBE88:
+.LBB89:
+ .loc 1 324 0
+#APP
+// 324 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w25, 2
+ str w25, [x0, 4144]
+.LVL127:
+.LBE89:
+.LBB90:
+ .loc 1 325 0
+#APP
+// 325 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4148]
+.LVL128:
+.LBE90:
+.LBB91:
+ .loc 1 326 0
+#APP
+// 326 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 64
+ str w1, [x0, 4152]
+.LVL129:
+.LBE91:
+.LBB92:
+ .loc 1 327 0
+#APP
+// 327 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE92:
+ .loc 1 328 0
+ mov w1, w25
+.LBB93:
+ .loc 1 327 0
+ str w19, [x0, 32]
+.LBE93:
+ .loc 1 328 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL130:
+ .loc 1 329 0
+ tbnz w0, #31, .L40
+.LVL131:
+.LBB94:
+ .loc 1 334 0
+#APP
+// 334 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL132:
+ str w22, [x0, 36]
+.LVL133:
+.LBE94:
+.LBB95:
+ .loc 1 335 0
+#APP
+// 335 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 252
+ str w1, [x0, 4096]
+.LVL134:
+.LBE95:
+.LBB96:
+ .loc 1 336 0
+#APP
+// 336 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL135:
+.LBE96:
+.LBB97:
+ .loc 1 337 0
+#APP
+// 337 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 112
+ str w1, [x0, 4104]
+.LVL136:
+.LBE97:
+.LBB98:
+ .loc 1 338 0
+#APP
+// 338 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE98:
+ .loc 1 339 0
+ mov w1, w25
+.LBB99:
+ .loc 1 338 0
+ str w19, [x0, 32]
+.LBE99:
+ .loc 1 339 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL137:
+ .loc 1 340 0
+ tbnz w0, #31, .L40
+.LVL138:
+.LBB100:
+ .loc 1 345 0
+#APP
+// 345 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL139:
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL140:
+.LBE100:
+.LBB101:
+ .loc 1 346 0
+#APP
+// 346 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w22, [x0, 36]
+.LVL141:
+.LBE101:
+.LBB102:
+ .loc 1 347 0
+#APP
+// 347 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 192
+ str w1, [x0, 4096]
+.LBE102:
+.LBB103:
+ .loc 1 348 0
+ and w1, w21, 255
+.LVL142:
+#APP
+// 348 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE103:
+.LBB104:
+ .loc 1 349 0
+ lsr w21, w21, 8
+.LVL143:
+.LBE104:
+.LBB105:
+ .loc 1 348 0
+ str w1, [x0, 4100]
+.LBE105:
+.LBB106:
+ .loc 1 349 0
+#APP
+// 349 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w21, [x0, 4104]
+.LVL144:
+.LBE106:
+.LBB107:
+ .loc 1 350 0
+#APP
+// 350 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE107:
+ .loc 1 351 0
+ mov w1, w25
+.LVL145:
+.LBB108:
+ .loc 1 350 0
+ str w19, [x0, 32]
+.LBE108:
+ .loc 1 351 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL146:
+ .loc 1 352 0
+ tbnz w0, #31, .L40
+.LVL147:
+.LBB109:
+ .loc 1 357 0
+#APP
+// 357 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL148:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL149:
+.LBE109:
+.LBB110:
+ .loc 1 358 0
+#APP
+// 358 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 224
+ str w1, [x0, 4096]
+.LVL150:
+.LBE110:
+.LBB111:
+ .loc 1 359 0
+#APP
+// 359 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL151:
+.LBE111:
+.LBB112:
+ .loc 1 360 0
+#APP
+// 360 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE112:
+ .loc 1 361 0
+ mov w1, w25
+.LBB113:
+ .loc 1 360 0
+ str w19, [x0, 32]
+.LBE113:
+ .loc 1 361 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL152:
+ .loc 1 362 0
+ tbnz w0, #31, .L40
+.LVL153:
+.LBB114:
+ .loc 1 367 0
+#APP
+// 367 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL154:
+ mov w22, -65535
+ str w22, [x0, 36]
+.LVL155:
+.LBE114:
+.LBB115:
+ .loc 1 368 0
+#APP
+// 368 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL156:
+.LBE115:
+.LBB116:
+ .loc 1 369 0
+#APP
+// 369 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 255
+ str w1, [x0, 4096]
+.LVL157:
+.LBE116:
+.LBB117:
+ .loc 1 370 0
+#APP
+// 370 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL158:
+.LBE117:
+.LBB118:
+ .loc 1 371 0
+#APP
+// 371 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w21, 65537
+.LVL159:
+.LBE118:
+ .loc 1 372 0
+ mov w1, w25
+.LBB119:
+ .loc 1 371 0
+ str w21, [x0, 32]
+.LBE119:
+ .loc 1 372 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL160:
+ .loc 1 373 0
+ tbnz w0, #31, .L40
+.LVL161:
+.LBB120:
+ .loc 1 378 0
+#APP
+// 378 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL162:
+ str w22, [x0, 36]
+.LVL163:
+.LBE120:
+.LBB121:
+ .loc 1 379 0
+#APP
+// 379 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 1
+ str w1, [x0, 4096]
+.LVL164:
+.LBE121:
+.LBB122:
+ .loc 1 380 0
+#APP
+// 380 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w24, 191
+.LVL165:
+ str w24, [x0, 4100]
+.LVL166:
+.LBE122:
+.LBB123:
+ .loc 1 381 0
+#APP
+// 381 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE123:
+ .loc 1 382 0
+ mov w1, w25
+.LBB124:
+ .loc 1 381 0
+ str w21, [x0, 32]
+.LBE124:
+ .loc 1 382 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL167:
+ .loc 1 383 0
+ tbnz w0, #31, .L40
+ .loc 1 388 0
+ mov x0, x26
+.LVL168:
+ bl rockchip_secure_otp_check_flag.isra.0
+.LVL169:
+ .loc 1 389 0
+ tbz w0, #31, .L41
+ .loc 1 390 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC6
+.LVL170:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC6
+ b .L46
+.LVL171:
+.L41:
+.LBB125:
+ .loc 1 394 0
+#APP
+// 394 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL172:
+ str w22, [x0, 36]
+.LVL173:
+.LBE125:
+.LBB126:
+ .loc 1 395 0
+#APP
+// 395 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w19, 2
+ str w19, [x0, 4096]
+.LVL174:
+.LBE126:
+.LBB127:
+ .loc 1 396 0
+#APP
+// 396 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w24, [x0, 4100]
+.LVL175:
+.LBE127:
+.LBB128:
+ .loc 1 397 0
+#APP
+// 397 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE128:
+ .loc 1 398 0
+ mov w1, w19
+.LBB129:
+ .loc 1 397 0
+ str w21, [x0, 32]
+.LBE129:
+ .loc 1 398 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL176:
+ .loc 1 399 0
+ tbnz w0, #31, .L40
+ .loc 1 404 0
+ mov x0, x26
+.LVL177:
+ bl rockchip_secure_otp_wait_flag.isra.1
+.LVL178:
+ .loc 1 405 0
+ tbz w0, #31, .L42
+ .loc 1 406 0
+ adrp x1, .LANCHOR1
+ adrp x0, .LC7
+.LVL179:
+ add x1, x1, :lo12:.LANCHOR1
+ add x0, x0, :lo12:.LC7
+ b .L46
+.LVL180:
+.L42:
+.LBB130:
+ .loc 1 410 0
+#APP
+// 410 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL181:
+ mov w1, -65533
+ str w1, [x0, 772]
+.LVL182:
+.LBE130:
+.LBB131:
+ .loc 1 411 0
+#APP
+// 411 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL183:
+.LBE131:
+.LBB132:
+ .loc 1 412 0
+#APP
+// 412 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w22, [x0, 36]
+.LVL184:
+.LBE132:
+.LBB133:
+ .loc 1 413 0
+#APP
+// 413 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str w19, [x0, 4096]
+.LVL185:
+.LBE133:
+.LBB134:
+ .loc 1 414 0
+#APP
+// 414 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 128
+ str w1, [x0, 4100]
+.LVL186:
+.LBE134:
+.LBB135:
+ .loc 1 415 0
+#APP
+// 415 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE135:
+ .loc 1 416 0
+ mov w1, w19
+.LBB136:
+ .loc 1 415 0
+ str w21, [x0, 32]
+.LBE136:
+ .loc 1 416 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL187:
+ .loc 1 417 0
+ tbnz w0, #31, .L40
+.LVL188:
+.LBB137:
+ .loc 1 422 0
+#APP
+// 422 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL189:
+ str w22, [x0, 36]
+.LVL190:
+.LBE137:
+.LBB138:
+ .loc 1 423 0
+#APP
+// 423 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 160
+ str w1, [x0, 4096]
+.LVL191:
+.LBE138:
+.LBB139:
+ .loc 1 424 0
+#APP
+// 424 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ str wzr, [x0, 4100]
+.LVL192:
+.LBE139:
+.LBB140:
+ .loc 1 425 0
+#APP
+// 425 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE140:
+ .loc 1 426 0
+ mov w1, w19
+.LBB141:
+ .loc 1 425 0
+ str w21, [x0, 32]
+.LBE141:
+ .loc 1 426 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL193:
+ .loc 1 427 0
+ tbnz w0, #31, .L40
+.LVL194:
+.LBB142:
+ .loc 1 432 0
+#APP
+// 432 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LVL195:
+ mov w1, 250
+ str w1, [x0, 4096]
+.LVL196:
+.LBE142:
+.LBB143:
+ .loc 1 433 0
+#APP
+// 433 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+ mov w1, 9
+ str w1, [x0, 4100]
+.LVL197:
+.LBE143:
+.LBB144:
+ .loc 1 434 0
+#APP
+// 434 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x26]
+.LBE144:
+ .loc 1 435 0
+ mov w1, w19
+.LBB145:
+ .loc 1 434 0
+ str w21, [x0, 32]
+.LBE145:
+ .loc 1 435 0
+ mov x0, x26
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL198:
+ .loc 1 436 0
+ tbz w0, #31, .L39
+ b .L40
+ .cfi_endproc
+.LFE269:
+ .size rk3562_secure_otp_write_2_bytes_noecc, .-rk3562_secure_otp_write_2_bytes_noecc
+ .section .text.rockchip_secure_otp_ecc_enable,"ax",@progbits
+ .align 2
+ .type rockchip_secure_otp_ecc_enable, %function
+rockchip_secure_otp_ecc_enable:
+.LFB267:
+ .loc 1 154 0
+ .cfi_startproc
+.LVL199:
+ stp x29, x30, [sp, -32]!
+ .cfi_def_cfa_offset 32
+ .cfi_offset 29, -32
+ .cfi_offset 30, -24
+ and w1, w1, 255
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ str x19, [sp, 16]
+ .cfi_offset 19, -16
+.LBB160:
+ .loc 1 157 0
+#APP
+// 157 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, 512
+ movk w3, 0xff00, lsl 16
+ str w3, [x2, 32]
+.LVL200:
+.LBE160:
+.LBB161:
+ .loc 1 158 0
+#APP
+// 158 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, -65535
+ str w3, [x2, 36]
+.LVL201:
+.LBE161:
+.LBB162:
+ .loc 1 159 0
+#APP
+// 159 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x2, [x0]
+ mov w3, 250
+ str w3, [x2, 4096]
+.LBE162:
+ .loc 1 160 0
+ cbz w1, .L48
+.LVL202:
+.LBB163:
+ .loc 1 161 0
+#APP
+// 161 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+.LVL203:
+ str wzr, [x1, 4100]
+.LVL204:
+.L49:
+.LBE163:
+.LBB164:
+ .loc 1 165 0
+#APP
+// 165 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+ mov w2, 65537
+ str w2, [x1, 32]
+.LBE164:
+ .loc 1 167 0
+ mov w1, 2
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL205:
+ mov w19, w0
+.LVL206:
+ .loc 1 168 0
+ tbz w0, #31, .L47
+.LVL207:
+.LBB165:
+.LBB166:
+ .loc 1 169 0
+ adrp x1, .LANCHOR2
+ adrp x0, .LC8
+.LVL208:
+ add x1, x1, :lo12:.LANCHOR2
+ add x0, x0, :lo12:.LC8
+ bl printf
+.LVL209:
+.L47:
+.LBE166:
+.LBE165:
+ .loc 1 172 0
+ mov w0, w19
+ ldr x19, [sp, 16]
+.LVL210:
+ ldp x29, x30, [sp], 32
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 19
+ .cfi_def_cfa 31, 0
+ ret
+.LVL211:
+.L48:
+ .cfi_restore_state
+.LBB167:
+ .loc 1 163 0
+#APP
+// 163 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x1, [x0]
+ mov w2, 9
+ str w2, [x1, 4100]
+ b .L49
+.LBE167:
+ .cfi_endproc
+.LFE267:
+ .size rockchip_secure_otp_ecc_enable, .-rockchip_secure_otp_ecc_enable
+ .section .text.rk3562_secure_otp_read,"ax",@progbits
+ .align 2
+ .type rk3562_secure_otp_read, %function
+rk3562_secure_otp_read:
+.LFB268:
+ .loc 1 176 0
+ .cfi_startproc
+.LVL212:
+ stp x29, x30, [sp, -80]!
+ .cfi_def_cfa_offset 80
+ .cfi_offset 29, -80
+ .cfi_offset 30, -72
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -64
+ .cfi_offset 20, -56
+ .loc 1 183 0
+ asr w19, w1, 1
+ .loc 1 176 0
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -48
+ .cfi_offset 22, -40
+ mov x21, x2
+ stp x23, x24, [sp, 48]
+ mov x22, x0
+ .cfi_offset 23, -32
+ .cfi_offset 24, -24
+ mov w23, w3
+ str x25, [sp, 64]
+ .cfi_offset 25, -16
+ .loc 1 177 0
+ bl dev_get_platdata
+.LVL213:
+ mov x20, x0
+.LVL214:
+ .loc 1 178 0
+ mov x0, x22
+.LVL215:
+ bl dev_get_driver_data
+.LVL216:
+ .loc 1 184 0
+ ldr x4, [x0, 16]
+ .loc 1 178 0
+ mov x24, x0
+.LVL217:
+ .loc 1 184 0
+ ldr x1, [x20, 24]
+ mov w3, w19
+ ldp x0, x2, [x20, 8]
+.LVL218:
+ blr x4
+.LVL219:
+ .loc 1 187 0
+ sub w1, w19, #16
+ sub w0, w19, #416
+ cmp w1, 15
+ ccmp w0, 31, 0, hi
+ bhi .L53
+ .loc 1 188 0
+ mov w1, 0
+.L65:
+ .loc 1 190 0
+ mov x0, x20
+ bl rockchip_secure_otp_ecc_enable
+.LVL220:
+.LBB168:
+ .loc 1 192 0
+#APP
+// 192 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+ mov w25, 65537
+.LBE168:
+ .loc 1 181 0
+ mov w22, 0
+.LVL221:
+.LBB169:
+ .loc 1 192 0
+ str w25, [x0, 256]
+.LBE169:
+ .loc 1 193 0
+ mov x0, 50
+ bl udelay
+.LVL222:
+.L55:
+ .loc 1 194 0
+ cbz w23, .L60
+ .loc 1 196 0
+ cmp w19, 447
+ ble .L56
+ .loc 1 197 0
+ adrp x0, .LC9
+ mov w1, w19
+ add x0, x0, :lo12:.LC9
+.L66:
+ .loc 1 205 0
+ mov w22, -1
+.LVL223:
+ .loc 1 204 0
+ bl printf
+.LVL224:
+.L52:
+ .loc 1 235 0
+ mov w0, w22
+ ldr x25, [sp, 64]
+ ldp x19, x20, [sp, 16]
+.LVL225:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL226:
+ ldp x29, x30, [sp], 80
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 25
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+ ret
+.LVL227:
+.L53:
+ .cfi_restore_state
+ .loc 1 190 0
+ mov w1, 1
+ b .L65
+.LVL228:
+.L56:
+ .loc 1 201 0
+ sub w0, w19, #192
+ cmp w0, 31
+ ccmp w19, 16, 4, hi
+ beq .L58
+ .loc 1 201 0 is_stmt 0 discriminator 1
+ sub w0, w19, #416
+ cmp w0, 15
+ bls .L58
+ .loc 1 204 0 is_stmt 1
+ adrp x0, .LC10
+ lsl w1, w19, 1
+ add x0, x0, :lo12:.LC10
+ b .L66
+.L58:
+.LBB170:
+ .loc 1 208 0
+ orr w1, w19, -65536
+.LVL229:
+#APP
+// 208 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+.LBE170:
+ .loc 1 209 0
+ add w19, w19, 1
+.LVL230:
+.LBB171:
+ .loc 1 208 0
+ str w1, [x0, 260]
+.LBE171:
+.LBB172:
+ .loc 1 210 0
+#APP
+// 210 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+.LBE172:
+ .loc 1 212 0
+ mov w1, 4
+.LVL231:
+.LBB173:
+ .loc 1 210 0
+ str w25, [x0, 264]
+.LVL232:
+.LBE173:
+ .loc 1 212 0
+ mov x0, x20
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL233:
+ mov w22, w0
+.LVL234:
+ .loc 1 213 0
+ tbz w0, #31, .L59
+ .loc 1 214 0
+ adrp x1, .LANCHOR3
+ adrp x0, .LC11
+.LVL235:
+ add x1, x1, :lo12:.LANCHOR3
+ add x0, x0, :lo12:.LC11
+ bl printf
+.LVL236:
+.L60:
+.LBB174:
+ .loc 1 228 0
+#APP
+// 228 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x20]
+ mov w1, 65536
+.LBE174:
+ .loc 1 230 0
+ ldr x2, [x20, 16]
+ mov w3, w19
+ ldr x4, [x24, 24]
+.LBB175:
+ .loc 1 228 0
+ str w1, [x0, 256]
+.LBE175:
+ .loc 1 230 0
+ ldr x0, [x20, 8]
+ ldr x1, [x20, 24]
+ blr x4
+.LVL237:
+ .loc 1 234 0
+ b .L52
+.LVL238:
+.L59:
+.LBB176:
+ .loc 1 218 0
+ ldr x0, [x20]
+.LVL239:
+ ldrh w0, [x0, 292]
+ and w0, w0, 65535
+.LVL240:
+#APP
+// 218 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+.LVL241:
+#NO_APP
+.LBE176:
+ .loc 1 220 0
+ strb w0, [x21]
+ .loc 1 221 0
+ cmp w23, 1
+ beq .L60
+.LVL242:
+ .loc 1 222 0
+ lsr w0, w0, 8
+.LVL243:
+ .loc 1 223 0
+ sub w23, w23, #2
+.LVL244:
+ .loc 1 222 0
+ strb w0, [x21, 1]
+ add x21, x21, 2
+.LVL245:
+ b .L55
+ .cfi_endproc
+.LFE268:
+ .size rk3562_secure_otp_read, .-rk3562_secure_otp_read
+ .section .text.rk3562_secure_otp_write,"ax",@progbits
+ .align 2
+ .type rk3562_secure_otp_write, %function
+rk3562_secure_otp_write:
+.LFB272:
+ .loc 1 621 0
+ .cfi_startproc
+.LVL246:
+ stp x29, x30, [sp, -144]!
+ .cfi_def_cfa_offset 144
+ .cfi_offset 29, -144
+ .cfi_offset 30, -136
+ add x29, sp, 0
+ .cfi_def_cfa_register 29
+ stp x19, x20, [sp, 16]
+ .cfi_offset 19, -128
+ .cfi_offset 20, -120
+ mov w20, w1
+ stp x21, x22, [sp, 32]
+ .cfi_offset 21, -112
+ .cfi_offset 22, -104
+ mov w21, w3
+ stp x23, x24, [sp, 48]
+ .cfi_offset 23, -96
+ .cfi_offset 24, -88
+ mov x24, x0
+ stp x27, x28, [sp, 80]
+ stp x25, x26, [sp, 64]
+ .cfi_offset 27, -64
+ .cfi_offset 28, -56
+ .cfi_offset 25, -80
+ .cfi_offset 26, -72
+ .loc 1 621 0
+ str x2, [x29, 112]
+ .loc 1 622 0
+ bl dev_get_platdata
+.LVL247:
+ mov x28, x0
+.LVL248:
+ .loc 1 625 0
+ sxtw x0, w21
+.LVL249:
+ bl malloc_simple
+.LVL250:
+ .loc 1 628 0
+ cbnz x0, .L68
+.LVL251:
+.L115:
+ .loc 1 643 0
+ mov w27, -1
+.LVL252:
+.L67:
+ .loc 1 669 0
+ mov w0, w27
+ ldp x19, x20, [sp, 16]
+.LVL253:
+ ldp x21, x22, [sp, 32]
+ ldp x23, x24, [sp, 48]
+.LVL254:
+ ldp x25, x26, [sp, 64]
+ ldp x27, x28, [sp, 80]
+.LVL255:
+ ldp x29, x30, [sp], 144
+ .cfi_remember_state
+ .cfi_restore 30
+ .cfi_restore 29
+ .cfi_restore 27
+ .cfi_restore 28
+ .cfi_restore 25
+ .cfi_restore 26
+ .cfi_restore 23
+ .cfi_restore 24
+ .cfi_restore 21
+ .cfi_restore 22
+ .cfi_restore 19
+ .cfi_restore 20
+ .cfi_def_cfa 31, 0
+.LVL256:
+ ret
+.LVL257:
+.L68:
+ .cfi_restore_state
+ mov x19, x0
+ .loc 1 631 0
+ sub w0, w20, #384
+.LVL258:
+ cmp w0, 63
+ bls .L70
+.LVL259:
+.L77:
+ .loc 1 649 0
+ sub w1, w20, #832
+ sub w0, w20, #32
+ cmp w1, 63
+ ccmp w0, 31, 0, hi
+ bls .L71
+ .loc 1 659 0
+ mov w0, 2
+.LBB244:
+.LBB245:
+ .loc 1 607 0
+ adrp x19, .LANCHOR4
+.LVL260:
+ add x19, x19, :lo12:.LANCHOR4
+.LBE245:
+.LBE244:
+ .loc 1 659 0
+ mov x23, 0
+ sdiv w0, w21, w0
+ str w0, [x29, 108]
+.LVL261:
+.L78:
+ .loc 1 659 0 is_stmt 0 discriminator 1
+ ldr w0, [x29, 108]
+ cmp w0, w23
+ ble .L97
+ .loc 1 660 0 is_stmt 1
+ ldr x0, [x29, 112]
+ add w21, w20, w23, lsl 1
+.LBB324:
+.LBB320:
+ .loc 1 477 0
+ asr w25, w21, 1
+.LBE320:
+.LBE324:
+ .loc 1 660 0
+ ldrh w26, [x0, x23, lsl 1]
+.LVL262:
+.LBB325:
+.LBB321:
+ .loc 1 475 0
+ mov x0, x24
+ bl dev_get_driver_data
+.LVL263:
+ str x0, [x29, 120]
+.LVL264:
+ .loc 1 478 0
+ cmp w25, 447
+ bgt .L99
+ .loc 1 482 0
+ sub w0, w25, #192
+.LVL265:
+ cmp w0, 31
+ bls .L85
+ .loc 1 485 0
+ adrp x0, .LC4
+ and w1, w21, -2
+ add x0, x0, :lo12:.LC4
+ bl printf
+.LVL266:
+.L99:
+ .loc 1 478 0
+ mov w27, -1
+ b .L84
+.LVL267:
+.L70:
+.LBE321:
+.LBE325:
+ .loc 1 633 0
+ mov w3, w21
+ mov x2, x19
+ mov w1, w20
+ mov x0, x24
+ bl rk3562_secure_otp_read
+.LVL268:
+ .loc 1 634 0
+ cbnz w0, .L115
+ mov x0, 0
+.LVL269:
+.L75:
+ .loc 1 639 0 discriminator 1
+ cmp w21, w0
+ ble .L77
+ add x0, x0, 1
+.LVL270:
+ .loc 1 640 0
+ add x1, x19, x0
+ ldrb w1, [x1, -1]
+ cbz w1, .L75
+ .loc 1 641 0
+ adrp x0, .LC12
+ add x0, x0, :lo12:.LC12
+ bl printf
+.LVL271:
+ b .L115
+.LVL272:
+.L83:
+.LBB326:
+.LBB327:
+ .loc 1 455 0
+ adds w25, w20, w19
+.LBE327:
+.LBE326:
+ .loc 1 652 0
+ ldr x0, [x29, 112]
+.LBB332:
+.LBB328:
+ .loc 1 455 0
+ and w26, w25, 1
+ mov w3, 2
+ csneg w22, w26, w26, pl
+ add x2, x29, 142
+ sub w22, w25, w22
+.LBE328:
+.LBE332:
+ .loc 1 652 0
+ ldrb w23, [x0, x19]
+.LVL273:
+.LBB333:
+.LBB329:
+ .loc 1 455 0
+ mov w1, w22
+ mov x0, x24
+ bl rk3562_secure_otp_read
+.LVL274:
+ .loc 1 456 0
+ cbnz w0, .L79
+ ldrh w3, [x29, 142]
+ .loc 1 459 0
+ cbnz w26, .L80
+.LVL275:
+ .loc 1 461 0
+ bic w3, w23, w3
+ mov w2, w25
+.LVL276:
+.L112:
+ .loc 1 464 0
+ mov x1, x28
+ mov x0, x24
+.LVL277:
+ add x19, x19, 1
+.LVL278:
+ bl rk3562_secure_otp_write_2_bytes_noecc
+.LVL279:
+ mov w27, w0
+.LVL280:
+.LBE329:
+.LBE333:
+ .loc 1 653 0
+ cbz w0, .L82
+.L98:
+ .loc 1 654 0
+ adrp x0, .LC13
+ add x0, x0, :lo12:.LC13
+.LVL281:
+.L114:
+ .loc 1 662 0
+ bl printf
+.LVL282:
+ .loc 1 663 0
+ b .L67
+.LVL283:
+.L80:
+.LBB334:
+.LBB330:
+ .loc 1 463 0
+ lsl w23, w23, 8
+.LVL284:
+ .loc 1 464 0
+ mov w2, w22
+ bic w3, w23, w3
+ b .L112
+.LVL285:
+.L71:
+.LBE330:
+.LBE334:
+ mov x19, 0
+.LVL286:
+.L82:
+ .loc 1 651 0 discriminator 1
+ cmp w21, w19
+ bgt .L83
+.LVL287:
+.L97:
+ .loc 1 629 0
+ mov w27, 0
+ b .L67
+.LVL288:
+.L85:
+.LBB335:
+.LBB322:
+ .loc 1 489 0
+ cbz w26, .L86
+ .loc 1 492 0
+ ldr x0, [x29, 120]
+ mov w3, w25
+ ldp x2, x1, [x28, 16]
+ ldr x5, [x0, 16]
+ ldr x0, [x28, 8]
+ blr x5
+.LVL289:
+.LBB246:
+ .loc 1 495 0
+#APP
+// 495 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 65536
+ str w1, [x0, 256]
+.LVL290:
+.LBE246:
+.LBB247:
+ .loc 1 496 0
+#APP
+// 496 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 262148
+ str w1, [x0, 32]
+.LVL291:
+.LBE247:
+.LBB248:
+ .loc 1 497 0
+#APP
+// 497 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65536
+ str w1, [x0, 40]
+.LVL292:
+.LBE248:
+.LBB249:
+ .loc 1 498 0
+#APP
+// 498 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL293:
+.LBE249:
+.LBB250:
+ .loc 1 499 0
+#APP
+// 499 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65522
+ str w1, [x0, 36]
+.LVL294:
+.LBE250:
+.LBB251:
+ .loc 1 500 0
+#APP
+// 500 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w3, 240
+ str w3, [x29, 100]
+.LVL295:
+ str w3, [x0, 4096]
+.LBE251:
+.LBB252:
+ .loc 1 501 0
+#APP
+// 501 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL296:
+.LBE252:
+.LBB253:
+ .loc 1 502 0
+#APP
+// 502 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 122
+ str w2, [x29, 104]
+.LVL297:
+ str w2, [x0, 4104]
+.LBE253:
+.LBB254:
+ .loc 1 503 0
+#APP
+// 503 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 37
+ str w1, [x0, 4108]
+.LVL298:
+.LBE254:
+.LBB255:
+ .loc 1 504 0
+#APP
+// 504 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4112]
+.LVL299:
+.LBE255:
+.LBB256:
+ .loc 1 505 0
+#APP
+// 505 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4116]
+.LVL300:
+.LBE256:
+.LBB257:
+ .loc 1 506 0
+#APP
+// 506 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4120]
+.LVL301:
+.LBE257:
+.LBB258:
+ .loc 1 507 0
+#APP
+// 507 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 31
+ str w1, [x0, 4124]
+.LVL302:
+.LBE258:
+.LBB259:
+ .loc 1 508 0
+#APP
+// 508 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 11
+ str w1, [x0, 4128]
+.LVL303:
+.LBE259:
+.LBB260:
+ .loc 1 509 0
+#APP
+// 509 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 8
+ str w1, [x0, 4132]
+.LVL304:
+.LBE260:
+.LBB261:
+ .loc 1 510 0
+#APP
+// 510 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4136]
+.LVL305:
+.LBE261:
+.LBB262:
+ .loc 1 511 0
+#APP
+// 511 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4140]
+.LVL306:
+.LBE262:
+.LBB263:
+ .loc 1 512 0
+#APP
+// 512 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4144]
+.LVL307:
+.LBE263:
+.LBB264:
+ .loc 1 513 0
+#APP
+// 513 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE264:
+.LBB265:
+ .loc 1 514 0
+ ubfx x21, x21, 9, 8
+.LVL308:
+.LBE265:
+.LBB266:
+ .loc 1 513 0
+ str w25, [x0, 4148]
+.LBE266:
+.LBB267:
+ .loc 1 514 0
+#APP
+// 514 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w21, [x0, 4152]
+.LVL309:
+.LBE267:
+.LBB268:
+ .loc 1 515 0
+#APP
+// 515 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w22, 65537
+.LBE268:
+ .loc 1 516 0
+ mov w1, 2
+.LBB269:
+ .loc 1 515 0
+ str w22, [x0, 32]
+.LBE269:
+ .loc 1 516 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL310:
+ mov w27, w0
+.LVL311:
+ .loc 1 517 0
+ ldp w3, w2, [x29, 100]
+ tbz w0, #31, .L87
+ .loc 1 518 0
+ adrp x0, .LC5
+.LVL312:
+ mov x1, x19
+ add x0, x0, :lo12:.LC5
+.LVL313:
+.L113:
+ .loc 1 607 0
+ bl printf
+.LVL314:
+.L88:
+.LBB270:
+ .loc 1 612 0
+#APP
+// 612 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65533
+.LBE270:
+ .loc 1 613 0
+ ldr x2, [x28, 16]
+ mov w3, w25
+.LBB271:
+ .loc 1 612 0
+ str w1, [x0, 772]
+.LBE271:
+ .loc 1 613 0
+ ldr x0, [x29, 120]
+ ldr x1, [x28, 24]
+ ldr x6, [x0, 24]
+ ldr x0, [x28, 8]
+ blr x6
+.LVL315:
+.LBE322:
+.LBE335:
+ .loc 1 661 0
+ cbz w27, .L86
+.LVL316:
+.L84:
+ .loc 1 662 0
+ adrp x0, .LC20
+ add x0, x0, :lo12:.LC20
+ b .L114
+.LVL317:
+.L87:
+.LBB336:
+.LBB323:
+.LBB272:
+ .loc 1 522 0
+#APP
+// 522 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL318:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL319:
+.LBE272:
+.LBB273:
+ .loc 1 523 0
+#APP
+// 523 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w3, [x0, 4096]
+.LVL320:
+.LBE273:
+.LBB274:
+ .loc 1 524 0
+#APP
+// 524 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4100]
+.LVL321:
+.LBE274:
+.LBB275:
+ .loc 1 525 0
+#APP
+// 525 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w2, [x0, 4104]
+.LVL322:
+.LBE275:
+.LBB276:
+ .loc 1 526 0
+#APP
+// 526 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 21
+ str w1, [x0, 4108]
+.LVL323:
+.LBE276:
+.LBB277:
+ .loc 1 527 0
+#APP
+// 527 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 220
+ str w1, [x0, 4112]
+.LVL324:
+.LBE277:
+.LBB278:
+ .loc 1 528 0
+#APP
+// 528 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 146
+ str w1, [x0, 4116]
+.LVL325:
+.LBE278:
+.LBB279:
+ .loc 1 529 0
+#APP
+// 529 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 121
+ str w1, [x0, 4120]
+.LVL326:
+.LBE279:
+.LBB280:
+ .loc 1 530 0
+#APP
+// 530 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 129
+ str w1, [x0, 4124]
+.LVL327:
+.LBE280:
+.LBB281:
+ .loc 1 531 0
+#APP
+// 531 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 126
+ str w1, [x0, 4128]
+.LVL328:
+.LBE281:
+.LBB282:
+ .loc 1 532 0
+#APP
+// 532 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 33
+ str w1, [x0, 4132]
+.LVL329:
+.LBE282:
+.LBB283:
+ .loc 1 533 0
+#APP
+// 533 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 17
+ str w1, [x0, 4136]
+.LVL330:
+.LBE283:
+.LBB284:
+ .loc 1 534 0
+#APP
+// 534 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 157
+ str w1, [x0, 4140]
+.LVL331:
+.LBE284:
+.LBB285:
+ .loc 1 535 0
+#APP
+// 535 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w21, 2
+.LVL332:
+ str w21, [x0, 4144]
+.LVL333:
+.LBE285:
+.LBB286:
+ .loc 1 536 0
+#APP
+// 536 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4148]
+.LVL334:
+.LBE286:
+.LBB287:
+ .loc 1 537 0
+#APP
+// 537 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4152]
+.LVL335:
+.LBE287:
+.LBB288:
+ .loc 1 538 0
+#APP
+// 538 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE288:
+ .loc 1 539 0
+ mov w1, w21
+.LBB289:
+ .loc 1 538 0
+ str w22, [x0, 32]
+.LBE289:
+ .loc 1 539 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL336:
+ mov w27, w0
+.LVL337:
+ .loc 1 540 0
+ tbz w0, #31, .L89
+ .loc 1 541 0
+ adrp x0, .LC14
+.LVL338:
+ mov x1, x19
+ add x0, x0, :lo12:.LC14
+ b .L113
+.LVL339:
+.L89:
+.LBB290:
+ .loc 1 545 0
+#APP
+// 545 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL340:
+ mov w1, 512
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL341:
+.LBE290:
+.LBB291:
+ .loc 1 546 0
+#APP
+// 546 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL342:
+.LBE291:
+.LBB292:
+ .loc 1 547 0
+#APP
+// 547 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 251
+ str w1, [x0, 4096]
+.LVL343:
+.LBE292:
+.LBB293:
+ .loc 1 548 0
+#APP
+// 548 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4100]
+.LVL344:
+.LBE293:
+.LBB294:
+ .loc 1 549 0
+#APP
+// 549 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE294:
+ .loc 1 550 0
+ mov w1, w21
+.LBB295:
+ .loc 1 549 0
+ str w22, [x0, 32]
+.LBE295:
+ .loc 1 550 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL345:
+ mov w27, w0
+.LVL346:
+ .loc 1 551 0
+ tbz w0, #31, .L90
+ .loc 1 552 0
+ adrp x0, .LC15
+.LVL347:
+ mov x1, x19
+ add x0, x0, :lo12:.LC15
+ b .L113
+.LVL348:
+.L90:
+.LBB296:
+ .loc 1 556 0
+#APP
+// 556 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL349:
+ mov w1, -65534
+ str w1, [x0, 36]
+.LVL350:
+.LBE296:
+.LBB297:
+ .loc 1 557 0
+#APP
+// 557 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 192
+ str w1, [x0, 4096]
+.LBE297:
+.LBB298:
+ .loc 1 558 0
+ and w1, w26, 255
+.LVL351:
+#APP
+// 558 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE298:
+.LBB299:
+ .loc 1 559 0
+ lsr w26, w26, 8
+.LVL352:
+.LBE299:
+.LBB300:
+ .loc 1 558 0
+ str w1, [x0, 4100]
+.LBE300:
+.LBB301:
+ .loc 1 559 0
+#APP
+// 559 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str w26, [x0, 4104]
+.LVL353:
+.LBE301:
+.LBB302:
+ .loc 1 560 0
+#APP
+// 560 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE302:
+ .loc 1 561 0
+ mov w1, w21
+.LVL354:
+.LBB303:
+ .loc 1 560 0
+ str w22, [x0, 32]
+.LBE303:
+ .loc 1 561 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL355:
+ mov w27, w0
+.LVL356:
+ .loc 1 562 0
+ tbz w0, #31, .L91
+ .loc 1 563 0
+ adrp x0, .LC16
+.LVL357:
+ mov x1, x19
+ add x0, x0, :lo12:.LC16
+ b .L113
+.LVL358:
+.L91:
+.LBB304:
+ .loc 1 567 0
+#APP
+// 567 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL359:
+ mov w1, 14848
+ movk w1, 0xff00, lsl 16
+ str w1, [x0, 32]
+.LVL360:
+.LBE304:
+.LBB305:
+ .loc 1 568 0
+#APP
+// 568 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL361:
+.LBE305:
+.LBB306:
+ .loc 1 569 0
+#APP
+// 569 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 255
+ str w1, [x0, 4096]
+.LVL362:
+.LBE306:
+.LBB307:
+ .loc 1 570 0
+#APP
+// 570 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 10
+ str w1, [x0, 4100]
+.LVL363:
+.LBE307:
+.LBB308:
+ .loc 1 571 0
+#APP
+// 571 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE308:
+ .loc 1 572 0
+ mov w1, w21
+.LBB309:
+ .loc 1 571 0
+ str w22, [x0, 32]
+.LBE309:
+ .loc 1 572 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL364:
+ mov w27, w0
+.LVL365:
+ .loc 1 573 0
+ tbz w0, #31, .L92
+ .loc 1 574 0
+ adrp x0, .LC17
+.LVL366:
+ mov x1, x19
+ add x0, x0, :lo12:.LC17
+ b .L113
+.LVL367:
+.L92:
+.LBB310:
+ .loc 1 578 0
+#APP
+// 578 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL368:
+ mov w1, -65534
+ str w1, [x0, 36]
+.LVL369:
+.LBE310:
+.LBB311:
+ .loc 1 579 0
+#APP
+// 579 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 1
+ str w1, [x0, 4096]
+.LVL370:
+.LBE311:
+.LBB312:
+ .loc 1 580 0
+#APP
+// 580 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 191
+ str w1, [x0, 4100]
+.LVL371:
+.LBE312:
+.LBB313:
+ .loc 1 581 0
+#APP
+// 581 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ str wzr, [x0, 4104]
+.LVL372:
+.LBE313:
+.LBB314:
+ .loc 1 582 0
+#APP
+// 582 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LBE314:
+ .loc 1 583 0
+ mov w1, w21
+.LBB315:
+ .loc 1 582 0
+ str w22, [x0, 32]
+.LBE315:
+ .loc 1 583 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL373:
+ mov w27, w0
+.LVL374:
+ .loc 1 584 0
+ tbz w0, #31, .L93
+ .loc 1 585 0
+ adrp x0, .LC18
+.LVL375:
+ mov x1, x19
+ add x0, x0, :lo12:.LC18
+ b .L113
+.LVL376:
+.L93:
+ .loc 1 589 0
+ mov x0, x28
+.LVL377:
+ bl rockchip_secure_otp_check_flag.isra.0
+.LVL378:
+ mov w27, w0
+.LVL379:
+ .loc 1 590 0
+ tbz w0, #31, .L94
+ .loc 1 591 0
+ adrp x0, .LC6
+.LVL380:
+ mov x1, x19
+ add x0, x0, :lo12:.LC6
+ b .L113
+.LVL381:
+.L94:
+.LBB316:
+ .loc 1 595 0
+#APP
+// 595 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+.LVL382:
+ mov w1, -65535
+ str w1, [x0, 36]
+.LVL383:
+.LBE316:
+.LBB317:
+ .loc 1 596 0
+#APP
+// 596 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w1, 2
+ str w1, [x0, 4096]
+.LVL384:
+.LBE317:
+.LBB318:
+ .loc 1 597 0
+#APP
+// 597 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 191
+ str w2, [x0, 4100]
+.LVL385:
+.LBE318:
+.LBB319:
+ .loc 1 598 0
+#APP
+// 598 "drivers/misc/rk3562-secure-otp.c" 1
+ dmb sy
+// 0 "" 2
+#NO_APP
+ ldr x0, [x28]
+ mov w2, 65537
+ str w2, [x0, 32]
+.LBE319:
+ .loc 1 599 0
+ mov x0, x28
+ bl rockchip_secure_otp_wait_status.isra.2
+.LVL386:
+ mov w27, w0
+.LVL387:
+ .loc 1 600 0
+ tbz w0, #31, .L95
+ .loc 1 601 0
+ adrp x0, .LC19
+.LVL388:
+ mov x1, x19
+ add x0, x0, :lo12:.LC19
+ b .L113
+.LVL389:
+.L95:
+ .loc 1 605 0
+ mov x0, x28
+.LVL390:
+ bl rockchip_secure_otp_wait_flag.isra.1
+.LVL391:
+ mov w27, w0
+.LVL392:
+ .loc 1 606 0
+ tbz w0, #31, .L88
+ .loc 1 607 0
+ adrp x0, .LC7
+.LVL393:
+ mov x1, x19
+ add x0, x0, :lo12:.LC7
+ b .L113
+.LVL394:
+.L86:
+ add x23, x23, 1
+.LVL395:
+ b .L78
+.LVL396:
+.L79:
+.LBE323:
+.LBE336:
+.LBB337:
+.LBB331:
+ .loc 1 457 0
+ mov w27, -1
+ b .L98
+.LBE331:
+.LBE337:
+ .cfi_endproc
+.LFE272:
+ .size rk3562_secure_otp_write, .-rk3562_secure_otp_write
+ .global _u_boot_list_2_driver_2_rockchip_secure_otp
+ .section .rodata.__func__.7582,"a",@progbits
+ .align 3
+ .set .LANCHOR0,. + 0
+ .type __func__.7582, %object
+ .size __func__.7582, 32
+__func__.7582:
+ .string "rockchip_secure_otp_wait_status"
+ .section .rodata.__func__.7625,"a",@progbits
+ .align 3
+ .set .LANCHOR2,. + 0
+ .type __func__.7625, %object
+ .size __func__.7625, 31
+__func__.7625:
+ .string "rockchip_secure_otp_ecc_enable"
+ .section .rodata.__func__.7643,"a",@progbits
+ .align 3
+ .set .LANCHOR3,. + 0
+ .type __func__.7643, %object
+ .size __func__.7643, 23
+__func__.7643:
+ .string "rk3562_secure_otp_read"
+ .section .rodata.__func__.7678,"a",@progbits
+ .align 3
+ .set .LANCHOR1,. + 0
+ .type __func__.7678, %object
+ .size __func__.7678, 38
+__func__.7678:
+ .string "rk3562_secure_otp_write_2_bytes_noecc"
+ .section .rodata.__func__.7899,"a",@progbits
+ .align 3
+ .set .LANCHOR4,. + 0
+ .type __func__.7899, %object
+ .size __func__.7899, 32
+__func__.7899:
+ .string "rk3562_secure_otp_write_2_bytes"
+ .section .rodata.rk3562_data,"a",@progbits
+ .align 3
+ .type rk3562_data, %object
+ .size rk3562_data, 32
+rk3562_data:
+ .xword rk3562_secure_otp_read
+ .xword rk3562_secure_otp_write
+ .xword rk3562_spl_rockchip_otp_start
+ .xword rk3562_spl_rockchip_otp_stop
+ .section .rodata.rk3562_secure_otp_read.str1.1,"aMS",@progbits,1
+.LC9:
+ .string "do not access non secure area, half word offset = %d\n"
+.LC10:
+ .string "Please input correct addr, offset(bytes) is 0x%x\n"
+.LC11:
+ .string "%s timeout during read setup\n"
+ .section .rodata.rk3562_secure_otp_write.str1.1,"aMS",@progbits,1
+.LC12:
+ .string "The zone is written.\n"
+.LC13:
+ .string "rk3562_secure_otp_write_byte_noecc error\n"
+.LC14:
+ .string "%s timeout during write setup 2\n"
+.LC15:
+ .string "%s timeout during write setup 3\n"
+.LC16:
+ .string "%s timeout during write setup 4\n"
+.LC17:
+ .string "%s timeout during write setup 5\n"
+.LC18:
+ .string "%s timeout during write setup 6\n"
+.LC19:
+ .string "%s timeout during write setup 8\n"
+.LC20:
+ .string "rk3562_secure_otp_write_2_bytes error\n"
+ .section .rodata.rk3562_secure_otp_write_2_bytes_noecc.str1.1,"aMS",@progbits,1
+.LC4:
+ .string "Please input correct addr, offset is 0x%x\n"
+.LC5:
+ .string "%s timeout during write setup 1\n"
+.LC6:
+ .string "%s timeout during write setup 7\n"
+.LC7:
+ .string "%s timeout during write setup 9\n"
+ .section .rodata.rockchip_otp_ids,"a",@progbits
+ .align 3
+ .type rockchip_otp_ids, %object
+ .size rockchip_otp_ids, 32
+rockchip_otp_ids:
+ .xword .LC22
+ .xword rk3562_data
+ .zero 16
+ .section .rodata.rockchip_secure_otp_ecc_enable.str1.1,"aMS",@progbits,1
+.LC8:
+ .string "%s timeout during ecc_enable\n"
+ .section .rodata.rockchip_secure_otp_ofdata_to_platdata.str1.1,"aMS",@progbits,1
+.LC0:
+ .string "secure_conf"
+.LC1:
+ .string "mask_addr"
+.LC2:
+ .string "cru_rst_addr"
+ .section .rodata.rockchip_secure_otp_ops,"a",@progbits
+ .align 3
+ .type rockchip_secure_otp_ops, %object
+ .size rockchip_secure_otp_ops, 32
+rockchip_secure_otp_ops:
+ .xword secure_otp_read
+ .xword secure_otp_write
+ .xword secure_otp_ioctl
+ .zero 8
+ .section .rodata.rockchip_secure_otp_wait_status.isra.2.str1.1,"aMS",@progbits,1
+.LC3:
+ .string "%s: wait init status timeout\n"
+ .section .rodata.str1.1,"aMS",@progbits,1
+.LC21:
+ .string "rockchip_secure_otp"
+.LC22:
+ .string "rockchip,rk3562-secure-otp"
+ .section .u_boot_list_2_driver_2_rockchip_secure_otp,"aw",@progbits
+ .align 2
+ .type _u_boot_list_2_driver_2_rockchip_secure_otp, %object
+ .size _u_boot_list_2_driver_2_rockchip_secure_otp, 120
+_u_boot_list_2_driver_2_rockchip_secure_otp:
+ .8byte .LC21
+ .word 36
+ .zero 4
+ .8byte rockchip_otp_ids
+ .zero 32
+ .8byte rockchip_secure_otp_ofdata_to_platdata
+ .zero 28
+ .word 32
+ .zero 8
+ .8byte rockchip_secure_otp_ops
+ .zero 8
+ .text
+.Letext0:
+ .file 2 "include/common.h"
+ .file 3 "./arch/arm/include/asm/types.h"
+ .file 4 "include/linux/types.h"
+ .file 5 "include/errno.h"
+ .file 6 "include/linux/string.h"
+ .file 7 "include/efi.h"
+ .file 8 "include/dm/device.h"
+ .file 9 "include/ide.h"
+ .file 10 "include/linux/list.h"
+ .file 11 "include/part.h"
+ .file 12 "include/flash.h"
+ .file 13 "include/lmb.h"
+ .file 14 "include/asm-generic/u-boot.h"
+ .file 15 "./arch/arm/include/asm/u-boot-arm.h"
+ .file 16 "include/linux/libfdt_env.h"
+ .file 17 "include/linux/../../scripts/dtc/libfdt/fdt.h"
+ .file 18 "include/linux/libfdt.h"
+ .file 19 "include/image.h"
+ .file 20 "./arch/arm/include/asm/global_data.h"
+ .file 21 "include/asm-generic/global_data.h"
+ .file 22 "include/dm/of.h"
+ .file 23 "include/net.h"
+ .file 24 "include/dm/uclass-id.h"
+ .file 25 "include/dm/ofnode.h"
+ .file 26 "include/malloc.h"
+ .file 27 "include/linux/compat.h"
+ .file 28 "include/dm/uclass.h"
+ .file 29 "include/asm-generic/ioctl.h"
+ .file 30 "include/misc.h"
+ .file 31 "include/rockchip-otp.h"
+ .file 32 "include/dm/read.h"
+ .file 33 "include/stdio.h"
+ .file 34 "include/linux/delay.h"
+ .file 35 "include/log.h"
+ .section .debug_info,"",@progbits
+.Ldebug_info0:
+ .4byte 0x42d6
+ .2byte 0x4
+ .4byte .Ldebug_abbrev0
+ .byte 0x8
+ .uleb128 0x1
+ .4byte .LASF459
+ .byte 0xc
+ .4byte .LASF460
+ .4byte .LASF461
+ .4byte .Ldebug_ranges0+0x6c0
+ .8byte 0
+ .4byte .Ldebug_line0
+ .uleb128 0x2
+ .4byte .LASF4
+ .byte 0x2
+ .byte 0xd
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF0
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF1
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x7
+ .4byte .LASF2
+ .uleb128 0x4
+ .4byte .LASF21
+ .byte 0x5
+ .byte 0xc
+ .4byte 0x54
+ .uleb128 0x5
+ .byte 0x4
+ .byte 0x5
+ .string "int"
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x6
+ .4byte .LASF3
+ .uleb128 0x2
+ .4byte .LASF5
+ .byte 0x3
+ .byte 0xc
+ .4byte 0x34
+ .uleb128 0x3
+ .byte 0x2
+ .byte 0x5
+ .4byte .LASF6
+ .uleb128 0x2
+ .4byte .LASF7
+ .byte 0x3
+ .byte 0x12
+ .4byte 0x7f
+ .uleb128 0x3
+ .byte 0x4
+ .byte 0x7
+ .4byte .LASF8
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF9
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF10
+ .uleb128 0x6
+ .string "u8"
+ .byte 0x3
+ .byte 0x1f
+ .4byte 0x34
+ .uleb128 0x7
+ .4byte 0x94
+ .uleb128 0x6
+ .string "u16"
+ .byte 0x3
+ .byte 0x22
+ .4byte 0x42
+ .uleb128 0x6
+ .string "u32"
+ .byte 0x3
+ .byte 0x25
+ .4byte 0x7f
+ .uleb128 0x6
+ .string "u64"
+ .byte 0x3
+ .byte 0x28
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF11
+ .byte 0x3
+ .byte 0x31
+ .4byte 0x8d
+ .uleb128 0x2
+ .4byte .LASF12
+ .byte 0x3
+ .byte 0x32
+ .4byte 0x8d
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x7
+ .4byte .LASF13
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xee
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x8
+ .4byte .LASF14
+ .uleb128 0x7
+ .4byte 0xe7
+ .uleb128 0x3
+ .byte 0x8
+ .byte 0x5
+ .4byte .LASF15
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xe7
+ .uleb128 0x2
+ .4byte .LASF16
+ .byte 0x4
+ .byte 0x59
+ .4byte 0x42
+ .uleb128 0x2
+ .4byte .LASF17
+ .byte 0x4
+ .byte 0x5b
+ .4byte 0x3b
+ .uleb128 0x2
+ .4byte .LASF18
+ .byte 0x4
+ .byte 0x69
+ .4byte 0x62
+ .uleb128 0x2
+ .4byte .LASF19
+ .byte 0x4
+ .byte 0x6b
+ .4byte 0x74
+ .uleb128 0x2
+ .4byte .LASF20
+ .byte 0x4
+ .byte 0x97
+ .4byte 0x74
+ .uleb128 0x9
+ .byte 0x8
+ .uleb128 0x4
+ .4byte .LASF22
+ .byte 0x6
+ .byte 0xb
+ .4byte 0xfa
+ .uleb128 0x3
+ .byte 0x1
+ .byte 0x2
+ .4byte .LASF23
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x156
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF24
+ .byte 0x7
+ .2byte 0x140
+ .4byte 0x14b
+ .uleb128 0xc
+ .4byte .LASF25
+ .byte 0x7
+ .2byte 0x143
+ .4byte 0x14b
+ .uleb128 0xc
+ .4byte .LASF26
+ .byte 0x7
+ .2byte 0x143
+ .4byte 0x14b
+ .uleb128 0xd
+ .4byte .LASF45
+ .byte 0xa0
+ .byte 0x8
+ .byte 0x83
+ .4byte 0x25f
+ .uleb128 0xe
+ .4byte .LASF27
+ .byte 0x8
+ .byte 0x84
+ .4byte 0x139d
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x8
+ .byte 0x85
+ .4byte 0xe1
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF29
+ .byte 0x8
+ .byte 0x86
+ .4byte 0x137
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF30
+ .byte 0x8
+ .byte 0x87
+ .4byte 0x137
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF31
+ .byte 0x8
+ .byte 0x88
+ .4byte 0x137
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF32
+ .byte 0x8
+ .byte 0x89
+ .4byte 0x1344
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF33
+ .byte 0x8
+ .byte 0x8a
+ .4byte 0x10b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF34
+ .byte 0x8
+ .byte 0x8b
+ .4byte 0x25f
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF35
+ .byte 0x8
+ .byte 0x8c
+ .4byte 0x137
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF36
+ .byte 0x8
+ .byte 0x8d
+ .4byte 0x13ec
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF37
+ .byte 0x8
+ .byte 0x8e
+ .4byte 0x137
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF38
+ .byte 0x8
+ .byte 0x8f
+ .4byte 0x137
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF39
+ .byte 0x8
+ .byte 0x90
+ .4byte 0x292
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF40
+ .byte 0x8
+ .byte 0x91
+ .4byte 0x292
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF41
+ .byte 0x8
+ .byte 0x92
+ .4byte 0x292
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x8
+ .byte 0x93
+ .4byte 0x121
+ .byte 0x90
+ .uleb128 0xe
+ .4byte .LASF43
+ .byte 0x8
+ .byte 0x94
+ .4byte 0x54
+ .byte 0x94
+ .uleb128 0xf
+ .string "seq"
+ .byte 0x8
+ .byte 0x95
+ .4byte 0x54
+ .byte 0x98
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x17a
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x26b
+ .uleb128 0x10
+ .uleb128 0xa
+ .4byte 0x10b
+ .4byte 0x277
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF44
+ .byte 0x9
+ .byte 0x10
+ .4byte 0x26c
+ .uleb128 0xa
+ .4byte 0x34
+ .4byte 0x292
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF46
+ .byte 0x10
+ .byte 0xa
+ .byte 0x16
+ .4byte 0x2b7
+ .uleb128 0xe
+ .4byte .LASF47
+ .byte 0xa
+ .byte 0x17
+ .4byte 0x2b7
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF48
+ .byte 0xa
+ .byte 0x17
+ .4byte 0x2b7
+ .byte 0x8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x292
+ .uleb128 0xd
+ .4byte .LASF49
+ .byte 0x10
+ .byte 0xb
+ .byte 0xf
+ .4byte 0x2e2
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0xb
+ .byte 0x10
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF50
+ .byte 0xb
+ .byte 0x11
+ .4byte 0x2fb
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x2bd
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x2fb
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x2e7
+ .uleb128 0xa
+ .4byte 0x2e2
+ .4byte 0x30c
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x301
+ .uleb128 0x4
+ .4byte .LASF49
+ .byte 0xb
+ .byte 0xe1
+ .4byte 0x30c
+ .uleb128 0x14
+ .2byte 0x1220
+ .byte 0xc
+ .byte 0x13
+ .4byte 0x370
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xc
+ .byte 0x14
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF52
+ .byte 0xc
+ .byte 0x15
+ .4byte 0x100
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF53
+ .byte 0xc
+ .byte 0x16
+ .4byte 0x10b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF54
+ .byte 0xc
+ .byte 0x17
+ .4byte 0x370
+ .byte 0x18
+ .uleb128 0x15
+ .4byte .LASF55
+ .byte 0xc
+ .byte 0x18
+ .4byte 0x381
+ .2byte 0x1018
+ .uleb128 0x16
+ .string "mtd"
+ .byte 0xc
+ .byte 0x31
+ .4byte 0x397
+ .2byte 0x1218
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x10b
+ .4byte 0x381
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x29
+ .4byte 0x392
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x1ff
+ .byte 0
+ .uleb128 0x18
+ .4byte .LASF318
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x392
+ .uleb128 0x2
+ .4byte .LASF56
+ .byte 0xc
+ .byte 0x37
+ .4byte 0x31c
+ .uleb128 0xa
+ .4byte 0x39d
+ .4byte 0x3b3
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF57
+ .byte 0xc
+ .byte 0x39
+ .4byte 0x3a8
+ .uleb128 0x3
+ .byte 0x10
+ .byte 0x4
+ .4byte .LASF58
+ .uleb128 0xd
+ .4byte .LASF59
+ .byte 0x10
+ .byte 0xd
+ .byte 0x10
+ .4byte 0x3ea
+ .uleb128 0xe
+ .4byte .LASF60
+ .byte 0xd
+ .byte 0x11
+ .4byte 0xc4
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xd
+ .byte 0x12
+ .4byte 0xcf
+ .byte 0x8
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF61
+ .2byte 0x120
+ .byte 0xd
+ .byte 0x15
+ .4byte 0x41c
+ .uleb128 0xf
+ .string "cnt"
+ .byte 0xd
+ .byte 0x16
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xd
+ .byte 0x17
+ .4byte 0xcf
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF62
+ .byte 0xd
+ .byte 0x18
+ .4byte 0x41c
+ .byte 0x10
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x3c5
+ .4byte 0x42c
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x10
+ .byte 0
+ .uleb128 0x1a
+ .string "lmb"
+ .2byte 0x240
+ .byte 0xd
+ .byte 0x1b
+ .4byte 0x453
+ .uleb128 0xe
+ .4byte .LASF63
+ .byte 0xd
+ .byte 0x1c
+ .4byte 0x3ea
+ .byte 0
+ .uleb128 0x15
+ .4byte .LASF64
+ .byte 0xd
+ .byte 0x1d
+ .4byte 0x3ea
+ .2byte 0x120
+ .byte 0
+ .uleb128 0x1b
+ .string "lmb"
+ .byte 0xd
+ .byte 0x20
+ .4byte 0x42c
+ .uleb128 0x1c
+ .byte 0x10
+ .byte 0xe
+ .byte 0x5d
+ .4byte 0x47f
+ .uleb128 0xe
+ .4byte .LASF54
+ .byte 0xe
+ .byte 0x5e
+ .4byte 0xb9
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF51
+ .byte 0xe
+ .byte 0x5f
+ .4byte 0xb9
+ .byte 0x8
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF65
+ .byte 0xb0
+ .byte 0xe
+ .byte 0x1b
+ .4byte 0x57c
+ .uleb128 0xe
+ .4byte .LASF66
+ .byte 0xe
+ .byte 0x1c
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF67
+ .byte 0xe
+ .byte 0x1d
+ .4byte 0xcf
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF68
+ .byte 0xe
+ .byte 0x1e
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF69
+ .byte 0xe
+ .byte 0x1f
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF70
+ .byte 0xe
+ .byte 0x20
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF71
+ .byte 0xe
+ .byte 0x21
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF72
+ .byte 0xe
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF73
+ .byte 0xe
+ .byte 0x24
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF74
+ .byte 0xe
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF75
+ .byte 0xe
+ .byte 0x26
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF76
+ .byte 0xe
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF77
+ .byte 0xe
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF78
+ .byte 0xe
+ .byte 0x33
+ .4byte 0x282
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF79
+ .byte 0xe
+ .byte 0x34
+ .4byte 0x42
+ .byte 0x66
+ .uleb128 0xe
+ .4byte .LASF80
+ .byte 0xe
+ .byte 0x35
+ .4byte 0x3b
+ .byte 0x68
+ .uleb128 0xe
+ .4byte .LASF81
+ .byte 0xe
+ .byte 0x36
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF82
+ .byte 0xe
+ .byte 0x57
+ .4byte 0x10b
+ .byte 0x78
+ .uleb128 0xe
+ .4byte .LASF83
+ .byte 0xe
+ .byte 0x58
+ .4byte 0x10b
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF84
+ .byte 0xe
+ .byte 0x5b
+ .4byte 0x7f
+ .byte 0x88
+ .uleb128 0xe
+ .4byte .LASF85
+ .byte 0xe
+ .byte 0x60
+ .4byte 0x57c
+ .byte 0x90
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x45e
+ .4byte 0x58c
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF86
+ .byte 0xe
+ .byte 0x62
+ .4byte 0x47f
+ .uleb128 0x4
+ .4byte .LASF87
+ .byte 0xf
+ .byte 0x13
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF88
+ .byte 0xf
+ .byte 0x14
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF89
+ .byte 0xf
+ .byte 0x15
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF90
+ .byte 0xf
+ .byte 0x16
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF91
+ .byte 0xf
+ .byte 0x17
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF92
+ .byte 0xf
+ .byte 0x18
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF93
+ .byte 0xf
+ .byte 0x19
+ .4byte 0x10b
+ .uleb128 0x2
+ .4byte .LASF94
+ .byte 0x10
+ .byte 0x11
+ .4byte 0x12c
+ .uleb128 0xd
+ .4byte .LASF95
+ .byte 0x28
+ .byte 0x11
+ .byte 0x39
+ .4byte 0x674
+ .uleb128 0xe
+ .4byte .LASF96
+ .byte 0x11
+ .byte 0x3a
+ .4byte 0x5e4
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF97
+ .byte 0x11
+ .byte 0x3b
+ .4byte 0x5e4
+ .byte 0x4
+ .uleb128 0xe
+ .4byte .LASF98
+ .byte 0x11
+ .byte 0x3c
+ .4byte 0x5e4
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF99
+ .byte 0x11
+ .byte 0x3d
+ .4byte 0x5e4
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF100
+ .byte 0x11
+ .byte 0x3e
+ .4byte 0x5e4
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF101
+ .byte 0x11
+ .byte 0x3f
+ .4byte 0x5e4
+ .byte 0x14
+ .uleb128 0xe
+ .4byte .LASF102
+ .byte 0x11
+ .byte 0x40
+ .4byte 0x5e4
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF103
+ .byte 0x11
+ .byte 0x43
+ .4byte 0x5e4
+ .byte 0x1c
+ .uleb128 0xe
+ .4byte .LASF104
+ .byte 0x11
+ .byte 0x46
+ .4byte 0x5e4
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF105
+ .byte 0x11
+ .byte 0x49
+ .4byte 0x5e4
+ .byte 0x24
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF106
+ .byte 0x12
+ .2byte 0x136
+ .4byte 0x680
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x5ef
+ .uleb128 0x1d
+ .4byte .LASF107
+ .byte 0x40
+ .byte 0x13
+ .2byte 0x137
+ .4byte 0x730
+ .uleb128 0x1e
+ .4byte .LASF108
+ .byte 0x13
+ .2byte 0x138
+ .4byte 0x12c
+ .byte 0
+ .uleb128 0x1e
+ .4byte .LASF109
+ .byte 0x13
+ .2byte 0x139
+ .4byte 0x12c
+ .byte 0x4
+ .uleb128 0x1e
+ .4byte .LASF110
+ .byte 0x13
+ .2byte 0x13a
+ .4byte 0x12c
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF111
+ .byte 0x13
+ .2byte 0x13b
+ .4byte 0x12c
+ .byte 0xc
+ .uleb128 0x1e
+ .4byte .LASF112
+ .byte 0x13
+ .2byte 0x13c
+ .4byte 0x12c
+ .byte 0x10
+ .uleb128 0x1e
+ .4byte .LASF113
+ .byte 0x13
+ .2byte 0x13d
+ .4byte 0x12c
+ .byte 0x14
+ .uleb128 0x1e
+ .4byte .LASF114
+ .byte 0x13
+ .2byte 0x13e
+ .4byte 0x12c
+ .byte 0x18
+ .uleb128 0x1e
+ .4byte .LASF115
+ .byte 0x13
+ .2byte 0x13f
+ .4byte 0x116
+ .byte 0x1c
+ .uleb128 0x1e
+ .4byte .LASF116
+ .byte 0x13
+ .2byte 0x140
+ .4byte 0x116
+ .byte 0x1d
+ .uleb128 0x1e
+ .4byte .LASF117
+ .byte 0x13
+ .2byte 0x141
+ .4byte 0x116
+ .byte 0x1e
+ .uleb128 0x1e
+ .4byte .LASF118
+ .byte 0x13
+ .2byte 0x142
+ .4byte 0x116
+ .byte 0x1f
+ .uleb128 0x1e
+ .4byte .LASF119
+ .byte 0x13
+ .2byte 0x143
+ .4byte 0x730
+ .byte 0x20
+ .byte 0
+ .uleb128 0xa
+ .4byte 0x116
+ .4byte 0x740
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF120
+ .byte 0x13
+ .2byte 0x144
+ .4byte 0x686
+ .uleb128 0x1d
+ .4byte .LASF121
+ .byte 0x30
+ .byte 0x13
+ .2byte 0x146
+ .4byte 0x7ce
+ .uleb128 0x1e
+ .4byte .LASF54
+ .byte 0x13
+ .2byte 0x147
+ .4byte 0x10b
+ .byte 0
+ .uleb128 0x20
+ .string "end"
+ .byte 0x13
+ .2byte 0x147
+ .4byte 0x10b
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF122
+ .byte 0x13
+ .2byte 0x148
+ .4byte 0x10b
+ .byte 0x10
+ .uleb128 0x1e
+ .4byte .LASF123
+ .byte 0x13
+ .2byte 0x148
+ .4byte 0x10b
+ .byte 0x18
+ .uleb128 0x1e
+ .4byte .LASF124
+ .byte 0x13
+ .2byte 0x149
+ .4byte 0x10b
+ .byte 0x20
+ .uleb128 0x1e
+ .4byte .LASF125
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x28
+ .uleb128 0x1e
+ .4byte .LASF126
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x29
+ .uleb128 0x20
+ .string "os"
+ .byte 0x13
+ .2byte 0x14a
+ .4byte 0x116
+ .byte 0x2a
+ .uleb128 0x1e
+ .4byte .LASF127
+ .byte 0x13
+ .2byte 0x14b
+ .4byte 0x116
+ .byte 0x2b
+ .byte 0
+ .uleb128 0x1f
+ .4byte .LASF128
+ .byte 0x13
+ .2byte 0x14c
+ .4byte 0x74c
+ .uleb128 0x21
+ .4byte .LASF129
+ .2byte 0x380
+ .byte 0x13
+ .2byte 0x152
+ .4byte 0x977
+ .uleb128 0x1e
+ .4byte .LASF130
+ .byte 0x13
+ .2byte 0x158
+ .4byte 0x977
+ .byte 0
+ .uleb128 0x1e
+ .4byte .LASF131
+ .byte 0x13
+ .2byte 0x159
+ .4byte 0x740
+ .byte 0x8
+ .uleb128 0x1e
+ .4byte .LASF132
+ .byte 0x13
+ .2byte 0x15a
+ .4byte 0x10b
+ .byte 0x48
+ .uleb128 0x1e
+ .4byte .LASF133
+ .byte 0x13
+ .2byte 0x15d
+ .4byte 0xe1
+ .byte 0x50
+ .uleb128 0x1e
+ .4byte .LASF134
+ .byte 0x13
+ .2byte 0x15f
+ .4byte 0x137
+ .byte 0x58
+ .uleb128 0x1e
+ .4byte .LASF135
+ .byte 0x13
+ .2byte 0x160
+ .4byte 0xe1
+ .byte 0x60
+ .uleb128 0x1e
+ .4byte .LASF136
+ .byte 0x13
+ .2byte 0x161
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0x1e
+ .4byte .LASF137
+ .byte 0x13
+ .2byte 0x163
+ .4byte 0x137
+ .byte 0x70
+ .uleb128 0x1e
+ .4byte .LASF138
+ .byte 0x13
+ .2byte 0x164
+ .4byte 0xe1
+ .byte 0x78
+ .uleb128 0x1e
+ .4byte .LASF139
+ .byte 0x13
+ .2byte 0x165
+ .4byte 0x54
+ .byte 0x80
+ .uleb128 0x1e
+ .4byte .LASF140
+ .byte 0x13
+ .2byte 0x167
+ .4byte 0x137
+ .byte 0x88
+ .uleb128 0x1e
+ .4byte .LASF141
+ .byte 0x13
+ .2byte 0x168
+ .4byte 0xe1
+ .byte 0x90
+ .uleb128 0x1e
+ .4byte .LASF142
+ .byte 0x13
+ .2byte 0x169
+ .4byte 0x54
+ .byte 0x98
+ .uleb128 0x1e
+ .4byte .LASF143
+ .byte 0x13
+ .2byte 0x16b
+ .4byte 0x137
+ .byte 0xa0
+ .uleb128 0x1e
+ .4byte .LASF144
+ .byte 0x13
+ .2byte 0x16c
+ .4byte 0xe1
+ .byte 0xa8
+ .uleb128 0x1e
+ .4byte .LASF145
+ .byte 0x13
+ .2byte 0x16d
+ .4byte 0x54
+ .byte 0xb0
+ .uleb128 0x20
+ .string "os"
+ .byte 0x13
+ .2byte 0x171
+ .4byte 0x7ce
+ .byte 0xb8
+ .uleb128 0x20
+ .string "ep"
+ .byte 0x13
+ .2byte 0x172
+ .4byte 0x10b
+ .byte 0xe8
+ .uleb128 0x1e
+ .4byte .LASF146
+ .byte 0x13
+ .2byte 0x174
+ .4byte 0x10b
+ .byte 0xf0
+ .uleb128 0x1e
+ .4byte .LASF147
+ .byte 0x13
+ .2byte 0x174
+ .4byte 0x10b
+ .byte 0xf8
+ .uleb128 0x22
+ .4byte .LASF148
+ .byte 0x13
+ .2byte 0x176
+ .4byte 0xfa
+ .2byte 0x100
+ .uleb128 0x22
+ .4byte .LASF149
+ .byte 0x13
+ .2byte 0x177
+ .4byte 0x10b
+ .2byte 0x108
+ .uleb128 0x22
+ .4byte .LASF150
+ .byte 0x13
+ .2byte 0x179
+ .4byte 0x10b
+ .2byte 0x110
+ .uleb128 0x22
+ .4byte .LASF151
+ .byte 0x13
+ .2byte 0x17a
+ .4byte 0x10b
+ .2byte 0x118
+ .uleb128 0x22
+ .4byte .LASF152
+ .byte 0x13
+ .2byte 0x17b
+ .4byte 0x10b
+ .2byte 0x120
+ .uleb128 0x22
+ .4byte .LASF153
+ .byte 0x13
+ .2byte 0x17c
+ .4byte 0x10b
+ .2byte 0x128
+ .uleb128 0x23
+ .string "kbd"
+ .byte 0x13
+ .2byte 0x17d
+ .4byte 0x97d
+ .2byte 0x130
+ .uleb128 0x22
+ .4byte .LASF154
+ .byte 0x13
+ .2byte 0x180
+ .4byte 0x54
+ .2byte 0x138
+ .uleb128 0x22
+ .4byte .LASF155
+ .byte 0x13
+ .2byte 0x18d
+ .4byte 0x54
+ .2byte 0x13c
+ .uleb128 0x23
+ .string "lmb"
+ .byte 0x13
+ .2byte 0x190
+ .4byte 0x42c
+ .2byte 0x140
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x740
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x58c
+ .uleb128 0x1f
+ .4byte .LASF156
+ .byte 0x13
+ .2byte 0x196
+ .4byte 0x7da
+ .uleb128 0xc
+ .4byte .LASF157
+ .byte 0x13
+ .2byte 0x198
+ .4byte 0x983
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x9ac
+ .uleb128 0x17
+ .4byte 0xda
+ .2byte 0x3ff
+ .byte 0
+ .uleb128 0x24
+ .4byte .LASF352
+ .byte 0x4
+ .4byte 0x54
+ .byte 0x18
+ .byte 0xe
+ .4byte 0xc15
+ .uleb128 0x25
+ .4byte .LASF158
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF159
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF160
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF161
+ .byte 0x3
+ .uleb128 0x25
+ .4byte .LASF162
+ .byte 0x4
+ .uleb128 0x25
+ .4byte .LASF163
+ .byte 0x5
+ .uleb128 0x25
+ .4byte .LASF164
+ .byte 0x6
+ .uleb128 0x25
+ .4byte .LASF165
+ .byte 0x7
+ .uleb128 0x25
+ .4byte .LASF166
+ .byte 0x8
+ .uleb128 0x25
+ .4byte .LASF167
+ .byte 0x9
+ .uleb128 0x25
+ .4byte .LASF168
+ .byte 0xa
+ .uleb128 0x25
+ .4byte .LASF169
+ .byte 0xb
+ .uleb128 0x25
+ .4byte .LASF170
+ .byte 0xc
+ .uleb128 0x25
+ .4byte .LASF171
+ .byte 0xd
+ .uleb128 0x25
+ .4byte .LASF172
+ .byte 0xe
+ .uleb128 0x25
+ .4byte .LASF173
+ .byte 0xf
+ .uleb128 0x25
+ .4byte .LASF174
+ .byte 0x10
+ .uleb128 0x25
+ .4byte .LASF175
+ .byte 0x11
+ .uleb128 0x25
+ .4byte .LASF176
+ .byte 0x12
+ .uleb128 0x25
+ .4byte .LASF177
+ .byte 0x13
+ .uleb128 0x25
+ .4byte .LASF178
+ .byte 0x14
+ .uleb128 0x25
+ .4byte .LASF179
+ .byte 0x15
+ .uleb128 0x25
+ .4byte .LASF180
+ .byte 0x16
+ .uleb128 0x25
+ .4byte .LASF181
+ .byte 0x17
+ .uleb128 0x25
+ .4byte .LASF182
+ .byte 0x18
+ .uleb128 0x25
+ .4byte .LASF183
+ .byte 0x19
+ .uleb128 0x25
+ .4byte .LASF184
+ .byte 0x1a
+ .uleb128 0x25
+ .4byte .LASF185
+ .byte 0x1b
+ .uleb128 0x25
+ .4byte .LASF186
+ .byte 0x1c
+ .uleb128 0x25
+ .4byte .LASF187
+ .byte 0x1d
+ .uleb128 0x25
+ .4byte .LASF188
+ .byte 0x1e
+ .uleb128 0x25
+ .4byte .LASF189
+ .byte 0x1f
+ .uleb128 0x25
+ .4byte .LASF190
+ .byte 0x20
+ .uleb128 0x25
+ .4byte .LASF191
+ .byte 0x21
+ .uleb128 0x25
+ .4byte .LASF192
+ .byte 0x22
+ .uleb128 0x25
+ .4byte .LASF193
+ .byte 0x23
+ .uleb128 0x25
+ .4byte .LASF194
+ .byte 0x24
+ .uleb128 0x25
+ .4byte .LASF195
+ .byte 0x25
+ .uleb128 0x25
+ .4byte .LASF196
+ .byte 0x26
+ .uleb128 0x25
+ .4byte .LASF197
+ .byte 0x27
+ .uleb128 0x25
+ .4byte .LASF198
+ .byte 0x28
+ .uleb128 0x25
+ .4byte .LASF199
+ .byte 0x29
+ .uleb128 0x25
+ .4byte .LASF200
+ .byte 0x2a
+ .uleb128 0x25
+ .4byte .LASF201
+ .byte 0x2b
+ .uleb128 0x25
+ .4byte .LASF202
+ .byte 0x2c
+ .uleb128 0x25
+ .4byte .LASF203
+ .byte 0x2d
+ .uleb128 0x25
+ .4byte .LASF204
+ .byte 0x2e
+ .uleb128 0x25
+ .4byte .LASF205
+ .byte 0x2f
+ .uleb128 0x25
+ .4byte .LASF206
+ .byte 0x30
+ .uleb128 0x25
+ .4byte .LASF207
+ .byte 0x31
+ .uleb128 0x25
+ .4byte .LASF208
+ .byte 0x32
+ .uleb128 0x25
+ .4byte .LASF209
+ .byte 0x33
+ .uleb128 0x25
+ .4byte .LASF210
+ .byte 0x34
+ .uleb128 0x25
+ .4byte .LASF211
+ .byte 0x35
+ .uleb128 0x25
+ .4byte .LASF212
+ .byte 0x36
+ .uleb128 0x25
+ .4byte .LASF213
+ .byte 0x37
+ .uleb128 0x25
+ .4byte .LASF214
+ .byte 0x38
+ .uleb128 0x25
+ .4byte .LASF215
+ .byte 0x39
+ .uleb128 0x25
+ .4byte .LASF216
+ .byte 0x3a
+ .uleb128 0x25
+ .4byte .LASF217
+ .byte 0x3b
+ .uleb128 0x25
+ .4byte .LASF218
+ .byte 0x3c
+ .uleb128 0x25
+ .4byte .LASF219
+ .byte 0x3d
+ .uleb128 0x25
+ .4byte .LASF220
+ .byte 0x3e
+ .uleb128 0x25
+ .4byte .LASF221
+ .byte 0x3f
+ .uleb128 0x25
+ .4byte .LASF222
+ .byte 0x40
+ .uleb128 0x25
+ .4byte .LASF223
+ .byte 0x41
+ .uleb128 0x25
+ .4byte .LASF224
+ .byte 0x42
+ .uleb128 0x25
+ .4byte .LASF225
+ .byte 0x43
+ .uleb128 0x25
+ .4byte .LASF226
+ .byte 0x44
+ .uleb128 0x25
+ .4byte .LASF227
+ .byte 0x45
+ .uleb128 0x25
+ .4byte .LASF228
+ .byte 0x46
+ .uleb128 0x25
+ .4byte .LASF229
+ .byte 0x47
+ .uleb128 0x25
+ .4byte .LASF230
+ .byte 0x48
+ .uleb128 0x25
+ .4byte .LASF231
+ .byte 0x49
+ .uleb128 0x25
+ .4byte .LASF232
+ .byte 0x4a
+ .uleb128 0x25
+ .4byte .LASF233
+ .byte 0x4b
+ .uleb128 0x25
+ .4byte .LASF234
+ .byte 0x4c
+ .uleb128 0x25
+ .4byte .LASF235
+ .byte 0x4d
+ .uleb128 0x25
+ .4byte .LASF236
+ .byte 0x4e
+ .uleb128 0x25
+ .4byte .LASF237
+ .byte 0x4f
+ .uleb128 0x25
+ .4byte .LASF238
+ .byte 0x50
+ .uleb128 0x25
+ .4byte .LASF239
+ .byte 0x51
+ .uleb128 0x25
+ .4byte .LASF240
+ .byte 0x52
+ .uleb128 0x25
+ .4byte .LASF241
+ .byte 0x53
+ .uleb128 0x25
+ .4byte .LASF242
+ .byte 0x54
+ .uleb128 0x25
+ .4byte .LASF243
+ .byte 0x55
+ .uleb128 0x25
+ .4byte .LASF244
+ .byte 0x56
+ .uleb128 0x25
+ .4byte .LASF245
+ .byte 0x57
+ .uleb128 0x25
+ .4byte .LASF246
+ .byte 0x58
+ .uleb128 0x25
+ .4byte .LASF247
+ .byte 0x59
+ .uleb128 0x25
+ .4byte .LASF248
+ .byte 0x5a
+ .uleb128 0x25
+ .4byte .LASF249
+ .byte 0x5b
+ .uleb128 0x25
+ .4byte .LASF250
+ .byte 0x5c
+ .uleb128 0x25
+ .4byte .LASF251
+ .byte 0x5d
+ .uleb128 0x25
+ .4byte .LASF252
+ .byte 0x5e
+ .uleb128 0x25
+ .4byte .LASF253
+ .byte 0x5f
+ .uleb128 0x25
+ .4byte .LASF254
+ .byte 0x60
+ .uleb128 0x25
+ .4byte .LASF255
+ .byte 0x61
+ .uleb128 0x25
+ .4byte .LASF256
+ .byte 0x62
+ .uleb128 0x26
+ .4byte .LASF257
+ .sleb128 -1
+ .byte 0
+ .uleb128 0x27
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x23
+ .byte 0xf6
+ .4byte 0xc28
+ .uleb128 0x25
+ .4byte .LASF258
+ .byte 0x5
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF259
+ .byte 0x40
+ .byte 0x14
+ .byte 0xc
+ .4byte 0xca1
+ .uleb128 0xe
+ .4byte .LASF260
+ .byte 0x14
+ .byte 0x22
+ .4byte 0x3b
+ .byte 0
+ .uleb128 0xf
+ .string "tbu"
+ .byte 0x14
+ .byte 0x23
+ .4byte 0x7f
+ .byte 0x8
+ .uleb128 0xf
+ .string "tbl"
+ .byte 0x14
+ .byte 0x24
+ .4byte 0x7f
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF261
+ .byte 0x14
+ .byte 0x25
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF262
+ .byte 0x14
+ .byte 0x26
+ .4byte 0x8d
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF263
+ .byte 0x14
+ .byte 0x29
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF264
+ .byte 0x14
+ .byte 0x2a
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF265
+ .byte 0x14
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF266
+ .byte 0x14
+ .byte 0x2d
+ .4byte 0x3b
+ .byte 0x38
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF267
+ .byte 0x18
+ .byte 0x15
+ .byte 0x22
+ .4byte 0xce9
+ .uleb128 0xe
+ .4byte .LASF268
+ .byte 0x15
+ .byte 0x23
+ .4byte 0xae
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF269
+ .byte 0x15
+ .byte 0x24
+ .4byte 0xae
+ .byte 0x4
+ .uleb128 0xf
+ .string "id"
+ .byte 0x15
+ .byte 0x25
+ .4byte 0xae
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF270
+ .byte 0x15
+ .byte 0x26
+ .4byte 0xae
+ .byte 0xc
+ .uleb128 0xe
+ .4byte .LASF271
+ .byte 0x15
+ .byte 0x27
+ .4byte 0x10b
+ .byte 0x10
+ .byte 0
+ .uleb128 0x19
+ .4byte .LASF272
+ .2byte 0x1c0
+ .byte 0x15
+ .byte 0x2a
+ .4byte 0xf12
+ .uleb128 0xf
+ .string "bd"
+ .byte 0x15
+ .byte 0x2b
+ .4byte 0x97d
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x15
+ .byte 0x2c
+ .4byte 0x3b
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF270
+ .byte 0x15
+ .byte 0x2d
+ .4byte 0x7f
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF273
+ .byte 0x15
+ .byte 0x2e
+ .4byte 0x3b
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF274
+ .byte 0x15
+ .byte 0x2f
+ .4byte 0x3b
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF275
+ .byte 0x15
+ .byte 0x31
+ .4byte 0x3b
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF276
+ .byte 0x15
+ .byte 0x32
+ .4byte 0x3b
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF277
+ .byte 0x15
+ .byte 0x3e
+ .4byte 0x3b
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF278
+ .byte 0x15
+ .byte 0x42
+ .4byte 0x3b
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF279
+ .byte 0x15
+ .byte 0x43
+ .4byte 0x3b
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF280
+ .byte 0x15
+ .byte 0x45
+ .4byte 0x3b
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF281
+ .byte 0x15
+ .byte 0x46
+ .4byte 0x3b
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF282
+ .byte 0x15
+ .byte 0x47
+ .4byte 0x3b
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF283
+ .byte 0x15
+ .byte 0x48
+ .4byte 0xcf
+ .byte 0x68
+ .uleb128 0xe
+ .4byte .LASF284
+ .byte 0x15
+ .byte 0x49
+ .4byte 0x3b
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF285
+ .byte 0x15
+ .byte 0x4a
+ .4byte 0x3b
+ .byte 0x78
+ .uleb128 0xe
+ .4byte .LASF286
+ .byte 0x15
+ .byte 0x4b
+ .4byte 0x3b
+ .byte 0x80
+ .uleb128 0xe
+ .4byte .LASF287
+ .byte 0x15
+ .byte 0x4c
+ .4byte 0x3b
+ .byte 0x88
+ .uleb128 0xe
+ .4byte .LASF288
+ .byte 0x15
+ .byte 0x4d
+ .4byte 0xf12
+ .byte 0x90
+ .uleb128 0xe
+ .4byte .LASF289
+ .byte 0x15
+ .byte 0x50
+ .4byte 0x25f
+ .byte 0x98
+ .uleb128 0xe
+ .4byte .LASF290
+ .byte 0x15
+ .byte 0x51
+ .4byte 0x25f
+ .byte 0xa0
+ .uleb128 0xe
+ .4byte .LASF291
+ .byte 0x15
+ .byte 0x52
+ .4byte 0x292
+ .byte 0xa8
+ .uleb128 0xe
+ .4byte .LASF292
+ .byte 0x15
+ .byte 0x57
+ .4byte 0x265
+ .byte 0xb8
+ .uleb128 0xe
+ .4byte .LASF293
+ .byte 0x15
+ .byte 0x58
+ .4byte 0x137
+ .byte 0xc0
+ .uleb128 0xe
+ .4byte .LASF294
+ .byte 0x15
+ .byte 0x59
+ .4byte 0x3b
+ .byte 0xc8
+ .uleb128 0xe
+ .4byte .LASF295
+ .byte 0x15
+ .byte 0x5b
+ .4byte 0xf8a
+ .byte 0xd0
+ .uleb128 0xe
+ .4byte .LASF296
+ .byte 0x15
+ .byte 0x5c
+ .4byte 0xf8a
+ .byte 0xd8
+ .uleb128 0xe
+ .4byte .LASF297
+ .byte 0x15
+ .byte 0x5e
+ .4byte 0x265
+ .byte 0xe0
+ .uleb128 0xe
+ .4byte .LASF298
+ .byte 0x15
+ .byte 0x5f
+ .4byte 0x265
+ .byte 0xe8
+ .uleb128 0xf
+ .string "jt"
+ .byte 0x15
+ .byte 0x60
+ .4byte 0xf95
+ .byte 0xf0
+ .uleb128 0xe
+ .4byte .LASF299
+ .byte 0x15
+ .byte 0x61
+ .4byte 0xf9b
+ .byte 0xf8
+ .uleb128 0x15
+ .4byte .LASF300
+ .byte 0x15
+ .byte 0x6b
+ .4byte 0x7f
+ .2byte 0x118
+ .uleb128 0x15
+ .4byte .LASF301
+ .byte 0x15
+ .byte 0x6c
+ .4byte 0x7f
+ .2byte 0x11c
+ .uleb128 0x15
+ .4byte .LASF302
+ .byte 0x15
+ .byte 0x6e
+ .4byte 0x3b
+ .2byte 0x120
+ .uleb128 0x15
+ .4byte .LASF303
+ .byte 0x15
+ .byte 0x6f
+ .4byte 0x3b
+ .2byte 0x128
+ .uleb128 0x15
+ .4byte .LASF304
+ .byte 0x15
+ .byte 0x70
+ .4byte 0x3b
+ .2byte 0x130
+ .uleb128 0x15
+ .4byte .LASF305
+ .byte 0x15
+ .byte 0x79
+ .4byte 0x25f
+ .2byte 0x138
+ .uleb128 0x15
+ .4byte .LASF127
+ .byte 0x15
+ .byte 0x7a
+ .4byte 0xc28
+ .2byte 0x140
+ .uleb128 0x15
+ .4byte .LASF306
+ .byte 0x15
+ .byte 0x80
+ .4byte 0x10b
+ .2byte 0x180
+ .uleb128 0x15
+ .4byte .LASF307
+ .byte 0x15
+ .byte 0x81
+ .4byte 0x10b
+ .2byte 0x188
+ .uleb128 0x15
+ .4byte .LASF308
+ .byte 0x15
+ .byte 0x87
+ .4byte 0xc4
+ .2byte 0x190
+ .uleb128 0x15
+ .4byte .LASF309
+ .byte 0x15
+ .byte 0x8c
+ .4byte 0xca1
+ .2byte 0x198
+ .uleb128 0x15
+ .4byte .LASF310
+ .byte 0x15
+ .byte 0x8d
+ .4byte 0x10b
+ .2byte 0x1b0
+ .uleb128 0x15
+ .4byte .LASF311
+ .byte 0x15
+ .byte 0x8e
+ .4byte 0x54
+ .2byte 0x1b8
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xce9
+ .uleb128 0xd
+ .4byte .LASF312
+ .byte 0x40
+ .byte 0x16
+ .byte 0x2c
+ .4byte 0xf85
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x16
+ .byte 0x2d
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF126
+ .byte 0x16
+ .byte 0x2e
+ .4byte 0xe1
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF313
+ .byte 0x16
+ .byte 0x2f
+ .4byte 0x12be
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF314
+ .byte 0x16
+ .byte 0x30
+ .4byte 0xe1
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF315
+ .byte 0x16
+ .byte 0x32
+ .4byte 0x1306
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF34
+ .byte 0x16
+ .byte 0x33
+ .4byte 0xf8a
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF316
+ .byte 0x16
+ .byte 0x34
+ .4byte 0xf8a
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF317
+ .byte 0x16
+ .byte 0x35
+ .4byte 0xf8a
+ .byte 0x38
+ .byte 0
+ .uleb128 0x7
+ .4byte 0xf18
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf18
+ .uleb128 0x18
+ .4byte .LASF319
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf90
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0xfab
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1f
+ .byte 0
+ .uleb128 0x2
+ .4byte .LASF320
+ .byte 0x15
+ .byte 0x9b
+ .4byte 0xce9
+ .uleb128 0x28
+ .4byte 0xfab
+ .uleb128 0x4
+ .4byte .LASF321
+ .byte 0x2
+ .byte 0xad
+ .4byte 0x10b
+ .uleb128 0xa
+ .4byte 0x94
+ .4byte 0xfd1
+ .uleb128 0xb
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF322
+ .byte 0x2
+ .byte 0xaf
+ .4byte 0xfc6
+ .uleb128 0x4
+ .4byte .LASF323
+ .byte 0x2
+ .byte 0xb0
+ .4byte 0xfc6
+ .uleb128 0x4
+ .4byte .LASF324
+ .byte 0x2
+ .byte 0xfe
+ .4byte 0x10b
+ .uleb128 0x4
+ .4byte .LASF325
+ .byte 0x2
+ .byte 0xff
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF326
+ .byte 0x2
+ .2byte 0x100
+ .4byte 0x10b
+ .uleb128 0xd
+ .4byte .LASF327
+ .byte 0x4
+ .byte 0x17
+ .byte 0x2e
+ .4byte 0x1022
+ .uleb128 0xe
+ .4byte .LASF328
+ .byte 0x17
+ .byte 0x2f
+ .4byte 0x12c
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x29
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x1037
+ .uleb128 0x13
+ .4byte 0x25f
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1028
+ .uleb128 0xa
+ .4byte 0x94
+ .4byte 0x104d
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF329
+ .byte 0x17
+ .2byte 0x1fd
+ .4byte 0x1009
+ .uleb128 0xc
+ .4byte .LASF330
+ .byte 0x17
+ .2byte 0x1fe
+ .4byte 0x1009
+ .uleb128 0xc
+ .4byte .LASF331
+ .byte 0x17
+ .2byte 0x200
+ .4byte 0x1009
+ .uleb128 0xc
+ .4byte .LASF332
+ .byte 0x17
+ .2byte 0x205
+ .4byte 0xf9b
+ .uleb128 0xc
+ .4byte .LASF333
+ .byte 0x17
+ .2byte 0x206
+ .4byte 0xf9b
+ .uleb128 0xa
+ .4byte 0xe7
+ .4byte 0x1099
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x3f
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF334
+ .byte 0x17
+ .2byte 0x207
+ .4byte 0x1089
+ .uleb128 0xc
+ .4byte .LASF335
+ .byte 0x17
+ .2byte 0x209
+ .4byte 0x103d
+ .uleb128 0xc
+ .4byte .LASF336
+ .byte 0x17
+ .2byte 0x20a
+ .4byte 0x103d
+ .uleb128 0xc
+ .4byte .LASF337
+ .byte 0x17
+ .2byte 0x20b
+ .4byte 0x1009
+ .uleb128 0xc
+ .4byte .LASF338
+ .byte 0x17
+ .2byte 0x20c
+ .4byte 0x1009
+ .uleb128 0xc
+ .4byte .LASF339
+ .byte 0x17
+ .2byte 0x20d
+ .4byte 0x1022
+ .uleb128 0xa
+ .4byte 0x1022
+ .4byte 0x10f1
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x3
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF340
+ .byte 0x17
+ .2byte 0x20e
+ .4byte 0x10e1
+ .uleb128 0xc
+ .4byte .LASF341
+ .byte 0x17
+ .2byte 0x20f
+ .4byte 0x1022
+ .uleb128 0xc
+ .4byte .LASF342
+ .byte 0x17
+ .2byte 0x210
+ .4byte 0x54
+ .uleb128 0xa
+ .4byte 0x9e
+ .4byte 0x1125
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x5
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x1115
+ .uleb128 0xc
+ .4byte .LASF343
+ .byte 0x17
+ .2byte 0x211
+ .4byte 0x1125
+ .uleb128 0xc
+ .4byte .LASF344
+ .byte 0x17
+ .2byte 0x212
+ .4byte 0x1125
+ .uleb128 0xc
+ .4byte .LASF345
+ .byte 0x17
+ .2byte 0x216
+ .4byte 0x100
+ .uleb128 0xc
+ .4byte .LASF346
+ .byte 0x17
+ .2byte 0x217
+ .4byte 0x100
+ .uleb128 0xc
+ .4byte .LASF347
+ .byte 0x17
+ .2byte 0x219
+ .4byte 0x54
+ .uleb128 0xc
+ .4byte .LASF348
+ .byte 0x17
+ .2byte 0x220
+ .4byte 0x99b
+ .uleb128 0xc
+ .4byte .LASF349
+ .byte 0x17
+ .2byte 0x222
+ .4byte 0xae
+ .uleb128 0xc
+ .4byte .LASF350
+ .byte 0x17
+ .2byte 0x224
+ .4byte 0xae
+ .uleb128 0xc
+ .4byte .LASF351
+ .byte 0x17
+ .2byte 0x230
+ .4byte 0x1009
+ .uleb128 0x29
+ .4byte .LASF353
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x17
+ .2byte 0x286
+ .4byte 0x11c0
+ .uleb128 0x25
+ .4byte .LASF354
+ .byte 0
+ .uleb128 0x25
+ .4byte .LASF355
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF356
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF357
+ .byte 0x3
+ .byte 0
+ .uleb128 0xc
+ .4byte .LASF358
+ .byte 0x17
+ .2byte 0x28c
+ .4byte 0x1196
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x94
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xa3
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xae
+ .uleb128 0xd
+ .4byte .LASF27
+ .byte 0x78
+ .byte 0x8
+ .byte 0xf1
+ .4byte 0x12b9
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x8
+ .byte 0xf2
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xf
+ .string "id"
+ .byte 0x8
+ .byte 0xf3
+ .4byte 0x9ac
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF359
+ .byte 0x8
+ .byte 0xf4
+ .4byte 0x141c
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF360
+ .byte 0x8
+ .byte 0xf5
+ .4byte 0x1037
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF361
+ .byte 0x8
+ .byte 0xf6
+ .4byte 0x1037
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF362
+ .byte 0x8
+ .byte 0xf7
+ .4byte 0x1037
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF363
+ .byte 0x8
+ .byte 0xf8
+ .4byte 0x1037
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF364
+ .byte 0x8
+ .byte 0xf9
+ .4byte 0x1037
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF365
+ .byte 0x8
+ .byte 0xfa
+ .4byte 0x1037
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF366
+ .byte 0x8
+ .byte 0xfb
+ .4byte 0x1037
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF367
+ .byte 0x8
+ .byte 0xfc
+ .4byte 0x1037
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF368
+ .byte 0x8
+ .byte 0xfd
+ .4byte 0x54
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF369
+ .byte 0x8
+ .byte 0xfe
+ .4byte 0x54
+ .byte 0x5c
+ .uleb128 0xe
+ .4byte .LASF370
+ .byte 0x8
+ .byte 0xff
+ .4byte 0x54
+ .byte 0x60
+ .uleb128 0x1e
+ .4byte .LASF371
+ .byte 0x8
+ .2byte 0x100
+ .4byte 0x54
+ .byte 0x64
+ .uleb128 0x20
+ .string "ops"
+ .byte 0x8
+ .2byte 0x101
+ .4byte 0x265
+ .byte 0x68
+ .uleb128 0x1e
+ .4byte .LASF42
+ .byte 0x8
+ .2byte 0x102
+ .4byte 0x121
+ .byte 0x70
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x11de
+ .uleb128 0x2
+ .4byte .LASF313
+ .byte 0x16
+ .byte 0xf
+ .4byte 0xae
+ .uleb128 0xd
+ .4byte .LASF372
+ .byte 0x20
+ .byte 0x16
+ .byte 0x19
+ .4byte 0x1306
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x16
+ .byte 0x1a
+ .4byte 0xfa
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF373
+ .byte 0x16
+ .byte 0x1b
+ .4byte 0x54
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF374
+ .byte 0x16
+ .byte 0x1c
+ .4byte 0x137
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF47
+ .byte 0x16
+ .byte 0x1d
+ .4byte 0x1306
+ .byte 0x18
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12c9
+ .uleb128 0x2a
+ .string "gd"
+ .byte 0x16
+ .byte 0x57
+ .4byte 0x1316
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xfb6
+ .uleb128 0x2b
+ .4byte .LASF462
+ .byte 0x8
+ .byte 0x19
+ .byte 0x33
+ .4byte 0x133e
+ .uleb128 0x2c
+ .string "np"
+ .byte 0x19
+ .byte 0x34
+ .4byte 0x133e
+ .uleb128 0x2d
+ .4byte .LASF375
+ .byte 0x19
+ .byte 0x35
+ .4byte 0xf3
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0xf85
+ .uleb128 0x2
+ .4byte .LASF376
+ .byte 0x19
+ .byte 0x36
+ .4byte 0x131c
+ .uleb128 0xc
+ .4byte .LASF377
+ .byte 0x1a
+ .2byte 0x3ba
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF378
+ .byte 0x1a
+ .2byte 0x3bb
+ .4byte 0x10b
+ .uleb128 0xc
+ .4byte .LASF379
+ .byte 0x1a
+ .2byte 0x3bc
+ .4byte 0x10b
+ .uleb128 0xd
+ .4byte .LASF380
+ .byte 0x4
+ .byte 0x1b
+ .byte 0xd
+ .4byte 0x138c
+ .uleb128 0xf
+ .string "pid"
+ .byte 0x1b
+ .byte 0xe
+ .4byte 0x54
+ .byte 0
+ .byte 0
+ .uleb128 0x4
+ .4byte .LASF381
+ .byte 0x1b
+ .byte 0x11
+ .4byte 0x1397
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1373
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x12b9
+ .uleb128 0xd
+ .4byte .LASF36
+ .byte 0x38
+ .byte 0x1c
+ .byte 0x23
+ .4byte 0x13ec
+ .uleb128 0xe
+ .4byte .LASF35
+ .byte 0x1c
+ .byte 0x24
+ .4byte 0x137
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF382
+ .byte 0x1c
+ .byte 0x25
+ .4byte 0x1506
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF383
+ .byte 0x1c
+ .byte 0x26
+ .4byte 0x292
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF41
+ .byte 0x1c
+ .byte 0x27
+ .4byte 0x292
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF384
+ .byte 0x1c
+ .byte 0x29
+ .4byte 0x2b7
+ .byte 0x30
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x13a3
+ .uleb128 0xd
+ .4byte .LASF385
+ .byte 0x10
+ .byte 0x8
+ .byte 0xb8
+ .4byte 0x1417
+ .uleb128 0xe
+ .4byte .LASF386
+ .byte 0x8
+ .byte 0xb9
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF387
+ .byte 0x8
+ .byte 0xba
+ .4byte 0x10b
+ .byte 0x8
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x13f2
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1417
+ .uleb128 0xd
+ .4byte .LASF388
+ .byte 0x80
+ .byte 0x1c
+ .byte 0x57
+ .4byte 0x1506
+ .uleb128 0xe
+ .4byte .LASF28
+ .byte 0x1c
+ .byte 0x58
+ .4byte 0xe1
+ .byte 0
+ .uleb128 0xf
+ .string "id"
+ .byte 0x1c
+ .byte 0x59
+ .4byte 0x9ac
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF389
+ .byte 0x1c
+ .byte 0x5a
+ .4byte 0x1037
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF390
+ .byte 0x1c
+ .byte 0x5b
+ .4byte 0x1037
+ .byte 0x18
+ .uleb128 0xe
+ .4byte .LASF391
+ .byte 0x1c
+ .byte 0x5c
+ .4byte 0x1037
+ .byte 0x20
+ .uleb128 0xe
+ .4byte .LASF392
+ .byte 0x1c
+ .byte 0x5d
+ .4byte 0x1037
+ .byte 0x28
+ .uleb128 0xe
+ .4byte .LASF393
+ .byte 0x1c
+ .byte 0x5e
+ .4byte 0x1037
+ .byte 0x30
+ .uleb128 0xe
+ .4byte .LASF365
+ .byte 0x1c
+ .byte 0x5f
+ .4byte 0x1037
+ .byte 0x38
+ .uleb128 0xe
+ .4byte .LASF366
+ .byte 0x1c
+ .byte 0x60
+ .4byte 0x1037
+ .byte 0x40
+ .uleb128 0xe
+ .4byte .LASF394
+ .byte 0x1c
+ .byte 0x61
+ .4byte 0x151b
+ .byte 0x48
+ .uleb128 0xe
+ .4byte .LASF395
+ .byte 0x1c
+ .byte 0x62
+ .4byte 0x151b
+ .byte 0x50
+ .uleb128 0xe
+ .4byte .LASF368
+ .byte 0x1c
+ .byte 0x63
+ .4byte 0x54
+ .byte 0x58
+ .uleb128 0xe
+ .4byte .LASF396
+ .byte 0x1c
+ .byte 0x64
+ .4byte 0x54
+ .byte 0x5c
+ .uleb128 0xe
+ .4byte .LASF397
+ .byte 0x1c
+ .byte 0x65
+ .4byte 0x54
+ .byte 0x60
+ .uleb128 0xe
+ .4byte .LASF370
+ .byte 0x1c
+ .byte 0x66
+ .4byte 0x54
+ .byte 0x64
+ .uleb128 0xe
+ .4byte .LASF371
+ .byte 0x1c
+ .byte 0x67
+ .4byte 0x54
+ .byte 0x68
+ .uleb128 0xf
+ .string "ops"
+ .byte 0x1c
+ .byte 0x68
+ .4byte 0x265
+ .byte 0x70
+ .uleb128 0xe
+ .4byte .LASF42
+ .byte 0x1c
+ .byte 0x69
+ .4byte 0x121
+ .byte 0x78
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1422
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x151b
+ .uleb128 0x13
+ .4byte 0x13ec
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x150c
+ .uleb128 0x4
+ .4byte .LASF398
+ .byte 0x1d
+ .byte 0x49
+ .4byte 0x7f
+ .uleb128 0x24
+ .4byte .LASF399
+ .byte 0x4
+ .4byte 0x7f
+ .byte 0x1e
+ .byte 0x15
+ .4byte 0x155b
+ .uleb128 0x25
+ .4byte .LASF400
+ .byte 0x1
+ .uleb128 0x25
+ .4byte .LASF401
+ .byte 0x2
+ .uleb128 0x25
+ .4byte .LASF402
+ .byte 0x4
+ .uleb128 0x25
+ .4byte .LASF403
+ .byte 0x8
+ .uleb128 0x25
+ .4byte .LASF404
+ .byte 0x10
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF405
+ .byte 0x20
+ .byte 0x1e
+ .byte 0x61
+ .4byte 0x1598
+ .uleb128 0xe
+ .4byte .LASF406
+ .byte 0x1e
+ .byte 0x6b
+ .4byte 0x15bb
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF407
+ .byte 0x1e
+ .byte 0x75
+ .4byte 0x15df
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF408
+ .byte 0x1e
+ .byte 0x7f
+ .4byte 0x15fe
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF409
+ .byte 0x1e
+ .byte 0x8c
+ .4byte 0x162c
+ .byte 0x18
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x155b
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15bb
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x159d
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15df
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x265
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x15c1
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x15fe
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x3b
+ .uleb128 0x13
+ .4byte 0x137
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x15e5
+ .uleb128 0x12
+ .4byte 0x54
+ .4byte 0x162c
+ .uleb128 0x13
+ .4byte 0x25f
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .uleb128 0x13
+ .4byte 0x137
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1604
+ .uleb128 0xd
+ .4byte .LASF410
+ .byte 0x20
+ .byte 0x1f
+ .byte 0x5e
+ .4byte 0x166f
+ .uleb128 0xe
+ .4byte .LASF60
+ .byte 0x1f
+ .byte 0x5f
+ .4byte 0x137
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF411
+ .byte 0x1f
+ .byte 0x60
+ .4byte 0x3b
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF412
+ .byte 0x1f
+ .byte 0x61
+ .4byte 0x3b
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF413
+ .byte 0x1f
+ .byte 0x62
+ .4byte 0x3b
+ .byte 0x18
+ .byte 0
+ .uleb128 0xd
+ .4byte .LASF414
+ .byte 0x20
+ .byte 0x1
+ .byte 0xf
+ .4byte 0x16ac
+ .uleb128 0xe
+ .4byte .LASF406
+ .byte 0x1
+ .byte 0x10
+ .4byte 0x15bb
+ .byte 0
+ .uleb128 0xe
+ .4byte .LASF407
+ .byte 0x1
+ .byte 0x11
+ .4byte 0x15df
+ .byte 0x8
+ .uleb128 0xe
+ .4byte .LASF415
+ .byte 0x1
+ .byte 0x12
+ .4byte 0x16cb
+ .byte 0x10
+ .uleb128 0xe
+ .4byte .LASF416
+ .byte 0x1
+ .byte 0x15
+ .4byte 0x16cb
+ .byte 0x18
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x166f
+ .uleb128 0x2e
+ .4byte 0x16cb
+ .uleb128 0x13
+ .4byte 0x11d8
+ .uleb128 0x13
+ .4byte 0x11d8
+ .uleb128 0x13
+ .4byte 0x3b
+ .uleb128 0x13
+ .4byte 0x54
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x16b1
+ .uleb128 0x2f
+ .4byte .LASF417
+ .byte 0x1
+ .2byte 0x2c7
+ .4byte 0x1598
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rockchip_secure_otp_ops
+ .uleb128 0x2f
+ .4byte .LASF418
+ .byte 0x1
+ .2byte 0x2dc
+ .4byte 0x16ac
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rk3562_data
+ .uleb128 0xa
+ .4byte 0x1417
+ .4byte 0x170d
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x16fd
+ .uleb128 0x2f
+ .4byte .LASF419
+ .byte 0x1
+ .2byte 0x2e3
+ .4byte 0x170d
+ .uleb128 0x9
+ .byte 0x3
+ .8byte rockchip_otp_ids
+ .uleb128 0x30
+ .4byte .LASF420
+ .byte 0x1
+ .2byte 0x2eb
+ .4byte 0x11de
+ .uleb128 0x9
+ .byte 0x3
+ .8byte _u_boot_list_2_driver_2_rockchip_secure_otp
+ .uleb128 0x31
+ .4byte .LASF421
+ .byte 0x1
+ .2byte 0x2cd
+ .4byte 0x54
+ .8byte .LFB277
+ .8byte .LFE277-.LFB277
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x182b
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2cd
+ .4byte 0x25f
+ .4byte .LLST14
+ .uleb128 0x33
+ .string "otp"
+ .byte 0x1
+ .2byte 0x2cf
+ .4byte 0x182b
+ .4byte .LLST15
+ .uleb128 0x34
+ .8byte .LVL20
+ .4byte 0x4289
+ .4byte 0x1798
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL23
+ .4byte 0x4295
+ .4byte 0x17b0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL24
+ .4byte 0x42a0
+ .4byte 0x17da
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL25
+ .4byte 0x42a0
+ .4byte 0x1804
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC1
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL26
+ .4byte 0x42a0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC2
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x1
+ .byte 0x30
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x1632
+ .uleb128 0x31
+ .4byte .LASF422
+ .byte 0x1
+ .2byte 0x2b6
+ .4byte 0x54
+ .8byte .LFB276
+ .8byte .LFE276-.LFB276
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x18b2
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2b6
+ .4byte 0x25f
+ .4byte .LLST1
+ .uleb128 0x37
+ .4byte .LASF423
+ .byte 0x1
+ .2byte 0x2b7
+ .4byte 0x3b
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x38
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2b8
+ .4byte 0x137
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x33
+ .string "ret"
+ .byte 0x1
+ .2byte 0x2ba
+ .4byte 0x54
+ .4byte .LLST2
+ .uleb128 0x39
+ .4byte 0x18b2
+ .8byte .LBB23
+ .8byte .LBE23-.LBB23
+ .byte 0x1
+ .2byte 0x2be
+ .uleb128 0x3a
+ .4byte 0x18c3
+ .4byte .LLST3
+ .byte 0
+ .byte 0
+ .uleb128 0x3b
+ .4byte .LASF431
+ .byte 0x1
+ .2byte 0x2af
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x18d0
+ .uleb128 0x3c
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2af
+ .4byte 0x11d8
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF424
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x54
+ .8byte .LFB274
+ .8byte .LFE274-.LFB274
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1981
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x25f
+ .4byte .LLST4
+ .uleb128 0x3d
+ .4byte .LASF425
+ .byte 0x1
+ .2byte 0x2a7
+ .4byte 0x54
+ .4byte .LLST5
+ .uleb128 0x32
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2a8
+ .4byte 0x265
+ .4byte .LLST6
+ .uleb128 0x3d
+ .4byte .LASF51
+ .byte 0x1
+ .2byte 0x2a8
+ .4byte 0x54
+ .4byte .LLST7
+ .uleb128 0x3e
+ .4byte .LASF426
+ .byte 0x1
+ .2byte 0x2aa
+ .4byte 0x1981
+ .4byte .LLST8
+ .uleb128 0x34
+ .8byte .LVL8
+ .4byte 0x42ab
+ .4byte 0x195a
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3f
+ .8byte .LVL12
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0
+ .byte 0
+ .uleb128 0x8
+ .byte 0x8
+ .4byte 0x166f
+ .uleb128 0x31
+ .4byte .LASF427
+ .byte 0x1
+ .2byte 0x29f
+ .4byte 0x54
+ .8byte .LFB273
+ .8byte .LFE273-.LFB273
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x1a38
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x29f
+ .4byte 0x25f
+ .4byte .LLST9
+ .uleb128 0x3d
+ .4byte .LASF425
+ .byte 0x1
+ .2byte 0x29f
+ .4byte 0x54
+ .4byte .LLST10
+ .uleb128 0x32
+ .string "buf"
+ .byte 0x1
+ .2byte 0x2a0
+ .4byte 0x137
+ .4byte .LLST11
+ .uleb128 0x3d
+ .4byte .LASF51
+ .byte 0x1
+ .2byte 0x2a0
+ .4byte 0x54
+ .4byte .LLST12
+ .uleb128 0x3e
+ .4byte .LASF426
+ .byte 0x1
+ .2byte 0x2a2
+ .4byte 0x1981
+ .4byte .LLST13
+ .uleb128 0x34
+ .8byte .LVL14
+ .4byte 0x42ab
+ .4byte 0x1a11
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x3f
+ .8byte .LVL18
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0
+ .byte 0
+ .uleb128 0x31
+ .4byte .LASF428
+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x54
+ .8byte .LFB272
+ .8byte .LFE272-.LFB272
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x2564
+ .uleb128 0x32
+ .string "dev"
+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x25f
+ .4byte .LLST69
+ .uleb128 0x3d
+ .4byte .LASF425
+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x54
+ .4byte .LLST70
+ .uleb128 0x32
+ .string "buf"
+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x265
+ .4byte .LLST71
+ .uleb128 0x3d
+ .4byte .LASF51
+ .byte 0x1
+ .2byte 0x26c
+ .4byte 0x54
+ .4byte .LLST72
+ .uleb128 0x33
+ .string "otp"
+ .byte 0x1
+ .2byte 0x26e
+ .4byte 0x182b
+ .4byte .LLST73
+ .uleb128 0x3e
+ .4byte .LASF387
+ .byte 0x1
+ .2byte 0x26f
+ .4byte 0x11d2
+ .4byte .LLST74
+ .uleb128 0x3e
+ .4byte .LASF429
+ .byte 0x1
+ .2byte 0x270
+ .4byte 0xfa
+ .4byte .LLST74
+ .uleb128 0x3e
+ .4byte .LASF430
+ .byte 0x1
+ .2byte 0x271
+ .4byte 0xfa
+ .4byte .LLST76
+ .uleb128 0x33
+ .string "i"
+ .byte 0x1
+ .2byte 0x272
+ .4byte 0x54
+ .4byte .LLST77
+ .uleb128 0x33
+ .string "ret"
+ .byte 0x1
+ .2byte 0x272
+ .4byte 0x54
+ .4byte .LLST78
+ .uleb128 0x40
+ .4byte 0x2564
+ .8byte .LBB244
+ .4byte .Ldebug_ranges0+0x3f0
+ .byte 0x1
+ .2byte 0x294
+ .4byte 0x2436
+ .uleb128 0x3a
+ .4byte 0x2599
+ .4byte .LLST79
+ .uleb128 0x3a
+ .4byte 0x258d
+ .4byte .LLST80
+ .uleb128 0x3a
+ .4byte 0x2581
+ .4byte .LLST81
+ .uleb128 0x3a
+ .4byte 0x2575
+ .4byte .LLST82
+ .uleb128 0x41
+ .4byte .Ldebug_ranges0+0x3f0
+ .uleb128 0x42
+ .4byte 0x25a5
+ .4byte .LLST83
+ .uleb128 0x42
+ .4byte 0x25b1
+ .4byte .LLST84
+ .uleb128 0x43
+ .4byte 0x25ca
+ .8byte .L88
+ .uleb128 0x44
+ .4byte 0x25bd
+ .uleb128 0x45
+ .8byte .LBB246
+ .8byte .LBE246-.LBB246
+ .4byte 0x1b7c
+ .uleb128 0x42
+ .4byte 0x25d7
+ .4byte .LLST85
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB247
+ .8byte .LBE247-.LBB247
+ .4byte 0x1b9b
+ .uleb128 0x42
+ .4byte 0x25e9
+ .4byte .LLST86
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB248
+ .8byte .LBE248-.LBB248
+ .4byte 0x1bba
+ .uleb128 0x42
+ .4byte 0x25fb
+ .4byte .LLST87
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB249
+ .8byte .LBE249-.LBB249
+ .4byte 0x1bd9
+ .uleb128 0x42
+ .4byte 0x260d
+ .4byte .LLST88
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB250
+ .8byte .LBE250-.LBB250
+ .4byte 0x1bf8
+ .uleb128 0x42
+ .4byte 0x261f
+ .4byte .LLST89
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB251
+ .8byte .LBE251-.LBB251
+ .4byte 0x1c17
+ .uleb128 0x42
+ .4byte 0x2631
+ .4byte .LLST90
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB252
+ .8byte .LBE252-.LBB252
+ .4byte 0x1c36
+ .uleb128 0x42
+ .4byte 0x2643
+ .4byte .LLST91
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB253
+ .8byte .LBE253-.LBB253
+ .4byte 0x1c55
+ .uleb128 0x42
+ .4byte 0x2655
+ .4byte .LLST92
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB254
+ .8byte .LBE254-.LBB254
+ .4byte 0x1c74
+ .uleb128 0x42
+ .4byte 0x2667
+ .4byte .LLST93
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB255
+ .8byte .LBE255-.LBB255
+ .4byte 0x1c93
+ .uleb128 0x42
+ .4byte 0x2679
+ .4byte .LLST94
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB256
+ .8byte .LBE256-.LBB256
+ .4byte 0x1cb2
+ .uleb128 0x42
+ .4byte 0x268b
+ .4byte .LLST95
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB257
+ .8byte .LBE257-.LBB257
+ .4byte 0x1cd1
+ .uleb128 0x42
+ .4byte 0x269d
+ .4byte .LLST96
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB258
+ .8byte .LBE258-.LBB258
+ .4byte 0x1cf0
+ .uleb128 0x42
+ .4byte 0x26af
+ .4byte .LLST97
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB259
+ .8byte .LBE259-.LBB259
+ .4byte 0x1d0f
+ .uleb128 0x42
+ .4byte 0x26c1
+ .4byte .LLST98
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB260
+ .8byte .LBE260-.LBB260
+ .4byte 0x1d2e
+ .uleb128 0x42
+ .4byte 0x26d3
+ .4byte .LLST99
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB261
+ .8byte .LBE261-.LBB261
+ .4byte 0x1d4d
+ .uleb128 0x42
+ .4byte 0x26e5
+ .4byte .LLST100
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB262
+ .8byte .LBE262-.LBB262
+ .4byte 0x1d6c
+ .uleb128 0x42
+ .4byte 0x26f7
+ .4byte .LLST101
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB263
+ .8byte .LBE263-.LBB263
+ .4byte 0x1d8b
+ .uleb128 0x42
+ .4byte 0x2709
+ .4byte .LLST102
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x450
+ .4byte 0x1d9e
+ .uleb128 0x42
+ .4byte 0x271b
+ .4byte .LLST103
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x480
+ .4byte 0x1db1
+ .uleb128 0x42
+ .4byte 0x272d
+ .4byte .LLST104
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x4b0
+ .4byte 0x1dc4
+ .uleb128 0x42
+ .4byte 0x273f
+ .4byte .LLST105
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x4e0
+ .4byte 0x1dd7
+ .uleb128 0x42
+ .4byte 0x2a2f
+ .4byte .LLST106
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB272
+ .8byte .LBE272-.LBB272
+ .4byte 0x1df6
+ .uleb128 0x42
+ .4byte 0x2751
+ .4byte .LLST107
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB273
+ .8byte .LBE273-.LBB273
+ .4byte 0x1e15
+ .uleb128 0x42
+ .4byte 0x2763
+ .4byte .LLST108
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB274
+ .8byte .LBE274-.LBB274
+ .4byte 0x1e34
+ .uleb128 0x42
+ .4byte 0x2775
+ .4byte .LLST109
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB275
+ .8byte .LBE275-.LBB275
+ .4byte 0x1e53
+ .uleb128 0x42
+ .4byte 0x2787
+ .4byte .LLST110
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB276
+ .8byte .LBE276-.LBB276
+ .4byte 0x1e72
+ .uleb128 0x42
+ .4byte 0x2799
+ .4byte .LLST111
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB277
+ .8byte .LBE277-.LBB277
+ .4byte 0x1e91
+ .uleb128 0x42
+ .4byte 0x27ab
+ .4byte .LLST112
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB278
+ .8byte .LBE278-.LBB278
+ .4byte 0x1eb0
+ .uleb128 0x42
+ .4byte 0x27bd
+ .4byte .LLST113
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB279
+ .8byte .LBE279-.LBB279
+ .4byte 0x1ecf
+ .uleb128 0x42
+ .4byte 0x27cf
+ .4byte .LLST114
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB280
+ .8byte .LBE280-.LBB280
+ .4byte 0x1eee
+ .uleb128 0x42
+ .4byte 0x27e1
+ .4byte .LLST115
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB281
+ .8byte .LBE281-.LBB281
+ .4byte 0x1f0d
+ .uleb128 0x42
+ .4byte 0x27f3
+ .4byte .LLST116
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB282
+ .8byte .LBE282-.LBB282
+ .4byte 0x1f2c
+ .uleb128 0x42
+ .4byte 0x2805
+ .4byte .LLST117
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB283
+ .8byte .LBE283-.LBB283
+ .4byte 0x1f4b
+ .uleb128 0x42
+ .4byte 0x2817
+ .4byte .LLST118
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB284
+ .8byte .LBE284-.LBB284
+ .4byte 0x1f6a
+ .uleb128 0x42
+ .4byte 0x2829
+ .4byte .LLST119
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB285
+ .8byte .LBE285-.LBB285
+ .4byte 0x1f89
+ .uleb128 0x42
+ .4byte 0x283b
+ .4byte .LLST120
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB286
+ .8byte .LBE286-.LBB286
+ .4byte 0x1fa8
+ .uleb128 0x42
+ .4byte 0x284d
+ .4byte .LLST121
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB287
+ .8byte .LBE287-.LBB287
+ .4byte 0x1fc7
+ .uleb128 0x42
+ .4byte 0x285f
+ .4byte .LLST122
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x510
+ .4byte 0x1fda
+ .uleb128 0x42
+ .4byte 0x2871
+ .4byte .LLST123
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB290
+ .8byte .LBE290-.LBB290
+ .4byte 0x1ff9
+ .uleb128 0x42
+ .4byte 0x2883
+ .4byte .LLST124
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB291
+ .8byte .LBE291-.LBB291
+ .4byte 0x2018
+ .uleb128 0x42
+ .4byte 0x2895
+ .4byte .LLST125
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB292
+ .8byte .LBE292-.LBB292
+ .4byte 0x2037
+ .uleb128 0x42
+ .4byte 0x28a7
+ .4byte .LLST126
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB293
+ .8byte .LBE293-.LBB293
+ .4byte 0x2056
+ .uleb128 0x42
+ .4byte 0x28b9
+ .4byte .LLST127
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x540
+ .4byte 0x2069
+ .uleb128 0x42
+ .4byte 0x28cb
+ .4byte .LLST128
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB296
+ .8byte .LBE296-.LBB296
+ .4byte 0x2088
+ .uleb128 0x42
+ .4byte 0x28dd
+ .4byte .LLST129
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB297
+ .8byte .LBE297-.LBB297
+ .4byte 0x20a7
+ .uleb128 0x42
+ .4byte 0x28ef
+ .4byte .LLST130
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x570
+ .4byte 0x20ba
+ .uleb128 0x42
+ .4byte 0x2901
+ .4byte .LLST131
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x5a0
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+ .4byte .LASF433
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+ .byte 0x3
+ .8byte __func__.7643
+ .uleb128 0x5d
+ .4byte .LASF440
+ .byte 0x1
+ .byte 0xe3
+ .8byte .L60
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x330
+ .4byte 0x3ab8
+ .uleb128 0x55
+ .string "__v"
+ .byte 0x1
+ .byte 0xc0
+ .4byte 0xae
+ .4byte .LLST64
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x360
+ .4byte 0x3ad1
+ .uleb128 0x55
+ .string "__v"
+ .byte 0x1
+ .byte 0xd0
+ .4byte 0xae
+ .4byte .LLST65
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x390
+ .4byte 0x3aea
+ .uleb128 0x55
+ .string "__v"
+ .byte 0x1
+ .byte 0xd2
+ .4byte 0xae
+ .4byte .LLST66
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB176
+ .8byte .LBE176-.LBB176
+ .4byte 0x3b0f
+ .uleb128 0x55
+ .string "__v"
+ .byte 0x1
+ .byte 0xda
+ .4byte 0xa3
+ .4byte .LLST68
+ .byte 0
+ .uleb128 0x46
+ .4byte .Ldebug_ranges0+0x3c0
+ .4byte 0x3b28
+ .uleb128 0x55
+ .string "__v"
+ .byte 0x1
+ .byte 0xe4
+ .4byte 0xae
+ .4byte .LLST67
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL213
+ .4byte 0x4289
+ .4byte 0x3b40
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL216
+ .4byte 0x42ab
+ .4byte 0x3b58
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x86
+ .sleb128 0
+ .byte 0
+ .uleb128 0x47
+ .8byte .LVL219
+ .4byte 0x3b6c
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL220
+ .4byte 0x3c20
+ .4byte 0x3b84
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL222
+ .4byte 0x42ce
+ .4byte 0x3b9c
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x8
+ .byte 0x32
+ .byte 0
+ .uleb128 0x49
+ .8byte .LVL224
+ .4byte 0x42b7
+ .uleb128 0x34
+ .8byte .LVL233
+ .4byte 0x401e
+ .4byte 0x3bce
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x34
+ .uleb128 0x48
+ .4byte 0x3d7a
+ .uleb128 0x2
+ .byte 0x84
+ .sleb128 0
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL236
+ .4byte 0x42b7
+ .4byte 0x3bfa
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC11
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR3
+ .byte 0
+ .uleb128 0x5e
+ .8byte .LVL237
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x2
+ .byte 0x83
+ .sleb128 0
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .4byte 0xee
+ .4byte 0x3c1b
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x16
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x3c0b
+ .uleb128 0x5f
+ .4byte .LASF441
+ .byte 0x1
+ .byte 0x98
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3cc1
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x98
+ .4byte 0x182b
+ .uleb128 0x61
+ .4byte .LASF269
+ .byte 0x1
+ .byte 0x99
+ .4byte 0x144
+ .uleb128 0x62
+ .string "ret"
+ .byte 0x1
+ .byte 0x9b
+ .4byte 0x54
+ .uleb128 0x4e
+ .4byte .LASF433
+ .4byte 0x3cd1
+ .4byte .LASF441
+ .uleb128 0x50
+ .4byte 0x3c6f
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x9d
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x50
+ .4byte 0x3c80
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x9e
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x50
+ .4byte 0x3c91
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x9f
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x50
+ .4byte 0x3ca2
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0xa1
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x50
+ .4byte 0x3cb3
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0xa3
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0xa5
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0xa
+ .4byte 0xee
+ .4byte 0x3cd1
+ .uleb128 0x11
+ .4byte 0xda
+ .byte 0x1e
+ .byte 0
+ .uleb128 0x7
+ .4byte 0x3cc1
+ .uleb128 0x5f
+ .4byte .LASF442
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3d20
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x81
+ .4byte 0x182b
+ .uleb128 0x63
+ .4byte .LASF443
+ .byte 0x1
+ .byte 0x83
+ .4byte 0x54
+ .uleb128 0x63
+ .4byte .LASF430
+ .byte 0x1
+ .byte 0x84
+ .4byte 0x54
+ .uleb128 0x62
+ .string "ret"
+ .byte 0x1
+ .byte 0x85
+ .4byte 0x54
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x88
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .4byte .LASF444
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3d6a
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x6a
+ .4byte 0x182b
+ .uleb128 0x63
+ .4byte .LASF443
+ .byte 0x1
+ .byte 0x6c
+ .4byte 0x54
+ .uleb128 0x63
+ .4byte .LASF430
+ .byte 0x1
+ .byte 0x6d
+ .4byte 0x54
+ .uleb128 0x62
+ .string "ret"
+ .byte 0x1
+ .byte 0x6e
+ .4byte 0x54
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x71
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .4byte .LASF445
+ .byte 0x1
+ .byte 0x56
+ .4byte 0x54
+ .byte 0x1
+ .4byte 0x3dc7
+ .uleb128 0x60
+ .string "otp"
+ .byte 0x1
+ .byte 0x56
+ .4byte 0x182b
+ .uleb128 0x61
+ .4byte .LASF446
+ .byte 0x1
+ .byte 0x57
+ .4byte 0xae
+ .uleb128 0x63
+ .4byte .LASF443
+ .byte 0x1
+ .byte 0x59
+ .4byte 0x54
+ .uleb128 0x4e
+ .4byte .LASF433
+ .4byte 0x2a4d
+ .4byte .LASF445
+ .uleb128 0x50
+ .4byte 0x3db9
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x5b
+ .4byte 0xae
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0x62
+ .string "__v"
+ .byte 0x1
+ .byte 0x65
+ .4byte 0xae
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .4byte .LASF450
+ .byte 0x1
+ .byte 0x4e
+ .8byte .LFB263
+ .8byte .LFE263-.LFB263
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3e3c
+ .uleb128 0x65
+ .4byte .LASF447
+ .byte 0x1
+ .byte 0x4e
+ .4byte 0x11d8
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x54
+ .4byte .LASF448
+ .byte 0x1
+ .byte 0x4f
+ .4byte 0x11d8
+ .4byte .LLST0
+ .uleb128 0x65
+ .4byte .LASF449
+ .byte 0x1
+ .byte 0x50
+ .4byte 0x3b
+ .uleb128 0x1
+ .byte 0x52
+ .uleb128 0x65
+ .4byte .LASF425
+ .byte 0x1
+ .byte 0x50
+ .4byte 0x54
+ .uleb128 0x1
+ .byte 0x53
+ .uleb128 0x66
+ .8byte .LBB22
+ .8byte .LBE22-.LBB22
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x52
+ .4byte 0xae
+ .4byte 0x80000
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .4byte .LASF451
+ .byte 0x1
+ .byte 0x42
+ .8byte .LFB262
+ .8byte .LFE262-.LFB262
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3f2f
+ .uleb128 0x54
+ .4byte .LASF447
+ .byte 0x1
+ .byte 0x42
+ .4byte 0x11d8
+ .4byte .LLST16
+ .uleb128 0x54
+ .4byte .LASF448
+ .byte 0x1
+ .byte 0x43
+ .4byte 0x11d8
+ .4byte .LLST17
+ .uleb128 0x54
+ .4byte .LASF449
+ .byte 0x1
+ .byte 0x44
+ .4byte 0x3b
+ .4byte .LLST18
+ .uleb128 0x54
+ .4byte .LASF425
+ .byte 0x1
+ .byte 0x44
+ .4byte 0x54
+ .4byte .LLST19
+ .uleb128 0x45
+ .8byte .LBB25
+ .8byte .LBE25-.LBB25
+ .4byte 0x3eba
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x47
+ .4byte 0xae
+ .4byte 0x80008
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB26
+ .8byte .LBE26-.LBB26
+ .4byte 0x3edf
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x48
+ .4byte 0xae
+ .4byte 0x100010
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB27
+ .8byte .LBE27-.LBB27
+ .4byte 0x3f04
+ .uleb128 0x67
+ .string "__v"
+ .byte 0x1
+ .byte 0x4a
+ .4byte 0xae
+ .4byte 0x100000
+ .byte 0
+ .uleb128 0x34
+ .8byte .LVL32
+ .4byte 0x42ce
+ .4byte 0x3f1b
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x32
+ .byte 0
+ .uleb128 0x68
+ .8byte .LVL34
+ .4byte 0x42ce
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x69
+ .4byte .LASF463
+ .byte 0x1a
+ .2byte 0x36f
+ .byte 0x3
+ .4byte 0x3f49
+ .uleb128 0x3c
+ .string "ptr"
+ .byte 0x1a
+ .2byte 0x36f
+ .4byte 0x137
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3cd6
+ .8byte .LFB278
+ .8byte .LFE278-.LFB278
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x3fb3
+ .uleb128 0x6b
+ .4byte 0x3ce6
+ .uleb128 0x42
+ .4byte 0x3cf1
+ .4byte .LLST20
+ .uleb128 0x42
+ .4byte 0x3cfc
+ .4byte .LLST21
+ .uleb128 0x44
+ .4byte 0x3d07
+ .uleb128 0x45
+ .8byte .LBB28
+ .8byte .LBE28-.LBB28
+ .4byte 0x3f9f
+ .uleb128 0x42
+ .4byte 0x3d13
+ .4byte .LLST22
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL40
+ .4byte 0x42ce
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3d20
+ .8byte .LFB279
+ .8byte .LFE279-.LFB279
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x401e
+ .uleb128 0x6b
+ .4byte 0x3d30
+ .uleb128 0x42
+ .4byte 0x3d3b
+ .4byte .LLST23
+ .uleb128 0x42
+ .4byte 0x3d46
+ .4byte .LLST24
+ .uleb128 0x6c
+ .4byte 0x3d51
+ .sleb128 -1
+ .uleb128 0x45
+ .8byte .LBB29
+ .8byte .LBE29-.LBB29
+ .4byte 0x400a
+ .uleb128 0x42
+ .4byte 0x3d5d
+ .4byte .LLST25
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL48
+ .4byte 0x42ce
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3d6a
+ .8byte .LFB280
+ .8byte .LFE280-.LFB280
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x410b
+ .uleb128 0x3a
+ .4byte 0x3d85
+ .4byte .LLST26
+ .uleb128 0x6b
+ .4byte 0x3d7a
+ .uleb128 0x42
+ .4byte 0x3d90
+ .4byte .LLST27
+ .uleb128 0x44
+ .4byte 0x3d9b
+ .uleb128 0x45
+ .8byte .LBB36
+ .8byte .LBE36-.LBB36
+ .4byte 0x4074
+ .uleb128 0x42
+ .4byte 0x3dad
+ .4byte .LLST28
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB37
+ .8byte .LBE37-.LBB37
+ .4byte 0x4093
+ .uleb128 0x42
+ .4byte 0x3dba
+ .4byte .LLST29
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB38
+ .8byte .LBE38-.LBB38
+ .4byte 0x40f7
+ .uleb128 0x6b
+ .4byte 0x3d85
+ .uleb128 0x6b
+ .4byte 0x3d7a
+ .uleb128 0x66
+ .8byte .LBB39
+ .8byte .LBE39-.LBB39
+ .uleb128 0x44
+ .4byte 0x3d90
+ .uleb128 0x44
+ .4byte 0x3d9b
+ .uleb128 0x36
+ .8byte .LVL63
+ .4byte 0x42b7
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC3
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR0
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL60
+ .4byte 0x42ce
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x1
+ .byte 0x31
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .4byte 0x3c20
+ .8byte .LFB267
+ .8byte .LFE267-.LFB267
+ .uleb128 0x1
+ .byte 0x9c
+ .4byte 0x4289
+ .uleb128 0x3a
+ .4byte 0x3c30
+ .4byte .LLST48
+ .uleb128 0x3a
+ .4byte 0x3c3b
+ .4byte .LLST49
+ .uleb128 0x42
+ .4byte 0x3c46
+ .4byte .LLST50
+ .uleb128 0x44
+ .4byte 0x3c51
+ .uleb128 0x45
+ .8byte .LBB160
+ .8byte .LBE160-.LBB160
+ .4byte 0x4165
+ .uleb128 0x6c
+ .4byte 0x3c63
+ .sleb128 -16776704
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB161
+ .8byte .LBE161-.LBB161
+ .4byte 0x4183
+ .uleb128 0x6c
+ .4byte 0x3c74
+ .sleb128 -65535
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB162
+ .8byte .LBE162-.LBB162
+ .4byte 0x419f
+ .uleb128 0x6d
+ .4byte 0x3c85
+ .byte 0xfa
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB163
+ .8byte .LBE163-.LBB163
+ .4byte 0x41be
+ .uleb128 0x42
+ .4byte 0x3c96
+ .4byte .LLST51
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB164
+ .8byte .LBE164-.LBB164
+ .4byte 0x41dd
+ .uleb128 0x42
+ .4byte 0x3cb4
+ .4byte .LLST52
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB165
+ .8byte .LBE165-.LBB165
+ .4byte 0x4249
+ .uleb128 0x3a
+ .4byte 0x3c30
+ .4byte .LLST53
+ .uleb128 0x3a
+ .4byte 0x3c3b
+ .4byte .LLST54
+ .uleb128 0x66
+ .8byte .LBB166
+ .8byte .LBE166-.LBB166
+ .uleb128 0x44
+ .4byte 0x4138
+ .uleb128 0x44
+ .4byte 0x4141
+ .uleb128 0x36
+ .8byte .LVL209
+ .4byte 0x42b7
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LC8
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x9
+ .byte 0x3
+ .8byte .LANCHOR2
+ .byte 0
+ .byte 0
+ .byte 0
+ .uleb128 0x45
+ .8byte .LBB167
+ .8byte .LBE167-.LBB167
+ .4byte 0x4265
+ .uleb128 0x6d
+ .4byte 0x3ca7
+ .byte 0x9
+ .byte 0
+ .uleb128 0x36
+ .8byte .LVL205
+ .4byte 0x401e
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .uleb128 0x35
+ .uleb128 0x1
+ .byte 0x51
+ .uleb128 0x1
+ .byte 0x32
+ .uleb128 0x48
+ .4byte 0x3d7a
+ .uleb128 0x3
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0
+ .byte 0
+ .uleb128 0x6e
+ .4byte .LASF452
+ .4byte .LASF452
+ .byte 0x8
+ .2byte 0x115
+ .uleb128 0x6f
+ .4byte .LASF453
+ .4byte .LASF453
+ .byte 0x20
+ .byte 0x85
+ .uleb128 0x6f
+ .4byte .LASF454
+ .4byte .LASF454
+ .byte 0x20
+ .byte 0x38
+ .uleb128 0x6e
+ .4byte .LASF455
+ .4byte .LASF455
+ .byte 0x8
+ .2byte 0x16e
+ .uleb128 0x6f
+ .4byte .LASF456
+ .4byte .LASF456
+ .byte 0x21
+ .byte 0x13
+ .uleb128 0x6e
+ .4byte .LASF457
+ .4byte .LASF457
+ .byte 0x1a
+ .2byte 0x393
+ .uleb128 0x6f
+ .4byte .LASF458
+ .4byte .LASF458
+ .byte 0x22
+ .byte 0xb
+ .byte 0
+ .section .debug_abbrev,"",@progbits
+.Ldebug_abbrev0:
+ .uleb128 0x1
+ .uleb128 0x11
+ .byte 0x1
+ .uleb128 0x25
+ .uleb128 0xe
+ .uleb128 0x13
+ .uleb128 0xb
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x1b
+ .uleb128 0xe
+ .uleb128 0x55
+ .uleb128 0x17
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x10
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x2
+ .uleb128 0x16
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x24
+ .byte 0
+ .uleb128 0xb
+ .uleb128 0xb
+ .uleb128 0x3e
+ .uleb128 0xb
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+ .uleb128 0x4c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4d
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x4e
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x34
+ .uleb128 0x19
+ .uleb128 0x1c
+ .uleb128 0xe
+ .byte 0
+ .byte 0
+ .uleb128 0x4f
+ .uleb128 0xa
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x50
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x51
+ .uleb128 0xb
+ .byte 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x52
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x53
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x54
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x55
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x56
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x17
+ .byte 0
+ .byte 0
+ .uleb128 0x57
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x34
+ .uleb128 0x19
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x58
+ .uleb128 0xa
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x11
+ .uleb128 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x59
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xd
+ .byte 0
+ .byte 0
+ .uleb128 0x5a
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x5b
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x5c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0x6
+ .byte 0
+ .byte 0
+ .uleb128 0x5d
+ .uleb128 0xa
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x11
+ .uleb128 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x5e
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .byte 0
+ .byte 0
+ .uleb128 0x5f
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x60
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x61
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x62
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x63
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x64
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x65
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x2
+ .uleb128 0x18
+ .byte 0
+ .byte 0
+ .uleb128 0x66
+ .uleb128 0xb
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .byte 0
+ .byte 0
+ .uleb128 0x67
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x3
+ .uleb128 0x8
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .uleb128 0x49
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0x6
+ .byte 0
+ .byte 0
+ .uleb128 0x68
+ .uleb128 0x4109
+ .byte 0x1
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x2115
+ .uleb128 0x19
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x69
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .uleb128 0x27
+ .uleb128 0x19
+ .uleb128 0x20
+ .uleb128 0xb
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6a
+ .uleb128 0x2e
+ .byte 0x1
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x11
+ .uleb128 0x1
+ .uleb128 0x12
+ .uleb128 0x7
+ .uleb128 0x40
+ .uleb128 0x18
+ .uleb128 0x2117
+ .uleb128 0x19
+ .uleb128 0x1
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6b
+ .uleb128 0x5
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .byte 0
+ .byte 0
+ .uleb128 0x6c
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xd
+ .byte 0
+ .byte 0
+ .uleb128 0x6d
+ .uleb128 0x34
+ .byte 0
+ .uleb128 0x31
+ .uleb128 0x13
+ .uleb128 0x1c
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .uleb128 0x6e
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0x5
+ .byte 0
+ .byte 0
+ .uleb128 0x6f
+ .uleb128 0x2e
+ .byte 0
+ .uleb128 0x3f
+ .uleb128 0x19
+ .uleb128 0x3c
+ .uleb128 0x19
+ .uleb128 0x6e
+ .uleb128 0xe
+ .uleb128 0x3
+ .uleb128 0xe
+ .uleb128 0x3a
+ .uleb128 0xb
+ .uleb128 0x3b
+ .uleb128 0xb
+ .byte 0
+ .byte 0
+ .byte 0
+ .section .debug_loc,"",@progbits
+.Ldebug_loc0:
+.LLST14:
+ .8byte .LVL19
+ .8byte .LVL20-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL20-1
+ .8byte .LVL27
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL27
+ .8byte .LFE277
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST15:
+ .8byte .LVL21
+ .8byte .LVL22
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL22
+ .8byte .LVL27
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST1:
+ .8byte .LVL2
+ .8byte .LVL3
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL3
+ .8byte .LFE276
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST2:
+ .8byte .LVL2
+ .8byte .LVL5
+ .2byte 0x3
+ .byte 0x9
+ .byte 0xea
+ .byte 0x9f
+ .8byte .LVL6
+ .8byte .LFE276
+ .2byte 0x3
+ .byte 0x9
+ .byte 0xea
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST3:
+ .8byte .LVL4
+ .8byte .LVL5
+ .2byte 0x1
+ .byte 0x52
+ .8byte 0
+ .8byte 0
+.LLST4:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL8-1
+ .8byte .LVL11
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL11
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST5:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL8-1
+ .8byte .LVL11
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL11
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST6:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL8-1
+ .8byte .LVL10
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL10
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST7:
+ .8byte .LVL7
+ .8byte .LVL8-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL8-1
+ .8byte .LVL10
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL10
+ .8byte .LVL12-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL12-1
+ .8byte .LFE274
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST8:
+ .8byte .LVL8
+ .8byte .LVL9
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST9:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL14-1
+ .8byte .LVL17
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL17
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST10:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL14-1
+ .8byte .LVL17
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL17
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST11:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL14-1
+ .8byte .LVL16
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL16
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST12:
+ .8byte .LVL13
+ .8byte .LVL14-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL14-1
+ .8byte .LVL16
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL16
+ .8byte .LVL18-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL18-1
+ .8byte .LFE273
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST13:
+ .8byte .LVL14
+ .8byte .LVL15
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST69:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL247-1
+ .8byte .LVL254
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL254
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST70:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL247-1
+ .8byte .LVL253
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL253
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST71:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL247-1
+ .8byte .LVL256
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte .LVL256
+ .8byte .LVL257
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 80
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte 0
+ .8byte 0
+.LLST72:
+ .8byte .LVL246
+ .8byte .LVL247-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL247-1
+ .8byte .LVL252
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL252
+ .8byte .LVL257
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LVL261
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL261
+ .8byte .LVL267
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL267
+ .8byte .LVL281
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL281
+ .8byte .LVL283
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL287
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL287
+ .8byte .LVL396
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte .LVL396
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST73:
+ .8byte .LVL248
+ .8byte .LVL249
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL249
+ .8byte .LVL255
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST74:
+ .8byte .LVL248
+ .8byte .LVL256
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte .LVL256
+ .8byte .LVL257
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 80
+ .8byte .LVL257
+ .8byte .LFE272
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 224
+ .8byte 0
+ .8byte 0
+.LLST76:
+ .8byte .LVL250
+ .8byte .LVL251
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL257
+ .8byte .LVL258
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL258
+ .8byte .LVL260
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL267
+ .8byte .LVL272
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL285
+ .8byte .LVL286
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST77:
+ .8byte .LVL261
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL269
+ .8byte .LVL270
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL272
+ .8byte .LVL278
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL286
+ .8byte .LVL287
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL288
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL394
+ .8byte .LVL395
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 1
+ .byte 0x9f
+ .8byte .LVL396
+ .8byte .LFE272
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST78:
+ .8byte .LVL250
+ .8byte .LVL251
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL257
+ .8byte .LVL268
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL268
+ .8byte .LVL269
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL272
+ .8byte .LVL280
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL315
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST79:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL288
+ .8byte .LVL313
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL317
+ .8byte .LVL352
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST80:
+ .8byte .LVL262
+ .8byte .LVL264
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL264
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST81:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST82:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST83:
+ .8byte .LVL262
+ .8byte .LVL267
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL288
+ .8byte .LVL311
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL311
+ .8byte .LVL312
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL312
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL317
+ .8byte .LVL318
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL318
+ .8byte .LVL337
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL337
+ .8byte .LVL338
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL338
+ .8byte .LVL339
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL339
+ .8byte .LVL340
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL340
+ .8byte .LVL346
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL346
+ .8byte .LVL347
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL347
+ .8byte .LVL348
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL348
+ .8byte .LVL349
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL349
+ .8byte .LVL356
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL356
+ .8byte .LVL357
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL357
+ .8byte .LVL358
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL358
+ .8byte .LVL359
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL359
+ .8byte .LVL365
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL365
+ .8byte .LVL366
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL366
+ .8byte .LVL367
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL367
+ .8byte .LVL368
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL368
+ .8byte .LVL374
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL374
+ .8byte .LVL375
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL375
+ .8byte .LVL376
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL376
+ .8byte .LVL377
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL377
+ .8byte .LVL379
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL379
+ .8byte .LVL380
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL380
+ .8byte .LVL381
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL381
+ .8byte .LVL382
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL382
+ .8byte .LVL387
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL387
+ .8byte .LVL388
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL388
+ .8byte .LVL389
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL389
+ .8byte .LVL390
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL390
+ .8byte .LVL392
+ .2byte 0x1
+ .byte 0x6b
+ .8byte .LVL392
+ .8byte .LVL393
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL393
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6b
+ .8byte 0
+ .8byte 0
+.LLST84:
+ .8byte .LVL264
+ .8byte .LVL265
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL265
+ .8byte .LVL267
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte .LVL288
+ .8byte .LVL315
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8f
+ .sleb128 232
+ .8byte 0
+ .8byte 0
+.LLST85:
+ .8byte .LVL289
+ .8byte .LVL316
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST86:
+ .8byte .LVL290
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST87:
+ .8byte .LVL291
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST88:
+ .8byte .LVL292
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST89:
+ .8byte .LVL293
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65522
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65522
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST90:
+ .8byte .LVL294
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST91:
+ .8byte .LVL295
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST92:
+ .8byte .LVL296
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST93:
+ .8byte .LVL297
+ .8byte .LVL316
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x25
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x25
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST94:
+ .8byte .LVL298
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST95:
+ .8byte .LVL299
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST96:
+ .8byte .LVL300
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST97:
+ .8byte .LVL301
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x4f
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x4f
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST98:
+ .8byte .LVL302
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x3b
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x3b
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST99:
+ .8byte .LVL303
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x38
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x38
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST100:
+ .8byte .LVL304
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST101:
+ .8byte .LVL305
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST102:
+ .8byte .LVL306
+ .8byte .LVL316
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST103:
+ .8byte .LVL307
+ .8byte .LVL315
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST104:
+ .8byte .LVL308
+ .8byte .LVL313
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL317
+ .8byte .LVL332
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST105:
+ .8byte .LVL309
+ .8byte .LVL316
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST106:
+ .8byte .LVL314
+ .8byte .LVL316
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65533
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST107:
+ .8byte .LVL317
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16762368
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST108:
+ .8byte .LVL319
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xf0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST109:
+ .8byte .LVL320
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST110:
+ .8byte .LVL321
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST111:
+ .8byte .LVL322
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x45
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST112:
+ .8byte .LVL323
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xdc
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST113:
+ .8byte .LVL324
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x92
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST114:
+ .8byte .LVL325
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x79
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST115:
+ .8byte .LVL326
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x81
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST116:
+ .8byte .LVL327
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x7e
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST117:
+ .8byte .LVL328
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x21
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST118:
+ .8byte .LVL329
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x41
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST119:
+ .8byte .LVL330
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0x9d
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST120:
+ .8byte .LVL331
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x32
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST121:
+ .8byte .LVL333
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST122:
+ .8byte .LVL334
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST123:
+ .8byte .LVL335
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST124:
+ .8byte .LVL339
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST125:
+ .8byte .LVL341
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST126:
+ .8byte .LVL342
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfb
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST127:
+ .8byte .LVL343
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST128:
+ .8byte .LVL344
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST129:
+ .8byte .LVL348
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST130:
+ .8byte .LVL350
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xc0
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST131:
+ .8byte .LVL351
+ .8byte .LVL354
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST132:
+ .8byte .LVL352
+ .8byte .LVL394
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST133:
+ .8byte .LVL353
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST134:
+ .8byte .LVL358
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16762368
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST135:
+ .8byte .LVL360
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST136:
+ .8byte .LVL361
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xff
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST137:
+ .8byte .LVL362
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x3a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST138:
+ .8byte .LVL363
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST139:
+ .8byte .LVL367
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST140:
+ .8byte .LVL369
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x31
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST141:
+ .8byte .LVL370
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xbf
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST142:
+ .8byte .LVL371
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST143:
+ .8byte .LVL372
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST144:
+ .8byte .LVL381
+ .8byte .LVL394
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65535
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST145:
+ .8byte .LVL383
+ .8byte .LVL394
+ .2byte 0x2
+ .byte 0x32
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST146:
+ .8byte .LVL384
+ .8byte .LVL394
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xbf
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST147:
+ .8byte .LVL385
+ .8byte .LVL394
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST148:
+ .8byte .LVL273
+ .8byte .LVL276
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL283
+ .8byte .LVL284
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST149:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x69
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x69
+ .8byte 0
+ .8byte 0
+.LLST150:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x6c
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x6c
+ .8byte 0
+ .8byte 0
+.LLST151:
+ .8byte .LVL273
+ .8byte .LVL280
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST152:
+ .8byte .LVL275
+ .8byte .LVL276
+ .2byte 0xd
+ .byte 0x8f
+ .sleb128 254
+ .byte 0x94
+ .byte 0x2
+ .byte 0x20
+ .byte 0x87
+ .sleb128 0
+ .byte 0x8
+ .byte 0xff
+ .byte 0x1a
+ .byte 0x1a
+ .byte 0x9f
+ .8byte .LVL283
+ .8byte .LVL284
+ .2byte 0xf
+ .byte 0x8f
+ .sleb128 254
+ .byte 0x94
+ .byte 0x2
+ .byte 0x20
+ .byte 0x87
+ .sleb128 0
+ .byte 0x8
+ .byte 0xff
+ .byte 0x1a
+ .byte 0x38
+ .byte 0x24
+ .byte 0x1a
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST153:
+ .8byte .LVL274
+ .8byte .LVL277
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL283
+ .8byte .LVL285
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST30:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL67-1
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST31:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL67-1
+ .8byte .LVL72
+ .2byte 0x1
+ .byte 0x6a
+ .8byte .LVL72
+ .8byte .LVL73
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x6a
+ .8byte 0
+ .8byte 0
+.LLST32:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL67-1
+ .8byte .LVL67
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL67
+ .8byte .LVL71
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL71
+ .8byte .LVL73
+ .2byte 0x6
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x31
+ .byte 0x26
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST33:
+ .8byte .LVL66
+ .8byte .LVL67-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL67-1
+ .8byte .LVL70
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL70
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST34:
+ .8byte .LVL66
+ .8byte .LVL70
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL73
+ .8byte .LVL83
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL83
+ .8byte .LVL84
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL87
+ .8byte .LVL88
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL104
+ .8byte .LVL106
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL110
+ .8byte .LVL112
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL130
+ .8byte .LVL132
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL137
+ .8byte .LVL139
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL146
+ .8byte .LVL148
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL152
+ .8byte .LVL154
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL160
+ .8byte .LVL162
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL167
+ .8byte .LVL168
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL169
+ .8byte .LVL170
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL171
+ .8byte .LVL172
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL176
+ .8byte .LVL177
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL178
+ .8byte .LVL179
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL180
+ .8byte .LVL181
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL187
+ .8byte .LVL189
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL193
+ .8byte .LVL195
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL198
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST35:
+ .8byte .LVL67
+ .8byte .LVL68
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL68
+ .8byte .LVL69
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL73
+ .8byte .LFE269
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST36:
+ .8byte .LVL74
+ .8byte .LVL86
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST37:
+ .8byte .LVL75
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x40004
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST38:
+ .8byte .LVL76
+ .8byte .LVL86
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST39:
+ .8byte .LVL77
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0x11
+ .sleb128 -16776704
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST40:
+ .8byte .LVL78
+ .8byte .LVL86
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x5
+ .byte 0x11
+ .sleb128 -65534
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST41:
+ .8byte .LVL79
+ .8byte .LVL86
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfc
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x3
+ .byte 0x8
+ .byte 0xfc
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST42:
+ .8byte .LVL80
+ .8byte .LVL86
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST43:
+ .8byte .LVL81
+ .8byte .LVL86
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST44:
+ .8byte .LVL82
+ .8byte .LVL86
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL87
+ .8byte .LFE269
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST45:
+ .8byte .LVL102
+ .8byte .LVL104-1
+ .2byte 0x1
+ .byte 0x55
+ .8byte .LVL104-1
+ .8byte .LVL165
+ .2byte 0x6
+ .byte 0x88
+ .sleb128 0
+ .byte 0x9
+ .byte 0xf7
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST46:
+ .8byte .LVL142
+ .8byte .LVL145
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST47:
+ .8byte .LVL143
+ .8byte .LVL159
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL159
+ .8byte .LFE269
+ .2byte 0xa
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0xa
+ .2byte 0xffff
+ .byte 0x1a
+ .byte 0x38
+ .byte 0x25
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST55:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL213-1
+ .8byte .LVL221
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL221
+ .8byte .LVL227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST56:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL213-1
+ .8byte .LVL217
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL217
+ .8byte .LVL225
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST57:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL213-1
+ .8byte .LVL222
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL222
+ .8byte .LVL227
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST58:
+ .8byte .LVL212
+ .8byte .LVL213-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL213-1
+ .8byte .LVL222
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL222
+ .8byte .LVL226
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x1
+ .byte 0x67
+ .8byte .LVL228
+ .8byte .LVL244
+ .2byte 0x3
+ .byte 0x87
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL244
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x67
+ .8byte 0
+ .8byte 0
+.LLST59:
+ .8byte .LVL214
+ .8byte .LVL215
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL215
+ .8byte .LVL225
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST60:
+ .8byte .LVL217
+ .8byte .LVL218
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL218
+ .8byte .LVL226
+ .2byte 0x1
+ .byte 0x68
+ .8byte .LVL227
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x68
+ .8byte 0
+ .8byte 0
+.LLST61:
+ .8byte .LVL217
+ .8byte .LVL224
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL227
+ .8byte .LVL236
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL238
+ .8byte .LVL241
+ .2byte 0x1
+ .byte 0x65
+ .8byte .LVL241
+ .8byte .LVL242
+ .2byte 0x3
+ .byte 0x85
+ .sleb128 1
+ .byte 0x9f
+ .8byte .LVL242
+ .8byte .LVL245
+ .2byte 0x3
+ .byte 0x85
+ .sleb128 2
+ .byte 0x9f
+ .8byte .LVL245
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x65
+ .8byte 0
+ .8byte 0
+.LLST62:
+ .8byte .LVL241
+ .8byte .LVL243
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST63:
+ .8byte .LVL217
+ .8byte .LVL222
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL222
+ .8byte .LVL223
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL227
+ .8byte .LVL228
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL228
+ .8byte .LVL234
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL234
+ .8byte .LVL235
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL235
+ .8byte .LVL238
+ .2byte 0x1
+ .byte 0x66
+ .8byte .LVL238
+ .8byte .LVL239
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL239
+ .8byte .LFE268
+ .2byte 0x1
+ .byte 0x66
+ .8byte 0
+ .8byte 0
+.LLST64:
+ .8byte .LVL220
+ .8byte .LVL227
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL228
+ .8byte .LFE268
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST65:
+ .8byte .LVL229
+ .8byte .LVL231
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL231
+ .8byte .LVL232
+ .2byte 0x6
+ .byte 0x84
+ .sleb128 0
+ .byte 0x6
+ .byte 0x23
+ .uleb128 0x104
+ .8byte .LVL232
+ .8byte .LVL236
+ .2byte 0x8
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x21
+ .byte 0x9f
+ .8byte .LVL238
+ .8byte .LFE268
+ .2byte 0x8
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x11
+ .sleb128 -65536
+ .byte 0x21
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST66:
+ .8byte .LVL230
+ .8byte .LVL236
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte .LVL238
+ .8byte .LFE268
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST68:
+ .8byte .LVL240
+ .8byte .LVL243
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST67:
+ .8byte .LVL236
+ .8byte .LVL238
+ .2byte 0x4
+ .byte 0x40
+ .byte 0x3c
+ .byte 0x24
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST0:
+ .8byte .LVL0
+ .8byte .LVL1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL1
+ .8byte .LFE263
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST16:
+ .8byte .LVL28
+ .8byte .LVL31
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL31
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST17:
+ .8byte .LVL28
+ .8byte .LVL29
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL29
+ .8byte .LVL33
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL33
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST18:
+ .8byte .LVL28
+ .8byte .LVL32-1
+ .2byte 0x1
+ .byte 0x52
+ .8byte .LVL32-1
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x52
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST19:
+ .8byte .LVL28
+ .8byte .LVL32-1
+ .2byte 0x1
+ .byte 0x53
+ .8byte .LVL32-1
+ .8byte .LFE262
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x53
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST20:
+ .8byte .LVL35
+ .8byte .LVL38
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL38
+ .8byte .LVL39
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL39
+ .8byte .LVL41
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL41
+ .8byte .LVL42
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST21:
+ .8byte .LVL37
+ .8byte .LVL40-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL41
+ .8byte .LFE278
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST22:
+ .8byte .LVL36
+ .8byte .LVL40-1
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL41
+ .8byte .LFE278
+ .2byte 0x1
+ .byte 0x51
+ .8byte 0
+ .8byte 0
+.LLST23:
+ .8byte .LVL43
+ .8byte .LVL46
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL46
+ .8byte .LVL48
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL48
+ .8byte .LVL50
+ .2byte 0x3
+ .byte 0x83
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL51
+ .8byte .LFE279
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST24:
+ .8byte .LVL45
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL49
+ .8byte .LVL50
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL51
+ .8byte .LVL52
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST25:
+ .8byte .LVL44
+ .8byte .LVL47
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL49
+ .8byte .LVL50
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL51
+ .8byte .LVL52
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST26:
+ .8byte .LVL53
+ .8byte .LVL54
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL54
+ .8byte .LVL56
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL56
+ .8byte .LVL58
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte .LVL58
+ .8byte .LVL64
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL64
+ .8byte .LFE280
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST27:
+ .8byte .LVL54
+ .8byte .LVL60
+ .2byte 0x1
+ .byte 0x64
+ .8byte .LVL60
+ .8byte .LVL61
+ .2byte 0x3
+ .byte 0x84
+ .sleb128 -1
+ .byte 0x9f
+ .8byte .LVL61
+ .8byte .LVL65
+ .2byte 0x1
+ .byte 0x64
+ .8byte 0
+ .8byte 0
+.LLST28:
+ .8byte .LVL55
+ .8byte .LVL57
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL58
+ .8byte .LVL59
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST29:
+ .8byte .LVL56
+ .8byte .LVL58
+ .2byte 0x1
+ .byte 0x63
+ .8byte 0
+ .8byte 0
+.LLST48:
+ .8byte .LVL199
+ .8byte .LVL205-1
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL205-1
+ .8byte .LVL211
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte .LVL211
+ .8byte .LFE267
+ .2byte 0x1
+ .byte 0x50
+ .8byte 0
+ .8byte 0
+.LLST49:
+ .8byte .LVL199
+ .8byte .LVL203
+ .2byte 0x1
+ .byte 0x51
+ .8byte .LVL203
+ .8byte .LFE267
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST50:
+ .8byte .LVL199
+ .8byte .LVL206
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte .LVL206
+ .8byte .LVL208
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL208
+ .8byte .LVL210
+ .2byte 0x1
+ .byte 0x63
+ .8byte .LVL210
+ .8byte .LVL211
+ .2byte 0x1
+ .byte 0x50
+ .8byte .LVL211
+ .8byte .LFE267
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST51:
+ .8byte .LVL202
+ .8byte .LVL204
+ .2byte 0x2
+ .byte 0x30
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST52:
+ .8byte .LVL204
+ .8byte .LVL211
+ .2byte 0x6
+ .byte 0xc
+ .4byte 0x10001
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST53:
+ .8byte .LVL207
+ .8byte .LVL209
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x50
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+.LLST54:
+ .8byte .LVL207
+ .8byte .LVL209
+ .2byte 0x4
+ .byte 0xf3
+ .uleb128 0x1
+ .byte 0x51
+ .byte 0x9f
+ .8byte 0
+ .8byte 0
+ .section .debug_aranges,"",@progbits
+ .4byte 0xec
+ .2byte 0x2
+ .4byte .Ldebug_info0
+ .byte 0x8
+ .byte 0
+ .2byte 0
+ .2byte 0
+ .8byte .LFB263
+ .8byte .LFE263-.LFB263
+ .8byte .LFB276
+ .8byte .LFE276-.LFB276
+ .8byte .LFB274
+ .8byte .LFE274-.LFB274
+ .8byte .LFB273
+ .8byte .LFE273-.LFB273
+ .8byte .LFB277
+ .8byte .LFE277-.LFB277
+ .8byte .LFB262
+ .8byte .LFE262-.LFB262
+ .8byte .LFB278
+ .8byte .LFE278-.LFB278
+ .8byte .LFB279
+ .8byte .LFE279-.LFB279
+ .8byte .LFB280
+ .8byte .LFE280-.LFB280
+ .8byte .LFB269
+ .8byte .LFE269-.LFB269
+ .8byte .LFB267
+ .8byte .LFE267-.LFB267
+ .8byte .LFB268
+ .8byte .LFE268-.LFB268
+ .8byte .LFB272
+ .8byte .LFE272-.LFB272
+ .8byte 0
+ .8byte 0
+ .section .debug_ranges,"",@progbits
+.Ldebug_ranges0:
+ .8byte .LBB48
+ .8byte .LBE48
+ .8byte .LBB49
+ .8byte .LBE49
+ .8byte 0
+ .8byte 0
+ .8byte .LBB64
+ .8byte .LBE64
+ .8byte .LBB66
+ .8byte .LBE66
+ .8byte 0
+ .8byte 0
+ .8byte .LBB65
+ .8byte .LBE65
+ .8byte .LBB67
+ .8byte .LBE67
+ .8byte 0
+ .8byte 0
+ .8byte .LBB68
+ .8byte .LBE68
+ .8byte .LBB69
+ .8byte .LBE69
+ .8byte 0
+ .8byte 0
+ .8byte .LBB73
+ .8byte .LBE73
+ .8byte .LBB74
+ .8byte .LBE74
+ .8byte 0
+ .8byte 0
+ .8byte .LBB92
+ .8byte .LBE92
+ .8byte .LBB93
+ .8byte .LBE93
+ .8byte 0
+ .8byte 0
+ .8byte .LBB98
+ .8byte .LBE98
+ .8byte .LBB99
+ .8byte .LBE99
+ .8byte 0
+ .8byte 0
+ .8byte .LBB103
+ .8byte .LBE103
+ .8byte .LBB105
+ .8byte .LBE105
+ .8byte 0
+ .8byte 0
+ .8byte .LBB104
+ .8byte .LBE104
+ .8byte .LBB106
+ .8byte .LBE106
+ .8byte 0
+ .8byte 0
+ .8byte .LBB107
+ .8byte .LBE107
+ .8byte .LBB108
+ .8byte .LBE108
+ .8byte 0
+ .8byte 0
+ .8byte .LBB112
+ .8byte .LBE112
+ .8byte .LBB113
+ .8byte .LBE113
+ .8byte 0
+ .8byte 0
+ .8byte .LBB118
+ .8byte .LBE118
+ .8byte .LBB119
+ .8byte .LBE119
+ .8byte 0
+ .8byte 0
+ .8byte .LBB123
+ .8byte .LBE123
+ .8byte .LBB124
+ .8byte .LBE124
+ .8byte 0
+ .8byte 0
+ .8byte .LBB128
+ .8byte .LBE128
+ .8byte .LBB129
+ .8byte .LBE129
+ .8byte 0
+ .8byte 0
+ .8byte .LBB135
+ .8byte .LBE135
+ .8byte .LBB136
+ .8byte .LBE136
+ .8byte 0
+ .8byte 0
+ .8byte .LBB140
+ .8byte .LBE140
+ .8byte .LBB141
+ .8byte .LBE141
+ .8byte 0
+ .8byte 0
+ .8byte .LBB144
+ .8byte .LBE144
+ .8byte .LBB145
+ .8byte .LBE145
+ .8byte 0
+ .8byte 0
+ .8byte .LBB168
+ .8byte .LBE168
+ .8byte .LBB169
+ .8byte .LBE169
+ .8byte 0
+ .8byte 0
+ .8byte .LBB170
+ .8byte .LBE170
+ .8byte .LBB171
+ .8byte .LBE171
+ .8byte 0
+ .8byte 0
+ .8byte .LBB172
+ .8byte .LBE172
+ .8byte .LBB173
+ .8byte .LBE173
+ .8byte 0
+ .8byte 0
+ .8byte .LBB174
+ .8byte .LBE174
+ .8byte .LBB175
+ .8byte .LBE175
+ .8byte 0
+ .8byte 0
+ .8byte .LBB244
+ .8byte .LBE244
+ .8byte .LBB324
+ .8byte .LBE324
+ .8byte .LBB325
+ .8byte .LBE325
+ .8byte .LBB335
+ .8byte .LBE335
+ .8byte .LBB336
+ .8byte .LBE336
+ .8byte 0
+ .8byte 0
+ .8byte .LBB264
+ .8byte .LBE264
+ .8byte .LBB266
+ .8byte .LBE266
+ .8byte 0
+ .8byte 0
+ .8byte .LBB265
+ .8byte .LBE265
+ .8byte .LBB267
+ .8byte .LBE267
+ .8byte 0
+ .8byte 0
+ .8byte .LBB268
+ .8byte .LBE268
+ .8byte .LBB269
+ .8byte .LBE269
+ .8byte 0
+ .8byte 0
+ .8byte .LBB270
+ .8byte .LBE270
+ .8byte .LBB271
+ .8byte .LBE271
+ .8byte 0
+ .8byte 0
+ .8byte .LBB288
+ .8byte .LBE288
+ .8byte .LBB289
+ .8byte .LBE289
+ .8byte 0
+ .8byte 0
+ .8byte .LBB294
+ .8byte .LBE294
+ .8byte .LBB295
+ .8byte .LBE295
+ .8byte 0
+ .8byte 0
+ .8byte .LBB298
+ .8byte .LBE298
+ .8byte .LBB300
+ .8byte .LBE300
+ .8byte 0
+ .8byte 0
+ .8byte .LBB299
+ .8byte .LBE299
+ .8byte .LBB301
+ .8byte .LBE301
+ .8byte 0
+ .8byte 0
+ .8byte .LBB302
+ .8byte .LBE302
+ .8byte .LBB303
+ .8byte .LBE303
+ .8byte 0
+ .8byte 0
+ .8byte .LBB308
+ .8byte .LBE308
+ .8byte .LBB309
+ .8byte .LBE309
+ .8byte 0
+ .8byte 0
+ .8byte .LBB314
+ .8byte .LBE314
+ .8byte .LBB315
+ .8byte .LBE315
+ .8byte 0
+ .8byte 0
+ .8byte .LBB326
+ .8byte .LBE326
+ .8byte .LBB332
+ .8byte .LBE332
+ .8byte .LBB333
+ .8byte .LBE333
+ .8byte .LBB334
+ .8byte .LBE334
+ .8byte .LBB337
+ .8byte .LBE337
+ .8byte 0
+ .8byte 0
+ .8byte .LFB263
+ .8byte .LFE263
+ .8byte .LFB276
+ .8byte .LFE276
+ .8byte .LFB274
+ .8byte .LFE274
+ .8byte .LFB273
+ .8byte .LFE273
+ .8byte .LFB277
+ .8byte .LFE277
+ .8byte .LFB262
+ .8byte .LFE262
+ .8byte .LFB278
+ .8byte .LFE278
+ .8byte .LFB279
+ .8byte .LFE279
+ .8byte .LFB280
+ .8byte .LFE280
+ .8byte .LFB269
+ .8byte .LFE269
+ .8byte .LFB267
+ .8byte .LFE267
+ .8byte .LFB268
+ .8byte .LFE268
+ .8byte .LFB272
+ .8byte .LFE272
+ .8byte 0
+ .8byte 0
+ .section .debug_line,"",@progbits
+.Ldebug_line0:
+ .section .debug_str,"MS",@progbits,1
+.LASF222:
+ .string "UCLASS_SERIAL"
+.LASF320:
+ .string "gd_t"
+.LASF15:
+ .string "long int"
+.LASF39:
+ .string "uclass_node"
+.LASF423:
+ .string "request"
+.LASF313:
+ .string "phandle"
+.LASF53:
+ .string "flash_id"
+.LASF405:
+ .string "misc_ops"
+.LASF377:
+ .string "mem_malloc_start"
+.LASF428:
+ .string "rk3562_secure_otp_write"
+.LASF333:
+ .string "net_hostname"
+.LASF28:
+ .string "name"
+.LASF249:
+ .string "UCLASS_ETH_PHY"
+.LASF229:
+ .string "UCLASS_THERMAL"
+.LASF60:
+ .string "base"
+.LASF355:
+ .string "NETLOOP_RESTART"
+.LASF288:
+ .string "new_gd"
+.LASF349:
+ .string "net_boot_file_size"
+.LASF134:
+ .string "fit_hdr_os"
+.LASF181:
+ .string "UCLASS_FIRMWARE"
+.LASF458:
+ .string "udelay"
+.LASF142:
+ .string "fit_noffset_fdt"
+.LASF74:
+ .string "bi_dsp_freq"
+.LASF304:
+ .string "malloc_ptr"
+.LASF91:
+ .string "_datarellocal_start_ofs"
+.LASF94:
+ .string "fdt32_t"
+.LASF146:
+ .string "rd_start"
+.LASF372:
+ .string "property"
+.LASF266:
+ .string "tlb_emerg"
+.LASF78:
+ .string "bi_enetaddr"
+.LASF291:
+ .string "uclass_root"
+.LASF188:
+ .string "UCLASS_IRQ"
+.LASF421:
+ .string "rockchip_secure_otp_ofdata_to_platdata"
+.LASF438:
+ .string "buffer"
+.LASF235:
+ .string "UCLASS_USB_HUB"
+.LASF230:
+ .string "UCLASS_TIMER"
+.LASF42:
+ .string "flags"
+.LASF139:
+ .string "fit_noffset_rd"
+.LASF270:
+ .string "baudrate"
+.LASF335:
+ .string "net_ethaddr"
+.LASF301:
+ .string "timebase_l"
+.LASF21:
+ .string "errno"
+.LASF32:
+ .string "node"
+.LASF360:
+ .string "bind"
+.LASF456:
+ .string "printf"
+.LASF402:
+ .string "DECOM_ZLIB"
+.LASF8:
+ .string "unsigned int"
+.LASF47:
+ .string "next"
+.LASF101:
+ .string "version"
+.LASF397:
+ .string "per_device_platdata_auto_alloc_size"
+.LASF131:
+ .string "legacy_hdr_os_copy"
+.LASF195:
+ .string "UCLASS_MMC"
+.LASF290:
+ .string "dm_root_f"
+.LASF341:
+ .string "net_rx_packet"
+.LASF38:
+ .string "parent_priv"
+.LASF176:
+ .string "UCLASS_CROS_EC"
+.LASF311:
+ .string "console_evt"
+.LASF191:
+ .string "UCLASS_LPC"
+.LASF105:
+ .string "size_dt_struct"
+.LASF380:
+ .string "p_current"
+.LASF345:
+ .string "net_our_vlan"
+.LASF22:
+ .string "___strtok"
+.LASF67:
+ .string "bi_memsize"
+.LASF121:
+ .string "image_info"
+.LASF200:
+ .string "UCLASS_NVME"
+.LASF156:
+ .string "bootm_headers_t"
+.LASF253:
+ .string "UCLASS_RNG"
+.LASF250:
+ .string "UCLASS_MDIO"
+.LASF187:
+ .string "UCLASS_IDE"
+.LASF274:
+ .string "bus_clk"
+.LASF378:
+ .string "mem_malloc_end"
+.LASF225:
+ .string "UCLASS_SPI_FLASH"
+.LASF189:
+ .string "UCLASS_KEYBOARD"
+.LASF72:
+ .string "bi_sramsize"
+.LASF185:
+ .string "UCLASS_I2C_MUX"
+.LASF298:
+ .string "fdt_blob_kern"
+.LASF278:
+ .string "env_addr"
+.LASF48:
+ .string "prev"
+.LASF227:
+ .string "UCLASS_SYSCON"
+.LASF171:
+ .string "UCLASS_BLK"
+.LASF212:
+ .string "UCLASS_PWRSEQ"
+.LASF132:
+ .string "legacy_hdr_valid"
+.LASF265:
+ .string "tlb_fillptr"
+.LASF82:
+ .string "bi_arch_number"
+.LASF324:
+ .string "load_addr"
+.LASF292:
+ .string "fdt_blob"
+.LASF329:
+ .string "net_gateway"
+.LASF166:
+ .string "UCLASS_PCI_EMUL"
+.LASF425:
+ .string "offset"
+.LASF350:
+ .string "net_boot_file_expected_size_in_blocks"
+.LASF404:
+ .string "OTP_NS"
+.LASF415:
+ .string "spl_rockchip_otp_start"
+.LASF206:
+ .string "UCLASS_PHY"
+.LASF455:
+ .string "dev_get_driver_data"
+.LASF3:
+ .string "signed char"
+.LASF203:
+ .string "UCLASS_PCH"
+.LASF100:
+ .string "off_mem_rsvmap"
+.LASF163:
+ .string "UCLASS_TEST_PROBE"
+.LASF149:
+ .string "ft_len"
+.LASF19:
+ .string "uint32_t"
+.LASF385:
+ .string "udevice_id"
+.LASF326:
+ .string "save_size"
+.LASF440:
+ .string "read_end"
+.LASF379:
+ .string "mem_malloc_brk"
+.LASF436:
+ .string "rk3562_secure_otp_write_2_bytes_noecc"
+.LASF143:
+ .string "fit_hdr_setup"
+.LASF300:
+ .string "timebase_h"
+.LASF160:
+ .string "UCLASS_TEST"
+.LASF87:
+ .string "IRQ_STACK_START"
+.LASF420:
+ .string "_u_boot_list_2_driver_2_rockchip_secure_otp"
+.LASF70:
+ .string "bi_flashoffset"
+.LASF201:
+ .string "UCLASS_PANEL"
+.LASF267:
+ .string "pre_serial"
+.LASF431:
+ .string "rockchip_secure_otp_capability"
+.LASF36:
+ .string "uclass"
+.LASF162:
+ .string "UCLASS_TEST_BUS"
+.LASF461:
+ .string "/home/lxh/uboot/u-boot"
+.LASF239:
+ .string "UCLASS_VIDEO_CONSOLE"
+.LASF361:
+ .string "probe"
+.LASF10:
+ .string "long long unsigned int"
+.LASF261:
+ .string "lastinc"
+.LASF389:
+ .string "post_bind"
+.LASF285:
+ .string "irq_sp"
+.LASF327:
+ .string "in_addr"
+.LASF197:
+ .string "UCLASS_MTD"
+.LASF216:
+ .string "UCLASS_RESET"
+.LASF117:
+ .string "ih_type"
+.LASF80:
+ .string "bi_intfreq"
+.LASF172:
+ .string "UCLASS_CLK"
+.LASF351:
+ .string "net_ping_ip"
+.LASF79:
+ .string "bi_ethspeed"
+.LASF376:
+ .string "ofnode"
+.LASF231:
+ .string "UCLASS_TPM"
+.LASF316:
+ .string "child"
+.LASF444:
+ .string "rockchip_secure_otp_wait_flag"
+.LASF457:
+ .string "malloc_simple"
+.LASF59:
+ .string "lmb_property"
+.LASF269:
+ .string "enable"
+.LASF429:
+ .string "data_byte"
+.LASF263:
+ .string "tlb_addr"
+.LASF374:
+ .string "value"
+.LASF184:
+ .string "UCLASS_I2C_GENERIC"
+.LASF99:
+ .string "off_dt_strings"
+.LASF419:
+ .string "rockchip_otp_ids"
+.LASF103:
+ .string "boot_cpuid_phys"
+.LASF362:
+ .string "remove"
+.LASF133:
+ .string "fit_uname_cfg"
+.LASF106:
+ .string "working_fdt"
+.LASF317:
+ .string "sibling"
+.LASF460:
+ .string "drivers/misc/rk3562-secure-otp.c"
+.LASF118:
+ .string "ih_comp"
+.LASF202:
+ .string "UCLASS_PANEL_BACKLIGHT"
+.LASF81:
+ .string "bi_busfreq"
+.LASF297:
+ .string "ufdt_blob"
+.LASF280:
+ .string "ram_top"
+.LASF272:
+ .string "global_data"
+.LASF328:
+ .string "s_addr"
+.LASF127:
+ .string "arch"
+.LASF226:
+ .string "UCLASS_SPI_GENERIC"
+.LASF318:
+ .string "mtd_info"
+.LASF95:
+ .string "fdt_header"
+.LASF177:
+ .string "UCLASS_DISPLAY"
+.LASF391:
+ .string "pre_probe"
+.LASF353:
+ .string "net_loop_state"
+.LASF55:
+ .string "protect"
+.LASF347:
+ .string "net_restart_wrap"
+.LASF307:
+ .string "video_bottom"
+.LASF439:
+ .string "write_end"
+.LASF71:
+ .string "bi_sramstart"
+.LASF224:
+ .string "UCLASS_SPMI"
+.LASF220:
+ .string "UCLASS_SCMI_AGENT"
+.LASF23:
+ .string "_Bool"
+.LASF12:
+ .string "phys_size_t"
+.LASF45:
+ .string "udevice"
+.LASF37:
+ .string "uclass_priv"
+.LASF123:
+ .string "image_len"
+.LASF319:
+ .string "jt_funcs"
+.LASF409:
+ .string "call"
+.LASF331:
+ .string "net_dns_server"
+.LASF398:
+ .string "__invalid_size_argument_for_IOC"
+.LASF57:
+ .string "flash_info"
+.LASF463:
+ .string "free"
+.LASF289:
+ .string "dm_root"
+.LASF108:
+ .string "ih_magic"
+.LASF218:
+ .string "UCLASS_RAMDISK"
+.LASF124:
+ .string "load"
+.LASF26:
+ .string "_binary_u_boot_bin_end"
+.LASF141:
+ .string "fit_uname_fdt"
+.LASF190:
+ .string "UCLASS_LED"
+.LASF293:
+ .string "new_fdt"
+.LASF408:
+ .string "ioctl"
+.LASF434:
+ .string "rk3562_secure_otp_write_byte_noecc"
+.LASF170:
+ .string "UCLASS_AHCI"
+.LASF41:
+ .string "sibling_node"
+.LASF334:
+ .string "net_root_path"
+.LASF49:
+ .string "block_drvr"
+.LASF9:
+ .string "long long int"
+.LASF251:
+ .string "UCLASS_EBC"
+.LASF325:
+ .string "save_addr"
+.LASF35:
+ .string "priv"
+.LASF209:
+ .string "UCLASS_PMIC"
+.LASF303:
+ .string "malloc_limit"
+.LASF14:
+ .string "char"
+.LASF414:
+ .string "secure_otp_data"
+.LASF180:
+ .string "UCLASS_GPIO"
+.LASF44:
+ .string "ide_bus_offset"
+.LASF255:
+ .string "UCLASS_PD"
+.LASF52:
+ .string "sector_count"
+.LASF145:
+ .string "fit_noffset_setup"
+.LASF122:
+ .string "image_start"
+.LASF56:
+ .string "flash_info_t"
+.LASF228:
+ .string "UCLASS_SYSRESET"
+.LASF115:
+ .string "ih_os"
+.LASF31:
+ .string "uclass_platdata"
+.LASF337:
+ .string "net_ip"
+.LASF459:
+ .ascii "GNU C11 6.3.1 201"
+ .string "70404 -mstrict-align -march=armv8-a+nosimd -mlittle-endian -mabi=lp64 -g -Os -fno-builtin -ffreestanding -fshort-wchar -fno-stack-protector -fno-delete-null-pointer-checks -fstack-usage -ffunction-sections -fdata-sections -ffixed-r9 -fno-common -ffixed-x18"
+.LASF306:
+ .string "video_top"
+.LASF258:
+ .string "LOGF_MAX_CATEGORIES"
+.LASF358:
+ .string "net_state"
+.LASF286:
+ .string "start_addr_sp"
+.LASF135:
+ .string "fit_uname_os"
+.LASF18:
+ .string "uint8_t"
+.LASF7:
+ .string "__u32"
+.LASF363:
+ .string "unbind"
+.LASF284:
+ .string "mon_len"
+.LASF357:
+ .string "NETLOOP_FAIL"
+.LASF418:
+ .string "rk3562_data"
+.LASF365:
+ .string "child_post_bind"
+.LASF314:
+ .string "full_name"
+.LASF214:
+ .string "UCLASS_REGULATOR"
+.LASF183:
+ .string "UCLASS_I2C_EEPROM"
+.LASF371:
+ .string "per_child_platdata_auto_alloc_size"
+.LASF445:
+ .string "rockchip_secure_otp_wait_status"
+.LASF129:
+ .string "bootm_headers"
+.LASF276:
+ .string "mem_clk"
+.LASF359:
+ .string "of_match"
+.LASF352:
+ .string "uclass_id"
+.LASF321:
+ .string "monitor_flash_len"
+.LASF367:
+ .string "child_post_remove"
+.LASF370:
+ .string "per_child_auto_alloc_size"
+.LASF213:
+ .string "UCLASS_RAM"
+.LASF451:
+ .string "rk3562_spl_rockchip_otp_start"
+.LASF364:
+ .string "ofdata_to_platdata"
+.LASF208:
+ .string "UCLASS_PINCTRL"
+.LASF29:
+ .string "platdata"
+.LASF260:
+ .string "timer_rate_hz"
+.LASF435:
+ .string "data_2b"
+.LASF90:
+ .string "_datarelrolocal_start_ofs"
+.LASF164:
+ .string "UCLASS_SPI_EMUL"
+.LASF196:
+ .string "UCLASS_MOD_EXP"
+.LASF97:
+ .string "totalsize"
+.LASF388:
+ .string "uclass_driver"
+.LASF73:
+ .string "bi_arm_freq"
+.LASF199:
+ .string "UCLASS_NORTHBRIDGE"
+.LASF236:
+ .string "UCLASS_USB_GADGET_GENERIC"
+.LASF120:
+ .string "image_header_t"
+.LASF68:
+ .string "bi_flashstart"
+.LASF92:
+ .string "_datarelro_start_ofs"
+.LASF13:
+ .string "sizetype"
+.LASF386:
+ .string "compatible"
+.LASF165:
+ .string "UCLASS_I2C_EMUL"
+.LASF275:
+ .string "pci_clk"
+.LASF173:
+ .string "UCLASS_CPU"
+.LASF344:
+ .string "net_null_ethaddr"
+.LASF86:
+ .string "bd_t"
+.LASF174:
+ .string "UCLASS_AMP"
+.LASF244:
+ .string "UCLASS_RC"
+.LASF454:
+ .string "dev_read_u32_default"
+.LASF338:
+ .string "net_server_ip"
+.LASF281:
+ .string "ram_top_ext_size"
+.LASF51:
+ .string "size"
+.LASF58:
+ .string "long double"
+.LASF76:
+ .string "bi_bootflags"
+.LASF83:
+ .string "bi_boot_params"
+.LASF442:
+ .string "rockchip_secure_otp_check_flag"
+.LASF449:
+ .string "mask"
+.LASF247:
+ .string "UCLASS_IO_DOMAIN"
+.LASF25:
+ .string "_binary_u_boot_bin_start"
+.LASF159:
+ .string "UCLASS_DEMO"
+.LASF107:
+ .string "image_header"
+.LASF102:
+ .string "last_comp_version"
+.LASF322:
+ .string "__dtb_dt_begin"
+.LASF252:
+ .string "UCLASS_EINK_DISPLAY"
+.LASF310:
+ .string "sys_start_tick"
+.LASF168:
+ .string "UCLASS_SIMPLE_BUS"
+.LASF179:
+ .string "UCLASS_ETH"
+.LASF153:
+ .string "cmdline_end"
+.LASF75:
+ .string "bi_ddr_freq"
+.LASF98:
+ .string "off_dt_struct"
+.LASF441:
+ .string "rockchip_secure_otp_ecc_enable"
+.LASF232:
+ .string "UCLASS_UFS"
+.LASF309:
+ .string "serial"
+.LASF387:
+ .string "data"
+.LASF330:
+ .string "net_netmask"
+.LASF323:
+ .string "__dtb_dt_spl_begin"
+.LASF65:
+ .string "bd_info"
+.LASF152:
+ .string "cmdline_start"
+.LASF157:
+ .string "images"
+.LASF268:
+ .string "using_pre_serial"
+.LASF130:
+ .string "legacy_hdr_os"
+.LASF426:
+ .string "otp_data"
+.LASF192:
+ .string "UCLASS_MAILBOX"
+.LASF217:
+ .string "UCLASS_RKNAND"
+.LASF138:
+ .string "fit_uname_rd"
+.LASF437:
+ .string "rk3562_secure_otp_read"
+.LASF77:
+ .string "bi_ip_addr"
+.LASF308:
+ .string "pm_ctx_phys"
+.LASF296:
+ .string "of_root_f"
+.LASF282:
+ .string "relocaddr"
+.LASF33:
+ .string "driver_data"
+.LASF0:
+ .string "unsigned char"
+.LASF11:
+ .string "phys_addr_t"
+.LASF390:
+ .string "pre_unbind"
+.LASF432:
+ .string "rk3562_secure_otp_write_2_bytes"
+.LASF339:
+ .string "net_tx_packet"
+.LASF396:
+ .string "per_device_auto_alloc_size"
+.LASF150:
+ .string "initrd_start"
+.LASF34:
+ .string "parent"
+.LASF381:
+ .string "current"
+.LASF6:
+ .string "short int"
+.LASF302:
+ .string "malloc_base"
+.LASF116:
+ .string "ih_arch"
+.LASF401:
+ .string "DECOM_GZIP"
+.LASF315:
+ .string "properties"
+.LASF241:
+ .string "UCLASS_WDT"
+.LASF443:
+ .string "delay"
+.LASF373:
+ .string "length"
+.LASF332:
+ .string "net_nis_domain"
+.LASF112:
+ .string "ih_load"
+.LASF299:
+ .string "env_buf"
+.LASF356:
+ .string "NETLOOP_SUCCESS"
+.LASF167:
+ .string "UCLASS_USB_EMUL"
+.LASF430:
+ .string "temp"
+.LASF161:
+ .string "UCLASS_TEST_FDT"
+.LASF294:
+ .string "fdt_size"
+.LASF416:
+ .string "spl_rockchip_otp_stop"
+.LASF446:
+ .string "flag"
+.LASF17:
+ .string "ulong"
+.LASF110:
+ .string "ih_time"
+.LASF111:
+ .string "ih_size"
+.LASF178:
+ .string "UCLASS_DMA"
+.LASF254:
+ .string "UCLASS_DMC"
+.LASF215:
+ .string "UCLASS_REMOTEPROC"
+.LASF354:
+ .string "NETLOOP_CONTINUE"
+.LASF219:
+ .string "UCLASS_RTC"
+.LASF262:
+ .string "timer_reset_value"
+.LASF295:
+ .string "of_root"
+.LASF340:
+ .string "net_rx_packets"
+.LASF194:
+ .string "UCLASS_MISC"
+.LASF62:
+ .string "region"
+.LASF148:
+ .string "ft_addr"
+.LASF417:
+ .string "rockchip_secure_otp_ops"
+.LASF406:
+ .string "read"
+.LASF54:
+ .string "start"
+.LASF144:
+ .string "fit_uname_setup"
+.LASF114:
+ .string "ih_dcrc"
+.LASF24:
+ .string "image_base"
+.LASF393:
+ .string "pre_remove"
+.LASF158:
+ .string "UCLASS_ROOT"
+.LASF96:
+ .string "magic"
+.LASF242:
+ .string "UCLASS_FG"
+.LASF137:
+ .string "fit_hdr_rd"
+.LASF140:
+ .string "fit_hdr_fdt"
+.LASF113:
+ .string "ih_ep"
+.LASF287:
+ .string "reloc_off"
+.LASF394:
+ .string "init"
+.LASF240:
+ .string "UCLASS_VIDEO_CRTC"
+.LASF237:
+ .string "UCLASS_VIDEO"
+.LASF447:
+ .string "secure_conf"
+.LASF205:
+ .string "UCLASS_PCI_GENERIC"
+.LASF1:
+ .string "long unsigned int"
+.LASF5:
+ .string "__u8"
+.LASF375:
+ .string "of_offset"
+.LASF259:
+ .string "arch_global_data"
+.LASF89:
+ .string "_datarel_start_ofs"
+.LASF312:
+ .string "device_node"
+.LASF264:
+ .string "tlb_size"
+.LASF66:
+ .string "bi_memstart"
+.LASF109:
+ .string "ih_hcrc"
+.LASF104:
+ .string "size_dt_strings"
+.LASF128:
+ .string "image_info_t"
+.LASF63:
+ .string "memory"
+.LASF27:
+ .string "driver"
+.LASF147:
+ .string "rd_end"
+.LASF193:
+ .string "UCLASS_MASS_STORAGE"
+.LASF450:
+ .string "rk3562_spl_rockchip_otp_stop"
+.LASF151:
+ .string "initrd_end"
+.LASF210:
+ .string "UCLASS_PWM"
+.LASF93:
+ .string "IRQ_STACK_START_IN"
+.LASF84:
+ .string "bi_andr_version"
+.LASF126:
+ .string "type"
+.LASF342:
+ .string "net_rx_packet_len"
+.LASF384:
+ .string "u_boot_dev_head"
+.LASF427:
+ .string "secure_otp_read"
+.LASF221:
+ .string "UCLASS_SCSI"
+.LASF16:
+ .string "ushort"
+.LASF204:
+ .string "UCLASS_PCI"
+.LASF198:
+ .string "UCLASS_NOP"
+.LASF395:
+ .string "destroy"
+.LASF448:
+ .string "otp_cru_rst"
+.LASF248:
+ .string "UCLASS_CRYPTO"
+.LASF453:
+ .string "dev_read_addr_ptr"
+.LASF277:
+ .string "have_console"
+.LASF400:
+ .string "DECOM_LZ4"
+.LASF175:
+ .string "UCLASS_CODEC"
+.LASF382:
+ .string "uc_drv"
+.LASF233:
+ .string "UCLASS_USB"
+.LASF305:
+ .string "cur_serial_dev"
+.LASF271:
+ .string "addr"
+.LASF46:
+ .string "list_head"
+.LASF155:
+ .string "state"
+.LASF20:
+ .string "__be32"
+.LASF207:
+ .string "UCLASS_PINCONFIG"
+.LASF234:
+ .string "UCLASS_USB_DEV_GENERIC"
+.LASF343:
+ .string "net_bcast_ethaddr"
+.LASF136:
+ .string "fit_noffset_os"
+.LASF223:
+ .string "UCLASS_SPI"
+.LASF336:
+ .string "net_server_ethaddr"
+.LASF256:
+ .string "UCLASS_COUNT"
+.LASF279:
+ .string "env_valid"
+.LASF246:
+ .string "UCLASS_DVFS"
+.LASF413:
+ .string "otp_cru_rst_base"
+.LASF40:
+ .string "child_head"
+.LASF50:
+ .string "select_hwpart"
+.LASF4:
+ .string "uchar"
+.LASF69:
+ .string "bi_flashsize"
+.LASF383:
+ .string "dev_head"
+.LASF410:
+ .string "rockchip_otp_platdata"
+.LASF2:
+ .string "short unsigned int"
+.LASF392:
+ .string "post_probe"
+.LASF366:
+ .string "child_pre_probe"
+.LASF422:
+ .string "secure_otp_ioctl"
+.LASF348:
+ .string "net_boot_file_name"
+.LASF407:
+ .string "write"
+.LASF245:
+ .string "UCLASS_CHARGE_DISPLAY"
+.LASF257:
+ .string "UCLASS_INVALID"
+.LASF403:
+ .string "OTP_S"
+.LASF433:
+ .string "__func__"
+.LASF64:
+ .string "reserved"
+.LASF182:
+ .string "UCLASS_I2C"
+.LASF119:
+ .string "ih_name"
+.LASF462:
+ .string "ofnode_union"
+.LASF412:
+ .string "otp_mask_base"
+.LASF169:
+ .string "UCLASS_ADC"
+.LASF43:
+ .string "req_seq"
+.LASF283:
+ .string "ram_size"
+.LASF452:
+ .string "dev_get_platdata"
+.LASF186:
+ .string "UCLASS_I2S"
+.LASF368:
+ .string "priv_auto_alloc_size"
+.LASF30:
+ .string "parent_platdata"
+.LASF411:
+ .string "secure_conf_base"
+.LASF154:
+ .string "verify"
+.LASF88:
+ .string "FIQ_STACK_START"
+.LASF85:
+ .string "bi_dram"
+.LASF125:
+ .string "comp"
+.LASF346:
+ .string "net_native_vlan"
+.LASF424:
+ .string "secure_otp_write"
+.LASF211:
+ .string "UCLASS_POWER_DOMAIN"
+.LASF399:
+ .string "misc_mode"
+.LASF273:
+ .string "cpu_clk"
+.LASF238:
+ .string "UCLASS_VIDEO_BRIDGE"
+.LASF369:
+ .string "platdata_auto_alloc_size"
+.LASF61:
+ .string "lmb_region"
+.LASF243:
+ .string "UCLASS_KEY"
+ .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404"
+ .section .note.GNU-stack,"",@progbits
diff --git a/u-boot/drivers/misc/rockchip-otp.c b/u-boot/drivers/misc/rockchip-otp.c
index 6782148..16d53bf 100644
--- a/u-boot/drivers/misc/rockchip-otp.c
+++ b/u-boot/drivers/misc/rockchip-otp.c
@@ -246,7 +246,7 @@
if (!buffer)
return -ENOMEM;
- ret = rockchip_otp_ecc_enable(otp, false);
+ ret = rockchip_otp_ecc_enable(otp, true);
if (ret < 0) {
printf("%s rockchip_otp_ecc_enable err\n", __func__);
return ret;
@@ -460,6 +460,14 @@
.data = (ulong)&rk3308bs_data,
},
{
+ .compatible = "rockchip,rk3528-otp",
+ .data = (ulong)&rk3568_data,
+ },
+ {
+ .compatible = "rockchip,rk3562-otp",
+ .data = (ulong)&rk3568_data,
+ },
+ {
.compatible = "rockchip,rk3568-otp",
.data = (ulong)&rk3568_data,
},
diff --git a/u-boot/drivers/mmc/dw_mmc.c b/u-boot/drivers/mmc/dw_mmc.c
index ae4a04d..aa31971 100644
--- a/u-boot/drivers/mmc/dw_mmc.c
+++ b/u-boot/drivers/mmc/dw_mmc.c
@@ -8,6 +8,7 @@
#include <common.h>
#include <bouncebuf.h>
+#include <div64.h>
#include <errno.h>
#include <malloc.h>
#include <memalign.h>
@@ -19,6 +20,7 @@
#endif
#define PAGE_SIZE 4096
+#define MSEC_PER_SEC 1000ULL
/*
* Currently it supports read/write up to 8*8*4 Bytes per
@@ -159,18 +161,62 @@
dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
}
-static unsigned int dwmci_get_timeout(struct mmc *mmc, const unsigned int size)
+#ifdef CONFIG_SPL_BUILD
+static unsigned int dwmci_get_drto(struct dwmci_host *host,
+ const unsigned int size)
+{
+ unsigned int drto_clks;
+ unsigned int drto_div;
+ unsigned int drto_ms;
+
+ drto_clks = dwmci_readl(host, DWMCI_TMOUT) >> 8;
+ drto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2;
+ if (drto_div == 0)
+ drto_div = 1;
+
+ drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
+ host->mmc->clock);
+
+ /* add a bit spare time */
+ drto_ms += 10;
+
+ return drto_ms;
+}
+#else
+static unsigned int dwmci_get_drto(struct dwmci_host *host,
+ const unsigned int size)
{
unsigned int timeout;
timeout = size * 8; /* counting in bits */
timeout *= 10; /* wait 10 times as long */
- timeout /= mmc->clock;
- timeout /= mmc->bus_width;
+ timeout /= host->mmc->clock;
+ timeout /= host->mmc->bus_width;
timeout *= 1000; /* counting in msec */
timeout = (timeout < 10000) ? 10000 : timeout;
return timeout;
+}
+#endif
+
+static unsigned int dwmci_get_cto(struct dwmci_host *host)
+{
+ unsigned int cto_clks;
+ unsigned int cto_div;
+ unsigned int cto_ms;
+
+ cto_clks = dwmci_readl(host, DWMCI_TMOUT) & 0xff;
+ cto_div = (dwmci_readl(host, DWMCI_CLKDIV) & 0xff) * 2;
+ if (cto_div == 0)
+ cto_div = 1;
+
+ cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
+ host->mmc->clock);
+
+ /* add a bit spare time */
+ cto_ms += 10;
+
+ return cto_ms;
}
static int dwmci_data_transfer(struct dwmci_host *host, struct mmc_data *data)
@@ -192,7 +238,7 @@
else
buf = (unsigned int *)data->src;
- timeout = dwmci_get_timeout(host->mmc, size);
+ timeout = dwmci_get_drto(host, size);
size /= 4;
for (;;) {
@@ -252,6 +298,7 @@
}
dwmci_writel(host, DWMCI_RINTSTS,
DWMCI_INTMSK_RXDR);
+ start = get_timer(0);
} else if (data->flags == MMC_DATA_WRITE &&
(mask & DWMCI_INTMSK_TXDR)) {
while (size) {
@@ -281,6 +328,7 @@
}
dwmci_writel(host, DWMCI_RINTSTS,
DWMCI_INTMSK_TXDR);
+ start = get_timer(0);
}
}
@@ -329,9 +377,8 @@
struct dwmci_host *host = mmc->priv;
ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
data ? DIV_ROUND_UP(data->blocks, 8) : 0);
- int ret = 0, flags = 0, i;
+ int ret = 0, flags = 0;
unsigned int timeout = 500;
- u32 retry = 100000;
u32 mask, ctrl;
ulong start = get_timer(0);
struct bounce_buffer bbstate;
@@ -400,16 +447,18 @@
dwmci_writel(host, DWMCI_CMD, flags);
- for (i = 0; i < retry; i++) {
+ timeout = dwmci_get_cto(host);
+ start = get_timer(0);
+ do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask & DWMCI_INTMSK_CDONE) {
if (!data)
dwmci_writel(host, DWMCI_RINTSTS, mask);
break;
}
- }
+ } while (!(get_timer(start) > timeout));
- if (i == retry) {
+ if (get_timer(start) > timeout) {
debug("%s: Timeout.\n", __func__);
return -ETIMEDOUT;
}
@@ -470,9 +519,8 @@
#endif
struct dwmci_host *host = mmc->priv;
struct dwmci_idmac *cur_idmac;
- int ret = 0, flags = 0, i;
+ int ret = 0, flags = 0;
unsigned int timeout = 500;
- u32 retry = 100000;
u32 mask;
ulong start = get_timer(0);
struct bounce_buffer bbstate;
@@ -541,16 +589,18 @@
dwmci_writel(host, DWMCI_CMD, flags);
- for (i = 0; i < retry; i++) {
+ timeout = dwmci_get_cto(host);
+ start = get_timer(0);
+ do {
mask = dwmci_readl(host, DWMCI_RINTSTS);
if (mask & DWMCI_INTMSK_CDONE) {
if (!data)
dwmci_writel(host, DWMCI_RINTSTS, mask);
break;
}
- }
+ } while (!(get_timer(start) > timeout));
- if (i == retry) {
+ if (get_timer(start) > timeout) {
debug("%s: Timeout.\n", __func__);
return -ETIMEDOUT;
}
diff --git a/u-boot/drivers/mmc/mmc-uclass.c b/u-boot/drivers/mmc/mmc-uclass.c
index 0b49d3d..eb44c38 100644
--- a/u-boot/drivers/mmc/mmc-uclass.c
+++ b/u-boot/drivers/mmc/mmc-uclass.c
@@ -143,6 +143,20 @@
return dm_mmc_get_cd(mmc->dev);
}
+static int dm_mmc_set_enhanced_strobe(struct udevice *dev)
+{
+ struct dm_mmc_ops *ops = mmc_get_ops(dev);
+
+ if (ops->set_enhanced_strobe)
+ return ops->set_enhanced_strobe(dev);
+
+ return -ENOTSUPP;
+}
+
+int mmc_set_enhanced_strobe(struct mmc *mmc)
+{
+ return dm_mmc_set_enhanced_strobe(mmc->dev);
+}
struct mmc *mmc_get_mmc_dev(struct udevice *dev)
{
struct mmc_uclass_priv *upriv;
diff --git a/u-boot/drivers/mmc/mmc.c b/u-boot/drivers/mmc/mmc.c
index 679fda6..590e4ba 100644
--- a/u-boot/drivers/mmc/mmc.c
+++ b/u-boot/drivers/mmc/mmc.c
@@ -1007,12 +1007,22 @@
return ret;
}
+static int mmc_switch_to_hs400(struct mmc *mmc)
+{
+ u8 val, fixed_drv_type, card_drv_type, drive_strength;
+
+ fixed_drv_type = mmc->cfg->fixed_drv_type;
+ card_drv_type = mmc->raw_driver_strength | mmc_driver_type_mask(0);
+ drive_strength = (card_drv_type & mmc_driver_type_mask(fixed_drv_type))
+ ? fixed_drv_type : 0;
+ val = EXT_CSD_TIMING_HS400 | drive_strength << EXT_CSD_DRV_STR_SHIFT;
+
+ return __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, val, false);
+}
+
static int mmc_select_hs400(struct mmc *mmc)
{
int ret;
-
- /* Reduce frequency to HS frequency */
- mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
/* Switch card to HS mode */
ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
@@ -1022,6 +1032,9 @@
/* Set host controller to HS timing */
mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+ /* Reduce frequency to HS frequency */
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
ret = mmc_send_status(mmc, 1000);
if (ret)
@@ -1035,8 +1048,7 @@
return ret;
/* Switch card to HS400 */
- ret = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS400, false);
+ ret = mmc_switch_to_hs400(mmc);
if (ret)
return ret;
@@ -1045,9 +1057,48 @@
return ret;
}
+
+static int mmc_select_hs400es(struct mmc *mmc)
+{
+ int err;
+
+ /* Switch card to HS mode */
+ err = __mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS, false);
+ if (err)
+ return err;
+
+ /* Set host controller to HS timing */
+ mmc_set_timing(mmc, MMC_TIMING_MMC_HS);
+
+ err = mmc_send_status(mmc, 1000);
+ if (err)
+ return err;
+
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
+
+ err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH,
+ EXT_CSD_DDR_BUS_WIDTH_8 |
+ EXT_CSD_BUS_WIDTH_STROBE);
+ if (err) {
+ printf("switch to bus width for hs400 failed\n");
+ return err;
+ }
+
+ /* Switch card to HS400 */
+ err = mmc_switch_to_hs400(mmc);
+ if (err)
+ return err;
+
+ /* Set host controller to HS400 timing and frequency */
+ mmc_set_timing(mmc, MMC_TIMING_MMC_HS400ES);
+
+ return mmc_set_enhanced_strobe(mmc);
+}
#else
static int mmc_select_hs200(struct mmc *mmc) { return 0; }
static int mmc_select_hs400(struct mmc *mmc) { return 0; }
+static int mmc_select_hs400es(struct mmc *mmc) { return 0; }
#endif
static u32 mmc_select_card_type(struct mmc *mmc, u8 *ext_csd)
@@ -1139,6 +1190,16 @@
return err;
avail_type = mmc_select_card_type(mmc, ext_csd);
+
+ if (avail_type & EXT_CSD_CARD_TYPE_HS400ES) {
+ err = mmc_select_bus_width(mmc);
+ if (err > 0 && mmc->bus_width == MMC_BUS_WIDTH_8BIT) {
+ err = mmc_select_hs400es(mmc);
+ mmc_set_bus_speed(mmc, avail_type);
+ if (!err)
+ return err;
+ }
+ }
if (avail_type & EXT_CSD_CARD_TYPE_HS200)
err = mmc_select_hs200(mmc);
@@ -1824,6 +1885,10 @@
mmc->erase_grp_size = 1;
mmc->part_config = MMCPART_NOAVAILABLE;
if (!IS_SD(mmc) && (mmc->version >= MMC_VERSION_4)) {
+ /* select high speed to reduce initialization time */
+ mmc_select_hs(mmc);
+ mmc_set_clock(mmc, MMC_HIGH_52_MAX_DTR);
+
/* check ext_csd version and capacity */
err = mmc_send_ext_csd(mmc, ext_csd);
if (err)
@@ -1973,6 +2038,8 @@
* ext_csd[EXT_CSD_HC_WP_GRP_SIZE];
mmc->wr_rel_set = ext_csd[EXT_CSD_WR_REL_SET];
+
+ mmc->raw_driver_strength = ext_csd[EXT_CSD_DRIVER_STRENGTH];
}
err = mmc_set_capacity(mmc, mmc_get_blk_desc(mmc)->hwpart);
diff --git a/u-boot/drivers/mmc/rockchip_dw_mmc.c b/u-boot/drivers/mmc/rockchip_dw_mmc.c
index 1287551..a78cb39 100644
--- a/u-boot/drivers/mmc/rockchip_dw_mmc.c
+++ b/u-boot/drivers/mmc/rockchip_dw_mmc.c
@@ -42,7 +42,7 @@
{
struct rockchip_dwmmc_priv *priv = dev_get_priv(dev);
- if (!priv || !&priv->clk)
+ if (!priv)
return 0;
if (!memcmp(dev->name, "dwmmc", strlen("dwmmc")))
diff --git a/u-boot/drivers/mmc/rockchip_sdhci.c b/u-boot/drivers/mmc/rockchip_sdhci.c
index d6224da..327c0d2 100644
--- a/u-boot/drivers/mmc/rockchip_sdhci.c
+++ b/u-boot/drivers/mmc/rockchip_sdhci.c
@@ -39,6 +39,12 @@
((((x) >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK) ==\
PHYCTRL_DLLRDY_DONE)
+#define ARASAN_VENDOR_REGISTER 0x78
+#define ARASAN_VENDOR_ENHANCED_STROBE BIT(0)
+
+/* DWC IP vendor area 1 pointer */
+#define DWCMSHC_P_VENDOR_AREA1 0xe8
+#define DWCMSHC_AREA1_MASK GENMASK(11, 0)
/* Rockchip specific Registers */
#define DWCMSHC_CTRL_HS400 0x7
#define DWCMSHC_CARD_IS_EMMC BIT(0)
@@ -46,6 +52,7 @@
#define DWCMSHC_HOST_CTRL3 0x508
#define DWCMSHC_EMMC_CONTROL 0x52c
+#define DWCMSHC_EMMC_ATCTRL 0x540
#define DWCMSHC_EMMC_DLL_CTRL 0x800
#define DWCMSHC_EMMC_DLL_CTRL_RESET BIT(1)
#define DWCMSHC_EMMC_DLL_RXCLK 0x804
@@ -55,25 +62,31 @@
#define DWCMSHC_EMMC_DLL_STATUS0 0x840
#define DWCMSHC_EMMC_DLL_STATUS1 0x844
#define DWCMSHC_EMMC_DLL_START BIT(0)
-#define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29
#define DWCMSHC_EMMC_DLL_START_POINT 16
#define DWCMSHC_EMMC_DLL_START_DEFAULT 5
#define DWCMSHC_EMMC_DLL_INC_VALUE 2
#define DWCMSHC_EMMC_DLL_INC 8
+#define DWCMSHC_EMMC_DLL_BYPASS BIT(24)
#define DWCMSHC_EMMC_DLL_DLYENA BIT(27)
#define DLL_TXCLK_TAPNUM_DEFAULT 0x10
-#define DLL_TXCLK_TAPNUM_90_DEGREES 0x8
-#define DLL_STRBIN_TAPNUM_DEFAULT 0x3
+#define DLL_TXCLK_TAPNUM_90_DEGREES 0x9
+#define DLL_STRBIN_TAPNUM_DEFAULT 0x4
+#define DLL_STRBIN_DELAY_NUM_OFFSET 16
+#define DLL_STRBIN_TAPNUM_FROM_SW BIT(24)
+#define DLL_STRBIN_DELAY_NUM_SEL BIT(26)
#define DLL_TXCLK_TAPNUM_FROM_SW BIT(24)
#define DLL_TXCLK_NO_INVERTER BIT(29)
#define DWCMSHC_EMMC_DLL_LOCKED BIT(8)
#define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9)
-#define DLL_RXCLK_NO_INVERTER 1
-#define DLL_RXCLK_INVERTER 0
+#define DLL_TAP_VALUE_SEL BIT(25)
+#define DLL_TAP_VALUE_OFFSET 8
+#define DLL_RXCLK_NO_INVERTER BIT(29)
+#define DLL_RXCLK_ORI_GATE BIT(31)
#define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8
#define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24)
#define DLL_CMDOUT_SRC_CLK_NEG BIT(28)
#define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29)
+#define DLL_CMDOUT_BOTH_CLK_EDGE BIT(30)
#define DWCMSHC_ENHANCED_STROBE BIT(8)
#define DLL_LOCK_WO_TMOUT(x) \
@@ -106,10 +119,18 @@
struct sdhci_data {
int (*emmc_set_clock)(struct sdhci_host *host, unsigned int clock);
void (*set_ios_post)(struct sdhci_host *host);
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
int (*get_phy)(struct udevice *dev);
u32 flags;
#define RK_DLL_CMD_OUT BIT(1)
#define RK_RXCLK_NO_INVERTER BIT(2)
+#define RK_TAP_VALUE_SEL BIT(3)
+
+ u8 hs200_tx_tap;
+ u8 hs400_tx_tap;
+ u8 hs400_cmd_tap;
+ u8 hs400_strbin_tap;
+ u8 ddr50_strbin_delay_num;
};
static void rk3399_emmc_phy_power_on(struct rockchip_emmc_phy *phy, u32 clock)
@@ -254,21 +275,7 @@
clk |= SDHCI_CLOCK_INT_EN;
sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
- /* Wait max 20 ms */
- timeout = 20;
- while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
- & SDHCI_CLOCK_INT_STABLE)) {
- if (timeout == 0) {
- printf("%s: Internal clock never stabilised.\n",
- __func__);
- return -EBUSY;
- }
- timeout--;
- udelay(1000);
- }
- clk |= SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
- host->clock = clock;
+ sdhci_enable_clk(host, clk);
return 0;
}
@@ -323,16 +330,24 @@
{
struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
- u32 extra;
+ u32 txclk_tapnum, extra, dll_lock_value;
int timeout = 500, ret;
ret = rockchip_emmc_set_clock(host, clock);
+
+ /* Disable output clock while config DLL */
+ sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock >= 100 * MHz) {
/* reset DLL */
sdhci_writel(host, DWCMSHC_EMMC_DLL_CTRL_RESET, DWCMSHC_EMMC_DLL_CTRL);
udelay(1);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+
+ extra = 0x1 << 16 | /* tune clock stop en */
+ 0x2 << 17 | /* pre-change delay */
+ 0x3 << 19; /* post-change delay */
+ sdhci_writel(host, extra, DWCMSHC_EMMC_ATCTRL);
/* Init DLL settings */
extra = DWCMSHC_EMMC_DLL_START_DEFAULT << DWCMSHC_EMMC_DLL_START_POINT |
@@ -341,48 +356,106 @@
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL);
while (1) {
- if (timeout < 0)
- return -ETIMEDOUT;
+ if (timeout < 0) {
+ ret = -ETIMEDOUT;
+ goto exit;
+ }
if (DLL_LOCK_WO_TMOUT((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0))))
break;
udelay(1);
timeout--;
}
- extra = DWCMSHC_EMMC_DLL_DLYENA;
+ dll_lock_value = ((sdhci_readl(host, DWCMSHC_EMMC_DLL_STATUS0) & 0xFF) * 2 ) & 0xFF;
+ extra = DWCMSHC_EMMC_DLL_DLYENA | DLL_RXCLK_ORI_GATE;
if (data->flags & RK_RXCLK_NO_INVERTER)
- extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL;
+ extra |= DLL_RXCLK_NO_INVERTER;
+ if (data->flags & RK_TAP_VALUE_SEL)
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK);
+
+ txclk_tapnum = data->hs200_tx_tap;
+ if ((data->flags & RK_DLL_CMD_OUT) &&
+ (host->mmc->timing == MMC_TIMING_MMC_HS400 ||
+ host->mmc->timing == MMC_TIMING_MMC_HS400ES)) {
+ txclk_tapnum = data->hs400_tx_tap;
+
+ extra = DLL_CMDOUT_SRC_CLK_NEG |
+ DLL_CMDOUT_BOTH_CLK_EDGE |
+ DWCMSHC_EMMC_DLL_DLYENA |
+ data->hs400_cmd_tap |
+ DLL_CMDOUT_TAPNUM_FROM_SW;
+ if (data->flags & RK_TAP_VALUE_SEL)
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
+ sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
+ }
extra = DWCMSHC_EMMC_DLL_DLYENA |
DLL_TXCLK_TAPNUM_FROM_SW |
DLL_TXCLK_NO_INVERTER|
- DLL_TXCLK_TAPNUM_DEFAULT;
-
+ txclk_tapnum;
+ if (data->flags & RK_TAP_VALUE_SEL)
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_STRBIN_TAPNUM_DEFAULT;
+ data->hs400_strbin_tap |
+ DLL_STRBIN_TAPNUM_FROM_SW;
+ if (data->flags & RK_TAP_VALUE_SEL)
+ extra |= DLL_TAP_VALUE_SEL | (dll_lock_value << DLL_TAP_VALUE_OFFSET);
sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
} else {
+ /* disable dll */
+ sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
+
/* Disable cmd conflict check */
extra = sdhci_readl(host, DWCMSHC_HOST_CTRL3);
extra &= ~BIT(0);
sdhci_writel(host, extra, DWCMSHC_HOST_CTRL3);
/* reset the clock phase when the frequency is lower than 100MHz */
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_CTRL);
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_RXCLK);
+ sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL);
+ sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK);
sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK);
- sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN);
sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT);
+ /*
+ * Before switching to hs400es mode, the driver will enable
+ * enhanced strobe first. PHY needs to configure the parameters
+ * of enhanced strobe first.
+ */
+ extra = DWCMSHC_EMMC_DLL_DLYENA |
+ DLL_STRBIN_DELAY_NUM_SEL |
+ data->ddr50_strbin_delay_num << DLL_STRBIN_DELAY_NUM_OFFSET;
+ sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN);
}
+
+exit:
+ /* enable output clock */
+ sdhci_enable_clk(host, 0);
+
return ret;
+}
+
+static int dwcmshc_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+ struct mmc *mmc = host->mmc;
+ u32 vendor;
+
+ vendor = sdhci_readl(host, DWCMSHC_EMMC_CONTROL);
+ if (mmc->timing == MMC_TIMING_MMC_HS400ES)
+ vendor |= DWCMSHC_ENHANCED_STROBE;
+ else
+ vendor &= ~DWCMSHC_ENHANCED_STROBE;
+ sdhci_writel(host, vendor, DWCMSHC_EMMC_CONTROL);
+
+ /* some emmc device need a delay before send command */
+ udelay(100);
+
+ return 0;
}
static void dwcmshc_sdhci_set_ios_post(struct sdhci_host *host)
{
u16 ctrl;
- u32 extra;
u32 timing = host->mmc->timing;
if (timing == MMC_TIMING_MMC_HS400 || timing == MMC_TIMING_MMC_HS400ES) {
@@ -395,16 +468,6 @@
ctrl = sdhci_readw(host, DWCMSHC_EMMC_CONTROL);
ctrl |= DWCMSHC_CARD_IS_EMMC;
sdhci_writew(host, ctrl, DWCMSHC_EMMC_CONTROL);
-
- extra = DLL_CMDOUT_SRC_CLK_NEG |
- DLL_CMDOUT_EN_SRC_CLK_NEG;
- sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT);
-
- extra = DWCMSHC_EMMC_DLL_DLYENA |
- DLL_TXCLK_TAPNUM_FROM_SW |
- DLL_TXCLK_NO_INVERTER|
- DLL_TXCLK_TAPNUM_90_DEGREES;
- sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK);
}
}
@@ -434,9 +497,21 @@
data->set_ios_post(host);
}
+static int rockchip_sdhci_set_enhanced_strobe(struct sdhci_host *host)
+{
+ struct rockchip_sdhc *priv = container_of(host, struct rockchip_sdhc, host);
+ struct sdhci_data *data = (struct sdhci_data *)dev_get_driver_data(priv->dev);
+
+ if (data->set_enhanced_strobe)
+ return data->set_enhanced_strobe(host);
+
+ return -ENOTSUPP;
+}
+
static struct sdhci_ops rockchip_sdhci_ops = {
.set_clock = rockchip_sdhci_set_clock,
.set_ios_post = rockchip_sdhci_set_ios_post,
+ .set_enhanced_strobe = rockchip_sdhci_set_enhanced_strobe,
};
static int rockchip_sdhci_probe(struct udevice *dev)
@@ -496,7 +571,13 @@
host->host_caps |= MMC_MODE_HS200;
else if (dev_read_bool(dev, "mmc-hs400-1_8v"))
host->host_caps |= MMC_MODE_HS400;
+
+ if (data->set_enhanced_strobe && dev_read_bool(dev, "mmc-hs400-enhanced-strobe"))
+ host->host_caps |= MMC_MODE_HS400ES;
+
ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ);
+
+ plat->cfg.fixed_drv_type = dev_read_u32_default(dev, "fixed-emmc-driver-type", 0);
host->mmc = &plat->mmc;
if (ret)
@@ -536,13 +617,50 @@
.emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
.get_phy = dwcmshc_emmc_get_phy,
.flags = RK_RXCLK_NO_INVERTER,
+ .hs200_tx_tap = 16,
+ .hs400_tx_tap = 8,
+ .hs400_cmd_tap = 8,
+ .hs400_strbin_tap = 3,
+ .ddr50_strbin_delay_num = 16,
};
static const struct sdhci_data rk3588_data = {
.emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
.get_phy = dwcmshc_emmc_get_phy,
.set_ios_post = dwcmshc_sdhci_set_ios_post,
- .flags = RK_DLL_CMD_OUT | RK_RXCLK_NO_INVERTER,
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
+ .flags = RK_DLL_CMD_OUT,
+ .hs200_tx_tap = 16,
+ .hs400_tx_tap = 9,
+ .hs400_cmd_tap = 8,
+ .hs400_strbin_tap = 3,
+ .ddr50_strbin_delay_num = 16,
+};
+
+static const struct sdhci_data rk3528_data = {
+ .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
+ .get_phy = dwcmshc_emmc_get_phy,
+ .set_ios_post = dwcmshc_sdhci_set_ios_post,
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
+ .flags = RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
+ .hs200_tx_tap = 12,
+ .hs400_tx_tap = 6,
+ .hs400_cmd_tap = 6,
+ .hs400_strbin_tap = 3,
+ .ddr50_strbin_delay_num = 10,
+};
+
+static const struct sdhci_data rk3562_data = {
+ .emmc_set_clock = dwcmshc_sdhci_emmc_set_clock,
+ .get_phy = dwcmshc_emmc_get_phy,
+ .set_ios_post = dwcmshc_sdhci_set_ios_post,
+ .set_enhanced_strobe = dwcmshc_sdhci_set_enhanced_strobe,
+ .flags = RK_DLL_CMD_OUT | RK_TAP_VALUE_SEL,
+ .hs200_tx_tap = 12,
+ .hs400_tx_tap = 6,
+ .hs400_cmd_tap = 6,
+ .hs400_strbin_tap = 3,
+ .ddr50_strbin_delay_num = 10,
};
static const struct udevice_id sdhci_ids[] = {
@@ -555,6 +673,14 @@
.data = (ulong)&rk3568_data,
},
{
+ .compatible = "rockchip,rk3528-dwcmshc",
+ .data = (ulong)&rk3528_data,
+ },
+ {
+ .compatible = "rockchip,rk3562-dwcmshc",
+ .data = (ulong)&rk3562_data,
+ },
+ {
.compatible = "rockchip,rk3588-dwcmshc",
.data = (ulong)&rk3588_data,
},
diff --git a/u-boot/drivers/mmc/sdhci.c b/u-boot/drivers/mmc/sdhci.c
index 8c2a9a6..a02baa5 100644
--- a/u-boot/drivers/mmc/sdhci.c
+++ b/u-boot/drivers/mmc/sdhci.c
@@ -178,6 +178,7 @@
} else {
puts("timeout.\n");
/* remove timeout return error and try to send command */
+ break;
}
}
time++;
@@ -313,6 +314,29 @@
return -ECOMM;
}
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk)
+{
+ unsigned int timeout;
+
+ clk |= SDHCI_CLOCK_INT_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Wait max 20 ms */
+ timeout = 20;
+ while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
+ printf("%s: Internal clock never stabilised.\n",
+ __func__);
+ return;
+ }
+ timeout--;
+ udelay(1000);
+ }
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+}
+
int sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
unsigned int div, clk = 0, timeout;
@@ -379,23 +403,8 @@
clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
- clk |= SDHCI_CLOCK_INT_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
- /* Wait max 20 ms */
- timeout = 20;
- while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
- & SDHCI_CLOCK_INT_STABLE)) {
- if (timeout == 0) {
- printf("%s: Internal clock never stabilised.\n",
- __func__);
- return -EBUSY;
- }
- timeout--;
- udelay(1000);
- }
- clk |= SDHCI_CLOCK_CARD_EN;
- sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+ sdhci_enable_clk(host, clk);
host->clock = clock;
return 0;
@@ -681,11 +690,23 @@
return sdhci_init(mmc);
}
+static int sdhci_set_enhanced_strobe(struct udevice *dev)
+{
+ struct mmc *mmc = mmc_get_mmc_dev(dev);
+ struct sdhci_host *host = mmc->priv;
+
+ if (host->ops && host->ops->set_enhanced_strobe)
+ return host->ops->set_enhanced_strobe(host);
+
+ return -ENOTSUPP;
+}
+
const struct dm_mmc_ops sdhci_ops = {
.card_busy = sdhci_card_busy,
.send_cmd = sdhci_send_command,
.set_ios = sdhci_set_ios,
.execute_tuning = sdhci_execute_tuning,
+ .set_enhanced_strobe = sdhci_set_enhanced_strobe,
};
#else
static const struct mmc_ops sdhci_ops = {
diff --git a/u-boot/drivers/mtd/mtd_blk.c b/u-boot/drivers/mtd/mtd_blk.c
index a8226d7..1ac6f81 100644
--- a/u-boot/drivers/mtd/mtd_blk.c
+++ b/u-boot/drivers/mtd/mtd_blk.c
@@ -22,9 +22,6 @@
#endif
#define MTD_PART_NAND_HEAD "mtdparts="
-#define MTD_ROOT_PART_NUM "ubi.mtd="
-#define MTD_ROOT_PART_NAME_UBIFS "root=ubi0:rootfs"
-#define MTD_ROOT_PART_NAME_SQUASHFS "root=/dev/ubiblock0_0"
#define MTD_PART_INFO_MAX_SIZE 512
#define MTD_SINGLE_PART_INFO_MAX_SIZE 40
@@ -371,20 +368,7 @@
mtd = (struct mtd_info *)dev_desc->bdev->priv;
if (!mtd)
return NULL;
-#ifndef CONFIG_SPL_BUILD
- char mtd_root_part_info[40] = {0};
- p = part_get_info_by_name(dev_desc, PART_SYSTEM, &info);
- if (p > 0) {
- if (strstr(env_get("bootargs"), "rootfstype=squashfs"))
- snprintf(mtd_root_part_info, ARRAY_SIZE(mtd_root_part_info), "%s%d %s",
- MTD_ROOT_PART_NUM, p - 1, MTD_ROOT_PART_NAME_SQUASHFS);
- else
- snprintf(mtd_root_part_info, ARRAY_SIZE(mtd_root_part_info), "%s%d %s",
- MTD_ROOT_PART_NUM, p - 1, MTD_ROOT_PART_NAME_UBIFS);
- env_update("bootargs", mtd_root_part_info);
- }
-#endif
mtd_part_info = (char *)calloc(MTD_PART_INFO_MAX_SIZE, sizeof(char));
if (!mtd_part_info) {
printf("%s: Fail to malloc!", __func__);
diff --git a/u-boot/drivers/mtd/nand/spi/Kconfig b/u-boot/drivers/mtd/nand/spi/Kconfig
index e599bb2..b6a4f99 100644
--- a/u-boot/drivers/mtd/nand/spi/Kconfig
+++ b/u-boot/drivers/mtd/nand/spi/Kconfig
@@ -52,6 +52,12 @@
help
Add support for various ESMT SPI Nand flash chips
+config SPI_NAND_XINCUN
+ bool "XINCUN SPI flash support"
+ default y
+ help
+ Add support for various XINCUN SPI Nand flash chips
+
config SPI_NAND_XTX
bool "XTX SPI flash support"
default y
@@ -112,4 +118,10 @@
bool "SKYHIGH SPI flash support"
help
Add support for various SKYHIGH SPI Nand flash chips
+
+config SPI_NAND_GSTO
+ default y
+ bool "GSTO SPI flash support"
+ help
+ Add support for various GSTO SPI Nand flash chips
endif
diff --git a/u-boot/drivers/mtd/nand/spi/Makefile b/u-boot/drivers/mtd/nand/spi/Makefile
index eaa587d..d60139d 100644
--- a/u-boot/drivers/mtd/nand/spi/Makefile
+++ b/u-boot/drivers/mtd/nand/spi/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_SPI_NAND_WINBOND) += winbond.o
obj-$(CONFIG_SPI_NAND_DOSILICON) += dosilicon.o
obj-$(CONFIG_SPI_NAND_ESMT) += esmt.o
+obj-$(CONFIG_SPI_NAND_XINCUN) += xincun.o
obj-$(CONFIG_SPI_NAND_XTX) += xtx.o
obj-$(CONFIG_SPI_NAND_HYF) += hyf.o
obj-$(CONFIG_SPI_NAND_FMSH) += fmsh.o
@@ -18,4 +19,5 @@
obj-$(CONFIG_SPI_NAND_SILICONGO) += silicongo.o
obj-$(CONFIG_SPI_NAND_UNIM) += unim.o
obj-$(CONFIG_SPI_NAND_SKYHIGH) += skyhigh.o
+obj-$(CONFIG_SPI_NAND_GSTO) += gsto.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/u-boot/drivers/mtd/nand/spi/core.c b/u-boot/drivers/mtd/nand/spi/core.c
index f83698f..4dae186 100644
--- a/u-boot/drivers/mtd/nand/spi/core.c
+++ b/u-boot/drivers/mtd/nand/spi/core.c
@@ -510,7 +510,7 @@
const struct nand_page_io_req *req,
bool ecc_enabled)
{
- u8 status;
+ u8 status = 0;
int ret;
ret = spinand_load_page_op(spinand, req);
@@ -518,6 +518,12 @@
return ret;
ret = spinand_wait(spinand, &status);
+ /*
+ * When there is data outside of OIP in the status, the status data is
+ * inaccurate and needs to be reconfirmed
+ */
+ if (spinand->id.data[0] == 0x01 && status && !ret)
+ ret = spinand_wait(spinand, &status);
if (ret < 0)
return ret;
@@ -837,6 +843,9 @@
#ifdef CONFIG_SPI_NAND_ESMT
&esmt_spinand_manufacturer,
#endif
+#ifdef CONFIG_SPI_NAND_XINCUN
+ &xincun_spinand_manufacturer,
+#endif
#ifdef CONFIG_SPI_NAND_XTX
&xtx_spinand_manufacturer,
#endif
@@ -867,6 +876,9 @@
#ifdef CONFIG_SPI_NAND_SKYHIGH
&skyhigh_spinand_manufacturer,
#endif
+#ifdef CONFIG_SPI_NAND_GSTO
+ &gsto_spinand_manufacturer,
+#endif
};
static int spinand_manufacturer_match(struct spinand_device *spinand,
diff --git a/u-boot/drivers/mtd/nand/spi/dosilicon.c b/u-boot/drivers/mtd/nand/spi/dosilicon.c
index fc87add..8a82134 100644
--- a/u-boot/drivers/mtd/nand/spi/dosilicon.c
+++ b/u-boot/drivers/mtd/nand/spi/dosilicon.c
@@ -14,7 +14,7 @@
#define SPINAND_MFR_DOSILICON 0xE5
-#define DOSICON_STATUS_ECC_MASK GENMASK(7, 4)
+#define DOSICON_STATUS_ECC_MASK GENMASK(6, 4)
#define DOSICON_STATUS_ECC_NO_BITFLIPS (0 << 4)
#define DOSICON_STATUS_ECC_1TO3_BITFLIPS (1 << 4)
#define DOSICON_STATUS_ECC_4TO6_BITFLIPS (3 << 4)
@@ -198,6 +198,26 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&ds35xxgb_ooblayout,
ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35Q12B",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xF5),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
+ SPINAND_INFO("DS35M12B",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
+ NAND_MEMORG(1, 2048, 128, 64, 512, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ds35xxgb_ooblayout,
+ ds35xxgb_ecc_get_status)),
};
static const struct spinand_manufacturer_ops dosilicon_spinand_manuf_ops = {
diff --git a/u-boot/drivers/mtd/nand/spi/fmsh.c b/u-boot/drivers/mtd/nand/spi/fmsh.c
index c65ff64..340edf0 100644
--- a/u-boot/drivers/mtd/nand/spi/fmsh.c
+++ b/u-boot/drivers/mtd/nand/spi/fmsh.c
@@ -82,6 +82,31 @@
.rfree = fm25s01_ooblayout_free,
};
+/*
+ * ecc bits: 0xC0[4,6]
+ * [0b000], No bit errors were detected;
+ * [0b001] and [0b011], 1~6 Bit errors were detected and corrected. Not
+ * reach Flipping Bits;
+ * [0b101], Bit error count equals the bit flip
+ * detection threshold
+ * [0b010], Multiple bit errors were detected and
+ * not corrected.
+ * others, Reserved.
+ */
+static int fm25s01bi3_ecc_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
+
+ if (eccsr <= 1 || eccsr == 3)
+ return eccsr;
+ else if (eccsr == 5)
+ return nand->eccreq.strength;
+ else
+ return -EBADMSG;
+}
+
static const struct spinand_info fmsh_spinand_table[] = {
SPINAND_INFO("FM25S01A",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xE4),
@@ -99,11 +124,11 @@
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 1,
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fm25s01a_ooblayout, NULL)),
SPINAND_INFO("FM25S01",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA1),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
@@ -112,13 +137,22 @@
SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
SPINAND_INFO("FM25LS01",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xA5),
- NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(1, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
0,
SPINAND_ECCINFO(&fm25s01_ooblayout, NULL)),
+ SPINAND_INFO("FM25S01BI3",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xD4),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fm25s01_ooblayout, fm25s01bi3_ecc_ecc_get_status)),
};
static const struct spinand_manufacturer_ops fmsh_spinand_manuf_ops = {
diff --git a/u-boot/drivers/mtd/nand/spi/foresee.c b/u-boot/drivers/mtd/nand/spi/foresee.c
index a67931f..5b3286e 100644
--- a/u-boot/drivers/mtd/nand/spi/foresee.c
+++ b/u-boot/drivers/mtd/nand/spi/foresee.c
@@ -28,7 +28,7 @@
static SPINAND_OP_VARIANTS(update_cache_variants,
SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int fsxxndxxg_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
@@ -117,6 +117,24 @@
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
+ SPINAND_INFO("F35UQA002G-WWT",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x62),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
+ SPINAND_INFO("F35UQA001G-WWT",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x61),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&fsxxndxxg_ooblayout, NULL)),
};
static const struct spinand_manufacturer_ops foresee_spinand_manuf_ops = {
diff --git a/u-boot/drivers/mtd/nand/spi/gigadevice.c b/u-boot/drivers/mtd/nand/spi/gigadevice.c
index 704ad55..ba67f1d 100644
--- a/u-boot/drivers/mtd/nand/spi/gigadevice.c
+++ b/u-boot/drivers/mtd/nand/spi/gigadevice.c
@@ -43,6 +43,22 @@
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0));
+static SPINAND_OP_VARIANTS(read_cache_variants_1gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
static SPINAND_OP_VARIANTS(write_cache_variants,
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
SPINAND_PROG_LOAD(true, 0, NULL, 0));
@@ -353,6 +369,36 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc1),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ4RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xc2),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UFxxG",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
@@ -373,36 +419,116 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F2GQ5UExxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52),
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ SPINAND_INFO("GD5F1GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x41),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq5xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F2GQ4UBxxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd2),
+ SPINAND_INFO("GD5F2GQ5UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GQ5RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GQ6RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 2, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq5xexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x91),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F1GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x81),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x92),
NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq4xa_ecc_get_status)),
- SPINAND_INFO("GD5F4GQ6UExxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55),
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F2GM7RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x82),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8UExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x95),
NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
- NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq5xexxg_ecc_get_status)),
+ gd5fxgq4uexxg_ecc_get_status)),
+ SPINAND_INFO("GD5F4GM8RExxG",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x85),
+ NAND_MEMORG(1, 2048, 128, 64, 4096, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+ gd5fxgq4uexxg_ecc_get_status)),
SPINAND_INFO("GD5F1GQ4UExxH",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd9),
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
@@ -412,56 +538,6 @@
&update_cache_variants),
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5fxgqx_variant3_ooblayout,
- gd5fxgq4xa_ecc_get_status)),
- SPINAND_INFO("GD5F1GQ5RExxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41),
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq5xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F2GQ5RExxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x42),
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- NAND_ECCREQ(4, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq5xexxg_ecc_get_status)),
- SPINAND_INFO("GD5F2GM7RxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82),
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq4xa_ecc_get_status)),
- SPINAND_INFO("GD5F1GM7UxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91),
- NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
- gd5fxgq4xa_ecc_get_status)),
- SPINAND_INFO("GD5F2GM7UxG",
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92),
- NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
- NAND_ECCREQ(8, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
- &write_cache_variants,
- &update_cache_variants),
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
gd5fxgq4xa_ecc_get_status)),
};
diff --git a/u-boot/drivers/mtd/nand/spi/gsto.c b/u-boot/drivers/mtd/nand/spi/gsto.c
new file mode 100644
index 0000000..a197c6c
--- /dev/null
+++ b/u-boot/drivers/mtd/nand/spi/gsto.c
@@ -0,0 +1,92 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2023 Rockchip Electronics Co., Ltd
+ *
+ * Authors:
+ * Dingqiang Lin <jon.lin@rock-chips.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_GSTO 0x52
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int gss0xgsak1_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 32;
+ region->length = 32;
+
+ return 0;
+}
+
+static int gss0xgsak1_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 2;
+ region->length = 30;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gss0xgsak1_ooblayout = {
+ .ecc = gss0xgsak1_ooblayout_ecc,
+ .rfree = gss0xgsak1_ooblayout_free,
+};
+
+static const struct spinand_info gsto_spinand_table[] = {
+ SPINAND_INFO("GSS01GSAK1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x13),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
+ SPINAND_INFO("GSS02GSAK1",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xBA, 0x23),
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&gss0xgsak1_ooblayout, NULL)),
+};
+
+static const struct spinand_manufacturer_ops gsto_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer gsto_spinand_manufacturer = {
+ .id = SPINAND_MFR_GSTO,
+ .name = "GSTO",
+ .chips = gsto_spinand_table,
+ .nchips = ARRAY_SIZE(gsto_spinand_table),
+ .ops = &gsto_spinand_manuf_ops,
+};
diff --git a/u-boot/drivers/mtd/nand/spi/hyf.c b/u-boot/drivers/mtd/nand/spi/hyf.c
index 1c95298..3a60296 100644
--- a/u-boot/drivers/mtd/nand/spi/hyf.c
+++ b/u-boot/drivers/mtd/nand/spi/hyf.c
@@ -106,7 +106,7 @@
if (section > 3)
return -ERANGE;
- region->offset = 16 * section;
+ region->offset = 32 * section;
region->length = 8;
return 0;
@@ -199,6 +199,26 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
hyf1gq4udacae_ecc_get_status)),
+ SPINAND_INFO("HYF2GQ4IAACAE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x82),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(14, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&hyf2gq4uaacae_ooblayout,
+ hyf1gq4udacae_ecc_get_status)),
+ SPINAND_INFO("HYF1GQ4IDACAE",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x81),
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&hyf1gq4udacae_ooblayout,
+ hyf1gq4udacae_ecc_get_status)),
};
static const struct spinand_manufacturer_ops hyf_spinand_manuf_ops = {
diff --git a/u-boot/drivers/mtd/nand/spi/jsc.c b/u-boot/drivers/mtd/nand/spi/jsc.c
index d0e3b24..d3f7e56 100644
--- a/u-boot/drivers/mtd/nand/spi/jsc.c
+++ b/u-boot/drivers/mtd/nand/spi/jsc.c
@@ -72,12 +72,13 @@
static int js28u1gqscahg_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
- u8 eccsr = (status & GENMASK(6, 4)) >> 2;
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
- if (eccsr <= 7)
+ if (eccsr < 4)
return eccsr;
- else if (eccsr == 12)
- return 8;
+ else if (eccsr == 4)
+ return nand->eccreq.strength;
else
return -EBADMSG;
}
diff --git a/u-boot/drivers/mtd/nand/spi/skyhigh.c b/u-boot/drivers/mtd/nand/spi/skyhigh.c
index 252382e..7cf58c6 100644
--- a/u-boot/drivers/mtd/nand/spi/skyhigh.c
+++ b/u-boot/drivers/mtd/nand/spi/skyhigh.c
@@ -14,6 +14,10 @@
#define SPINAND_MFR_SKYHIGH 0x01
+#define SKYHIGH_STATUS_ECC_1_2_BITFLIPS (1 << 4)
+#define SKYHIGH_STATUS_ECC_3_4_BITFLIPS (2 << 4)
+#define SKYHIGH_STATUS_ECC_UNCOR_ERROR (3 << 4)
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -27,8 +31,8 @@
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
- SPINAND_PROG_LOAD(false, 0, NULL, 0));
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
static int s35ml04g3_ooblayout_ecc(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
@@ -53,7 +57,48 @@
.rfree = s35ml04g3_ooblayout_free,
};
+
+static int s35ml0xg3_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case SKYHIGH_STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case SKYHIGH_STATUS_ECC_1_2_BITFLIPS:
+ return 2;
+
+ default:
+ return nand->eccreq.strength;
+ }
+
+ return -EINVAL;
+}
+
static const struct spinand_info skyhigh_spinand_table[] = {
+ SPINAND_INFO("S35ML01G3",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
+ SPINAND_INFO("S35ML02G3",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
SPINAND_INFO("S35ML04G3",
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
NAND_MEMORG(1, 2048, 128, 64, 4096, 2, 1, 1),
@@ -62,7 +107,7 @@
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&s35ml04g3_ooblayout, NULL)),
+ SPINAND_ECCINFO(&s35ml04g3_ooblayout, s35ml0xg3_ecc_get_status)),
};
static const struct spinand_manufacturer_ops skyhigh_spinand_manuf_ops = {
diff --git a/u-boot/drivers/mtd/nand/spi/unim.c b/u-boot/drivers/mtd/nand/spi/unim.c
index 8dd0b9b..b4e3e5b 100644
--- a/u-boot/drivers/mtd/nand/spi/unim.c
+++ b/u-boot/drivers/mtd/nand/spi/unim.c
@@ -71,12 +71,13 @@
static int tx25g01_ecc_get_status(struct spinand_device *spinand,
u8 status)
{
- u8 eccsr = (status & GENMASK(6, 4)) >> 2;
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr = (status & GENMASK(6, 4)) >> 4;
- if (eccsr <= 7)
+ if (eccsr < 4)
return eccsr;
- else if (eccsr == 12)
- return 8;
+ else if (eccsr == 4)
+ return nand->eccreq.strength;
else
return -EBADMSG;
}
diff --git a/u-boot/drivers/mtd/nand/spi/xincun.c b/u-boot/drivers/mtd/nand/spi/xincun.c
new file mode 100644
index 0000000..dc6334d
--- /dev/null
+++ b/u-boot/drivers/mtd/nand/spi/xincun.c
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd
+ *
+ * Authors:
+ * Dingqiang Lin <jon.lin@rock-chips.com>
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_XINCUN 0x8C
+#define XINCUN_STATUS_ECC_HAS_BITFLIPS_T (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int xcsp2aapk_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = mtd->oobsize / 2;
+ region->length = mtd->oobsize / 2;
+
+ return 0;
+}
+
+static int xcsp2aapk_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = mtd->oobsize / 2 - 2;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops xcsp2aapk_ooblayout = {
+ .ecc = xcsp2aapk_ooblayout_ecc,
+ .rfree = xcsp2aapk_ooblayout_free,
+};
+
+static int xcsp2aapk_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return 0;
+ case XINCUN_STATUS_ECC_HAS_BITFLIPS_T:
+ return nand->eccreq.strength;
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info xincun_spinand_table[] = {
+ SPINAND_INFO("XCSP2AAPK",
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xA1),
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&xcsp2aapk_ooblayout, xcsp2aapk_ecc_get_status)),
+};
+
+static const struct spinand_manufacturer_ops xincun_spinand_manuf_ops = {
+};
+
+const struct spinand_manufacturer xincun_spinand_manufacturer = {
+ .id = SPINAND_MFR_XINCUN,
+ .name = "XINCUN",
+ .chips = xincun_spinand_table,
+ .nchips = ARRAY_SIZE(xincun_spinand_table),
+ .ops = &xincun_spinand_manuf_ops,
+};
diff --git a/u-boot/drivers/mtd/spi/sf_internal.h b/u-boot/drivers/mtd/spi/sf_internal.h
index 19b5c7d..7de3035 100644
--- a/u-boot/drivers/mtd/spi/sf_internal.h
+++ b/u-boot/drivers/mtd/spi/sf_internal.h
@@ -68,6 +68,7 @@
#define USE_CLSR BIT(14) /* use CLSR command */
#define SPI_NOR_HAS_SST26LOCK BIT(15) /* Flash supports lock/unlock via BPR */
#define SPI_NOR_OCTAL_READ BIT(16) /* Flash supports Octal Read */
+#define SPI_NOR_OCTAL_DTR_READ BIT(17) /* Flash supports Octal DTR Read */
};
extern const struct flash_info spi_nor_ids[];
diff --git a/u-boot/drivers/mtd/spi/spi-nor-ids.c b/u-boot/drivers/mtd/spi/spi-nor-ids.c
index 8d1784c..8be74f3 100644
--- a/u-boot/drivers/mtd/spi/spi-nor-ids.c
+++ b/u-boot/drivers/mtd/spi/spi-nor-ids.c
@@ -85,6 +85,9 @@
{ INFO("en25qh64", 0x1c7017, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K) },
{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("en25qh256a", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("en25qx256a", 0x1c7119, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("en25qx128a", 0x1c7118, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
/* GigaDevice */
@@ -118,28 +121,18 @@
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
- {
- INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_HAS_TB)
- },
- { INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
- SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
- SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
- SPI_NOR_HAS_TB)
- },
{ INFO("gd25q512", 0xc84020, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK |
SPI_NOR_HAS_TB)
},
{
- INFO("gd25lq255", 0xc86019, 0, 64 * 1024, 512,
+ INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
},
{
- INFO("gd25lb512m", 0xc8671a, 0, 64 * 1024, 1024,
+ INFO("gd55lb01ge", 0xc8671b, 0, 64 * 1024, 2048,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
},
@@ -148,17 +141,112 @@
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
},
+ {
+ INFO("gd55b01ge", 0xc8471b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_4B_OPCODES | SPI_NOR_HAS_LOCK)
+ },
+ /* adding these 3V QSPI flash parts */
+ {INFO("gd25b256", 0xc84019, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES) },
+ {INFO("gd25b512", 0xc8471A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b01g", 0xc8471B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55b02g", 0xc8471C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25f64", 0xc84317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f128", 0xc84318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25f256", 0xc84319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55f512", 0xc8431A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25t512", 0xc8461A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t01g", 0xc8461B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55t02g", 0xc8461C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ /* adding these 3V OSPI flash parts */
+ {INFO("gd25x512", 0xc8481A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x01g", 0xc8481B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {
+ INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("gd25lq256d", 0xc86019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ /* adding these 1.8V QSPI flash parts */
+ {INFO("gd25lb256", 0xc86719, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lb512", 0xc8671A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb01g", 0xc8671B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lb02g", 0xc8671C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf80", 0xc86314, 0, 64 * 1024, 16, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf16", 0xc86315, 0, 64 * 1024, 32, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK)},
+ {INFO("gd25lf32", 0xc86316, 0, 64 * 1024, 64, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf64", 0xc86317, 0, 64 * 1024, 128, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf128", 0xc86318, 0, 64 * 1024, 256, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK) },
+ {INFO("gd25lf255", 0xc86319, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lf511", 0xc8631A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt256", 0xc86619, 0, 64 * 1024, 512, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd25lt512", 0xc8661A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt01g", 0xc8661B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lt02g", 0xc8661C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_4B_OPCODES)},
+ {
+ INFO("gd25lx256e", 0xc86819, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)
+ },
+ /* adding these 1.8V OSPI flash parts */
+ {INFO("gd25lx512", 0xc8681A, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx01g", 0xc8681B, 0, 64 * 1024, 2048, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
+ {INFO("gd55lx02g", 0xc8681C, 0, 64 * 1024, 4096, SECT_4K |
+ SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)},
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
/* ISSI */
{ INFO("is25lq040b", 0x9d4013, 0, 64 * 1024, 8,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp008", 0x9d6014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25lp016", 0x9d6015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25lp032", 0x9d6016, 0, 64 * 1024, 64, 0) },
{ INFO("is25lp064", 0x9d6017, 0, 64 * 1024, 128, 0) },
{ INFO("is25lp128", 0x9d6018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ) },
{ INFO("is25lp256", 0x9d6019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ) },
+ { INFO("is25lp512", 0x9d601a, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25lp01g", 0x9d601b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp008", 0x9d7014, 0, 64 * 1024, 16, SPI_NOR_QUAD_READ) },
+ { INFO("is25wp016", 0x9d7015, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ) },
{ INFO("is25wp032", 0x9d7016, 0, 64 * 1024, 64,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp064", 0x9d7017, 0, 64 * 1024, 128,
@@ -168,6 +256,12 @@
{ INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_4B_OPCODES) },
+ { INFO("is25wp512", 0x9d701a, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp01g", 0x9d701b, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wx256", 0x9d5b19, 0, 128 * 1024, 256,
+ SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
@@ -183,17 +277,41 @@
{ INFO("mx25u6435f", 0xc22537, 0, 64 * 1024, 128, SECT_4K) },
{ INFO("mx25l12805d", 0xc22018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u12835f", 0xc22538, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx25u51245g", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K |
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l12855e", 0xc22618, 0, 64 * 1024, 256, 0) },
{ INFO("mx25l25635e", 0xc22019, 0, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25u25635f", 0xc22539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25v8035f", 0xc22314, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx25r1635f", 0xc22815, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) },
{ INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25u51245f", 0xc2953a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66u1g45g", 0xc2253b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("mx66l2g45g", 0xc2201c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) },
{ INFO("mx25r6435f", 0xc22817, 0, 64 * 1024, 128, SECT_4K) },
- { INFO("mx66uw2g345g", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66uw2g345gx0", 0xc2943c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66lm1g45g", 0xc2853b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25lm51245g", 0xc2853a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25lw51245g", 0xc2863a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25lm25645g", 0xc28539, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66uw2g345g", 0xc2843c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66um1g45g", 0xc2803b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx66uw1g45g", 0xc2813b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw51245g", 0xc2813a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw51345g", 0xc2843a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25um25645g", 0xc28039, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw25645g", 0xc28139, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25um25345g", 0xc28339, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw25345g", 0xc28439, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw12845g", 0xc28138, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw12345g", 0xc28438, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw6445g", 0xc28137, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mx25uw6345g", 0xc28437, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_OCTAL_DTR_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
@@ -210,7 +328,7 @@
{ INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
{ INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
USE_FSR) },
{ INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
@@ -219,7 +337,12 @@
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25ql01g", 0x21ba20, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
- { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("mt25ql02g", 0x20ba22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE | SPI_NOR_4B_OPCODES) },
+#ifdef CONFIG_SPI_FLASH_MT35XU
+ { INFO("mt35xl512aba", 0x2c5a1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+ { INFO("mt35xu512aba", 0x2c5b1a, 0, 128 * 1024, 512, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ) },
+#endif /* CONFIG_SPI_FLASH_MT35XU */
+ { INFO6("mt35xu01g", 0x2c5b1b, 0x104100, 128 * 1024, 1024, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
{ INFO("mt35xu02g", 0x2c5b1c, 0, 128 * 1024, 2048, USE_FSR | SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_SPANSION /* SPANSION */
@@ -235,6 +358,7 @@
{ INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
{ INFO("s25fl512s_512k", 0x010220, 0x4f00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
+ { INFO("s70fs01gs_256k", 0x010221, 0x4d00, 256 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("s25sl12800", 0x012018, 0x0300, 256 * 1024, 64, 0) },
{ INFO("s25sl12801", 0x012018, 0x0301, 64 * 1024, 256, 0) },
{ INFO6("s25fl128s", 0x012018, 0x4d0180, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
@@ -347,6 +471,31 @@
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
},
+ {
+ INFO("w25q512jv", 0xef7119, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q512nwq", 0xef6020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q512nwm", 0xef8020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q512jvq", 0xef4020, 0, 64 * 1024, 1024,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
+ {
+ INFO("w25q01jv", 0xef4021, 0, 64 * 1024, 2048,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
+ },
{ INFO("w25q80", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },
{ INFO("w25q80bl", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25q16cl", 0xef4015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@@ -358,6 +507,7 @@
{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_XMC
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
@@ -376,17 +526,23 @@
/* XTX Technology (Shenzhen) Limited */
{ INFO("xt25f64f", 0x0b4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("xt25f128b", 0x0b4018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("xt25f256b", 0x0b4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("xt25q64d", 0x0b6017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("xt25q128d", 0x0b6018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_PUYA
/* PUYA Semiconductor (Shanghai) Co., Ltd. */
{ INFO("P25Q64H", 0x856017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("P25Q128H", 0x856018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("PY25Q64HA", 0x852017, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("PY25Q128HA", 0x852018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("PY25Q256HB", 0x852019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_FMSH
/* FUDAN MICRO (Shanghai) Co., Ltd. */
{ INFO("FM25Q128A", 0xA14018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("FM25Q64", 0xA14017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("FM25Q256I3", 0xA14019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
#endif
#ifdef CONFIG_SPI_FLASH_DOSILICON
/* Dosilicon Co., Ltd. */
diff --git a/u-boot/drivers/mtd/ubi/debug.h b/u-boot/drivers/mtd/ubi/debug.h
index 215fca7..c4f0bc5 100644
--- a/u-boot/drivers/mtd/ubi/debug.h
+++ b/u-boot/drivers/mtd/ubi/debug.h
@@ -28,13 +28,8 @@
} \
} while (0)
#else
-#define ubi_assert(expr) do { \
- if (unlikely(!(expr))) { \
- pr_debug("UBI assert failed in %s at %u\n", \
- __func__, __LINE__); \
- dump_stack(); \
- } \
-} while (0)
+#include <log.h>
+#define ubi_assert(expr) assert(expr)
#endif
#define ubi_dbg_print_hex_dump(ps, pt, r, g, b, len, a) \
diff --git a/u-boot/drivers/net/gmac_rockchip.c b/u-boot/drivers/net/gmac_rockchip.c
index bc8dcc9..dfb8342 100644
--- a/u-boot/drivers/net/gmac_rockchip.c
+++ b/u-boot/drivers/net/gmac_rockchip.c
@@ -18,6 +18,9 @@
#include <asm/arch/clock.h>
#include <asm/arch/hardware.h>
#ifdef CONFIG_DWC_ETH_QOS
+#include <asm/arch/grf_rk3528.h>
+#include <asm/arch/grf_rk3562.h>
+#include <asm/arch/ioc_rk3562.h>
#include <asm/arch/grf_rk3568.h>
#include <asm/arch/grf_rk3588.h>
#include <asm/arch/grf_rv1106.h>
@@ -516,6 +519,147 @@
return 0;
}
#else
+static int rk3528_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
+ struct rockchip_eth_dev *dev)
+{
+ struct eqos_priv *priv = &dev->eqos;
+ struct rk3528_grf *grf;
+ unsigned int div;
+
+ enum {
+ RK3528_GMAC0_CLK_RMII_DIV_SHIFT = 3,
+ RK3528_GMAC0_CLK_RMII_DIV_MASK = GENMASK(4, 3),
+ RK3528_GMAC0_CLK_RMII_DIV2 = BIT(3),
+ RK3528_GMAC0_CLK_RMII_DIV20 = 0,
+ };
+
+ enum {
+ RK3528_GMAC1_CLK_RGMII_DIV_SHIFT = 10,
+ RK3528_GMAC1_CLK_RGMII_DIV_MASK = GENMASK(11, 10),
+ RK3528_GMAC1_CLK_RGMII_DIV1 = 0,
+ RK3528_GMAC1_CLK_RGMII_DIV5 = GENMASK(11, 10),
+ RK3528_GMAC1_CLK_RGMII_DIV50 = BIT(11),
+ RK3528_GMAC1_CLK_RMII_DIV2 = BIT(11),
+ RK3528_GMAC1_CLK_RMII_DIV20 = 0,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ switch (priv->phy->speed) {
+ case 10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV20 :
+ RK3528_GMAC0_CLK_RMII_DIV20;
+ else
+ div = RK3528_GMAC1_CLK_RGMII_DIV50;
+ break;
+ case 100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII)
+ div = pdata->bus_id ? RK3528_GMAC1_CLK_RMII_DIV2 :
+ RK3528_GMAC0_CLK_RMII_DIV2;
+ else
+ div = RK3528_GMAC1_CLK_RGMII_DIV5;
+ break;
+ case 1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ div = RK3528_GMAC1_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
+ return -EINVAL;
+ }
+
+ if (pdata->bus_id)
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_RGMII_DIV_MASK, div);
+ else
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_DIV_MASK, div);
+
+ return 0;
+}
+
+static int rk3562_set_gmac_speed(struct gmac_rockchip_platdata *pdata,
+ struct rockchip_eth_dev *dev)
+{
+ struct eqos_priv *priv = &dev->eqos;
+ struct rk3562_grf *grf;
+ unsigned int div;
+
+ enum {
+ RK3562_GMAC0_CLK_RGMII_DIV_SHIFT = 7,
+ RK3562_GMAC0_CLK_RGMII_DIV_MASK = GENMASK(8, 7),
+ RK3562_GMAC0_CLK_RGMII_DIV1 = 0,
+ RK3562_GMAC0_CLK_RGMII_DIV5 = GENMASK(8, 7),
+ RK3562_GMAC0_CLK_RGMII_DIV50 = BIT(8),
+ RK3562_GMAC0_CLK_RMII_DIV2 = BIT(7),
+ RK3562_GMAC0_CLK_RMII_DIV20 = 0,
+ };
+
+ enum {
+ RK3562_GMAC1_SPEED_SHIFT = 0x0,
+ RK3562_GMAC1_SPEED_MASK = BIT(0),
+ RK3562_GMAC1_SPEED_10M = 0,
+ RK3562_GMAC1_SPEED_100M = BIT(0),
+ };
+
+ enum {
+ RK3562_GMAC1_CLK_RMII_DIV_SHIFT = 13,
+ RK3562_GMAC1_CLK_RMII_DIV_MASK = BIT(13),
+ RK3562_GMAC1_CLK_RMII_DIV2 = BIT(13),
+ RK3562_GMAC1_CLK_RMII_DIV20 = 0,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ switch (priv->phy->speed) {
+ case 10:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ if (pdata->bus_id > 0) {
+ div = RK3562_GMAC1_CLK_RMII_DIV20;
+ rk_clrsetreg(&grf->soc_con[0],
+ RK3562_GMAC1_SPEED_MASK,
+ RK3562_GMAC1_SPEED_10M);
+ } else {
+ div = RK3562_GMAC0_CLK_RMII_DIV20;
+ }
+ } else {
+ div = RK3562_GMAC0_CLK_RGMII_DIV50;
+ }
+ break;
+ case 100:
+ if (pdata->phy_interface == PHY_INTERFACE_MODE_RMII) {
+ if (pdata->bus_id > 0) {
+ div = RK3562_GMAC1_CLK_RMII_DIV2;
+ rk_clrsetreg(&grf->soc_con[0],
+ RK3562_GMAC1_SPEED_MASK,
+ RK3562_GMAC1_SPEED_100M);
+ } else {
+ div = RK3562_GMAC0_CLK_RMII_DIV2;
+ }
+ } else {
+ div = RK3562_GMAC0_CLK_RGMII_DIV5;
+ }
+ break;
+ case 1000:
+ if (pdata->phy_interface != PHY_INTERFACE_MODE_RMII)
+ div = RK3562_GMAC0_CLK_RGMII_DIV1;
+ else
+ return -EINVAL;
+ break;
+ default:
+ debug("Unknown phy speed: %d\n", priv->phy->speed);
+ return -EINVAL;
+ }
+
+ if (pdata->bus_id)
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_RMII_DIV_MASK, div);
+ else
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_RGMII_DIV_MASK, div);
+
+ return 0;
+}
+
static int rk3588_set_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct rockchip_eth_dev *dev)
{
@@ -1064,6 +1208,251 @@
}
#else
+static void rk3528_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3528_grf *grf;
+ unsigned char bgs[1] = {0};
+
+ enum {
+ RK3528_MACPHY_ENABLE_MASK = BIT(1),
+ RK3528_MACPHY_DISENABLE = BIT(1),
+ RK3528_MACPHY_ENABLE = 0,
+ RK3528_MACPHY_XMII_SEL_MASK = GENMASK(6, 5),
+ RK3528_MACPHY_XMII_SEL = BIT(6),
+ RK3528_MACPHY_24M_CLK_SEL_MASK = GENMASK(9, 7),
+ RK3528_MACPHY_24M_CLK_SEL_24M = (BIT(8) | BIT(9)),
+ RK3528_MACPHY_PHY_ID_MASK = GENMASK(14, 10),
+ RK3528_MACPHY_PHY_ID = BIT(11),
+ };
+
+ enum {
+ RK3528_MACPHY_BGS_MASK = GENMASK(3, 0),
+ };
+
+#if defined(CONFIG_ROCKCHIP_EFUSE) || defined(CONFIG_ROCKCHIP_OTP)
+ struct udevice *dev;
+ u32 regs[2] = {0};
+ ofnode node;
+ int ret = 0;
+
+ /* retrieve the device */
+ if (IS_ENABLED(CONFIG_ROCKCHIP_EFUSE))
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(rockchip_efuse),
+ &dev);
+ else
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_GET_DRIVER(rockchip_otp),
+ &dev);
+ if (!ret) {
+ node = dev_read_subnode(dev, "macphy-bgs");
+ if (ofnode_valid(node)) {
+ if (!ofnode_read_u32_array(node, "reg", regs, 2)) {
+ /* read the bgs from the efuses */
+ ret = misc_read(dev, regs[0], &bgs, 1);
+ if (ret) {
+ printf("read bgs from efuse/otp failed, ret=%d\n",
+ ret);
+ bgs[0] = 0;
+ }
+ }
+ }
+ }
+#endif
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ reset_assert(&pdata->phy_reset);
+ udelay(20);
+ rk_clrsetreg(&grf->macphy_con0,
+ RK3528_MACPHY_ENABLE_MASK |
+ RK3528_MACPHY_XMII_SEL_MASK |
+ RK3528_MACPHY_24M_CLK_SEL_MASK |
+ RK3528_MACPHY_PHY_ID_MASK,
+ RK3528_MACPHY_ENABLE |
+ RK3528_MACPHY_XMII_SEL |
+ RK3528_MACPHY_24M_CLK_SEL_24M |
+ RK3528_MACPHY_PHY_ID);
+
+ rk_clrsetreg(&grf->macphy_con1,
+ RK3528_MACPHY_BGS_MASK,
+ bgs[0]);
+ udelay(20);
+ reset_deassert(&pdata->phy_reset);
+ udelay(30 * 1000);
+}
+
+static void rk3528_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ unsigned int clk_mode;
+ struct rk3528_grf *grf;
+
+ enum {
+ RK3528_GMAC0_CLK_RMII_MODE_SHIFT = 0x1,
+ RK3528_GMAC0_CLK_RMII_MODE_MASK = BIT(1),
+ RK3528_GMAC0_CLK_RMII_MODE = 0x1,
+ };
+
+ enum {
+ RK3528_GMAC1_CLK_RMII_MODE_SHIFT = 0x8,
+ RK3528_GMAC1_CLK_RMII_MODE_MASK = BIT(8),
+ RK3528_GMAC1_CLK_RMII_MODE = 0x1,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (pdata->bus_id == 1) {
+ clk_mode = RK3528_GMAC1_CLK_RMII_MODE << RK3528_GMAC1_CLK_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->gmac1_con1, RK3528_GMAC1_CLK_RMII_MODE_MASK, clk_mode);
+ } else {
+ clk_mode = RK3528_GMAC0_CLK_RMII_MODE << RK3528_GMAC0_CLK_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->gmac0_con, RK3528_GMAC0_CLK_RMII_MODE_MASK, clk_mode);
+ }
+}
+
+static void rk3528_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ unsigned int rx_enable;
+ unsigned int rx_delay;
+ struct rk3528_grf *grf;
+
+ enum {
+ RK3528_GMAC1_RGMII_MODE_SHIFT = 0x8,
+ RK3528_GMAC1_RGMII_MODE_MASK = BIT(8),
+ RK3528_GMAC1_RGMII_MODE = 0x0,
+
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK = BIT(14),
+ RK3528_GMAC1_TXCLK_DLY_ENA_DISABLE = 0,
+ RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE = BIT(14),
+
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK = BIT(15),
+ RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE = 0,
+ RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE = BIT(15),
+ };
+
+ enum {
+ RK3528_GMAC1_RX_DL_CFG_SHIFT = 0x8,
+ RK3528_GMAC1_RX_DL_CFG_MASK = GENMASK(15, 8),
+
+ RK3528_GMAC1_TX_DL_CFG_SHIFT = 0x0,
+ RK3528_GMAC1_TX_DL_CFG_MASK = GENMASK(7, 0),
+ };
+
+ if (!pdata->bus_id)
+ return;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (pdata->rx_delay < 0) {
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_DISABLE;
+ rx_delay = 0;
+ } else {
+ rx_enable = RK3528_GMAC1_RXCLK_DLY_ENA_ENABLE;
+ rx_delay = pdata->rx_delay << RK3528_GMAC1_RX_DL_CFG_SHIFT;
+ }
+
+ rk_clrsetreg(&grf->gmac1_con0,
+ RK3528_GMAC1_TXCLK_DLY_ENA_MASK |
+ RK3528_GMAC1_RXCLK_DLY_ENA_MASK |
+ RK3528_GMAC1_RGMII_MODE_MASK,
+ rx_enable | RK3528_GMAC1_TXCLK_DLY_ENA_ENABLE |
+ (RK3528_GMAC1_RGMII_MODE << RK3528_GMAC1_RGMII_MODE_SHIFT));
+
+ rk_clrsetreg(&grf->gmac1_con1,
+ RK3528_GMAC1_RX_DL_CFG_MASK |
+ RK3528_GMAC1_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3528_GMAC1_TX_DL_CFG_SHIFT) |
+ rx_delay);
+}
+
+static void rk3562_set_to_rmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ unsigned int mode;
+
+ enum {
+ RK3562_GMAC0_RMII_MODE_SHIFT = 0x5,
+ RK3562_GMAC0_RMII_MODE_MASK = BIT(5),
+ RK3562_GMAC0_RMII_MODE = 0x1,
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (!pdata->bus_id) {
+ mode = RK3562_GMAC0_RMII_MODE << RK3562_GMAC0_RMII_MODE_SHIFT;
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RMII_MODE_MASK, mode);
+ }
+}
+
+static void rk3562_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ struct rk3562_ioc *ioc;
+ unsigned int rx_enable;
+ unsigned int rx_delay;
+
+ enum {
+ RK3562_GMAC0_RGMII_MODE_SHIFT = 0x5,
+ RK3562_GMAC0_RGMII_MODE_MASK = BIT(5),
+ RK3562_GMAC0_RGMII_MODE = 0x0,
+
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK = BIT(0),
+ RK3562_GMAC0_TXCLK_DLY_ENA_DISABLE = 0,
+ RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE = BIT(0),
+
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK = BIT(1),
+ RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE = 0,
+ RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE = BIT(1),
+ };
+
+ enum {
+ RK3562_GMAC0_RX_DL_CFG_SHIFT = 0x8,
+ RK3562_GMAC0_RX_DL_CFG_MASK = GENMASK(15, 8),
+
+ RK3562_GMAC0_TX_DL_CFG_SHIFT = 0x0,
+ RK3562_GMAC0_TX_DL_CFG_MASK = GENMASK(7, 0),
+ };
+
+ if (pdata->bus_id)
+ return;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
+
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_RGMII_MODE_MASK,
+ RK3562_GMAC0_RGMII_MODE << RK3562_GMAC0_RGMII_MODE_SHIFT);
+
+ if (pdata->rx_delay < 0) {
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_DISABLE;
+ rx_delay = 0;
+ } else {
+ rx_enable = RK3562_GMAC0_RXCLK_DLY_ENA_ENABLE;
+ rx_delay = pdata->rx_delay << RK3562_GMAC0_RX_DL_CFG_SHIFT;
+ }
+
+ rk_clrsetreg(&ioc->mac0_io_con1,
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
+
+ rk_clrsetreg(&ioc->mac0_io_con0,
+ RK3562_GMAC0_RX_DL_CFG_MASK |
+ RK3562_GMAC0_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
+ rx_delay);
+
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC0_TXCLK_DLY_ENA_MASK |
+ RK3562_GMAC0_RXCLK_DLY_ENA_MASK,
+ rx_enable | RK3562_GMAC0_TXCLK_DLY_ENA_ENABLE);
+
+ rk_clrsetreg(&ioc->mac1_io_con0,
+ RK3562_GMAC0_RX_DL_CFG_MASK |
+ RK3562_GMAC0_TX_DL_CFG_MASK,
+ (pdata->tx_delay << RK3562_GMAC0_TX_DL_CFG_SHIFT) |
+ rx_delay);
+}
+
static void rk3568_set_to_rmii(struct gmac_rockchip_platdata *pdata)
{
struct rk3568_grf *grf;
@@ -1438,6 +1827,86 @@
#endif
#ifdef CONFIG_DWC_ETH_QOS
+static void rk3528_set_clock_selection(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3528_grf *grf;
+ unsigned int val;
+
+ enum {
+ RK3528_GMAC1_CLK_SELET_SHIFT = 0x12,
+ RK3528_GMAC1_CLK_SELET_MASK = BIT(12),
+ RK3528_GMAC1_CLK_SELET_CRU = 0,
+ RK3528_GMAC1_CLK_SELET_IO = BIT(12),
+ };
+
+ if (!pdata->bus_id)
+ return;
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ val = pdata->clock_input ? RK3528_GMAC1_CLK_SELET_IO :
+ RK3528_GMAC1_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->gmac1_con0, RK3528_GMAC1_CLK_SELET_MASK, val);
+}
+
+static void rk3562_set_clock_selection(struct gmac_rockchip_platdata *pdata)
+{
+ struct rk3562_grf *grf;
+ struct rk3562_ioc *ioc;
+ unsigned int val;
+
+ enum {
+ RK3562_GMAC0_CLK_SELET_SHIFT = 0x9,
+ RK3562_GMAC0_CLK_SELET_MASK = BIT(9),
+ RK3562_GMAC0_CLK_SELET_CRU = 0,
+ RK3562_GMAC0_CLK_SELET_IO = BIT(9),
+ };
+
+ enum {
+ RK3562_GMAC1_CLK_SELET_SHIFT = 15,
+ RK3562_GMAC1_CLK_SELET_MASK = BIT(15),
+ RK3562_GMAC1_CLK_SELET_CRU = 0,
+ RK3562_GMAC1_CLK_SELET_IO = BIT(15),
+ };
+
+ enum {
+ RK3562_GMAC0_IO_EXTCLK_SELET_SHIFT = 0x2,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK = BIT(2),
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU = 0,
+ RK3562_GMAC0_IO_EXTCLK_SELET_IO = BIT(2),
+ };
+
+ enum {
+ RK3562_GMAC1_IO_EXTCLK_SELET_SHIFT = 0x3,
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK = BIT(3),
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU = 0,
+ RK3562_GMAC1_IO_EXTCLK_SELET_IO = BIT(3),
+ };
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ ioc = syscon_get_first_range(ROCKCHIP_SYSCON_IOC);
+
+ if (!pdata->bus_id) {
+ val = pdata->clock_input ? RK3562_GMAC0_CLK_SELET_IO :
+ RK3562_GMAC0_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->soc_con[0], RK3562_GMAC0_CLK_SELET_MASK, val);
+ val = pdata->clock_input ? RK3562_GMAC0_IO_EXTCLK_SELET_IO :
+ RK3562_GMAC0_IO_EXTCLK_SELET_CRU;
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
+ rk_clrsetreg(&ioc->mac0_io_con1,
+ RK3562_GMAC0_IO_EXTCLK_SELET_MASK, val);
+
+ } else {
+ val = pdata->clock_input ? RK3562_GMAC1_CLK_SELET_IO :
+ RK3562_GMAC1_CLK_SELET_CRU;
+ rk_clrsetreg(&grf->soc_con[1], RK3562_GMAC1_CLK_SELET_MASK, val);
+ val = pdata->clock_input ? RK3562_GMAC1_IO_EXTCLK_SELET_IO :
+ RK3562_GMAC1_IO_EXTCLK_SELET_CRU;
+ rk_clrsetreg(&ioc->mac1_io_con1,
+ RK3562_GMAC1_IO_EXTCLK_SELET_MASK, val);
+ }
+}
+
static void rk3588_set_clock_selection(struct gmac_rockchip_platdata *pdata)
{
struct rk3588_php_grf *php_grf;
@@ -1701,6 +2170,21 @@
.set_to_rmii = rv1108_gmac_set_to_rmii,
};
#else
+const struct rk_gmac_ops rk3528_gmac_ops = {
+ .fix_mac_speed = rk3528_set_rgmii_speed,
+ .set_to_rgmii = rk3528_set_to_rgmii,
+ .set_to_rmii = rk3528_set_to_rmii,
+ .set_clock_selection = rk3528_set_clock_selection,
+ .integrated_phy_powerup = rk3528_gmac_integrated_phy_powerup,
+};
+
+const struct rk_gmac_ops rk3562_gmac_ops = {
+ .fix_mac_speed = rk3562_set_gmac_speed,
+ .set_to_rgmii = rk3562_set_to_rgmii,
+ .set_to_rmii = rk3562_set_to_rmii,
+ .set_clock_selection = rk3562_set_clock_selection,
+};
+
const struct rk_gmac_ops rk3568_gmac_ops = {
.fix_mac_speed = rv1126_set_rgmii_speed,
.set_to_rgmii = rk3568_set_to_rgmii,
@@ -1774,6 +2258,16 @@
.data = (ulong)&rv1108_gmac_ops },
#endif
#else
+#ifdef CONFIG_ROCKCHIP_RK3528
+ { .compatible = "rockchip,rk3528-gmac",
+ .data = (ulong)&rk3528_gmac_ops },
+#endif
+
+#ifdef CONFIG_ROCKCHIP_RK3562
+ { .compatible = "rockchip,rk3562-gmac",
+ .data = (ulong)&rk3562_gmac_ops },
+#endif
+
#ifdef CONFIG_ROCKCHIP_RK3568
{ .compatible = "rockchip,rk3568-gmac",
.data = (ulong)&rk3568_gmac_ops },
diff --git a/u-boot/drivers/net/phy/rk630phy.c b/u-boot/drivers/net/phy/rk630phy.c
index 9f1ec14..cc35bc4 100644
--- a/u-boot/drivers/net/phy/rk630phy.c
+++ b/u-boot/drivers/net/phy/rk630phy.c
@@ -50,6 +50,7 @@
#define REG_PAGE6_CP_CURRENT 0x17
#define REG_PAGE6_ADC_OP_BIAS 0x18
#define REG_PAGE6_RX_DECTOR 0x19
+#define REG_PAGE6_TX_MOS_DRV 0x1B
#define REG_PAGE6_AFE_PDCW 0x1c
/* PAGE 8 */
@@ -201,6 +202,8 @@
phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_RX_DECTOR, 0x0408);
/* PHYAFE PDCW optimization */
phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_AFE_PDCW, 0x8880);
+ /* Add PHY Tx mos drive, reduce power noise/jitter */
+ phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE6_TX_MOS_DRV, 0x888e);
/* Switch to page 8 */
phy_write(phydev, MDIO_DEVAD_NONE, REG_PAGE_SEL, 0x0800);
diff --git a/u-boot/drivers/nvme/nvme.c b/u-boot/drivers/nvme/nvme.c
index 55600c8..402e992 100644
--- a/u-boot/drivers/nvme/nvme.c
+++ b/u-boot/drivers/nvme/nvme.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <bouncebuf.h>
#include <dm.h>
#include <errno.h>
#include <memalign.h>
@@ -740,13 +741,25 @@
u64 prp2;
u64 total_len = blkcnt << desc->log2blksz;
u64 temp_len = total_len;
+ uintptr_t temp_buffer;
u64 slba = blknr;
u16 lbas = 1 << (dev->max_transfer_shift - ns->lba_shift);
u64 total_lbas = blkcnt;
- flush_dcache_range((unsigned long)buffer,
- (unsigned long)buffer + total_len);
+ struct bounce_buffer bb;
+ unsigned int bb_flags;
+ int ret;
+
+ if (read)
+ bb_flags = GEN_BB_WRITE;
+ else
+ bb_flags = GEN_BB_READ;
+
+ ret = bounce_buffer_start(&bb, buffer, total_len, bb_flags);
+ if (ret)
+ return -ENOMEM;
+ temp_buffer = (unsigned long)bb.bounce_buffer;
c.rw.opcode = read ? nvme_cmd_read : nvme_cmd_write;
c.rw.flags = 0;
@@ -771,24 +784,22 @@
}
if (nvme_setup_prps(dev, &prp2,
- lbas << ns->lba_shift, (ulong)buffer))
+ lbas << ns->lba_shift, temp_buffer))
return -EIO;
c.rw.slba = cpu_to_le64(slba);
slba += lbas;
c.rw.length = cpu_to_le16(lbas - 1);
- c.rw.prp1 = cpu_to_le64((ulong)buffer);
+ c.rw.prp1 = cpu_to_le64(temp_buffer);
c.rw.prp2 = cpu_to_le64(prp2);
status = nvme_submit_sync_cmd(dev->queues[NVME_IO_Q],
&c, NULL, IO_TIMEOUT);
if (status)
break;
temp_len -= (u32)lbas << ns->lba_shift;
- buffer += lbas << ns->lba_shift;
+ temp_buffer += lbas << ns->lba_shift;
}
- if (read)
- invalidate_dcache_range((unsigned long)buffer,
- (unsigned long)buffer + total_len);
+ bounce_buffer_stop(&bb);
return (total_len - temp_len) >> desc->log2blksz;
}
diff --git a/u-boot/drivers/pci/pcie_dw_rockchip.c b/u-boot/drivers/pci/pcie_dw_rockchip.c
index 27312d1..dd81acf 100644
--- a/u-boot/drivers/pci/pcie_dw_rockchip.c
+++ b/u-boot/drivers/pci/pcie_dw_rockchip.c
@@ -18,8 +18,41 @@
#include <asm-generic/gpio.h>
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
+#include <linux/ioport.h>
DECLARE_GLOBAL_DATA_PTR;
+
+#define RK_PCIE_DBG 0
+
+#define __pcie_dev_print_emit(fmt, ...) \
+({ \
+ printf(fmt, ##__VA_ARGS__); \
+})
+
+#ifdef dev_err
+#undef dev_err
+#define dev_err(dev, fmt, ...) \
+({ \
+ if (dev) \
+ __pcie_dev_print_emit("%s: " fmt, dev->name, \
+ ##__VA_ARGS__); \
+})
+#endif
+
+#ifdef dev_info
+#undef dev_info
+#define dev_info dev_err
+#endif
+
+#ifdef DEBUG
+#define dev_dbg dev_err
+#else
+#define dev_dbg(dev, fmt, ...) \
+({ \
+ if (0) \
+ __dev_printk(7, dev, fmt, ##__VA_ARGS__); \
+})
+#endif
struct rk_pcie {
struct udevice *dev;
@@ -62,7 +95,6 @@
#define PCIE_CLIENT_DBG_FIFO_STATUS 0x350
#define PCIE_CLIENT_DBG_TRANSITION_DATA 0xffff0000
#define PCIE_CLIENT_DBF_EN 0xffff0003
-#define RK_PCIE_DBG 0
/* PCI DBICS registers */
#define PCIE_LINK_STATUS_REG 0x80
@@ -119,6 +151,8 @@
#define LINK_WAIT_MAX_IATU_RETRIES 5
#define LINK_WAIT_IATU 10000
+#define PCIE_TYPE0_HDR_DBI2_OFFSET 0x100000
+
static int rk_pcie_read(void __iomem *addr, int size, u32 *val)
{
if ((uintptr_t)addr & (size - 1)) {
@@ -165,7 +199,7 @@
ret = rk_pcie_read(base + reg, size, &val);
if (ret)
- dev_err(rk_pcie->pci->dev, "Read APB address failed\n");
+ dev_err(rk_pcie->dev, "Read APB address failed\n");
return val;
}
@@ -177,7 +211,7 @@
ret = rk_pcie_write(base + reg, size, val);
if (ret)
- dev_err(rk_pcie->pci->dev, "Write APB address failed\n");
+ dev_err(rk_pcie->dev, "Write APB address failed\n");
}
static inline u32 rk_pcie_readl_apb(struct rk_pcie *rk_pcie, u32 reg)
@@ -272,6 +306,10 @@
val = readl(rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
val |= PORT_LOGIC_SPEED_CHANGE;
writel(val, rk_pcie->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
+
+ /* Disable BAR0 BAR1 */
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 0 * 4);
+ writel(0, rk_pcie->dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET + 0x10 + 1 * 4);
rk_pcie_dbi_write_enable(rk_pcie, false);
}
@@ -469,10 +507,10 @@
#if RK_PCIE_DBG
u32 loop;
- dev_info(rk_pcie->dev, "ltssm = 0x%x\n",
+ dev_err(rk_pcie->dev, "ltssm = 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_LTSSM_STATUS));
for (loop = 0; loop < 64; loop++)
- dev_info(rk_pcie->dev, "fifo_status = 0x%x\n",
+ dev_err(rk_pcie->dev, "fifo_status = 0x%x\n",
rk_pcie_readl_apb(rk_pcie, PCIE_CLIENT_DBG_FIFO_STATUS));
#endif
}
@@ -641,17 +679,18 @@
struct rk_pcie *priv = dev_get_priv(dev);
u32 max_link_speed;
int ret;
+ struct resource res;
- priv->dbi_base = (void *)dev_read_addr_index(dev, 0);
- if (!priv->dbi_base)
+ ret = dev_read_resource_byname(dev, "pcie-dbi", &res);
+ if (ret)
return -ENODEV;
-
+ priv->dbi_base = (void *)(res.start);
dev_dbg(dev, "DBI address is 0x%p\n", priv->dbi_base);
- priv->apb_base = (void *)dev_read_addr_index(dev, 1);
- if (!priv->apb_base)
+ ret = dev_read_resource_byname(dev, "pcie-apb", &res);
+ if (ret)
return -ENODEV;
-
+ priv->apb_base = (void *)(res.start);
dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base);
ret = gpio_request_by_name(dev, "reset-gpios", 0,
@@ -771,6 +810,8 @@
};
static const struct udevice_id rockchip_pcie_ids[] = {
+ { .compatible = "rockchip,rk3528-pcie" },
+ { .compatible = "rockchip,rk3562-pcie" },
{ .compatible = "rockchip,rk3568-pcie" },
{ .compatible = "rockchip,rk3588-pcie" },
{ }
diff --git a/u-boot/drivers/phy/Makefile b/u-boot/drivers/phy/Makefile
index 27c423e..a94cb39 100644
--- a/u-boot/drivers/phy/Makefile
+++ b/u-boot/drivers/phy/Makefile
@@ -18,3 +18,5 @@
obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o
obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o
obj-$(CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY) += phy-rockchip-naneng-combphy.o
+
+CFLAGS_phy-rockchip-inno-usb2.o := -Wno-error=unused-function -Wno-error=unused-const-variable -Wunused-const-variable=0
diff --git a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
index 6ff06f7..92a9181 100644
--- a/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/u-boot/drivers/phy/phy-rockchip-inno-usb2.c
@@ -149,6 +149,7 @@
* primary stage.
* @grf: General Register Files register base.
* @usbgrf_base : USB General Register Files register base.
+ * @phy_base: the base address of USB PHY.
* @phy_rst: phy reset control.
* @phy_cfg: phy register configuration, assigned by driver data.
*/
@@ -157,6 +158,7 @@
u8 primary_retries;
struct regmap *grf_base;
struct regmap *usbgrf_base;
+ void __iomem *phy_base;
struct udevice *vbus_supply[USB2PHY_NUM_PORTS];
struct reset_ctl phy_rst;
const struct rockchip_usb2phy_cfg *phy_cfg;
@@ -282,6 +284,11 @@
return POWER_SUPPLY_TYPE_UNKNOWN;
}
+#ifdef CONFIG_ROCKCHIP_RK3036
+ chg_type = POWER_SUPPLY_TYPE_USB;
+ goto out;
+#endif
+
/* Suspend USB-PHY and put the controller in non-driving mode */
property_enable(base, &port_cfg->phy_sus, true);
property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
@@ -388,36 +395,14 @@
port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
/* Set the USB-PHY COMMONONN to 1'b0 to ensure USB's clocks */
- property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
+ if(rphy->phy_cfg->clkout_ctl.disable)
+ property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
/* Reset USB-PHY */
property_enable(base, &port_cfg->phy_sus, true);
udelay(20);
property_enable(base, &port_cfg->phy_sus, false);
mdelay(2);
-}
-
-static struct udevice *rockchip_usb2phy_check_vbus(struct phy *phy)
-{
- struct udevice *parent = phy->dev->parent;
- struct rockchip_usb2phy *rphy = dev_get_priv(parent);
- const struct rockchip_usb2phy_port_cfg *port_cfg;
- struct regmap *base = get_reg_base(rphy);
- struct udevice *vbus = NULL;
- bool iddig = true;
-
- if (phy->id == USB2PHY_PORT_HOST) {
- vbus = rphy->vbus_supply[USB2PHY_PORT_HOST];
- } else if (phy->id == USB2PHY_PORT_OTG) {
- port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
- if (port_cfg->utmi_iddig.offset) {
- iddig = property_enabled(base, &port_cfg->utmi_iddig);
- if (!iddig)
- vbus = rphy->vbus_supply[USB2PHY_PORT_OTG];
- }
- }
-
- return vbus;
}
static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
@@ -492,10 +477,11 @@
static int rockchip_usb2phy_power_on(struct phy *phy)
{
- struct udevice *vbus = NULL;
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
int ret;
- vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, true);
if (ret) {
@@ -509,10 +495,11 @@
static int rockchip_usb2phy_power_off(struct phy *phy)
{
- struct udevice *vbus = NULL;
+ struct udevice *parent = phy->dev->parent;
+ struct rockchip_usb2phy *rphy = dev_get_priv(parent);
+ struct udevice *vbus = rphy->vbus_supply[phy->id];
int ret;
- vbus = rockchip_usb2phy_check_vbus(phy);
if (vbus) {
ret = regulator_set_enable(vbus, false);
if (ret) {
@@ -587,6 +574,11 @@
struct resource res;
u32 reg, index;
int ret;
+
+ rphy->phy_base = (void __iomem *)dev_read_addr(dev);
+ if (IS_ERR(rphy->phy_base)) {
+ dev_err(dev, "get the base address of usb phy failed\n");
+ }
if (!strncmp(parent->name, "root_driver", 11) &&
dev_read_bool(dev, "rockchip,grf")) {
@@ -818,6 +810,102 @@
return 0;
}
+static int rv1106_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+
+ /* Set HS disconnect detect mode to single ended detect mode */
+ reg = readl(rphy->phy_base + 0x70);
+ writel(reg | BIT(2), rphy->phy_base + 0x70);
+
+ return 0;
+}
+
+static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+ int ret = 0;
+
+ if (IS_ERR(rphy->phy_base)) {
+ return PTR_ERR(rphy->phy_base);
+ }
+
+ /* Turn off otg port differential receiver in suspend mode */
+ reg = readl(rphy->phy_base + 0x30);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
+
+ /* Turn off host port differential receiver in suspend mode */
+ reg = readl(rphy->phy_base + 0x0430);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
+
+ /* Set otg port HS eye height to 400mv(default is 450mv) */
+ reg = readl(rphy->phy_base + 0x30);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x00 << 4);
+ writel(reg, rphy->phy_base + 0x30);
+
+ /* Set host port HS eye height to 400mv(default is 450mv) */
+ reg = readl(rphy->phy_base + 0x430);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x00 << 4);
+ writel(reg, rphy->phy_base + 0x430);
+
+ /* Choose the Tx fs/ls data as linestate from TX driver for otg port */
+ reg = readl(rphy->phy_base + 0x94);
+ reg &= ~GENMASK(6, 3);
+ reg |= (0x03 << 3);
+ writel(reg, rphy->phy_base + 0x94);
+
+ /* Turn on output clk of phy*/
+ reg = readl(rphy->phy_base + 0x41c);
+ reg &= ~GENMASK(7, 2);
+ reg |= (0x27 << 2);
+ writel(reg, rphy->phy_base + 0x41c);
+
+ return ret;
+}
+
+static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
+{
+ u32 reg;
+ int ret = 0;
+
+ if (IS_ERR(rphy->phy_base)) {
+ return PTR_ERR(rphy->phy_base);
+ }
+
+ /* Turn off differential receiver by default to save power */
+ reg = readl(rphy->phy_base + 0x30);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x30);
+
+ reg = readl(rphy->phy_base + 0x0430);
+ writel(reg & ~BIT(2), rphy->phy_base + 0x0430);
+
+ /* Enable pre-emphasis during non-chirp phase */
+ reg = readl(rphy->phy_base);
+ reg &= ~GENMASK(2, 0);
+ reg |= 0x04;
+ writel(reg, rphy->phy_base);
+
+ reg = readl(rphy->phy_base + 0x0400);
+ reg &= ~GENMASK(2, 0);
+ reg |= 0x04;
+ writel(reg, rphy->phy_base + 0x0400);
+
+ /* Set HS eye height to 425mv(default is 400mv) */
+ reg = readl(rphy->phy_base + 0x0030);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x05 << 4);
+ writel(reg, rphy->phy_base + 0x0030);
+
+ reg = readl(rphy->phy_base + 0x0430);
+ reg &= ~GENMASK(6, 4);
+ reg |= (0x05 << 4);
+ writel(reg, rphy->phy_base + 0x0430);
+
+ return ret;
+}
+
static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
{
struct regmap *base = get_reg_base(rphy);
@@ -902,6 +990,43 @@
.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3036_phy_cfgs[] = {
+ {
+ .reg = 0x17c,
+ .num_ports = 2,
+ .clkout_ctl = { 0x017c, 11, 11, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x017c, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x017c, 14, 14, 0, 1 },
+ .bvalid_det_st = { 0x017c, 15, 15, 0, 1 },
+ .bvalid_det_clr = { 0x017c, 15, 15, 0, 1 },
+ .iddig_output = { 0x017c, 10, 10, 0, 1 },
+ .iddig_en = { 0x017c, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x01a0, 2, 2, 0, 1 },
+ .idfall_det_st = { 0x01a0, 3, 3, 0, 1 },
+ .idfall_det_clr = { 0x01a0, 3, 3, 0, 1 },
+ .idrise_det_en = { 0x01a0, 0, 0, 0, 1 },
+ .idrise_det_st = { 0x01a0, 1, 1, 0, 1 },
+ .idrise_det_clr = { 0x01a0, 1, 1, 0, 1 },
+ .ls_det_en = { 0x017c, 12, 12, 0, 1 },
+ .ls_det_st = { 0x017c, 13, 13, 0, 1 },
+ .ls_det_clr = { 0x017c, 13, 13, 0, 1 },
+ .utmi_bvalid = { 0x014c, 5, 5, 0, 1 },
+ .utmi_iddig = { 0x014c, 8, 8, 0, 1 },
+ .utmi_ls = { 0x014c, 7, 6, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0194, 8, 0, 0, 0x1d1 },
+ .ls_det_en = { 0x0194, 14, 14, 0, 1 },
+ .ls_det_st = { 0x0194, 15, 15, 0, 1 },
+ .ls_det_clr = { 0x0194, 15, 15, 0, 1 }
+ }
},
},
{ /* sentinel */ }
@@ -1272,6 +1397,51 @@
{ /* sentinel */ }
};
+static const struct rockchip_usb2phy_cfg rv1106_phy_cfgs[] = {
+ {
+ .reg = 0xff3e0000,
+ .num_ports = 1,
+ .phy_tuning = rv1106_usb2phy_tuning,
+ .clkout_ctl = { 0x0058, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0050, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0100, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x0104, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x0108, 2, 2, 0, 1 },
+ .iddig_output = { 0x0050, 10, 10, 0, 1 },
+ .iddig_en = { 0x0050, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x0100, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0104, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0108, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0100, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0104, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0108, 4, 4, 0, 1 },
+ .ls_det_en = { 0x0100, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0104, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0108, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x0060, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0x0060, 9, 9, 0, 1 },
+ .utmi_iddig = { 0x0060, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0060, 5, 4, 0, 1 },
+ },
+ },
+ .chg_det = {
+ .opmode = { 0x0050, 3, 0, 5, 1 },
+ .cp_det = { 0x0060, 13, 13, 0, 1 },
+ .dcp_det = { 0x0060, 12, 12, 0, 1 },
+ .dp_det = { 0x0060, 14, 14, 0, 1 },
+ .idm_sink_en = { 0x0058, 8, 8, 0, 1 },
+ .idp_sink_en = { 0x0058, 7, 7, 0, 1 },
+ .idp_src_en = { 0x0058, 9, 9, 0, 1 },
+ .rdm_pdwn_en = { 0x0058, 10, 10, 0, 1 },
+ .vdm_src_en = { 0x0058, 12, 12, 0, 1 },
+ .vdp_src_en = { 0x0058, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
{
.reg = 0x100,
@@ -1309,6 +1479,110 @@
.rdm_pdwn_en = { 0x0ffa0108, 10, 10, 0, 1 },
.vdm_src_en = { 0x0ffa0108, 12, 12, 0, 1 },
.vdp_src_en = { 0x0ffa0108, 11, 11, 0, 1 },
+ },
+ },
+ { /* sentinel */ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
+ {
+ .reg = 0xffdf0000,
+ .num_ports = 2,
+ .phy_tuning = rk3528_usb2phy_tuning,
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x6004c, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x60074, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x60078, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x6007c, 2, 2, 0, 1 },
+ .iddig_output = { 0x6004c, 10, 10, 0, 1 },
+ .iddig_en = { 0x6004c, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x60074, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x60078, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x6007c, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x60074, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x60078, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x6007c, 4, 4, 0, 1 },
+ .ls_det_en = { 0x60074, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60078, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x6007c, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x6006c, 1, 1, 0, 1 },
+ .utmi_bvalid = { 0x6006c, 0, 0, 0, 1 },
+ .utmi_iddig = { 0x6006c, 6, 6, 0, 1 },
+ .utmi_ls = { 0x6006c, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x6005c, 8, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x60090, 0, 0, 0, 1 },
+ .ls_det_st = { 0x60094, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x60098, 0, 0, 0, 1 },
+ .utmi_ls = { 0x6006c, 13, 12, 0, 1 },
+ .utmi_hstdet = { 0x6006c, 15, 15, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x6004c, 3, 0, 5, 1 },
+ .cp_det = { 0x6006c, 19, 19, 0, 1 },
+ .dcp_det = { 0x6006c, 18, 18, 0, 1 },
+ .dp_det = { 0x6006c, 20, 20, 0, 1 },
+ .idm_sink_en = { 0x60058, 1, 1, 0, 1 },
+ .idp_sink_en = { 0x60058, 0, 0, 0, 1 },
+ .idp_src_en = { 0x60058, 2, 2, 0, 1 },
+ .rdm_pdwn_en = { 0x60058, 3, 3, 0, 1 },
+ .vdm_src_en = { 0x60058, 5, 5, 0, 1 },
+ .vdp_src_en = { 0x60058, 4, 4, 0, 1 },
+ },
+ }
+};
+
+static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
+ {
+ .reg = 0xff740000,
+ .num_ports = 2,
+ .phy_tuning = rk3562_usb2phy_tuning,
+ .clkout_ctl = { 0x0108, 4, 4, 1, 0 },
+ .port_cfgs = {
+ [USB2PHY_PORT_OTG] = {
+ .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
+ .bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
+ .bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
+ .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
+ .iddig_output = { 0x0100, 10, 10, 0, 1 },
+ .iddig_en = { 0x0100, 9, 9, 0, 1 },
+ .idfall_det_en = { 0x0110, 5, 5, 0, 1 },
+ .idfall_det_st = { 0x0114, 5, 5, 0, 1 },
+ .idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
+ .idrise_det_en = { 0x0110, 4, 4, 0, 1 },
+ .idrise_det_st = { 0x0114, 4, 4, 0, 1 },
+ .idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
+ .ls_det_en = { 0x0110, 0, 0, 0, 1 },
+ .ls_det_st = { 0x0114, 0, 0, 0, 1 },
+ .ls_det_clr = { 0x0118, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x0120, 10, 10, 0, 1 },
+ .utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
+ .utmi_iddig = { 0x0120, 6, 6, 0, 1 },
+ .utmi_ls = { 0x0120, 5, 4, 0, 1 },
+ },
+ [USB2PHY_PORT_HOST] = {
+ .phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
+ .ls_det_en = { 0x0110, 1, 1, 0, 1 },
+ .ls_det_st = { 0x0114, 1, 1, 0, 1 },
+ .ls_det_clr = { 0x0118, 1, 1, 0, 1 },
+ .utmi_ls = { 0x0120, 17, 16, 0, 1 },
+ .utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
+ }
+ },
+ .chg_det = {
+ .opmode = { 0x0100, 3, 0, 5, 1 },
+ .cp_det = { 0x0120, 24, 24, 0, 1 },
+ .dcp_det = { 0x0120, 23, 23, 0, 1 },
+ .dp_det = { 0x0120, 25, 25, 0, 1 },
+ .idm_sink_en = { 0x0108, 8, 8, 0, 1 },
+ .idp_sink_en = { 0x0108, 7, 7, 0, 1 },
+ .idp_src_en = { 0x0108, 9, 9, 0, 1 },
+ .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
+ .vdm_src_en = { 0x0108, 12, 12, 0, 1 },
+ .vdp_src_en = { 0x0108, 11, 11, 0, 1 },
},
},
{ /* sentinel */ }
@@ -1401,6 +1675,8 @@
.ls_det_en = { 0x0080, 0, 0, 0, 1 },
.ls_det_st = { 0x0084, 0, 0, 0, 1 },
.ls_det_clr = { 0x0088, 0, 0, 0, 1 },
+ .utmi_avalid = { 0x00c0, 7, 7, 0, 1 },
+ .utmi_bvalid = { 0x00c0, 6, 6, 0, 1 },
.utmi_iddig = { 0x00c0, 5, 5, 0, 1 },
.utmi_ls = { 0x00c0, 10, 9, 0, 1 },
}
@@ -1468,16 +1744,48 @@
};
static const struct udevice_id rockchip_usb2phy_ids[] = {
+#ifdef CONFIG_ROCKCHIP_RK1808
{ .compatible = "rockchip,rk1808-usb2phy", .data = (ulong)&rk1808_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3036
+ { .compatible = "rockchip,rk3036-usb2phy", .data = (ulong)&rk3036_phy_cfgs },
+#endif
+#if defined CONFIG_ROCKCHIP_RK3128 || defined CONFIG_ROCKCHIP_RK3126
{ .compatible = "rockchip,rk3128-usb2phy", .data = (ulong)&rk312x_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK322X
{ .compatible = "rockchip,rk322x-usb2phy", .data = (ulong)&rk322x_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3308
{ .compatible = "rockchip,rk3308-usb2phy", .data = (ulong)&rk3308_phy_cfgs },
+#endif
+#if defined CONFIG_ROCKCHIP_RK3328 || defined CONFIG_ROCKCHIP_PX30
{ .compatible = "rockchip,rk3328-usb2phy", .data = (ulong)&rk3328_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3368
{ .compatible = "rockchip,rk3368-usb2phy", .data = (ulong)&rk3368_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3399
{ .compatible = "rockchip,rk3399-usb2phy", .data = (ulong)&rk3399_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3528
+ { .compatible = "rockchip,rk3528-usb2phy", .data = (ulong)&rk3528_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3562
+ { .compatible = "rockchip,rk3562-usb2phy", .data = (ulong)&rk3562_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3568
{ .compatible = "rockchip,rk3568-usb2phy", .data = (ulong)&rk3568_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RK3588
{ .compatible = "rockchip,rk3588-usb2phy", .data = (ulong)&rk3588_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RV1106
+ { .compatible = "rockchip,rv1106-usb2phy", .data = (ulong)&rv1106_phy_cfgs },
+#endif
+#ifdef CONFIG_ROCKCHIP_RV1108
{ .compatible = "rockchip,rv1108-usb2phy", .data = (ulong)&rv1108_phy_cfgs },
+#endif
{ }
};
diff --git a/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c b/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c
index 1867865..451a90f 100644
--- a/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c
+++ b/u-boot/drivers/phy/phy-rockchip-naneng-combphy.c
@@ -22,7 +22,7 @@
struct rockchip_combphy_priv;
struct combphy_reg {
- u16 offset;
+ u32 offset;
u16 bitend;
u16 bitstart;
u16 disable;
@@ -37,6 +37,7 @@
struct combphy_reg pipe_rxterm_set;
struct combphy_reg pipe_txelec_set;
struct combphy_reg pipe_txcomp_set;
+ struct combphy_reg pipe_clk_24m;
struct combphy_reg pipe_clk_25m;
struct combphy_reg pipe_clk_100m;
struct combphy_reg pipe_phymode_sel;
@@ -62,6 +63,7 @@
struct combphy_reg pipe_xpcs_phy_ready;
struct combphy_reg u3otg0_port_en;
struct combphy_reg u3otg1_port_en;
+ struct combphy_reg pipe_phy_grf_reset;
};
struct rockchip_combphy_cfg {
@@ -179,6 +181,7 @@
static int rockchip_combphy_init(struct phy *phy)
{
struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
int ret;
ret = clk_enable(&priv->ref_clk);
@@ -191,6 +194,9 @@
reset_deassert(&priv->phy_rst);
+ if (cfg->pipe_phy_grf_reset.enable)
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
+
return 0;
err_clk:
@@ -202,9 +208,13 @@
static int rockchip_combphy_exit(struct phy *phy)
{
struct rockchip_combphy_priv *priv = dev_get_priv(phy->dev);
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
- clk_disable(&priv->ref_clk);
+ if (cfg->pipe_phy_grf_reset.enable)
+ param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
+
reset_assert(&priv->phy_rst);
+ clk_disable(&priv->ref_clk);
return 0;
}
@@ -291,6 +301,215 @@
return rockchip_combphy_parse_dt(udev, priv);
}
+
+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ u32 val;
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + 0x18);
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x18);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + 0x200);
+ val &= ~GENMASK(17, 17);
+ val |= 0x01;
+ writel(val, priv->mmio + 0x200);
+
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+ default:
+ dev_err(priv->dev, "incompatible PHY type\n");
+ return -EINVAL;
+ }
+
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + 0x18);
+ val &= ~(0x7 << 10);
+ val |= 0x2 << 10;
+ writel(val, priv->mmio + 0x18);
+
+ /* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
+ val = readl(priv->mmio + 0x108);
+ val &= ~(0x7f7);
+ val |= 0x4f0;
+ writel(val, priv->mmio + 0x108);
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x48000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x48000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x48000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x48004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x48004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_24m = { 0x48004, 14, 13, 0x00, 0x00 },
+ .pipe_clk_100m = { 0x48004, 14, 13, 0x00, 0x02 },
+ .pipe_rxterm_sel = { 0x48008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x48008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x48008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x4800c, 9, 8, 0x02, 0x01 },
+ .pipe_phy_status = { 0x48034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x48000, 15, 0, 0x00, 0x110 },
+ .con1_for_pcie = { 0x48004, 15, 0, 0x00, 0x00 },
+ .con2_for_pcie = { 0x48008, 15, 0, 0x00, 0x101 },
+ .con3_for_pcie = { 0x4800c, 15, 0, 0x00, 0x0200 },
+ /* pipe-grf */
+ .u3otg0_port_en = { 0x40044, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
+ .grfcfg = &rk3528_combphy_grfcfgs,
+ .combphy_cfg = rk3528_combphy_cfg,
+};
+
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
+{
+ const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
+ u32 val;
+
+ switch (priv->mode) {
+ case PHY_TYPE_PCIE:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
+ param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
+ break;
+ case PHY_TYPE_USB3:
+ /* Set SSC downward spread spectrum */
+ val = readl(priv->mmio + (0x1f << 2));
+ val &= ~GENMASK(5, 4);
+ val |= 0x01 << 4;
+ writel(val, priv->mmio + 0x7c);
+
+ /* Enable adaptive CTLE for USB3.0 Rx */
+ val = readl(priv->mmio + (0x0e << 2));
+ val &= ~GENMASK(0, 0);
+ val |= 0x01;
+ writel(val, priv->mmio + (0x0e << 2));
+
+ /* Set PLL KVCO fine tuning signals */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Set PLL LPF R1 to su_trim[10:7]=1001 */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ /* Set PLL input clock divider 1/2 */
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ /* Set PLL loop divider */
+ writel(0x32, priv->mmio + (0x11 << 2));
+
+ /* Set PLL KVCO to min and set PLL charge pump current to max */
+ writel(0xf0, priv->mmio + (0xa << 2));
+
+ param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
+ param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
+ param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
+ param_write(priv->phy_grf, &cfg->usb_mode_set, true);
+ break;
+ default:
+ pr_err("%s, phy-type %d\n", __func__, priv->mode);
+ return -EINVAL;
+ }
+
+ clk_set_rate(&priv->ref_clk, 100000000);
+ param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
+
+ if (priv->mode == PHY_TYPE_PCIE) {
+ /* PLL KVCO tuning fine */
+ val = readl(priv->mmio + (0x20 << 2));
+ val &= ~(0x7 << 2);
+ val |= 0x2 << 2;
+ writel(val, priv->mmio + (0x20 << 2));
+
+ /* Enable controlling random jitter, aka RMJ */
+ writel(0x4, priv->mmio + (0xb << 2));
+
+ val = readl(priv->mmio + (0x5 << 2));
+ val &= ~(0x3 << 6);
+ val |= 0x1 << 6;
+ writel(val, priv->mmio + (0x5 << 2));
+
+ writel(0x32, priv->mmio + (0x11 << 2));
+ writel(0xf0, priv->mmio + (0xa << 2));
+ }
+
+ if (dev_read_bool(priv->dev, "rockchip,enable-ssc")) {
+ val = readl(priv->mmio + (0x7 << 2));
+ val |= BIT(4);
+ writel(val, priv->mmio + (0x7 << 2));
+ }
+
+ return 0;
+}
+
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
+ /* pipe-phy-grf */
+ .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
+ .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
+ .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
+ .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
+ .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
+ .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
+ .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
+ .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
+ .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
+ .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
+ .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
+ .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
+ .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
+ .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
+ .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
+ .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
+ .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
+ .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
+ .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
+ .pipe_phy_grf_reset = { 0x0014, 1, 0, 0x3, 0x1 },
+ /* pipe-grf */
+ .u3otg0_port_en = { 0x0094, 15, 0, 0x0181, 0x1100 },
+};
+
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
+ .grfcfg = &rk3562_combphy_grfcfgs,
+ .combphy_cfg = rk3562_combphy_cfg,
+};
static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
{
@@ -565,6 +784,14 @@
static const struct udevice_id rockchip_combphy_ids[] = {
{
+ .compatible = "rockchip,rk3528-naneng-combphy",
+ .data = (ulong)&rk3528_combphy_cfgs
+ },
+ {
+ .compatible = "rockchip,rk3562-naneng-combphy",
+ .data = (ulong)&rk3562_combphy_cfgs
+ },
+ {
.compatible = "rockchip,rk3568-naneng-combphy",
.data = (ulong)&rk3568_combphy_cfgs
},
diff --git a/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c b/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c
index 4044db6..bc718d0 100644
--- a/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c
+++ b/u-boot/drivers/phy/phy-rockchip-samsung-hdptx.c
@@ -592,9 +592,21 @@
struct phy_configure_opts_dp *dp)
{
u8 lane;
+ u32 status;
+ int ret;
for (lane = 0; lane < dp->lanes; lane++)
rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
+
+ reset_deassert(&hdptx->lane_reset);
+
+ ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
+ status, FIELD_GET(PHY_RDY, status),
+ 50, 5000);
+ if (ret) {
+ dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
+ return ret;
+ }
return 0;
}
@@ -676,17 +688,6 @@
regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
-
- reset_deassert(&hdptx->lane_reset);
- udelay(10);
-
- ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
- status, FIELD_GET(PHY_RDY, status),
- 50, 1000);
- if (ret) {
- dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
- return ret;
- }
return 0;
}
diff --git a/u-boot/drivers/phy/phy-rockchip-usbdp.c b/u-boot/drivers/phy/phy-rockchip-usbdp.c
index 7b624f8..cefceff 100644
--- a/u-boot/drivers/phy/phy-rockchip-usbdp.c
+++ b/u-boot/drivers/phy/phy-rockchip-usbdp.c
@@ -549,14 +549,15 @@
return 0;
}
-static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, const struct device_node *np)
+static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct udevice *dev)
{
+ const struct device_node *np = ofnode_to_np(dev->node);
struct property *prop;
int ret, i, len, num_lanes;
prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
if (!prop) {
- dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
+ dev_dbg(dev, "failed to find dp lane mux, following dp alt mode\n");
udphy->mode = UDPHY_MODE_USB;
return 0;
}
@@ -564,13 +565,13 @@
num_lanes = len / sizeof(u32);
if (num_lanes != 2 && num_lanes != 4) {
- dev_err(udphy->dev, "invalid number of lane mux\n");
+ dev_err(dev, "invalid number of lane mux\n");
return -EINVAL;
}
ret = of_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
if (ret) {
- dev_err(udphy->dev, "get dp lane mux failed\n");
+ dev_err(dev, "get dp lane mux failed\n");
return -EINVAL;
}
@@ -578,7 +579,7 @@
int j;
if (udphy->dp_lane_sel[i] > 3) {
- dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
+ dev_err(dev, "lane mux between 0 and 3, exceeding the range\n");
return -EINVAL;
}
@@ -586,22 +587,23 @@
for (j = i + 1; j < num_lanes; j++) {
if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
- dev_err(udphy->dev, "set repeat lane mux value\n");
+ dev_err(dev, "set repeat lane mux value\n");
return -EINVAL;
}
}
}
udphy->mode = UDPHY_MODE_DP;
- if (num_lanes == 2)
+ if (num_lanes == 2) {
udphy->mode |= UDPHY_MODE_USB;
+ udphy->flip = udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP ? true : false;
+ }
return 0;
}
static int udphy_parse_dt(struct rockchip_udphy *udphy, struct udevice *dev)
{
- const struct device_node *np = ofnode_to_np(dev->node);
enum usb_device_speed maximum_speed;
int ret;
@@ -645,7 +647,7 @@
}
}
- ret = udphy_parse_lane_mux_data(udphy, np);
+ ret = udphy_parse_lane_mux_data(udphy, dev);
if (ret)
return ret;
@@ -947,7 +949,7 @@
dev_for_each_subnode(subnode, parent) {
if (!ofnode_valid(subnode)) {
- printf("%s: no subnode for %s", __func__, parent->name);
+ printf("%s: no subnode for %s\n", __func__, parent->name);
return -ENXIO;
}
@@ -1014,14 +1016,14 @@
val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
200, 100);
if (ret)
- dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
+ dev_notice(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
} else {
ret = regmap_read_poll_timeout(udphy->pma_regmap,
TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
200, 100);
if (ret)
- dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
+ dev_notice(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
}
}
diff --git a/u-boot/drivers/pinctrl/Kconfig b/u-boot/drivers/pinctrl/Kconfig
index b6c741c..4899c71 100644
--- a/u-boot/drivers/pinctrl/Kconfig
+++ b/u-boot/drivers/pinctrl/Kconfig
@@ -145,14 +145,6 @@
This option is to enable the pinctrl driver for Maxim
MAX96745.
-config PINCTRL_MAX96752F
- bool "Maxim MAX96752F pinctrl driver"
- depends on DM && I2C_MUX_MAX96752F
- select PINCONF
- help
- This option is to enable the pinctrl driver for Maxim
- MAX96752F.
-
config PINCTRL_MAX96755F
bool "Maxim MAX96755F pinctrl driver"
depends on DM && I2C_MUX_MAX96755F
diff --git a/u-boot/drivers/pinctrl/Makefile b/u-boot/drivers/pinctrl/Makefile
index 6fd7798..23f26a6 100644
--- a/u-boot/drivers/pinctrl/Makefile
+++ b/u-boot/drivers/pinctrl/Makefile
@@ -24,6 +24,5 @@
obj-$(CONFIG_PINCTRL_STM32) += pinctrl_stm32.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_PINCTRL_MAX96745) += pinctrl-max96745.o
-obj-$(CONFIG_PINCTRL_MAX96752F) += pinctrl-max96752f.o
obj-$(CONFIG_PINCTRL_MAX96755F) += pinctrl-max96755f.o
endif
diff --git a/u-boot/drivers/pinctrl/pinctrl-max96752f.c b/u-boot/drivers/pinctrl/pinctrl-max96752f.c
deleted file mode 100644
index e24df35..0000000
--- a/u-boot/drivers/pinctrl/pinctrl-max96752f.c
+++ /dev/null
@@ -1,491 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <dm/pinctrl.h>
-#include <errno.h>
-#include <i2c.h>
-#include <max96752f.h>
-
-struct config_desc {
- u16 reg;
- u8 mask;
- u8 val;
-};
-
-struct function_desc {
- const char *name;
- const char **group_names;
- int num_group_names;
-
- u8 gpio_out_dis:1;
- u8 gpio_tx_en:1;
- u8 gpio_rx_en:1;
- u8 oldi:1;
- u8 gpio_tx_id;
- u8 gpio_rx_id;
-};
-
-struct group_desc {
- const char *name;
- int *pins;
- int num_pins;
-
- const struct config_desc *configs;
- int num_configs;
-};
-
-struct pin_desc {
- unsigned number;
- const char *name;
-};
-
-static const struct pin_desc max96752f_pins[] = {
- {0, "oldi"},
- {1, "gpio1"},
- {2, "gpio2"},
- {3, "gpio3"},
- {4, "gpio4"},
- {5, "gpio5"},
- {6, "gpio6"},
- {7, "gpio7"},
- {8, "gpio8"},
- {9, "gpio9"},
- {10, "gpio10"},
- {11, "gpio11"},
- {12, "gpio12"},
- {13, "gpio13"},
- {14, "gpio14"},
- {15, "gpio15"},
-};
-
-static int oldi_pins[] = {0};
-static int gpio1_pins[] = {1};
-static int gpio2_pins[] = {2};
-static int gpio3_pins[] = {3};
-static int gpio4_pins[] = {4};
-static int gpio5_pins[] = {5};
-static int gpio6_pins[] = {6};
-static int gpio7_pins[] = {7};
-static int gpio8_pins[] = {8};
-static int gpio9_pins[] = {9};
-static int gpio10_pins[] = {10};
-static int gpio11_pins[] = {11};
-static int gpio12_pins[] = {12};
-static int gpio13_pins[] = {13};
-static int gpio14_pins[] = {14};
-static int gpio15_pins[] = {15};
-
-#define GROUP_DESC(nm) \
-{ \
- .name = #nm, \
- .pins = nm ## _pins, \
- .num_pins = ARRAY_SIZE(nm ## _pins), \
-}
-
-#define GROUP_DESC_CONFIG(nm) \
-{ \
- .name = #nm, \
- .pins = nm ## _pins, \
- .num_pins = ARRAY_SIZE(nm ## _pins), \
- .configs = nm ## _configs, \
- .num_configs = ARRAY_SIZE(nm ## _configs), \
-}
-
-static const struct config_desc gpio6_configs[] = {
- { 0x0002, AUD_TX_EN, 0 },
-};
-
-static const struct config_desc gpio7_configs[] = {
- { 0x0002, AUD_TX_EN, 0 },
-};
-
-static const struct config_desc gpio8_configs[] = {
- { 0x0002, AUD_TX_EN, 0 },
-};
-
-static const struct config_desc gpio11_configs[] = {
- { 0x0140, AUD_RX_EN, 0 },
-};
-
-static const struct config_desc gpio12_configs[] = {
- { 0x0140, AUD_RX_EN, 0 },
-};
-
-static const struct config_desc gpio13_configs[] = {
- { 0x0140, AUD_RX_EN, 0 },
-};
-
-static const struct group_desc max96752f_groups[] = {
- GROUP_DESC(oldi),
- GROUP_DESC(gpio1),
- GROUP_DESC(gpio2),
- GROUP_DESC(gpio3),
- GROUP_DESC(gpio4),
- GROUP_DESC(gpio5),
- GROUP_DESC_CONFIG(gpio6),
- GROUP_DESC_CONFIG(gpio7),
- GROUP_DESC_CONFIG(gpio8),
- GROUP_DESC(gpio9),
- GROUP_DESC(gpio10),
- GROUP_DESC_CONFIG(gpio11),
- GROUP_DESC_CONFIG(gpio12),
- GROUP_DESC_CONFIG(gpio13),
- GROUP_DESC(gpio14),
- GROUP_DESC(gpio15),
-};
-
-static const char *gpio_groups[] = {
- "reserved", "gpio1", "gpio2", "gpio3", "gpio4",
- "gpio5", "gpio6", "gpio7", "gpio8", "gpio9",
- "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
- "gpio15",
-};
-
-static const char *oldi_groups[] = { "oldi" };
-
-#define FUNCTION_DESC_GPIO_RX(id) \
-{ \
- .name = "GPIO_RX_"#id, \
- .group_names = gpio_groups, \
- .num_group_names = ARRAY_SIZE(gpio_groups), \
- .gpio_rx_en = 1, \
- .gpio_rx_id = id, \
-} \
-
-#define FUNCTION_DESC_GPIO_TX(id) \
-{ \
- .name = "GPIO_TX_"#id, \
- .group_names = gpio_groups, \
- .num_group_names = ARRAY_SIZE(gpio_groups), \
- .gpio_out_dis = 1, \
- .gpio_tx_en = 1, \
- .gpio_tx_id = id \
-} \
-
-#define FUNCTION_DESC_GPIO() \
-{ \
- .name = "GPIO", \
- .group_names = gpio_groups, \
- .num_group_names = ARRAY_SIZE(gpio_groups), \
-} \
-
-#define FUNCTION_DESC_OLDI() \
-{ \
- .name = "OLDI", \
- .group_names = oldi_groups, \
- .num_group_names = ARRAY_SIZE(oldi_groups), \
- .oldi = 1, \
-} \
-
-static const struct function_desc max96752f_functions[] = {
- FUNCTION_DESC_GPIO_TX(0),
- FUNCTION_DESC_GPIO_TX(1),
- FUNCTION_DESC_GPIO_TX(2),
- FUNCTION_DESC_GPIO_TX(3),
- FUNCTION_DESC_GPIO_TX(4),
- FUNCTION_DESC_GPIO_TX(5),
- FUNCTION_DESC_GPIO_TX(6),
- FUNCTION_DESC_GPIO_TX(7),
- FUNCTION_DESC_GPIO_TX(8),
- FUNCTION_DESC_GPIO_TX(9),
- FUNCTION_DESC_GPIO_TX(10),
- FUNCTION_DESC_GPIO_TX(11),
- FUNCTION_DESC_GPIO_TX(12),
- FUNCTION_DESC_GPIO_TX(13),
- FUNCTION_DESC_GPIO_TX(14),
- FUNCTION_DESC_GPIO_TX(15),
- FUNCTION_DESC_GPIO_TX(16),
- FUNCTION_DESC_GPIO_TX(17),
- FUNCTION_DESC_GPIO_TX(18),
- FUNCTION_DESC_GPIO_TX(19),
- FUNCTION_DESC_GPIO_TX(20),
- FUNCTION_DESC_GPIO_TX(21),
- FUNCTION_DESC_GPIO_TX(22),
- FUNCTION_DESC_GPIO_TX(23),
- FUNCTION_DESC_GPIO_TX(24),
- FUNCTION_DESC_GPIO_TX(25),
- FUNCTION_DESC_GPIO_TX(26),
- FUNCTION_DESC_GPIO_TX(27),
- FUNCTION_DESC_GPIO_TX(28),
- FUNCTION_DESC_GPIO_TX(29),
- FUNCTION_DESC_GPIO_TX(30),
- FUNCTION_DESC_GPIO_TX(31),
- FUNCTION_DESC_GPIO_RX(0),
- FUNCTION_DESC_GPIO_RX(1),
- FUNCTION_DESC_GPIO_RX(2),
- FUNCTION_DESC_GPIO_RX(3),
- FUNCTION_DESC_GPIO_RX(4),
- FUNCTION_DESC_GPIO_RX(5),
- FUNCTION_DESC_GPIO_RX(6),
- FUNCTION_DESC_GPIO_RX(7),
- FUNCTION_DESC_GPIO_RX(8),
- FUNCTION_DESC_GPIO_RX(9),
- FUNCTION_DESC_GPIO_RX(10),
- FUNCTION_DESC_GPIO_RX(11),
- FUNCTION_DESC_GPIO_RX(12),
- FUNCTION_DESC_GPIO_RX(13),
- FUNCTION_DESC_GPIO_RX(14),
- FUNCTION_DESC_GPIO_RX(15),
- FUNCTION_DESC_GPIO_RX(16),
- FUNCTION_DESC_GPIO_RX(17),
- FUNCTION_DESC_GPIO_RX(18),
- FUNCTION_DESC_GPIO_RX(19),
- FUNCTION_DESC_GPIO_RX(20),
- FUNCTION_DESC_GPIO_RX(21),
- FUNCTION_DESC_GPIO_RX(22),
- FUNCTION_DESC_GPIO_RX(23),
- FUNCTION_DESC_GPIO_RX(24),
- FUNCTION_DESC_GPIO_RX(25),
- FUNCTION_DESC_GPIO_RX(26),
- FUNCTION_DESC_GPIO_RX(27),
- FUNCTION_DESC_GPIO_RX(28),
- FUNCTION_DESC_GPIO_RX(29),
- FUNCTION_DESC_GPIO_RX(30),
- FUNCTION_DESC_GPIO_RX(31),
- FUNCTION_DESC_GPIO(),
- FUNCTION_DESC_OLDI(),
-};
-
-static int max96752f_get_pins_count(struct udevice *dev)
-{
- return ARRAY_SIZE(max96752f_pins);
-}
-
-static const char *max96752f_get_pin_name(struct udevice *dev,
- unsigned selector)
-{
- return max96752f_pins[selector].name;
-}
-
-static int max96752f_pinctrl_get_groups_count(struct udevice *dev)
-{
- return ARRAY_SIZE(max96752f_groups);
-}
-
-static const char *max96752f_pinctrl_get_group_name(struct udevice *dev,
- unsigned selector)
-{
- return max96752f_groups[selector].name;
-}
-
-static int max96752f_pinctrl_get_functions_count(struct udevice *dev)
-{
- return ARRAY_SIZE(max96752f_functions);
-}
-
-static const char *max96752f_pinctrl_get_function_name(struct udevice *dev,
- unsigned selector)
-{
- return max96752f_functions[selector].name;
-}
-
-static int max96752f_pinmux_set(struct udevice *dev, unsigned group_selector,
- unsigned func_selector)
-{
- const struct group_desc *grp = &max96752f_groups[group_selector];
- const struct function_desc *func = &max96752f_functions[func_selector];
- int i, ret;
-
- if (func->oldi)
- return 0;
-
- for (i = 0; i < grp->num_configs; i++) {
- const struct config_desc *config = &grp->configs[i];
-
- ret = dm_i2c_reg_clrset(dev->parent, config->reg, config->mask,
- config->val);
- if (ret < 0)
- return ret;
- }
-
- for (i = 0; i < grp->num_pins; i++) {
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(grp->pins[i]),
- GPIO_OUT_DIS | GPIO_RX_EN | GPIO_TX_EN,
- FIELD_PREP(GPIO_OUT_DIS, func->gpio_out_dis) |
- FIELD_PREP(GPIO_RX_EN, func->gpio_rx_en) |
- FIELD_PREP(GPIO_TX_EN, func->gpio_tx_en));
- if (ret < 0)
- return ret;
-
- if (func->gpio_tx_en) {
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(grp->pins[i]),
- GPIO_TX_ID,
- FIELD_PREP(GPIO_TX_ID, func->gpio_tx_id));
- if (ret < 0)
- return ret;
- }
-
- if (func->gpio_rx_en) {
- ret = dm_i2c_reg_clrset(dev->parent,
- GPIO_C_REG(grp->pins[i]),
- GPIO_RX_ID,
- FIELD_PREP(GPIO_RX_ID, func->gpio_rx_id));
- if (ret < 0)
- return ret;
- }
- }
-
- return 0;
-}
-
-#define PIN_CONFIG_OLDI_SPL_EN (PIN_CONFIG_END + 1)
-#define PIN_CONFIG_OLDI_SWAP_AB (PIN_CONFIG_END + 2)
-
-static const struct pinconf_param max96752f_pinconf_params[] = {
- { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
- { "drive-push-pull", PIN_CONFIG_DRIVE_PUSH_PULL, 0 },
- { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
- { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 40000 },
- { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 40000 },
- { "output-low", PIN_CONFIG_OUTPUT, 0 },
- { "output-high", PIN_CONFIG_OUTPUT, 1 },
- { "oldi-spl-en", PIN_CONFIG_OLDI_SPL_EN, 0 },
- { "oldi-swap-ab", PIN_CONFIG_OLDI_SWAP_AB, 0 },
-};
-
-static int max96752f_pinconf_set(struct udevice *dev, unsigned int pin,
- unsigned int param, unsigned int arg)
-{
- u8 res_cfg;
- int ret;
-
- switch (param) {
- case PIN_CONFIG_DRIVE_OPEN_DRAIN:
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
- FIELD_PREP(OUT_TYPE, 0));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_DRIVE_PUSH_PULL:
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_B_REG(pin), OUT_TYPE,
- FIELD_PREP(OUT_TYPE, 1));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_BIAS_DISABLE:
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
- PULL_UPDN_SEL,
- FIELD_PREP(PULL_UPDN_SEL, 0));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_BIAS_PULL_UP:
- switch (arg) {
- case 40000:
- res_cfg = 0;
- break;
- case 1000000:
- res_cfg = 1;
- break;
- default:
- return -EINVAL;
- }
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
- FIELD_PREP(RES_CFG, res_cfg));
- if (ret < 0)
- return ret;
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
- PULL_UPDN_SEL,
- FIELD_PREP(PULL_UPDN_SEL, 1));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_BIAS_PULL_DOWN:
- switch (arg) {
- case 40000:
- res_cfg = 0;
- break;
- case 1000000:
- res_cfg = 1;
- break;
- default:
- return -EINVAL;
- }
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin), RES_CFG,
- FIELD_PREP(RES_CFG, res_cfg));
- if (ret < 0)
- return ret;
-
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_C_REG(pin),
- PULL_UPDN_SEL,
- FIELD_PREP(PULL_UPDN_SEL, 2));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_OUTPUT:
- ret = dm_i2c_reg_clrset(dev->parent, GPIO_A_REG(pin),
- GPIO_OUT_DIS | GPIO_OUT,
- FIELD_PREP(GPIO_OUT_DIS, 0) |
- FIELD_PREP(GPIO_OUT, arg));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_OLDI_SPL_EN:
- if (pin > 0)
- return -EINVAL;
-
- ret = dm_i2c_reg_clrset(dev->parent, OLDI_REG(1),
- OLDI_SPL_EN | OLDI_SPL_POL,
- FIELD_PREP(OLDI_SPL_EN, 1) |
- FIELD_PREP(OLDI_SPL_POL, 0));
- if (ret < 0)
- return ret;
-
- break;
- case PIN_CONFIG_OLDI_SWAP_AB:
- if (pin > 0)
- return -EINVAL;
-
- ret = dm_i2c_reg_clrset(dev->parent, OLDI_REG(1), OLDI_SWAP_AB,
- FIELD_PREP(OLDI_SWAP_AB, 1));
- if (ret < 0)
- return ret;
-
- break;
- default:
- dev_err(dev, "unsupported configuration parameter %u\n", param);
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static const struct pinctrl_ops max96752f_pinctrl_ops = {
- .get_pins_count = max96752f_get_pins_count,
- .get_pin_name = max96752f_get_pin_name,
- .get_groups_count = max96752f_pinctrl_get_groups_count,
- .get_group_name = max96752f_pinctrl_get_group_name,
- .get_functions_count = max96752f_pinctrl_get_functions_count,
- .get_function_name = max96752f_pinctrl_get_function_name,
- .set_state = pinctrl_generic_set_state,
- .pinmux_set = max96752f_pinmux_set,
- .pinmux_group_set = max96752f_pinmux_set,
- .pinconf_num_params = ARRAY_SIZE(max96752f_pinconf_params),
- .pinconf_params = max96752f_pinconf_params,
- .pinconf_set = max96752f_pinconf_set,
-};
-
-static const struct udevice_id max96752f_pinctrl_of_match[] = {
- { .compatible = "maxim,max96752f-pinctrl" },
- { }
-};
-
-U_BOOT_DRIVER(max96752f_pinctrl) = {
- .name = "pinctrl-max96752f",
- .id = UCLASS_PINCTRL,
- .of_match = max96752f_pinctrl_of_match,
- .ops = &max96752f_pinctrl_ops,
-};
diff --git a/u-boot/drivers/pinctrl/rockchip/Makefile b/u-boot/drivers/pinctrl/rockchip/Makefile
index 9b3c7fc..b82e92b 100644
--- a/u-boot/drivers/pinctrl/rockchip/Makefile
+++ b/u-boot/drivers/pinctrl/rockchip/Makefile
@@ -12,6 +12,8 @@
#obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o
#obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o
#obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += pinctrl-rk3528.o
+obj-$(CONFIG_ROCKCHIP_RK3562) += pinctrl-rk3562.o
obj-$(CONFIG_ROCKCHIP_RK3568) += pinctrl-rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += pinctrl-rk3588.o
obj-$(CONFIG_ROCKCHIP_RV1106) += pinctrl-rv1106.o
diff --git a/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c
new file mode 100644
index 0000000..33d44c9
--- /dev/null
+++ b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3528.c
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static int rk3528_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+
+ debug("iomux write reg = %x data = %x\n", reg, data);
+
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3528_DRV_BITS_PER_PIN 8
+#define RK3528_DRV_PINS_PER_REG 2
+#define RK3528_DRV_GPIO0_OFFSET 0x100
+#define RK3528_DRV_GPIO1_OFFSET 0x20120
+#define RK3528_DRV_GPIO2_OFFSET 0x30160
+#define RK3528_DRV_GPIO3_OFFSET 0x20190
+#define RK3528_DRV_GPIO4_OFFSET 0x101C0
+
+static void rk3528_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_DRV_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_DRV_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_DRV_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_DRV_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_DRV_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_DRV_PINS_PER_REG;
+ *bit *= RK3528_DRV_BITS_PER_PIN;
+}
+
+static int rk3528_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+
+ rk3528_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3528_PULL_BITS_PER_PIN 2
+#define RK3528_PULL_PINS_PER_REG 8
+#define RK3528_PULL_GPIO0_OFFSET 0x200
+#define RK3528_PULL_GPIO1_OFFSET 0x20210
+#define RK3528_PULL_GPIO2_OFFSET 0x30220
+#define RK3528_PULL_GPIO3_OFFSET 0x20230
+#define RK3528_PULL_GPIO4_OFFSET 0x10240
+
+static void rk3528_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_PULL_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_PULL_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_PULL_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_PULL_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_PULL_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_PULL_PINS_PER_REG;
+ *bit *= RK3528_PULL_BITS_PER_PIN;
+}
+
+static int rk3528_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3528_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3528_SMT_BITS_PER_PIN 1
+#define RK3528_SMT_PINS_PER_REG 8
+#define RK3528_SMT_GPIO0_OFFSET 0x400
+#define RK3528_SMT_GPIO1_OFFSET 0x20410
+#define RK3528_SMT_GPIO2_OFFSET 0x30420
+#define RK3528_SMT_GPIO3_OFFSET 0x20430
+#define RK3528_SMT_GPIO4_OFFSET 0x10440
+
+static int rk3528_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3528_SMT_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3528_SMT_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3528_SMT_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3528_SMT_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3528_SMT_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3528_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3528_SMT_PINS_PER_REG;
+ *bit *= RK3528_SMT_BITS_PER_PIN;
+ return 0;
+}
+
+static int rk3528_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+
+ rk3528_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3528_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_pin_bank rk3528_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20020, 0x20028, 0x20030, 0x20038),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x30040, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20060, 0x20068, 0x20070, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 32, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10080, 0x10088, 0x10090, 0x10098),
+};
+
+static const struct rockchip_pin_ctrl rk3528_pin_ctrl = {
+ .pin_banks = rk3528_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3528_pin_banks),
+ .nr_pins = 160,
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3528_set_mux,
+ .set_pull = rk3528_set_pull,
+ .set_drive = rk3528_set_drive,
+ .set_schmitt = rk3528_set_schmitt,
+};
+
+static const struct udevice_id rk3528_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3528-pinctrl",
+ .data = (ulong)&rk3528_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3528) = {
+ .name = "rockchip_rk3528_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3528_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
+
diff --git a/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c
new file mode 100644
index 0000000..d81fb79
--- /dev/null
+++ b/u-boot/drivers/pinctrl/rockchip/pinctrl-rk3562.c
@@ -0,0 +1,324 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <regmap.h>
+#include <syscon.h>
+
+#include "pinctrl-rockchip.h"
+
+static int rk3562_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+ int iomux_num = (pin / 8);
+ struct regmap *regmap;
+ int reg, ret, mask;
+ u8 bit;
+ u32 data;
+
+ debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux);
+
+ regmap = priv->regmap_base;
+ reg = bank->iomux[iomux_num].offset;
+ if ((pin % 8) >= 4)
+ reg += 0x4;
+ bit = (pin % 4) * 4;
+ mask = 0xf;
+
+ data = (mask << (bit + 16));
+ data |= (mux & mask) << bit;
+
+ /* force jtag m1 */
+ if (bank->bank_num == 1) {
+ if ((pin == 13) || (pin == 14)) {
+ if (mux == 1) {
+ regmap_write(regmap, 0x504, 0x10001);
+ } else {
+ regmap_write(regmap, 0x504, 0x10000);
+ }
+ }
+ }
+
+ debug("iomux write reg = %x data = %x\n", reg, data);
+
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3562_DRV_BITS_PER_PIN 8
+#define RK3562_DRV_PINS_PER_REG 2
+#define RK3562_DRV_GPIO0_OFFSET 0x20070
+#define RK3562_DRV_GPIO1_OFFSET 0x200
+#define RK3562_DRV_GPIO2_OFFSET 0x240
+#define RK3562_DRV_GPIO3_OFFSET 0x10280
+#define RK3562_DRV_GPIO4_OFFSET 0x102C0
+
+static void rk3562_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3562_DRV_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3562_DRV_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3562_DRV_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3562_DRV_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3562_DRV_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3562_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3562_DRV_PINS_PER_REG;
+ *bit *= RK3562_DRV_BITS_PER_PIN;
+}
+
+static int rk3562_set_drive(struct rockchip_pin_bank *bank,
+ int pin_num, int strength)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+ int drv = (1 << (strength + 1)) - 1;
+
+ rk3562_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3562_DRV_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (drv << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3562_PULL_BITS_PER_PIN 2
+#define RK3562_PULL_PINS_PER_REG 8
+#define RK3562_PULL_GPIO0_OFFSET 0x20020
+#define RK3562_PULL_GPIO1_OFFSET 0x80
+#define RK3562_PULL_GPIO2_OFFSET 0x90
+#define RK3562_PULL_GPIO3_OFFSET 0x100A0
+#define RK3562_PULL_GPIO4_OFFSET 0x100B0
+
+static void rk3562_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3562_PULL_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3562_PULL_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3562_PULL_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3562_PULL_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3562_PULL_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3562_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3562_PULL_PINS_PER_REG;
+ *bit *= RK3562_PULL_BITS_PER_PIN;
+}
+
+static int rk3562_set_pull(struct rockchip_pin_bank *bank,
+ int pin_num, int pull)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u8 bit, type;
+ u32 data;
+
+ if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
+ return -ENOTSUPP;
+
+ rk3562_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+ type = bank->pull_type[pin_num / 8];
+ ret = rockchip_translate_pull_value(type, pull);
+ if (ret < 0) {
+ debug("unsupported pull setting %d\n", pull);
+ return ret;
+ }
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3562_PULL_BITS_PER_PIN) - 1) << (bit + 16);
+
+ data |= (ret << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+#define RK3562_SMT_BITS_PER_PIN 2
+#define RK3562_SMT_PINS_PER_REG 8
+#define RK3562_SMT_GPIO0_OFFSET 0x20030
+#define RK3562_SMT_GPIO1_OFFSET 0xC0
+#define RK3562_SMT_GPIO2_OFFSET 0xD0
+#define RK3562_SMT_GPIO3_OFFSET 0x100E0
+#define RK3562_SMT_GPIO4_OFFSET 0x100F0
+
+static int rk3562_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl_priv *priv = bank->priv;
+
+ *regmap = priv->regmap_base;
+ switch (bank->bank_num) {
+ case 0:
+ *reg = RK3562_SMT_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *reg = RK3562_SMT_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *reg = RK3562_SMT_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *reg = RK3562_SMT_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *reg = RK3562_SMT_GPIO4_OFFSET;
+ break;
+
+ default:
+ *reg = 0;
+ dev_err(priv->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RK3562_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RK3562_SMT_PINS_PER_REG;
+ *bit *= RK3562_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
+static int rk3562_set_schmitt(struct rockchip_pin_bank *bank,
+ int pin_num, int enable)
+{
+ struct regmap *regmap;
+ int reg, ret;
+ u32 data;
+ u8 bit;
+
+ rk3562_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit);
+
+ /* enable the write to the equivalent lower bits */
+ data = ((1 << RK3562_SMT_BITS_PER_PIN) - 1) << (bit + 16);
+ data |= (enable << bit);
+ ret = regmap_write(regmap, reg, data);
+
+ return ret;
+}
+
+static struct rockchip_pin_bank rk3562_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS_OFFSET(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20000, 0x20008, 0x20010, 0x20018),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0x08, 0x10, 0x18),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20, 0, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10040, 0x10048, 0x10050, 0x10058),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 16, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0,
+ 0,
+ 0x10060, 0x10068, 0, 0),
+};
+
+static const struct rockchip_pin_ctrl rk3562_pin_ctrl = {
+ .pin_banks = rk3562_pin_banks,
+ .nr_banks = ARRAY_SIZE(rk3562_pin_banks),
+ .nr_pins = 144,
+ .grf_mux_offset = 0x0,
+ .set_mux = rk3562_set_mux,
+ .set_pull = rk3562_set_pull,
+ .set_drive = rk3562_set_drive,
+ .set_schmitt = rk3562_set_schmitt,
+};
+
+static const struct udevice_id rk3562_pinctrl_ids[] = {
+ {
+ .compatible = "rockchip,rk3562-pinctrl",
+ .data = (ulong)&rk3562_pin_ctrl
+ },
+ { }
+};
+
+U_BOOT_DRIVER(pinctrl_rk3562) = {
+ .name = "rockchip_rk3562_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = rk3562_pinctrl_ids,
+ .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
+ .ops = &rockchip_pinctrl_ops,
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
+ .bind = dm_scan_fdt_dev,
+#endif
+ .probe = rockchip_pinctrl_probe,
+};
diff --git a/u-boot/drivers/power/charge_animation.c b/u-boot/drivers/power/charge_animation.c
index c16f40e..63c99a7 100644
--- a/u-boot/drivers/power/charge_animation.c
+++ b/u-boot/drivers/power/charge_animation.c
@@ -499,6 +499,7 @@
struct charge_animation_priv *priv = dev_get_priv(dev);
struct udevice *fg = priv->fg;
int voltage, soc, charging = 1;
+ int first_poll_fg = 1;
static int timer_initialized;
voltage = fuel_gauge_get_voltage(fg);
@@ -506,6 +507,11 @@
return -EINVAL;
while (voltage < pdata->low_power_voltage + 50) {
+ if (!first_poll_fg)
+ mdelay(FUEL_GAUGE_POLL_MS);
+
+ first_poll_fg = 0;
+
/* Check charger online */
charging = fg_charger_get_chrg_online(dev);
if (charging <= 0) {
diff --git a/u-boot/drivers/power/pmic/rk8xx.c b/u-boot/drivers/power/pmic/rk8xx.c
index e361015..19877f3 100644
--- a/u-boot/drivers/power/pmic/rk8xx.c
+++ b/u-boot/drivers/power/pmic/rk8xx.c
@@ -152,7 +152,8 @@
{ RK817_PMIC_SYS_CFG1, 0x20, 0x70},
/* Set pmic_sleep as none function */
{ RK817_PMIC_SYS_CFG3, 0x00, 0x18 },
-
+ /* GATE pin function: gate function */
+ { RK817_GPIO_INT_CFG, 0x00, 0x20 },
#ifdef CONFIG_DM_CHARGE_DISPLAY
/* Set pmic_int active low */
{ RK817_GPIO_INT_CFG, 0x00, 0x02 },
@@ -408,6 +409,9 @@
val = dev_read_u32_default(dev, "not-save-power-en", 0);
rk8xx->not_save_power_en = val;
+ val = dev_read_bool(dev, "vsys-off-shutdown");
+ rk8xx->sys_can_sd = val;
+
return 0;
}
@@ -534,6 +538,16 @@
break;
case RK809_ID:
case RK817_ID:
+ if (device_is_compatible(dev, "rockchip,rk809") && (priv->variant != RK809_ID)) {
+ dev_err(dev, "the dts is RK809, the hardware is RK817\n");
+ run_command("download", 0);
+ }
+
+ if (device_is_compatible(dev, "rockchip,rk817") && (priv->variant != RK817_ID)) {
+ dev_err(dev, "the dts is RK817, the hardware is RK809\n");
+ run_command("download", 0);
+ }
+
on_source = RK817_ON_SOURCE;
off_source = RK817_OFF_SOURCE;
pwron_key = RK817_PWRON_KEY;
@@ -541,27 +555,46 @@
lp_act_msk = RK8XX_LP_ACTION_MSK;
init_data = rk817_init_reg;
init_data_num = ARRAY_SIZE(rk817_init_reg);
+
+ /* whether the system voltage can be shutdown in PWR_off mode */
+ if (priv->sys_can_sd) {
+ ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1);
+ if (ret)
+ return ret;
+ value |= 0x80;
+ ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1);
+ if (ret)
+ return ret;
+ } else {
+ ret = rk8xx_read(dev, RK817_PMIC_CHRG_TERM, &value, 1);
+ if (ret)
+ return ret;
+ value &= 0x7f;
+ ret = rk8xx_write(dev, RK817_PMIC_CHRG_TERM, &value, 1);
+ if (ret)
+ return ret;
+ }
+
/* judge whether save the PMIC_POWER_EN register */
- if (priv->not_save_power_en)
- break;
+ if (!priv->not_save_power_en) {
+ ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1);
+ if (ret)
+ return ret;
+ ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1);
+ if (ret)
+ return ret;
+ ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1);
+ if (ret)
+ return ret;
+ ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1);
+ if (ret)
+ return ret;
- ret = rk8xx_read(dev, RK817_POWER_EN0, &power_en0, 1);
- if (ret)
- return ret;
- ret = rk8xx_read(dev, RK817_POWER_EN1, &power_en1, 1);
- if (ret)
- return ret;
- ret = rk8xx_read(dev, RK817_POWER_EN2, &power_en2, 1);
- if (ret)
- return ret;
- ret = rk8xx_read(dev, RK817_POWER_EN3, &power_en3, 1);
- if (ret)
- return ret;
-
- value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4);
- rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1);
- value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
- rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1);
+ value = (power_en0 & 0x0f) | ((power_en1 & 0x0f) << 4);
+ rk8xx_write(dev, RK817_POWER_EN_SAVE0, &value, 1);
+ value = (power_en2 & 0x0f) | ((power_en3 & 0x0f) << 4);
+ rk8xx_write(dev, RK817_POWER_EN_SAVE1, &value, 1);
+ }
break;
default:
printf("Unknown PMIC: RK%x!!\n", priv->variant);
diff --git a/u-boot/drivers/power/regulator/fixed.c b/u-boot/drivers/power/regulator/fixed.c
index c35ca2a..172eb56 100644
--- a/u-boot/drivers/power/regulator/fixed.c
+++ b/u-boot/drivers/power/regulator/fixed.c
@@ -45,10 +45,12 @@
gpio = &dev_pdata->gpio;
ret = gpio_request_by_name(dev, "gpio", 0, gpio, flags);
if (ret) {
- debug("Fixed regulator optional enable GPIO - not found! Error: %d\n",
- ret);
- if (ret != -ENOENT)
- return ret;
+ ret = gpio_request_by_name(dev, "gpios", 0, gpio, flags);
+ if (ret) {
+ debug("Fixed regulator optional enable GPIO - not found! Error: %d\n", ret);
+ if (ret != -ENOENT)
+ return ret;
+ }
}
/* Get optional ramp up delay */
diff --git a/u-boot/drivers/power/regulator/regulator-uclass.c b/u-boot/drivers/power/regulator/regulator-uclass.c
index 4679249..0c692bb 100644
--- a/u-boot/drivers/power/regulator/regulator-uclass.c
+++ b/u-boot/drivers/power/regulator/regulator-uclass.c
@@ -8,7 +8,6 @@
#include <common.h>
#include <errno.h>
#include <dm.h>
-#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
#include <power/pmic.h>
#include <power/regulator.h>
@@ -413,16 +412,10 @@
if (regulator_name_is_unique(dev, uc_pdata->name))
return 0;
-#ifdef CONFIG_USING_KERNEL_DTB
- printf("Pre-reloc: %s\n", uc_pdata->name);
-
- return 0;
-#else
debug("'%s' of dev: '%s', has nonunique value: '%s\n",
property, dev->name, uc_pdata->name);
return -EINVAL;
-#endif
}
static int regulator_pre_probe(struct udevice *dev)
@@ -505,90 +498,6 @@
return ret;
}
-#ifdef CONFIG_USING_KERNEL_DTB
-/*
- * Skip probed pre-reloc regulators.
- *
- * Some regulator like fixed/gpio regultor applies a default output state
- * when probed. It maybe reverse the state which was set by the pre-reloc
- * regulator. Example: vcc3v3_pcie.
- */
-int regulators_enable_boot_on(bool verbose)
-{
- struct dm_regulator_uclass_platdata *uc_pdata;
- struct udevice *dev;
- struct uclass *uc;
- char **pre_probed = NULL;
- int i = 0, num = 0;
- int ret;
- bool skip;
-
- ret = uclass_get(UCLASS_REGULATOR, &uc);
- if (ret)
- return ret;
-
- /* find probed pre-reloc regulators */
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
- dev;
- uclass_find_next_device(&dev)) {
- if (!(dev->flags & DM_FLAG_KNRL_DTB) &&
- (dev->flags & DM_FLAG_ACTIVATED))
- num++;
- }
- if (num) {
- pre_probed = calloc(num, sizeof(char *));
- if (!pre_probed)
- return -ENOMEM;
-
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
- dev;
- uclass_find_next_device(&dev)) {
- if (!(dev->flags & DM_FLAG_KNRL_DTB) &&
- (dev->flags & DM_FLAG_ACTIVATED)) {
- uc_pdata = dev_get_uclass_platdata(dev);
- pre_probed[i++] = (char *)uc_pdata->name;
- }
- }
- }
-
- /* Skip kernel regulators whose name matches probed pre-reloc regulators */
- for (uclass_find_first_device(UCLASS_REGULATOR, &dev);
- dev;
- uclass_find_next_device(&dev)) {
- uc_pdata = dev_get_uclass_platdata(dev);
- debug("%s: %s%s\n", __func__, uc_pdata->name,
- dev->flags & DM_FLAG_KNRL_DTB ? "" : "*");
- if (dev->flags & DM_FLAG_KNRL_DTB) {
- for (i = 0, skip = false; i < num; i++) {
- if (!strcmp(pre_probed[i], uc_pdata->name)) {
- skip = true;
- break;
- }
- }
- if (skip)
- continue;
- }
-
- /* Probe and init */
- ret = device_probe(dev);
- if (ret)
- continue;
- ret = regulator_autoset(dev);
- if (ret == -EMEDIUMTYPE)
- ret = 0;
- if (verbose)
- regulator_show(dev, ret);
- if (ret == -ENOSYS)
- ret = 0;
- }
-
- if (pre_probed)
- free(pre_probed);
-
- return ret;
-}
-
-#else
int regulators_enable_boot_on(bool verbose)
{
struct udevice *dev;
@@ -613,7 +522,6 @@
return ret;
}
-#endif
UCLASS_DRIVER(regulator) = {
.id = UCLASS_REGULATOR,
diff --git a/u-boot/drivers/ram/rockchip/Makefile b/u-boot/drivers/ram/rockchip/Makefile
index 48df397..5532a80 100644
--- a/u-boot/drivers/ram/rockchip/Makefile
+++ b/u-boot/drivers/ram/rockchip/Makefile
@@ -16,6 +16,8 @@
obj-$(CONFIG_ROCKCHIP_RK3308) += sdram_rv1108_pctl_phy.o sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) += sdram_rk3328.o sdram_pctl_px30.o sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3528) += sdram_rk3528.o
+obj-$(CONFIG_ROCKCHIP_RK3562) += sdram_rk3562.o
obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
obj-$(CONFIG_ROCKCHIP_RK3588) += sdram_rk3588.o
obj-$(CONFIG_ROCKCHIP_PX30) += sdram_px30.o sdram_pctl_px30.o sdram_phy_px30.o
diff --git a/u-boot/drivers/ram/rockchip/sdram_rk3528.c b/u-boot/drivers/ram/rockchip/sdram_rk3528.c
new file mode 100644
index 0000000..e8b0b36
--- /dev/null
+++ b/u-boot/drivers/ram/rockchip/sdram_rk3528.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_TPL_BUILD
+#ifndef CONFIG_TPL_TINY_FRAMEWORK
+#error please defined CONFIG_TPL_TINY_FRAMEWORK for RK3528 !!!
+#endif
+#endif
+
+#ifdef CONFIG_TPL_BUILD
+
+/* return: 0 = success, other = fail */
+int sdram_init(void)
+{
+ return (-1);
+}
+#endif /* CONFIG_TPL_BUILD */
diff --git a/u-boot/drivers/ram/rockchip/sdram_rk3562.c b/u-boot/drivers/ram/rockchip/sdram_rk3562.c
new file mode 100644
index 0000000..60f2987
--- /dev/null
+++ b/u-boot/drivers/ram/rockchip/sdram_rk3562.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd.
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <dm.h>
+#include <ram.h>
+#include <syscon.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/rk_atags.h>
+#include <asm/arch/cru_rk3562.h>
+#include <asm/arch/grf_rk3562.h>
+
+#ifdef CONFIG_TPL_BUILD
+#ifndef CONFIG_TPL_TINY_FRAMEWORK
+#error please defined CONFIG_TPL_TINY_FRAMEWORK for RK3562 !!!
+#endif
+#endif
+
+#ifdef CONFIG_TPL_BUILD
+
+/* return: 0 = success, other = fail */
+int sdram_init(void)
+{
+ return (-1);
+}
+#endif /* CONFIG_TPL_BUILD */
diff --git a/u-boot/drivers/ram/rockchip/sdram_rv1126.c b/u-boot/drivers/ram/rockchip/sdram_rv1126.c
index bb2ce37..65f08a2 100644
--- a/u-boot/drivers/ram/rockchip/sdram_rv1126.c
+++ b/u-boot/drivers/ram/rockchip/sdram_rv1126.c
@@ -374,6 +374,8 @@
break;
delay--;
}
+ if (delay <= 0)
+ printascii("ERROR: DPLL lock timeout!\n");
writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode);
}
@@ -557,11 +559,18 @@
{
void __iomem *phy_base = dram->phy;
u32 fbdiv, prediv, postdiv, postdiv_en;
+ int delay = 1000;
if (wait) {
clrbits_le32(PHY_REG(phy_base, 0x53), PHY_PD_DISB);
- while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK))
- continue;
+ while (!(readl(PHY_REG(phy_base, 0x90)) & PHY_PLL_LOCK)) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: phy pll lock timeout!\n");
+ while (1)
+ ;
+ }
+ }
} else {
freq /= MHz;
prediv = 1;
@@ -2484,13 +2493,13 @@
return 0;
}
-static int sdram_init_(struct dram_info *dram,
- struct rv1126_sdram_params *sdram_params, u32 post_init)
+int sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init)
{
void __iomem *pctl_base = dram->pctl;
void __iomem *phy_base = dram->phy;
u32 ddr4_vref;
u32 mr_tmp, tmp;
+ int delay = 1000;
rkclk_configure_ddr(dram, sdram_params);
@@ -2538,8 +2547,14 @@
rkclk_ddr_reset(dram, 0, 0, 0, 0);
- while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0)
- continue;
+ while ((readl(pctl_base + DDR_PCTL2_STAT) & 0x7) == 0) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: Cannot wait dfi_init_done!\n");
+ while (1)
+ ;
+ }
+ }
if (sdram_params->base.dramtype == LPDDR3) {
pctl_write_mr(dram->pctl, 3, 11, lp3_odt_value, LPDDR3);
@@ -3300,6 +3315,7 @@
struct rv1126_sdram_params *sdram_params_new;
void __iomem *pctl_base = dram->pctl;
void __iomem *phy_base = dram->phy;
+ int delay = 1000;
lp_stat = low_power_update(dram, 0);
sdram_params_new = get_default_sdram_config(freq);
@@ -3388,8 +3404,14 @@
(0x0 << ACLK_DDR_UPCTL_EN_SHIFT),
BUS_SGRF_BASE_ADDR + SGRF_SOC_CON12);
while ((readl(pctl_base + DDR_PCTL2_DFISTAT) &
- PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE)
- continue;
+ PCTL2_DFI_INIT_COMPLETE) != PCTL2_DFI_INIT_COMPLETE) {
+ udelay(1);
+ if (delay-- <= 0) {
+ printascii("ERROR: Cannot wait DFI_INIT_COMPLETE\n");
+ while (1)
+ ;
+ }
+ }
sw_set_req(dram);
setbits_le32(pctl_base + DDR_PCTL2_MSTR, 0x1 << 29);
diff --git a/u-boot/drivers/rkflash/sfc_nand.c b/u-boot/drivers/rkflash/sfc_nand.c
index 82a5f52..ae5c999 100644
--- a/u-boot/drivers/rkflash/sfc_nand.c
+++ b/u-boot/drivers/rkflash/sfc_nand.c
@@ -49,6 +49,12 @@
{ 0xC2, 0x92, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
/* MX35UF2GE4AC */
{ 0xC2, 0xA2, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
+ /* MX35UF1GE4AD */
+ { 0xC2, 0x96, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
+ /* MX35UF2GE4AD */
+ { 0xC2, 0xA6, 0x00, 4, 0x40, 1, 2048, 0x0C, 19, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
+ /* MX35UF4GE4AD */
+ { 0xC2, 0xB7, 0x00, 8, 0x40, 1, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x08, 0x14, 0x18 }, &sfc_nand_get_ecc_status0 },
/* GD5F1GQ4UAYIG */
{ 0xC8, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
@@ -93,6 +99,8 @@
{ 0xEF, 0xBA, 0x22, 4, 0x40, 1, 2048, 0x4C, 19, 0x8, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status0 },
/* W25N512GVEIG */
{ 0xEF, 0xAA, 0x20, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 0, { 0x04, 0x14, 0x24, 0xFF }, &sfc_nand_get_ecc_status1 },
+ /* W25N01KV */
+ { 0xEF, 0xAE, 0x21, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
/* HYF2GQ4UAACAE */
{ 0xC9, 0x52, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
@@ -105,7 +113,11 @@
/* HYF2GQ4UHCCAE */
{ 0xC9, 0x5A, 0x00, 4, 0x40, 1, 2048, 0x4C, 19, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
/* HYF4GQ4UAACBE */
- { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0x4, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 },
+ { 0xC9, 0xD4, 0x00, 8, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x20, 0x40, 0x24, 0x44 }, &sfc_nand_get_ecc_status0 },
+ /* HYF2GQ4IAACAE */
+ { 0xC9, 0x82, 0x00, 4, 0x40, 1, 2048, 0x4C, 20, 0xE, 1, { 0x04, 0x24, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
+ /* HYF1GQ4IDACAE */
+ { 0xC9, 0x81, 0x00, 4, 0x40, 1, 1024, 0x4C, 20, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
/* FS35ND01G-S1 */
{ 0xCD, 0xB1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x10, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status5 },
@@ -124,7 +136,7 @@
/* F35SQA512M */
{ 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
/* F35UQA512M */
- { 0xCD, 0x70, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
+ { 0xCD, 0x60, 0x00, 4, 0x40, 1, 512, 0x4C, 17, 0x1, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
/* DS35Q1GA-IB */
{ 0xE5, 0x71, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
@@ -142,6 +154,10 @@
{ 0xE5, 0xF4, 0x00, 4, 0x40, 2, 2048, 0x0C, 20, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
/* DS35M1GB-IB */
{ 0xE5, 0xA1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
+ /* DS35Q12B-IB */
+ { 0xE5, 0xF5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
+ /* DS35M12B-IB */
+ { 0xE5, 0xA5, 0x00, 4, 0x40, 1, 512, 0x0C, 17, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status6 },
/* EM73C044VCC-H */
{ 0xD5, 0x22, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x8, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status0 },
@@ -199,8 +215,16 @@
{ 0xEA, 0xC1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
/* TX25G01 */
{ 0xA1, 0xF1, 0x00, 4, 0x40, 1, 1024, 0x0C, 18, 0x4, 1, { 0x04, 0x14, 0xFF, 0xFF }, &sfc_nand_get_ecc_status8 },
+ /* ANV1GCP0CLG, HYF1GQ4UTXCAE */
+ { 0x01, 0x15, 0x00, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status9 },
+ /* S35ML02G3, ANV1GCP0CLG */
+ { 0x01, 0x25, 0x00, 4, 0x40, 2, 1024, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
/* S35ML04G3 */
- { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 1, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
+ { 0x01, 0x35, 0x00, 4, 0x40, 2, 2048, 0x4C, 20, 0x4, 0, { 0x04, 0x08, 0x0C, 0x10 }, &sfc_nand_get_ecc_status9 },
+ /* GSS01GSAK1 */
+ { 0x52, 0xBA, 0x13, 4, 0x40, 1, 1024, 0x4C, 18, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
+ /* GSS02GSAK1 */
+ { 0x52, 0xBA, 0x23, 4, 0x40, 1, 2048, 0x4C, 19, 0x4, 0, { 0x04, 0x08, 0xFF, 0xFF }, &sfc_nand_get_ecc_status1 },
};
static struct nand_info *p_nand_info;
diff --git a/u-boot/drivers/rkflash/sfc_nor.c b/u-boot/drivers/rkflash/sfc_nor.c
index afbcbd7..6471efa 100644
--- a/u-boot/drivers/rkflash/sfc_nor.c
+++ b/u-boot/drivers/rkflash/sfc_nor.c
@@ -32,10 +32,14 @@
{ 0xc86016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
/* GD25B512MEYIG */
{ 0xc8471A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
+ /* GD55B01GE */
+ { 0xc8471B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
/* GD25LQ255E and GD25LQ256C */
{ 0xc86019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1D, 16, 9, 0 },
/* GD25LB512MEYIG */
{ 0xc8671A, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 17, 0, 0 },
+ /* GD55LB01GEFIRR */
+ { 0xc8671B, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 18, 0, 0 },
/* W25Q32JV */
{ 0xef4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
@@ -112,6 +116,10 @@
{ 0x0b4016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 13, 9, 0 },
/* XT25F16BS */
{ 0x0b4015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
+ /* XT25Q64D */
+ { 0x0b6017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
+ /* XT25Q128D */
+ { 0x0b6018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
/* EN25QH64A */
{ 0x1c7017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
@@ -124,7 +132,11 @@
/* EN25S64A */
{ 0x1c3817, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 0, 0 },
/* EN25QH256A */
- { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x3C, 16, 0, 0 },
+ { 0x1c7019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 0, 0 },
+ /* EN25QX256A */
+ { 0x1c7119, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
+ /* EN25QX128A */
+ { 0x1c7118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
/* P25Q64H */
{ 0x856017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
@@ -134,8 +146,12 @@
{ 0x856015, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 12, 9, 0 },
/* P25Q32SL P25Q32SH-SSH-IT */
{ 0x856016, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 13, 9, 0 },
+ /* PY25Q64HA */
+ { 0x852017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
/* PY25Q128H */
{ 0x852018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
+ /* PY25Q256H */
+ { 0x852019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
/* ZB25VQ64 */
{ 0x5e4017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
@@ -153,6 +169,8 @@
{ 0xA14018, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 9, 0 },
/* FM25Q64-SOB-T-G */
{ 0xA14017, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 14, 9, 0 },
+ /* FM25Q256I3 */
+ { 0xA14019, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
/* FM25Q64A */
{ 0xf83217, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0D, 14, 9, 0 },
@@ -174,6 +192,9 @@
/* BY25Q256FSEIG */
{ 0x684919, 128, 8, 0x13, 0x12, 0x6C, 0x34, 0x21, 0xDC, 0x1C, 16, 9, 0 },
+
+ /* NM25Q128EVB */
+ { 0x522118, 128, 8, 0x03, 0x02, 0x6B, 0x32, 0x20, 0xD8, 0x0C, 15, 10, 0 },
};
static int snor_write_en(void)
diff --git a/u-boot/drivers/rng/rockchip_rng.c b/u-boot/drivers/rng/rockchip_rng.c
index 7287afd..d85cf65 100644
--- a/u-boot/drivers/rng/rockchip_rng.c
+++ b/u-boot/drivers/rng/rockchip_rng.c
@@ -2,13 +2,14 @@
/*
* Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
*/
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <rng.h>
#include <asm/arch-rockchip/hardware.h>
#include <asm/io.h>
-#include <common.h>
-#include <dm.h>
#include <linux/iopoll.h>
#include <linux/string.h>
-#include <rng.h>
#define RK_HW_RNG_MAX 32
@@ -70,6 +71,27 @@
#define TRNG_v1_VERSION_CODE 0x46BC
/* end of TRNG V1 register define */
+/* start of RKRNG register define */
+#define RKRNG_CTRL 0x0010
+#define RKRNG_CTRL_INST_REQ BIT(0)
+#define RKRNG_CTRL_RESEED_REQ BIT(1)
+#define RKRNG_CTRL_TEST_REQ BIT(2)
+#define RKRNG_CTRL_SW_DRNG_REQ BIT(3)
+#define RKRNG_CTRL_SW_TRNG_REQ BIT(4)
+
+#define RKRNG_STATE 0x0014
+#define RKRNG_STATE_INST_ACK BIT(0)
+#define RKRNG_STATE_RESEED_ACK BIT(1)
+#define RKRNG_STATE_TEST_ACK BIT(2)
+#define RKRNG_STATE_SW_DRNG_ACK BIT(3)
+#define RKRNG_STATE_SW_TRNG_ACK BIT(4)
+
+/* DRNG_DATA_0 ~ DNG_DATA_7 */
+#define RKRNG_DRNG_DATA_0 0x0070
+#define RKRNG_DRNG_DATA_7 0x008C
+
+/* end of RKRNG register define */
+
#define RK_RNG_TIME_OUT 50000 /* max 50ms */
#define trng_write(pdata, pos, val) writel(val, (pdata)->base + (pos))
@@ -83,7 +105,36 @@
struct rk_rng_platdata {
fdt_addr_t base;
struct rk_rng_soc_data *soc_data;
+ struct clk hclk;
};
+
+static int rk_rng_do_enable_clk(struct udevice *dev, int enable)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ int ret;
+
+ if (!pdata->hclk.dev)
+ return 0;
+
+ ret = enable ? clk_enable(&pdata->hclk) : clk_disable(&pdata->hclk);
+ if (ret == -ENOSYS || !ret)
+ return 0;
+
+ printf("rk rng: failed to %s clk, ret=%d\n",
+ enable ? "enable" : "disable", ret);
+
+ return ret;
+}
+
+static int rk_rng_enable_clk(struct udevice *dev)
+{
+ return rk_rng_do_enable_clk(dev, 1);
+}
+
+static int rk_rng_disable_clk(struct udevice *dev)
+{
+ return rk_rng_do_enable_clk(dev, 0);
+}
static int rk_rng_read_regs(fdt_addr_t addr, void *buf, size_t size)
{
@@ -106,7 +157,7 @@
return 0;
}
-static int rk_cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
+static int cryptov1_rng_read(struct udevice *dev, void *data, size_t len)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
u32 reg = 0;
@@ -137,7 +188,7 @@
return 0;
}
-static int rk_cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
+static int cryptov2_rng_read(struct udevice *dev, void *data, size_t len)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
u32 reg = 0;
@@ -171,7 +222,7 @@
return retval;
}
-static int rk_trngv1_init(struct udevice *dev)
+static int trngv1_init(struct udevice *dev)
{
u32 status, version;
u32 auto_reseed_cnt = 1000;
@@ -198,7 +249,7 @@
return 0;
}
-static int rk_trngv1_rng_read(struct udevice *dev, void *data, size_t len)
+static int trngv1_rng_read(struct udevice *dev, void *data, size_t len)
{
struct rk_rng_platdata *pdata = dev_get_priv(dev);
u32 reg = 0;
@@ -224,6 +275,53 @@
exit:
/* close TRNG */
trng_write(pdata, TRNG_V1_CTRL, TRNG_V1_CTRL_NOP);
+
+ return retval;
+}
+
+static int rkrng_init(struct udevice *dev)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ reg = trng_read(pdata, RKRNG_STATE);
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ return 0;
+}
+
+static int rkrng_rng_read(struct udevice *dev, void *data, size_t len)
+{
+ struct rk_rng_platdata *pdata = dev_get_priv(dev);
+ u32 reg = 0;
+ int retval;
+
+ if (len > RK_HW_RNG_MAX)
+ return -EINVAL;
+
+ rk_rng_enable_clk(dev);
+
+ reg = RKRNG_CTRL_SW_DRNG_REQ;
+
+ rk_clrsetreg(pdata->base + RKRNG_CTRL, 0xffff, reg);
+
+ retval = readl_poll_timeout(pdata->base + RKRNG_STATE, reg,
+ (reg & RKRNG_STATE_SW_DRNG_ACK),
+ RK_RNG_TIME_OUT);
+ if (retval)
+ goto exit;
+
+ trng_write(pdata, RKRNG_STATE, reg);
+
+ rk_rng_read_regs(pdata->base + RKRNG_DRNG_DATA_0, data, len);
+
+exit:
+ /* close TRNG */
+ rk_clrreg(pdata->base + RKRNG_CTRL, 0xffff);
+
+ rk_rng_disable_clk(dev);
return retval;
}
@@ -266,6 +364,8 @@
if (!pdata->base)
return -ENOMEM;
+ clk_get_by_index(dev, 0, &pdata->hclk);
+
return 0;
}
@@ -282,17 +382,22 @@
return ret;
}
-static const struct rk_rng_soc_data rk_cryptov1_soc_data = {
- .rk_rng_read = rk_cryptov1_rng_read,
+static const struct rk_rng_soc_data cryptov1_soc_data = {
+ .rk_rng_read = cryptov1_rng_read,
};
-static const struct rk_rng_soc_data rk_cryptov2_soc_data = {
- .rk_rng_read = rk_cryptov2_rng_read,
+static const struct rk_rng_soc_data cryptov2_soc_data = {
+ .rk_rng_read = cryptov2_rng_read,
};
-static const struct rk_rng_soc_data rk_trngv1_soc_data = {
- .rk_rng_init = rk_trngv1_init,
- .rk_rng_read = rk_trngv1_rng_read,
+static const struct rk_rng_soc_data trngv1_soc_data = {
+ .rk_rng_init = trngv1_init,
+ .rk_rng_read = trngv1_rng_read,
+};
+
+static const struct rk_rng_soc_data rkrng_soc_data = {
+ .rk_rng_init = rkrng_init,
+ .rk_rng_read = rkrng_rng_read,
};
static const struct dm_rng_ops rockchip_rng_ops = {
@@ -302,15 +407,19 @@
static const struct udevice_id rockchip_rng_match[] = {
{
.compatible = "rockchip,cryptov1-rng",
- .data = (ulong)&rk_cryptov1_soc_data,
+ .data = (ulong)&cryptov1_soc_data,
},
{
.compatible = "rockchip,cryptov2-rng",
- .data = (ulong)&rk_cryptov2_soc_data,
+ .data = (ulong)&cryptov2_soc_data,
},
{
.compatible = "rockchip,trngv1",
- .data = (ulong)&rk_trngv1_soc_data,
+ .data = (ulong)&trngv1_soc_data,
+ },
+ {
+ .compatible = "rockchip,rkrng",
+ .data = (ulong)&rkrng_soc_data,
},
{},
};
diff --git a/u-boot/drivers/scsi/scsi.c b/u-boot/drivers/scsi/scsi.c
index 1a65a3f..9089c29 100644
--- a/u-boot/drivers/scsi/scsi.c
+++ b/u-boot/drivers/scsi/scsi.c
@@ -172,6 +172,7 @@
block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
+ pccb->dma_dir = DMA_FROM_DEVICE;
#ifdef CONFIG_SYS_64BIT_LBA
if (start > SCSI_LBA48_READ) {
unsigned long blocks;
@@ -247,6 +248,7 @@
__func__, block_dev->devnum, start, blks, (unsigned long)buffer);
do {
pccb->pdata = (unsigned char *)buf_addr;
+ pccb->dma_dir = DMA_TO_DEVICE;
if (blks > SCSI_MAX_WRITE_BLK) {
pccb->datalen = (block_dev->blksz *
SCSI_MAX_WRITE_BLK);
@@ -395,6 +397,7 @@
pccb->msgout[0] = SCSI_IDENTIFY; /* NOT USED */
pccb->datalen = 16;
+ pccb->dma_dir = DMA_FROM_DEVICE;
if (scsi_exec(dev, pccb))
return 1;
@@ -500,6 +503,7 @@
pccb->lun = lun;
pccb->pdata = (unsigned char *)&tempbuff;
pccb->datalen = 512;
+ pccb->dma_dir = DMA_FROM_DEVICE;
scsi_setup_inquiry(pccb);
if (scsi_exec(dev, pccb)) {
if (pccb->contr_stat == SCSI_SEL_TIME_OUT) {
diff --git a/u-boot/drivers/spi/rockchip_sfc.c b/u-boot/drivers/spi/rockchip_sfc.c
index 63ca2c0..13e4ab0 100644
--- a/u-boot/drivers/spi/rockchip_sfc.c
+++ b/u-boot/drivers/spi/rockchip_sfc.c
@@ -108,6 +108,7 @@
#define SFC_VER_4 0x4
#define SFC_VER_5 0x5
#define SFC_VER_6 0x6
+#define SFC_VER_8 0x8
/* Delay line controller resiter */
#define SFC_DLL_CTRL0 0x3C
@@ -225,6 +226,7 @@
static u32 rockchip_sfc_get_max_dll_cells(struct rockchip_sfc *sfc)
{
switch (rockchip_sfc_get_version(sfc)) {
+ case SFC_VER_8:
case SFC_VER_6:
case SFC_VER_5:
return SFC_DLL_CTRL0_DLL_MAX_VER5;
diff --git a/u-boot/drivers/spi/soft_spi.c b/u-boot/drivers/spi/soft_spi.c
index 1690cd7..64a4862 100644
--- a/u-boot/drivers/spi/soft_spi.c
+++ b/u-boot/drivers/spi/soft_spi.c
@@ -201,10 +201,8 @@
static int soft_spi_ofdata_to_platdata(struct udevice *dev)
{
struct soft_spi_platdata *plat = dev->platdata;
- const void *blob = gd->fdt_blob;
- int node = dev_of_offset(dev);
- plat->spi_delay_us = fdtdec_get_int(blob, node, "spi-delay-us", 0);
+ plat->spi_delay_us = dev_read_u32_default(dev, "spi-delay-us", 0);
return 0;
}
@@ -216,24 +214,34 @@
int cs_flags, clk_flags;
int ret;
- cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
- clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
+ if (slave) {
+ cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
+ clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
+ } else {
+ cs_flags = GPIOD_ACTIVE_LOW;
+ clk_flags = 0;
+ }
- if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs,
- GPIOD_IS_OUT | cs_flags) ||
- gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
- GPIOD_IS_OUT | clk_flags))
+ if (gpio_request_by_name(dev, "cs-gpios", 0, &plat->cs, GPIOD_IS_OUT | cs_flags) ||
+ (gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags) &&
+ gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk, GPIOD_IS_OUT | clk_flags)))
return -EINVAL;
ret = gpio_request_by_name(dev, "gpio-mosi", 0, &plat->mosi,
GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
- if (ret)
- plat->flags |= SPI_MASTER_NO_TX;
+ if (ret) {
+ if (gpio_request_by_name(dev, "mosi-gpios", 0, &plat->mosi,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE))
+ plat->flags |= SPI_MASTER_NO_TX;
+ }
ret = gpio_request_by_name(dev, "gpio-miso", 0, &plat->miso,
GPIOD_IS_IN);
- if (ret)
- plat->flags |= SPI_MASTER_NO_RX;
+ if (ret) {
+ if (gpio_request_by_name(dev, "miso-gpios", 0, &plat->miso,
+ GPIOD_IS_IN))
+ plat->flags |= SPI_MASTER_NO_RX;
+ }
if ((plat->flags & (SPI_MASTER_NO_RX | SPI_MASTER_NO_TX)) ==
(SPI_MASTER_NO_RX | SPI_MASTER_NO_TX))
diff --git a/u-boot/drivers/thermal/rockchip_thermal.c b/u-boot/drivers/thermal/rockchip_thermal.c
index 1bd6e31..e5551d4 100644
--- a/u-boot/drivers/thermal/rockchip_thermal.c
+++ b/u-boot/drivers/thermal/rockchip_thermal.c
@@ -78,6 +78,7 @@
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV3_AUTO_PERIOD 0x154
#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV3_Q_MAX 0x210
#define TSADCV2_AUTO_EN BIT(0)
#define TSADCV2_AUTO_EN_MASK BIT(16)
@@ -88,6 +89,7 @@
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
@@ -101,6 +103,7 @@
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
#define TSADCV4_DATA_MASK 0x1ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
@@ -112,6 +115,14 @@
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
+#define TSADCV12_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV12_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV12_Q_MAX_VAL 0xfff /* 12bit 4095 */
+#define TSADCV9_Q_MAX 0x210
+#define TSADCV9_Q_MAX_VAL (0xffff0400 << 0)
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -123,7 +134,10 @@
#define PX30_GRF_SOC_CON0 0x0400
#define PX30_GRF_SOC_CON2 0x0408
+#define RK3562_GRF_TSADC_CON 0x0580
+
#define RK3568_GRF_TSADC_CON 0x0600
+#define RK3528_GRF_TSADC_CON 0x40030
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
@@ -137,9 +151,10 @@
#define GRF_CON_TSADC_CH_INV (0x10001 << 1)
#define PX30S_TSADC_TDC_MODE (0x10001 << 4)
-#define MIN_TEMP (-40000)
+/* -40 to 125 is reliable, outside the range existed unreliability */
+#define MIN_TEMP (-60000)
#define LOWEST_TEMP (-273000)
-#define MAX_TEMP (125000)
+#define MAX_TEMP (180000)
#define MAX_ENV_TEMP (85000)
#define BASE (1024)
@@ -208,7 +223,8 @@
};
static const struct tsadc_table rk1808_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {3423, MIN_TEMP},
{3455, -40000},
{3463, -35000},
{3471, -30000},
@@ -243,11 +259,13 @@
{3709, 115000},
{3718, 120000},
{3726, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3820, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3228_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {568, MIN_TEMP},
{588, -40000},
{593, -35000},
{598, -30000},
@@ -282,11 +300,13 @@
{749, 115000},
{754, 120000},
{760, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {821, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3288_code_table[] = {
- {TSADCV2_DATA_MASK, -40000},
+ {TSADCV2_DATA_MASK, MIN_TEMP},
+ {3833, MIN_TEMP},
{3800, -40000},
{3792, -35000},
{3783, -30000},
@@ -321,10 +341,15 @@
{3452, 115000},
{3437, 120000},
{3421, 125000},
+ {3350, 145000},
+ {3270, 165000},
+ {3195, MAX_TEMP},
+ {0, MAX_TEMP},
};
static const struct tsadc_table rk3328_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {261, MIN_TEMP},
{296, -40000},
{304, -35000},
{313, -30000},
@@ -358,11 +383,15 @@
{644, 115000},
{659, 120000},
{675, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {745, 145000},
+ {825, 165000},
+ {900, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3368_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {98, MIN_TEMP},
{106, -40000},
{108, -35000},
{110, -30000},
@@ -397,11 +426,13 @@
{167, 115000},
{169, 120000},
{171, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {193, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3399_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {368, MIN_TEMP},
{402, -40000},
{410, -35000},
{419, -30000},
@@ -436,11 +467,95 @@
{668, 115000},
{677, 120000},
{685, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {782, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
+};
+
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, MIN_TEMP},
+ {1386, MIN_TEMP},
+ {1419, -40000},
+ {1427, -35000},
+ {1435, -30000},
+ {1443, -25000},
+ {1452, -20000},
+ {1460, -15000},
+ {1468, -10000},
+ {1477, -5000},
+ {1486, 0},
+ {1494, 5000},
+ {1502, 10000},
+ {1510, 15000},
+ {1519, 20000},
+ {1527, 25000},
+ {1535, 30000},
+ {1544, 35000},
+ {1552, 40000},
+ {1561, 45000},
+ {1569, 50000},
+ {1578, 55000},
+ {1586, 60000},
+ {1594, 65000},
+ {1603, 70000},
+ {1612, 75000},
+ {1620, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1662, 105000},
+ {1671, 110000},
+ {1679, 115000},
+ {1688, 120000},
+ {1696, 125000},
+ {1790, MAX_TEMP},
+ {TSADCV5_DATA_MASK, MAX_TEMP},
+};
+
+static const struct tsadc_table rk3562_code_table[] = {
+ {0, MIN_TEMP},
+ {1385, MIN_TEMP},
+ {1419, -40000},
+ {1428, -35000},
+ {1436, -30000},
+ {1445, -25000},
+ {1453, -20000},
+ {1462, -15000},
+ {1470, -10000},
+ {1479, -5000},
+ {1487, 0},
+ {1496, 5000},
+ {1504, 10000},
+ {1512, 15000},
+ {1521, 20000},
+ {1529, 25000},
+ {1538, 30000},
+ {1546, 35000},
+ {1555, 40000},
+ {1563, 45000},
+ {1572, 50000},
+ {1580, 55000},
+ {1589, 60000},
+ {1598, 65000},
+ {1606, 70000},
+ {1615, 75000},
+ {1623, 80000},
+ {1632, 85000},
+ {1640, 90000},
+ {1648, 95000},
+ {1657, 100000},
+ {1666, 105000},
+ {1674, 110000},
+ {1682, 115000},
+ {1691, 120000},
+ {1699, 125000},
+ {1793, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3568_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {1448, MIN_TEMP},
{1584, -40000},
{1620, -35000},
{1652, -30000},
@@ -475,16 +590,19 @@
{2636, 115000},
{2672, 120000},
{2704, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3076, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3588_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {194, MIN_TEMP},
{215, -40000},
{285, 25000},
{350, 85000},
{395, 125000},
- {TSADCV4_DATA_MASK, 125000},
+ {455, MAX_TEMP},
+ {TSADCV4_DATA_MASK, MAX_TEMP},
};
/*
@@ -806,6 +924,81 @@
tsadc_init_v2(dev);
if (!IS_ERR(priv->grf))
writel(PX30S_TSADC_TDC_MODE, priv->grf + PX30_GRF_SOC_CON0);
+}
+
+static void tsadc_init_v11(struct udevice *dev)
+{
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
+
+ writel(TSADCV7_AUTO_PERIOD_TIME, priv->base + TSADCV3_AUTO_PERIOD);
+ writel(TSADCV7_AUTO_PERIOD_HT_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel(TSADCV3_Q_MAX_VAL, priv->base + TSADCV3_Q_MAX);
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ else
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(priv->grf)) {
+ writel(RK3568_GRF_TSADC_TSEN,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ udelay(15);
+ writel(RK3568_GRF_TSADC_ANA_REG0,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG1,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG2,
+ priv->grf + RK3528_GRF_TSADC_CON);
+ udelay(200);
+ }
+}
+
+static void tsadc_init_v12(struct udevice *dev)
+{
+ struct rockchip_thermal_priv *priv = dev_get_priv(dev);
+
+ writel(TSADCV12_AUTO_PERIOD_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD);
+ writel(TSADCV12_AUTO_PERIOD_HT_TIME,
+ priv->base + TSADCV3_AUTO_PERIOD_HT);
+ writel(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ priv->base + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel(TSADCV12_Q_MAX_VAL,
+ priv->base + TSADCV9_Q_MAX);
+ writel(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ if (priv->tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+ else
+ writel(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ priv->base + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(priv->grf)) {
+ writel(RK3568_GRF_TSADC_TSEN,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ udelay(15);
+ writel(RK3568_GRF_TSADC_ANA_REG0,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG1,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ writel(RK3568_GRF_TSADC_ANA_REG2,
+ priv->grf + RK3562_GRF_TSADC_CON);
+ udelay(200);
+ }
}
static int tsadc_get_temp_v2(struct udevice *dev,
@@ -1381,6 +1574,54 @@
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .tsadc_init = tsadc_init_v11,
+ .tsadc_control = tsadc_control_v4,
+ .tsadc_get_temp = tsadc_get_temp_v4,
+ .irq_ack = tsadc_irq_ack_v4,
+ .set_alarm_temp = tsadc_alarm_temp_v3,
+ .set_tshut_temp = tsadc_tshut_temp_v3,
+ .set_tshut_mode = tsadc_tshut_mode_v4,
+
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
+static const struct rockchip_tsadc_chip rk3562_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .tsadc_init = tsadc_init_v12,
+ .tsadc_control = tsadc_control_v4,
+ .tsadc_get_temp = tsadc_get_temp_v4,
+ .irq_ack = tsadc_irq_ack_v4,
+ .set_alarm_temp = tsadc_alarm_temp_v3,
+ .set_tshut_temp = tsadc_tshut_temp_v3,
+ .set_tshut_mode = tsadc_tshut_mode_v4,
+
+ .table = {
+ .id = rk3562_code_table,
+ .length = ARRAY_SIZE(rk3562_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1477,6 +1718,14 @@
.data = (ulong)&rk3399_tsadc_data,
},
{
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (ulong)&rk3528_tsadc_data,
+ },
+ {
+ .compatible = "rockchip,rk3562-tsadc",
+ .data = (ulong)&rk3562_tsadc_data,
+ },
+ {
.compatible = "rockchip,rk3568-tsadc",
.data = (ulong)&rk3568_tsadc_data,
},
diff --git a/u-boot/drivers/ufs/Kconfig b/u-boot/drivers/ufs/Kconfig
new file mode 100644
index 0000000..69ea18e
--- /dev/null
+++ b/u-boot/drivers/ufs/Kconfig
@@ -0,0 +1,24 @@
+menu "UFS Host Controller Support"
+
+config UFS
+ bool "Support UFS controllers"
+ depends on DM_SCSI
+ select CHARSET
+ help
+ This selects support for Universal Flash Subsystem (UFS).
+ Say Y here if you want UFS Support.
+
+config CADENCE_UFS
+ bool "Cadence platform driver for UFS"
+ depends on UFS
+ help
+ This selects the platform driver for the Cadence UFS host
+ controller present on present TI's J721e devices.
+
+config TI_J721E_UFS
+ bool "Glue Layer driver for UFS on TI J721E devices"
+ help
+ This selects the glue layer driver for Cadence controller
+ present on TI's J721E devices.
+
+endmenu
diff --git a/u-boot/drivers/ufs/Makefile b/u-boot/drivers/ufs/Makefile
new file mode 100644
index 0000000..62ed016
--- /dev/null
+++ b/u-boot/drivers/ufs/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+#
+
+obj-$(CONFIG_UFS) += ufs.o ufs-uclass.o
+obj-$(CONFIG_CADENCE_UFS) += cdns-platform.o
+obj-$(CONFIG_TI_J721E_UFS) += ti-j721e-ufs.o
diff --git a/u-boot/drivers/ufs/cdns-platform.c b/u-boot/drivers/ufs/cdns-platform.c
new file mode 100644
index 0000000..dc78c9d
--- /dev/null
+++ b/u-boot/drivers/ufs/cdns-platform.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * cdns-platform.c - Platform driver for Cadence UFSHCI device
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+#include <ufs.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include "ufs.h"
+
+#define USEC_PER_SEC 1000000L
+
+#define CDNS_UFS_REG_HCLKDIV 0xFC
+#define CDNS_UFS_REG_PHY_XCFGD1 0x113C
+
+static int cdns_ufs_link_startup_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ hba->quirks |= UFSHCD_QUIRK_BROKEN_LCC;
+ switch (status) {
+ case PRE_CHANGE:
+ return ufshcd_dme_set(hba,
+ UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE),
+ 0);
+ case POST_CHANGE:
+ ;
+ }
+
+ return 0;
+}
+
+static int cdns_ufs_set_hclkdiv(struct ufs_hba *hba)
+{
+ struct clk clk;
+ unsigned long core_clk_rate = 0;
+ u32 core_clk_div = 0;
+ int ret;
+
+ ret = clk_get_by_name(hba->dev, "core_clk", &clk);
+ if (ret) {
+ dev_err(hba->dev, "failed to get core_clk clock\n");
+ return ret;
+ }
+
+ core_clk_rate = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(core_clk_rate)) {
+ dev_err(hba->dev, "%s: unable to find core_clk rate\n",
+ __func__);
+ return core_clk_rate;
+ }
+
+ core_clk_div = core_clk_rate / USEC_PER_SEC;
+ ufshcd_writel(hba, core_clk_div, CDNS_UFS_REG_HCLKDIV);
+
+ return 0;
+}
+
+static int cdns_ufs_hce_enable_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ switch (status) {
+ case PRE_CHANGE:
+ return cdns_ufs_set_hclkdiv(hba);
+ case POST_CHANGE:
+ ;
+ }
+
+ return 0;
+}
+
+static int cdns_ufs_init(struct ufs_hba *hba)
+{
+ u32 data;
+
+ /* Increase RX_Advanced_Min_ActivateTime_Capability */
+ data = ufshcd_readl(hba, CDNS_UFS_REG_PHY_XCFGD1);
+ data |= BIT(24);
+ ufshcd_writel(hba, data, CDNS_UFS_REG_PHY_XCFGD1);
+
+ return 0;
+}
+
+static struct ufs_hba_ops cdns_pltfm_hba_ops = {
+ .init = cdns_ufs_init,
+ .hce_enable_notify = cdns_ufs_hce_enable_notify,
+ .link_startup_notify = cdns_ufs_link_startup_notify,
+};
+
+static int cdns_ufs_pltfm_probe(struct udevice *dev)
+{
+ int err = ufshcd_probe(dev, &cdns_pltfm_hba_ops);
+ if (err)
+ dev_err(dev, "ufshcd_probe() failed %d\n", err);
+
+ return err;
+}
+
+static int cdns_ufs_pltfm_bind(struct udevice *dev)
+{
+ struct udevice *scsi_dev;
+
+ return ufs_scsi_bind(dev, &scsi_dev);
+}
+
+static const struct udevice_id cdns_ufs_pltfm_ids[] = {
+ {
+ .compatible = "cdns,ufshc-m31-16nm",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(cdns_ufs_pltfm) = {
+ .name = "cdns-ufs-pltfm",
+ .id = UCLASS_UFS,
+ .of_match = cdns_ufs_pltfm_ids,
+ .probe = cdns_ufs_pltfm_probe,
+ .bind = cdns_ufs_pltfm_bind,
+};
diff --git a/u-boot/drivers/ufs/ti-j721e-ufs.c b/u-boot/drivers/ufs/ti-j721e-ufs.c
new file mode 100644
index 0000000..7b157ed
--- /dev/null
+++ b/u-boot/drivers/ufs/ti-j721e-ufs.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <asm/io.h>
+#include <clk.h>
+#include <common.h>
+#include <dm.h>
+//#include <dm/device_compat.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+
+#define UFS_SS_CTRL 0x4
+#define UFS_SS_RST_N_PCS BIT(0)
+#define UFS_SS_CLK_26MHZ BIT(4)
+
+static int ti_j721e_ufs_probe(struct udevice *dev)
+{
+ void __iomem *base;
+ unsigned int clock;
+ struct clk clk;
+ u32 reg = 0;
+ int ret;
+
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret) {
+ dev_err(dev, "failed to get M-PHY clock\n");
+ return ret;
+ }
+
+ clock = clk_get_rate(&clk);
+ if (IS_ERR_VALUE(clock)) {
+ dev_err(dev, "failed to get rate\n");
+ return ret;
+ }
+
+ base = dev_remap_addr_index(dev, 0);
+
+ if (clock == 26000000)
+ reg |= UFS_SS_CLK_26MHZ;
+ /* Take UFS slave device out of reset */
+ reg |= UFS_SS_RST_N_PCS;
+ writel(reg, base + UFS_SS_CTRL);
+
+ return 0;
+}
+
+static int ti_j721e_ufs_remove(struct udevice *dev)
+{
+ void __iomem *base = dev_remap_addr_index(dev, 0);
+ u32 reg = readl(base + UFS_SS_CTRL);
+
+ reg &= ~UFS_SS_RST_N_PCS;
+ writel(reg, base + UFS_SS_CTRL);
+
+ return 0;
+}
+
+static const struct udevice_id ti_j721e_ufs_ids[] = {
+ {
+ .compatible = "ti,j721e-ufs",
+ },
+ {},
+};
+
+U_BOOT_DRIVER(ti_j721e_ufs) = {
+ .name = "ti-j721e-ufs",
+ .id = UCLASS_MISC,
+ .of_match = ti_j721e_ufs_ids,
+ .probe = ti_j721e_ufs_probe,
+ .remove = ti_j721e_ufs_remove,
+ .flags = DM_FLAG_OS_PREPARE,
+};
diff --git a/u-boot/drivers/ufs/ufs-uclass.c b/u-boot/drivers/ufs/ufs-uclass.c
new file mode 100644
index 0000000..6612f44
--- /dev/null
+++ b/u-boot/drivers/ufs/ufs-uclass.c
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * ufs-uclass.c - Universal Flash Subsystem (UFS) Uclass driver
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ */
+
+#define LOG_CATEGORY UCLASS_UFS
+
+#include <common.h>
+#include "ufs.h"
+#include <dm.h>
+
+UCLASS_DRIVER(ufs) = {
+ .id = UCLASS_UFS,
+ .name = "ufs",
+ .per_device_auto_alloc_size = sizeof(struct ufs_hba),
+};
diff --git a/u-boot/drivers/ufs/ufs.c b/u-boot/drivers/ufs/ufs.c
new file mode 100644
index 0000000..6273b29
--- /dev/null
+++ b/u-boot/drivers/ufs/ufs.c
@@ -0,0 +1,1970 @@
+// SPDX-License-Identifier: GPL-2.0+
+/**
+ * ufs.c - Universal Flash Subsystem (UFS) driver
+ *
+ * Taken from Linux Kernel v5.2 (drivers/scsi/ufs/ufshcd.c) and ported
+ * to u-boot.
+ *
+ * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
+ */
+#include <charset.h>
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <dm/lists.h>
+#include <dm/device-internal.h>
+#include <malloc.h>
+#include <hexdump.h>
+#include <scsi.h>
+#include <asm/io.h>
+#include <asm/dma-mapping.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+
+#include "ufs.h"
+
+#define UFSHCD_ENABLE_INTRS (UTP_TRANSFER_REQ_COMPL |\
+ UTP_TASK_REQ_COMPL |\
+ UFSHCD_ERROR_MASK)
+/* maximum number of link-startup retries */
+#define DME_LINKSTARTUP_RETRIES 3
+
+/* maximum number of retries for a general UIC command */
+#define UFS_UIC_COMMAND_RETRIES 3
+
+/* Query request retries */
+#define QUERY_REQ_RETRIES 3
+/* Query request timeout */
+#define QUERY_REQ_TIMEOUT 1500 /* 1.5 seconds */
+
+/* maximum timeout in ms for a general UIC command */
+#define UFS_UIC_CMD_TIMEOUT 1000
+/* NOP OUT retries waiting for NOP IN response */
+#define NOP_OUT_RETRIES 10
+/* Timeout after 30 msecs if NOP OUT hangs without response */
+#define NOP_OUT_TIMEOUT 30 /* msecs */
+
+/* Only use one Task Tag for all requests */
+#define TASK_TAG 0
+
+/* Expose the flag value from utp_upiu_query.value */
+#define MASK_QUERY_UPIU_FLAG_LOC 0xFF
+
+#define MAX_PRDT_ENTRY 262144
+
+/* maximum bytes per request */
+#define UFS_MAX_BYTES (128 * 256 * 1024)
+
+static inline bool ufshcd_is_hba_active(struct ufs_hba *hba);
+static inline void ufshcd_hba_stop(struct ufs_hba *hba);
+static int ufshcd_hba_enable(struct ufs_hba *hba);
+
+/*
+ * ufshcd_wait_for_register - wait for register value to change
+ */
+static int ufshcd_wait_for_register(struct ufs_hba *hba, u32 reg, u32 mask,
+ u32 val, unsigned long timeout_ms)
+{
+ int err = 0;
+ unsigned long start = get_timer(0);
+
+ /* ignore bits that we don't intend to wait on */
+ val = val & mask;
+
+ while ((ufshcd_readl(hba, reg) & mask) != val) {
+ if (get_timer(start) > timeout_ms) {
+ if ((ufshcd_readl(hba, reg) & mask) != val)
+ err = -ETIMEDOUT;
+ break;
+ }
+ }
+
+ return err;
+}
+
+/**
+ * ufshcd_init_pwr_info - setting the POR (power on reset)
+ * values in hba power info
+ */
+static void ufshcd_init_pwr_info(struct ufs_hba *hba)
+{
+ hba->pwr_info.gear_rx = UFS_PWM_G1;
+ hba->pwr_info.gear_tx = UFS_PWM_G1;
+ hba->pwr_info.lane_rx = 1;
+ hba->pwr_info.lane_tx = 1;
+ hba->pwr_info.pwr_rx = SLOWAUTO_MODE;
+ hba->pwr_info.pwr_tx = SLOWAUTO_MODE;
+ hba->pwr_info.hs_rate = 0;
+}
+
+/**
+ * ufshcd_print_pwr_info - print power params as saved in hba
+ * power info
+ */
+static void ufshcd_print_pwr_info(struct ufs_hba *hba)
+{
+ static const char * const names[] = {
+ "INVALID MODE",
+ "FAST MODE",
+ "SLOW_MODE",
+ "INVALID MODE",
+ "FASTAUTO_MODE",
+ "SLOWAUTO_MODE",
+ "INVALID MODE",
+ };
+
+ dev_err(hba->dev, "[RX, TX]: gear=[%d, %d], lane[%d, %d], pwr[%s, %s], rate = %d\n",
+ hba->pwr_info.gear_rx, hba->pwr_info.gear_tx,
+ hba->pwr_info.lane_rx, hba->pwr_info.lane_tx,
+ names[hba->pwr_info.pwr_rx],
+ names[hba->pwr_info.pwr_tx],
+ hba->pwr_info.hs_rate);
+}
+
+/**
+ * ufshcd_ready_for_uic_cmd - Check if controller is ready
+ * to accept UIC commands
+ */
+static inline bool ufshcd_ready_for_uic_cmd(struct ufs_hba *hba)
+{
+ if (ufshcd_readl(hba, REG_CONTROLLER_STATUS) & UIC_COMMAND_READY)
+ return true;
+ else
+ return false;
+}
+
+/**
+ * ufshcd_get_uic_cmd_result - Get the UIC command result
+ */
+static inline int ufshcd_get_uic_cmd_result(struct ufs_hba *hba)
+{
+ return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_2) &
+ MASK_UIC_COMMAND_RESULT;
+}
+
+/**
+ * ufshcd_get_dme_attr_val - Get the value of attribute returned by UIC command
+ */
+static inline u32 ufshcd_get_dme_attr_val(struct ufs_hba *hba)
+{
+ return ufshcd_readl(hba, REG_UIC_COMMAND_ARG_3);
+}
+
+/**
+ * ufshcd_is_device_present - Check if any device connected to
+ * the host controller
+ */
+static inline bool ufshcd_is_device_present(struct ufs_hba *hba)
+{
+ return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) &
+ DEVICE_PRESENT) ? true : false;
+}
+
+/**
+ * ufshcd_send_uic_cmd - UFS Interconnect layer command API
+ *
+ */
+static int ufshcd_send_uic_cmd(struct ufs_hba *hba, struct uic_command *uic_cmd)
+{
+ unsigned long start = 0;
+ u32 intr_status;
+ u32 enabled_intr_status;
+
+ if (!ufshcd_ready_for_uic_cmd(hba)) {
+ dev_err(hba->dev,
+ "Controller not ready to accept UIC commands\n");
+ return -EIO;
+ }
+
+ debug("sending uic command:%d\n", uic_cmd->command);
+
+ /* Write Args */
+ ufshcd_writel(hba, uic_cmd->argument1, REG_UIC_COMMAND_ARG_1);
+ ufshcd_writel(hba, uic_cmd->argument2, REG_UIC_COMMAND_ARG_2);
+ ufshcd_writel(hba, uic_cmd->argument3, REG_UIC_COMMAND_ARG_3);
+
+ /* Write UIC Cmd */
+ ufshcd_writel(hba, uic_cmd->command & COMMAND_OPCODE_MASK,
+ REG_UIC_COMMAND);
+
+ start = get_timer(0);
+ do {
+ intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
+ enabled_intr_status = intr_status & hba->intr_mask;
+ ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
+
+ if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
+ dev_err(hba->dev,
+ "Timedout waiting for UIC response\n");
+
+ return -ETIMEDOUT;
+ }
+
+ if (enabled_intr_status & UFSHCD_ERROR_MASK) {
+ dev_err(hba->dev, "Error in status:%08x\n",
+ enabled_intr_status);
+
+ return -1;
+ }
+ } while (!(enabled_intr_status & UFSHCD_UIC_MASK));
+
+ uic_cmd->argument2 = ufshcd_get_uic_cmd_result(hba);
+ uic_cmd->argument3 = ufshcd_get_dme_attr_val(hba);
+
+ debug("Sent successfully\n");
+
+ return 0;
+}
+
+/**
+ * ufshcd_dme_set_attr - UIC command for DME_SET, DME_PEER_SET
+ *
+ */
+int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel, u8 attr_set,
+ u32 mib_val, u8 peer)
+{
+ struct uic_command uic_cmd = {0};
+ static const char *const action[] = {
+ "dme-set",
+ "dme-peer-set"
+ };
+ const char *set = action[!!peer];
+ int ret;
+ int retries = UFS_UIC_COMMAND_RETRIES;
+
+ uic_cmd.command = peer ?
+ UIC_CMD_DME_PEER_SET : UIC_CMD_DME_SET;
+ uic_cmd.argument1 = attr_sel;
+ uic_cmd.argument2 = UIC_ARG_ATTR_TYPE(attr_set);
+ uic_cmd.argument3 = mib_val;
+
+ do {
+ /* for peer attributes we retry upon failure */
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_dbg(hba->dev, "%s: attr-id 0x%x val 0x%x error code %d\n",
+ set, UIC_GET_ATTR_ID(attr_sel), mib_val, ret);
+ } while (ret && peer && --retries);
+
+ if (ret)
+ dev_err(hba->dev, "%s: attr-id 0x%x val 0x%x failed %d retries\n",
+ set, UIC_GET_ATTR_ID(attr_sel), mib_val,
+ UFS_UIC_COMMAND_RETRIES - retries);
+
+ return ret;
+}
+
+/**
+ * ufshcd_dme_get_attr - UIC command for DME_GET, DME_PEER_GET
+ *
+ */
+int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
+ u32 *mib_val, u8 peer)
+{
+ struct uic_command uic_cmd = {0};
+ static const char *const action[] = {
+ "dme-get",
+ "dme-peer-get"
+ };
+ const char *get = action[!!peer];
+ int ret;
+ int retries = UFS_UIC_COMMAND_RETRIES;
+
+ uic_cmd.command = peer ?
+ UIC_CMD_DME_PEER_GET : UIC_CMD_DME_GET;
+ uic_cmd.argument1 = attr_sel;
+
+ do {
+ /* for peer attributes we retry upon failure */
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_dbg(hba->dev, "%s: attr-id 0x%x error code %d\n",
+ get, UIC_GET_ATTR_ID(attr_sel), ret);
+ } while (ret && peer && --retries);
+
+ if (ret)
+ dev_err(hba->dev, "%s: attr-id 0x%x failed %d retries\n",
+ get, UIC_GET_ATTR_ID(attr_sel),
+ UFS_UIC_COMMAND_RETRIES - retries);
+
+ if (mib_val && !ret)
+ *mib_val = uic_cmd.argument3;
+
+ return ret;
+}
+
+static int ufshcd_disable_tx_lcc(struct ufs_hba *hba, bool peer)
+{
+ u32 tx_lanes, i, err = 0;
+
+ if (!peer)
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
+ &tx_lanes);
+ else
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
+ &tx_lanes);
+ for (i = 0; i < tx_lanes; i++) {
+ if (!peer)
+ err = ufshcd_dme_set(hba,
+ UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
+ 0);
+ else
+ err = ufshcd_dme_peer_set(hba,
+ UIC_ARG_MIB_SEL(TX_LCC_ENABLE,
+ UIC_ARG_MPHY_TX_GEN_SEL_INDEX(i)),
+ 0);
+ if (err) {
+ dev_err(hba->dev, "%s: TX LCC Disable failed, peer = %d, lane = %d, err = %d",
+ __func__, peer, i, err);
+ break;
+ }
+ }
+
+ return err;
+}
+
+static inline int ufshcd_disable_device_tx_lcc(struct ufs_hba *hba)
+{
+ return ufshcd_disable_tx_lcc(hba, true);
+}
+
+/**
+ * ufshcd_dme_link_startup - Notify Unipro to perform link startup
+ *
+ */
+static int ufshcd_dme_link_startup(struct ufs_hba *hba)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_LINK_STARTUP;
+
+ ret = ufshcd_send_uic_cmd(hba, &uic_cmd);
+ if (ret)
+ dev_dbg(hba->dev,
+ "dme-link-startup: error code %d\n", ret);
+ return ret;
+}
+
+/**
+ * ufshcd_disable_intr_aggr - Disables interrupt aggregation.
+ *
+ */
+static inline void ufshcd_disable_intr_aggr(struct ufs_hba *hba)
+{
+ ufshcd_writel(hba, 0, REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL);
+}
+
+/**
+ * ufshcd_get_lists_status - Check UCRDY, UTRLRDY and UTMRLRDY
+ */
+static inline int ufshcd_get_lists_status(u32 reg)
+{
+ return !((reg & UFSHCD_STATUS_READY) == UFSHCD_STATUS_READY);
+}
+
+/**
+ * ufshcd_enable_run_stop_reg - Enable run-stop registers,
+ * When run-stop registers are set to 1, it indicates the
+ * host controller that it can process the requests
+ */
+static void ufshcd_enable_run_stop_reg(struct ufs_hba *hba)
+{
+ ufshcd_writel(hba, UTP_TASK_REQ_LIST_RUN_STOP_BIT,
+ REG_UTP_TASK_REQ_LIST_RUN_STOP);
+ ufshcd_writel(hba, UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT,
+ REG_UTP_TRANSFER_REQ_LIST_RUN_STOP);
+}
+
+/**
+ * ufshcd_enable_intr - enable interrupts
+ */
+static void ufshcd_enable_intr(struct ufs_hba *hba, u32 intrs)
+{
+ u32 set = ufshcd_readl(hba, REG_INTERRUPT_ENABLE);
+ u32 rw;
+
+ if (hba->version == UFSHCI_VERSION_10) {
+ rw = set & INTERRUPT_MASK_RW_VER_10;
+ set = rw | ((set ^ intrs) & intrs);
+ } else {
+ set |= intrs;
+ }
+
+ ufshcd_writel(hba, set, REG_INTERRUPT_ENABLE);
+
+ hba->intr_mask = set;
+}
+
+/**
+ * ufshcd_make_hba_operational - Make UFS controller operational
+ *
+ * To bring UFS host controller to operational state,
+ * 1. Enable required interrupts
+ * 2. Configure interrupt aggregation
+ * 3. Program UTRL and UTMRL base address
+ * 4. Configure run-stop-registers
+ *
+ */
+static int ufshcd_make_hba_operational(struct ufs_hba *hba)
+{
+ int err = 0;
+ u32 reg;
+
+ /* Enable required interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_ENABLE_INTRS);
+
+ /* Disable interrupt aggregation */
+ ufshcd_disable_intr_aggr(hba);
+
+ /* Configure UTRL and UTMRL base address registers */
+ ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utrdl),
+ REG_UTP_TRANSFER_REQ_LIST_BASE_L);
+ ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utrdl),
+ REG_UTP_TRANSFER_REQ_LIST_BASE_H);
+ ufshcd_writel(hba, lower_32_bits((dma_addr_t)hba->utmrdl),
+ REG_UTP_TASK_REQ_LIST_BASE_L);
+ ufshcd_writel(hba, upper_32_bits((dma_addr_t)hba->utmrdl),
+ REG_UTP_TASK_REQ_LIST_BASE_H);
+
+ /*
+ * UCRDY, UTMRLDY and UTRLRDY bits must be 1
+ */
+ reg = ufshcd_readl(hba, REG_CONTROLLER_STATUS);
+ if (!(ufshcd_get_lists_status(reg))) {
+ ufshcd_enable_run_stop_reg(hba);
+ } else {
+ dev_err(hba->dev,
+ "Host controller not ready to process requests");
+ err = -EIO;
+ goto out;
+ }
+
+out:
+ return err;
+}
+
+/**
+ * ufshcd_link_startup - Initialize unipro link startup
+ */
+static int ufshcd_link_startup(struct ufs_hba *hba)
+{
+ int ret;
+ int retries = DME_LINKSTARTUP_RETRIES;
+ bool link_startup_again = true;
+
+link_startup:
+ do {
+ ufshcd_ops_link_startup_notify(hba, PRE_CHANGE);
+
+ ret = ufshcd_dme_link_startup(hba);
+
+ /* check if device is detected by inter-connect layer */
+ if (!ret && !ufshcd_is_device_present(hba)) {
+ dev_err(hba->dev, "%s: Device not present\n", __func__);
+ ret = -ENXIO;
+ goto out;
+ }
+
+ /*
+ * DME link lost indication is only received when link is up,
+ * but we can't be sure if the link is up until link startup
+ * succeeds. So reset the local Uni-Pro and try again.
+ */
+ if (ret && ufshcd_hba_enable(hba))
+ goto out;
+ } while (ret && retries--);
+
+ if (ret)
+ /* failed to get the link up... retire */
+ goto out;
+
+ if (link_startup_again) {
+ link_startup_again = false;
+ retries = DME_LINKSTARTUP_RETRIES;
+ goto link_startup;
+ }
+
+ /* Mark that link is up in PWM-G1, 1-lane, SLOW-AUTO mode */
+ ufshcd_init_pwr_info(hba);
+
+ if (hba->quirks & UFSHCD_QUIRK_BROKEN_LCC) {
+ ret = ufshcd_disable_device_tx_lcc(hba);
+ if (ret)
+ goto out;
+ }
+
+ /* Include any host controller configuration via UIC commands */
+ ret = ufshcd_ops_link_startup_notify(hba, POST_CHANGE);
+ if (ret)
+ goto out;
+
+ ret = ufshcd_make_hba_operational(hba);
+out:
+ if (ret)
+ dev_err(hba->dev, "link startup failed %d\n", ret);
+
+ return ret;
+}
+
+/**
+ * ufshcd_hba_stop - Send controller to reset state
+ */
+static inline void ufshcd_hba_stop(struct ufs_hba *hba)
+{
+ int err;
+
+ ufshcd_writel(hba, CONTROLLER_DISABLE, REG_CONTROLLER_ENABLE);
+ err = ufshcd_wait_for_register(hba, REG_CONTROLLER_ENABLE,
+ CONTROLLER_ENABLE, CONTROLLER_DISABLE,
+ 10);
+ if (err)
+ dev_err(hba->dev, "%s: Controller disable failed\n", __func__);
+}
+
+/**
+ * ufshcd_is_hba_active - Get controller state
+ */
+static inline bool ufshcd_is_hba_active(struct ufs_hba *hba)
+{
+ return (ufshcd_readl(hba, REG_CONTROLLER_ENABLE) & CONTROLLER_ENABLE)
+ ? false : true;
+}
+
+/**
+ * ufshcd_hba_start - Start controller initialization sequence
+ */
+static inline void ufshcd_hba_start(struct ufs_hba *hba)
+{
+ ufshcd_writel(hba, CONTROLLER_ENABLE, REG_CONTROLLER_ENABLE);
+}
+
+/**
+ * ufshcd_hba_enable - initialize the controller
+ */
+static int ufshcd_hba_enable(struct ufs_hba *hba)
+{
+ int retry;
+
+ if (!ufshcd_is_hba_active(hba))
+ /* change controller state to "reset state" */
+ ufshcd_hba_stop(hba);
+
+ ufshcd_ops_hce_enable_notify(hba, PRE_CHANGE);
+
+ /* start controller initialization sequence */
+ ufshcd_hba_start(hba);
+
+ /*
+ * To initialize a UFS host controller HCE bit must be set to 1.
+ * During initialization the HCE bit value changes from 1->0->1.
+ * When the host controller completes initialization sequence
+ * it sets the value of HCE bit to 1. The same HCE bit is read back
+ * to check if the controller has completed initialization sequence.
+ * So without this delay the value HCE = 1, set in the previous
+ * instruction might be read back.
+ * This delay can be changed based on the controller.
+ */
+ mdelay(1);
+
+ /* wait for the host controller to complete initialization */
+ retry = 10;
+ while (ufshcd_is_hba_active(hba)) {
+ if (retry) {
+ retry--;
+ } else {
+ dev_err(hba->dev, "Controller enable failed\n");
+ return -EIO;
+ }
+ mdelay(5);
+ }
+
+ /* enable UIC related interrupts */
+ ufshcd_enable_intr(hba, UFSHCD_UIC_MASK);
+
+ ufshcd_ops_hce_enable_notify(hba, POST_CHANGE);
+
+ return 0;
+}
+
+/**
+ * ufshcd_host_memory_configure - configure local reference block with
+ * memory offsets
+ */
+static void ufshcd_host_memory_configure(struct ufs_hba *hba)
+{
+ struct utp_transfer_req_desc *utrdlp;
+ dma_addr_t cmd_desc_dma_addr;
+ u16 response_offset;
+ u16 prdt_offset;
+
+ utrdlp = hba->utrdl;
+ cmd_desc_dma_addr = (dma_addr_t)hba->ucdl;
+
+ utrdlp->command_desc_base_addr_lo =
+ cpu_to_le32(lower_32_bits(cmd_desc_dma_addr));
+ utrdlp->command_desc_base_addr_hi =
+ cpu_to_le32(upper_32_bits(cmd_desc_dma_addr));
+
+ response_offset = offsetof(struct utp_transfer_cmd_desc, response_upiu);
+ prdt_offset = offsetof(struct utp_transfer_cmd_desc, prd_table);
+
+ utrdlp->response_upiu_offset = cpu_to_le16(response_offset >> 2);
+ utrdlp->prd_table_offset = cpu_to_le16(prdt_offset >> 2);
+ utrdlp->response_upiu_length = cpu_to_le16(ALIGNED_UPIU_SIZE >> 2);
+
+ hba->ucd_req_ptr = (struct utp_upiu_req *)hba->ucdl;
+ hba->ucd_rsp_ptr =
+ (struct utp_upiu_rsp *)&hba->ucdl->response_upiu;
+ hba->ucd_prdt_ptr =
+ (struct ufshcd_sg_entry *)&hba->ucdl->prd_table;
+}
+
+/**
+ * ufshcd_memory_alloc - allocate memory for host memory space data structures
+ */
+static int ufshcd_memory_alloc(struct ufs_hba *hba)
+{
+ /* Allocate one Transfer Request Descriptor
+ * Should be aligned to 1k boundary.
+ */
+ hba->utrdl = memalign(1024, sizeof(struct utp_transfer_req_desc));
+ if (!hba->utrdl) {
+ dev_err(hba->dev, "Transfer Descriptor memory allocation failed\n");
+ return -ENOMEM;
+ }
+
+ /* Allocate one Command Descriptor
+ * Should be aligned to 1k boundary.
+ */
+ hba->ucdl = memalign(1024, sizeof(struct utp_transfer_cmd_desc));
+ if (!hba->ucdl) {
+ dev_err(hba->dev, "Command descriptor memory allocation failed\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+/**
+ * ufshcd_get_intr_mask - Get the interrupt bit mask
+ */
+static inline u32 ufshcd_get_intr_mask(struct ufs_hba *hba)
+{
+ u32 intr_mask = 0;
+
+ switch (hba->version) {
+ case UFSHCI_VERSION_10:
+ intr_mask = INTERRUPT_MASK_ALL_VER_10;
+ break;
+ case UFSHCI_VERSION_11:
+ case UFSHCI_VERSION_20:
+ intr_mask = INTERRUPT_MASK_ALL_VER_11;
+ break;
+ case UFSHCI_VERSION_21:
+ default:
+ intr_mask = INTERRUPT_MASK_ALL_VER_21;
+ break;
+ }
+
+ return intr_mask;
+}
+
+/**
+ * ufshcd_get_ufs_version - Get the UFS version supported by the HBA
+ */
+static inline u32 ufshcd_get_ufs_version(struct ufs_hba *hba)
+{
+ return ufshcd_readl(hba, REG_UFS_VERSION);
+}
+
+/**
+ * ufshcd_get_upmcrs - Get the power mode change request status
+ */
+static inline u8 ufshcd_get_upmcrs(struct ufs_hba *hba)
+{
+ return (ufshcd_readl(hba, REG_CONTROLLER_STATUS) >> 8) & 0x7;
+}
+
+/**
+ * ufshcd_prepare_req_desc_hdr() - Fills the requests header
+ * descriptor according to request
+ */
+static void ufshcd_prepare_req_desc_hdr(struct utp_transfer_req_desc *req_desc,
+ u32 *upiu_flags,
+ enum dma_data_direction cmd_dir)
+{
+ u32 data_direction;
+ u32 dword_0;
+
+ if (cmd_dir == DMA_FROM_DEVICE) {
+ data_direction = UTP_DEVICE_TO_HOST;
+ *upiu_flags = UPIU_CMD_FLAGS_READ;
+ } else if (cmd_dir == DMA_TO_DEVICE) {
+ data_direction = UTP_HOST_TO_DEVICE;
+ *upiu_flags = UPIU_CMD_FLAGS_WRITE;
+ } else {
+ data_direction = UTP_NO_DATA_TRANSFER;
+ *upiu_flags = UPIU_CMD_FLAGS_NONE;
+ }
+
+ dword_0 = data_direction | (0x1 << UPIU_COMMAND_TYPE_OFFSET);
+
+ /* Enable Interrupt for command */
+ dword_0 |= UTP_REQ_DESC_INT_CMD;
+
+ /* Transfer request descriptor header fields */
+ req_desc->header.dword_0 = cpu_to_le32(dword_0);
+ /* dword_1 is reserved, hence it is set to 0 */
+ req_desc->header.dword_1 = 0;
+ /*
+ * assigning invalid value for command status. Controller
+ * updates OCS on command completion, with the command
+ * status
+ */
+ req_desc->header.dword_2 =
+ cpu_to_le32(OCS_INVALID_COMMAND_STATUS);
+ /* dword_3 is reserved, hence it is set to 0 */
+ req_desc->header.dword_3 = 0;
+
+ req_desc->prd_table_length = 0;
+}
+
+static void ufshcd_prepare_utp_query_req_upiu(struct ufs_hba *hba,
+ u32 upiu_flags)
+{
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
+ struct ufs_query *query = &hba->dev_cmd.query;
+ u16 len = be16_to_cpu(query->request.upiu_req.length);
+
+ /* Query request header */
+ ucd_req_ptr->header.dword_0 =
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_QUERY_REQ,
+ upiu_flags, 0, TASK_TAG);
+ ucd_req_ptr->header.dword_1 =
+ UPIU_HEADER_DWORD(0, query->request.query_func,
+ 0, 0);
+
+ /* Data segment length only need for WRITE_DESC */
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
+ ucd_req_ptr->header.dword_2 =
+ UPIU_HEADER_DWORD(0, 0, (len >> 8), (u8)len);
+ else
+ ucd_req_ptr->header.dword_2 = 0;
+
+ /* Copy the Query Request buffer as is */
+ memcpy(&ucd_req_ptr->qr, &query->request.upiu_req, QUERY_OSF_SIZE);
+
+ /* Copy the Descriptor */
+ if (query->request.upiu_req.opcode == UPIU_QUERY_OPCODE_WRITE_DESC)
+ memcpy(ucd_req_ptr + 1, query->descriptor, len);
+
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+}
+
+static inline void ufshcd_prepare_utp_nop_upiu(struct ufs_hba *hba)
+{
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
+
+ memset(ucd_req_ptr, 0, sizeof(struct utp_upiu_req));
+
+ /* command descriptor fields */
+ ucd_req_ptr->header.dword_0 =
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_NOP_OUT, 0, 0, TASK_TAG);
+ /* clear rest of the fields of basic header */
+ ucd_req_ptr->header.dword_1 = 0;
+ ucd_req_ptr->header.dword_2 = 0;
+
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+}
+
+/**
+ * ufshcd_comp_devman_upiu - UFS Protocol Information Unit(UPIU)
+ * for Device Management Purposes
+ */
+static int ufshcd_comp_devman_upiu(struct ufs_hba *hba,
+ enum dev_cmd_type cmd_type)
+{
+ u32 upiu_flags;
+ int ret = 0;
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
+
+ hba->dev_cmd.type = cmd_type;
+
+ ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, DMA_NONE);
+ switch (cmd_type) {
+ case DEV_CMD_TYPE_QUERY:
+ ufshcd_prepare_utp_query_req_upiu(hba, upiu_flags);
+ break;
+ case DEV_CMD_TYPE_NOP:
+ ufshcd_prepare_utp_nop_upiu(hba);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+static int ufshcd_send_command(struct ufs_hba *hba, unsigned int task_tag)
+{
+ unsigned long start;
+ u32 intr_status;
+ u32 enabled_intr_status;
+
+ ufshcd_writel(hba, 1 << task_tag, REG_UTP_TRANSFER_REQ_DOOR_BELL);
+
+ start = get_timer(0);
+ do {
+ intr_status = ufshcd_readl(hba, REG_INTERRUPT_STATUS);
+ enabled_intr_status = intr_status & hba->intr_mask;
+ ufshcd_writel(hba, intr_status, REG_INTERRUPT_STATUS);
+
+ if (get_timer(start) > QUERY_REQ_TIMEOUT) {
+ dev_err(hba->dev,
+ "Timedout waiting for UTP response\n");
+
+ return -ETIMEDOUT;
+ }
+
+ if (enabled_intr_status & UFSHCD_ERROR_MASK) {
+ dev_err(hba->dev, "Error in status:%08x\n",
+ enabled_intr_status);
+
+ return -1;
+ }
+ } while (!(enabled_intr_status & UTP_TRANSFER_REQ_COMPL));
+
+ return 0;
+}
+
+/**
+ * ufshcd_get_req_rsp - returns the TR response transaction type
+ */
+static inline int ufshcd_get_req_rsp(struct utp_upiu_rsp *ucd_rsp_ptr)
+{
+ return be32_to_cpu(ucd_rsp_ptr->header.dword_0) >> 24;
+}
+
+/**
+ * ufshcd_get_tr_ocs - Get the UTRD Overall Command Status
+ *
+ */
+static inline int ufshcd_get_tr_ocs(struct ufs_hba *hba)
+{
+ return le32_to_cpu(hba->utrdl->header.dword_2) & MASK_OCS;
+}
+
+static inline int ufshcd_get_rsp_upiu_result(struct utp_upiu_rsp *ucd_rsp_ptr)
+{
+ return be32_to_cpu(ucd_rsp_ptr->header.dword_1) & MASK_RSP_UPIU_RESULT;
+}
+
+static int ufshcd_check_query_response(struct ufs_hba *hba)
+{
+ struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
+
+ /* Get the UPIU response */
+ query_res->response = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr) >>
+ UPIU_RSP_CODE_OFFSET;
+ return query_res->response;
+}
+
+/**
+ * ufshcd_copy_query_response() - Copy the Query Response and the data
+ * descriptor
+ */
+static int ufshcd_copy_query_response(struct ufs_hba *hba)
+{
+ struct ufs_query_res *query_res = &hba->dev_cmd.query.response;
+
+ memcpy(&query_res->upiu_res, &hba->ucd_rsp_ptr->qr, QUERY_OSF_SIZE);
+
+ /* Get the descriptor */
+ if (hba->dev_cmd.query.descriptor &&
+ hba->ucd_rsp_ptr->qr.opcode == UPIU_QUERY_OPCODE_READ_DESC) {
+ u8 *descp = (u8 *)hba->ucd_rsp_ptr +
+ GENERAL_UPIU_REQUEST_SIZE;
+ u16 resp_len;
+ u16 buf_len;
+
+ /* data segment length */
+ resp_len = be32_to_cpu(hba->ucd_rsp_ptr->header.dword_2) &
+ MASK_QUERY_DATA_SEG_LEN;
+ buf_len =
+ be16_to_cpu(hba->dev_cmd.query.request.upiu_req.length);
+ if (likely(buf_len >= resp_len)) {
+ memcpy(hba->dev_cmd.query.descriptor, descp, resp_len);
+ } else {
+ dev_warn(hba->dev,
+ "%s: Response size is bigger than buffer",
+ __func__);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * ufshcd_exec_dev_cmd - API for sending device management requests
+ */
+static int ufshcd_exec_dev_cmd(struct ufs_hba *hba, enum dev_cmd_type cmd_type,
+ int timeout)
+{
+ int err;
+ int resp;
+
+ err = ufshcd_comp_devman_upiu(hba, cmd_type);
+ if (err)
+ return err;
+
+ err = ufshcd_send_command(hba, TASK_TAG);
+ if (err)
+ return err;
+
+ err = ufshcd_get_tr_ocs(hba);
+ if (err) {
+ dev_err(hba->dev, "Error in OCS:%d\n", err);
+ return -EINVAL;
+ }
+
+ resp = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
+ switch (resp) {
+ case UPIU_TRANSACTION_NOP_IN:
+ break;
+ case UPIU_TRANSACTION_QUERY_RSP:
+ err = ufshcd_check_query_response(hba);
+ if (!err)
+ err = ufshcd_copy_query_response(hba);
+ break;
+ case UPIU_TRANSACTION_REJECT_UPIU:
+ /* TODO: handle Reject UPIU Response */
+ err = -EPERM;
+ dev_err(hba->dev, "%s: Reject UPIU not fully implemented\n",
+ __func__);
+ break;
+ default:
+ err = -EINVAL;
+ dev_err(hba->dev, "%s: Invalid device management cmd response: %x\n",
+ __func__, resp);
+ }
+
+ return err;
+}
+
+/**
+ * ufshcd_init_query() - init the query response and request parameters
+ */
+static inline void ufshcd_init_query(struct ufs_hba *hba,
+ struct ufs_query_req **request,
+ struct ufs_query_res **response,
+ enum query_opcode opcode,
+ u8 idn, u8 index, u8 selector)
+{
+ *request = &hba->dev_cmd.query.request;
+ *response = &hba->dev_cmd.query.response;
+ memset(*request, 0, sizeof(struct ufs_query_req));
+ memset(*response, 0, sizeof(struct ufs_query_res));
+ (*request)->upiu_req.opcode = opcode;
+ (*request)->upiu_req.idn = idn;
+ (*request)->upiu_req.index = index;
+ (*request)->upiu_req.selector = selector;
+}
+
+/**
+ * ufshcd_query_flag() - API function for sending flag query requests
+ */
+int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
+ enum flag_idn idn, bool *flag_res)
+{
+ struct ufs_query_req *request = NULL;
+ struct ufs_query_res *response = NULL;
+ int err, index = 0, selector = 0;
+ int timeout = QUERY_REQ_TIMEOUT;
+
+ ufshcd_init_query(hba, &request, &response, opcode, idn, index,
+ selector);
+
+ switch (opcode) {
+ case UPIU_QUERY_OPCODE_SET_FLAG:
+ case UPIU_QUERY_OPCODE_CLEAR_FLAG:
+ case UPIU_QUERY_OPCODE_TOGGLE_FLAG:
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
+ break;
+ case UPIU_QUERY_OPCODE_READ_FLAG:
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
+ if (!flag_res) {
+ /* No dummy reads */
+ dev_err(hba->dev, "%s: Invalid argument for read request\n",
+ __func__);
+ err = -EINVAL;
+ goto out;
+ }
+ break;
+ default:
+ dev_err(hba->dev,
+ "%s: Expected query flag opcode but got = %d\n",
+ __func__, opcode);
+ err = -EINVAL;
+ goto out;
+ }
+
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, timeout);
+
+ if (err) {
+ dev_err(hba->dev,
+ "%s: Sending flag query for idn %d failed, err = %d\n",
+ __func__, idn, err);
+ goto out;
+ }
+
+ if (flag_res)
+ *flag_res = (be32_to_cpu(response->upiu_res.value) &
+ MASK_QUERY_UPIU_FLAG_LOC) & 0x1;
+
+out:
+ return err;
+}
+
+static int ufshcd_query_flag_retry(struct ufs_hba *hba,
+ enum query_opcode opcode,
+ enum flag_idn idn, bool *flag_res)
+{
+ int ret;
+ int retries;
+
+ for (retries = 0; retries < QUERY_REQ_RETRIES; retries++) {
+ ret = ufshcd_query_flag(hba, opcode, idn, flag_res);
+ if (ret)
+ dev_dbg(hba->dev,
+ "%s: failed with error %d, retries %d\n",
+ __func__, ret, retries);
+ else
+ break;
+ }
+
+ if (ret)
+ dev_err(hba->dev,
+ "%s: query attribute, opcode %d, idn %d, failed with error %d after %d retires\n",
+ __func__, opcode, idn, ret, retries);
+ return ret;
+}
+
+static int __ufshcd_query_descriptor(struct ufs_hba *hba,
+ enum query_opcode opcode,
+ enum desc_idn idn, u8 index, u8 selector,
+ u8 *desc_buf, int *buf_len)
+{
+ struct ufs_query_req *request = NULL;
+ struct ufs_query_res *response = NULL;
+ int err;
+
+ if (!desc_buf) {
+ dev_err(hba->dev, "%s: descriptor buffer required for opcode 0x%x\n",
+ __func__, opcode);
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (*buf_len < QUERY_DESC_MIN_SIZE || *buf_len > QUERY_DESC_MAX_SIZE) {
+ dev_err(hba->dev, "%s: descriptor buffer size (%d) is out of range\n",
+ __func__, *buf_len);
+ err = -EINVAL;
+ goto out;
+ }
+
+ ufshcd_init_query(hba, &request, &response, opcode, idn, index,
+ selector);
+ hba->dev_cmd.query.descriptor = desc_buf;
+ request->upiu_req.length = cpu_to_be16(*buf_len);
+
+ switch (opcode) {
+ case UPIU_QUERY_OPCODE_WRITE_DESC:
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST;
+ break;
+ case UPIU_QUERY_OPCODE_READ_DESC:
+ request->query_func = UPIU_QUERY_FUNC_STANDARD_READ_REQUEST;
+ break;
+ default:
+ dev_err(hba->dev, "%s: Expected query descriptor opcode but got = 0x%.2x\n",
+ __func__, opcode);
+ err = -EINVAL;
+ goto out;
+ }
+
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_QUERY, QUERY_REQ_TIMEOUT);
+
+ if (err) {
+ dev_err(hba->dev, "%s: opcode 0x%.2x for idn %d failed, index %d, err = %d\n",
+ __func__, opcode, idn, index, err);
+ goto out;
+ }
+
+ hba->dev_cmd.query.descriptor = NULL;
+ *buf_len = be16_to_cpu(response->upiu_res.length);
+
+out:
+ return err;
+}
+
+/**
+ * ufshcd_query_descriptor_retry - API function for sending descriptor requests
+ */
+int ufshcd_query_descriptor_retry(struct ufs_hba *hba, enum query_opcode opcode,
+ enum desc_idn idn, u8 index, u8 selector,
+ u8 *desc_buf, int *buf_len)
+{
+ int err;
+ int retries;
+
+ for (retries = QUERY_REQ_RETRIES; retries > 0; retries--) {
+ err = __ufshcd_query_descriptor(hba, opcode, idn, index,
+ selector, desc_buf, buf_len);
+ if (!err || err == -EINVAL)
+ break;
+ }
+
+ return err;
+}
+
+/**
+ * ufshcd_read_desc_length - read the specified descriptor length from header
+ */
+static int ufshcd_read_desc_length(struct ufs_hba *hba, enum desc_idn desc_id,
+ int desc_index, int *desc_length)
+{
+ int ret;
+ u8 header[QUERY_DESC_HDR_SIZE];
+ int header_len = QUERY_DESC_HDR_SIZE;
+
+ if (desc_id >= QUERY_DESC_IDN_MAX)
+ return -EINVAL;
+
+ ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
+ desc_id, desc_index, 0, header,
+ &header_len);
+
+ if (ret) {
+ dev_err(hba->dev, "%s: Failed to get descriptor header id %d",
+ __func__, desc_id);
+ return ret;
+ } else if (desc_id != header[QUERY_DESC_DESC_TYPE_OFFSET]) {
+ dev_warn(hba->dev, "%s: descriptor header id %d and desc_id %d mismatch",
+ __func__, header[QUERY_DESC_DESC_TYPE_OFFSET],
+ desc_id);
+ ret = -EINVAL;
+ }
+
+ *desc_length = header[QUERY_DESC_LENGTH_OFFSET];
+
+ return ret;
+}
+
+static void ufshcd_init_desc_sizes(struct ufs_hba *hba)
+{
+ int err;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_DEVICE, 0,
+ &hba->desc_size.dev_desc);
+ if (err)
+ hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_POWER, 0,
+ &hba->desc_size.pwr_desc);
+ if (err)
+ hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_INTERCONNECT, 0,
+ &hba->desc_size.interc_desc);
+ if (err)
+ hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_CONFIGURATION, 0,
+ &hba->desc_size.conf_desc);
+ if (err)
+ hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_UNIT, 0,
+ &hba->desc_size.unit_desc);
+ if (err)
+ hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_GEOMETRY, 0,
+ &hba->desc_size.geom_desc);
+ if (err)
+ hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
+
+ err = ufshcd_read_desc_length(hba, QUERY_DESC_IDN_HEALTH, 0,
+ &hba->desc_size.hlth_desc);
+ if (err)
+ hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
+}
+
+/**
+ * ufshcd_map_desc_id_to_length - map descriptor IDN to its length
+ *
+ */
+int ufshcd_map_desc_id_to_length(struct ufs_hba *hba, enum desc_idn desc_id,
+ int *desc_len)
+{
+ switch (desc_id) {
+ case QUERY_DESC_IDN_DEVICE:
+ *desc_len = hba->desc_size.dev_desc;
+ break;
+ case QUERY_DESC_IDN_POWER:
+ *desc_len = hba->desc_size.pwr_desc;
+ break;
+ case QUERY_DESC_IDN_GEOMETRY:
+ *desc_len = hba->desc_size.geom_desc;
+ break;
+ case QUERY_DESC_IDN_CONFIGURATION:
+ *desc_len = hba->desc_size.conf_desc;
+ break;
+ case QUERY_DESC_IDN_UNIT:
+ *desc_len = hba->desc_size.unit_desc;
+ break;
+ case QUERY_DESC_IDN_INTERCONNECT:
+ *desc_len = hba->desc_size.interc_desc;
+ break;
+ case QUERY_DESC_IDN_STRING:
+ *desc_len = QUERY_DESC_MAX_SIZE;
+ break;
+ case QUERY_DESC_IDN_HEALTH:
+ *desc_len = hba->desc_size.hlth_desc;
+ break;
+ case QUERY_DESC_IDN_RFU_0:
+ case QUERY_DESC_IDN_RFU_1:
+ *desc_len = 0;
+ break;
+ default:
+ *desc_len = 0;
+ return -EINVAL;
+ }
+ return 0;
+}
+EXPORT_SYMBOL(ufshcd_map_desc_id_to_length);
+
+/**
+ * ufshcd_read_desc_param - read the specified descriptor parameter
+ *
+ */
+int ufshcd_read_desc_param(struct ufs_hba *hba, enum desc_idn desc_id,
+ int desc_index, u8 param_offset, u8 *param_read_buf,
+ u8 param_size)
+{
+ int ret;
+ u8 *desc_buf;
+ int buff_len;
+ bool is_kmalloc = true;
+
+ /* Safety check */
+ if (desc_id >= QUERY_DESC_IDN_MAX || !param_size)
+ return -EINVAL;
+
+ /* Get the max length of descriptor from structure filled up at probe
+ * time.
+ */
+ ret = ufshcd_map_desc_id_to_length(hba, desc_id, &buff_len);
+
+ /* Sanity checks */
+ if (ret || !buff_len) {
+ dev_err(hba->dev, "%s: Failed to get full descriptor length",
+ __func__);
+ return ret;
+ }
+
+ /* Check whether we need temp memory */
+ if (param_offset != 0 || param_size < buff_len) {
+ desc_buf = kmalloc(buff_len, GFP_KERNEL);
+ if (!desc_buf)
+ return -ENOMEM;
+ } else {
+ desc_buf = param_read_buf;
+ is_kmalloc = false;
+ }
+
+ /* Request for full descriptor */
+ ret = ufshcd_query_descriptor_retry(hba, UPIU_QUERY_OPCODE_READ_DESC,
+ desc_id, desc_index, 0, desc_buf,
+ &buff_len);
+
+ if (ret) {
+ dev_err(hba->dev, "%s: Failed reading descriptor. desc_id %d, desc_index %d, param_offset %d, ret %d",
+ __func__, desc_id, desc_index, param_offset, ret);
+ goto out;
+ }
+
+ /* Sanity check */
+ if (desc_buf[QUERY_DESC_DESC_TYPE_OFFSET] != desc_id) {
+ dev_err(hba->dev, "%s: invalid desc_id %d in descriptor header",
+ __func__, desc_buf[QUERY_DESC_DESC_TYPE_OFFSET]);
+ ret = -EINVAL;
+ goto out;
+ }
+
+ /* Check wherher we will not copy more data, than available */
+ if (is_kmalloc && param_size > buff_len)
+ param_size = buff_len;
+
+ if (is_kmalloc)
+ memcpy(param_read_buf, &desc_buf[param_offset], param_size);
+out:
+ if (is_kmalloc)
+ kfree(desc_buf);
+ return ret;
+}
+
+/* replace non-printable or non-ASCII characters with spaces */
+static inline void ufshcd_remove_non_printable(uint8_t *val)
+{
+ if (!val)
+ return;
+
+ if (*val < 0x20 || *val > 0x7e)
+ *val = ' ';
+}
+
+/**
+ * ufshcd_uic_pwr_ctrl - executes UIC commands (which affects the link power
+ * state) and waits for it to take effect.
+ *
+ */
+static int ufshcd_uic_pwr_ctrl(struct ufs_hba *hba, struct uic_command *cmd)
+{
+ unsigned long start = 0;
+ u8 status;
+ int ret;
+
+ ret = ufshcd_send_uic_cmd(hba, cmd);
+ if (ret) {
+ dev_err(hba->dev,
+ "pwr ctrl cmd 0x%x with mode 0x%x uic error %d\n",
+ cmd->command, cmd->argument3, ret);
+
+ return ret;
+ }
+
+ start = get_timer(0);
+ do {
+ status = ufshcd_get_upmcrs(hba);
+ if (get_timer(start) > UFS_UIC_CMD_TIMEOUT) {
+ dev_err(hba->dev,
+ "pwr ctrl cmd 0x%x failed, host upmcrs:0x%x\n",
+ cmd->command, status);
+ ret = (status != PWR_OK) ? status : -1;
+ break;
+ }
+ } while (status != PWR_LOCAL);
+
+ return ret;
+}
+
+/**
+ * ufshcd_uic_change_pwr_mode - Perform the UIC power mode change
+ * using DME_SET primitives.
+ */
+static int ufshcd_uic_change_pwr_mode(struct ufs_hba *hba, u8 mode)
+{
+ struct uic_command uic_cmd = {0};
+ int ret;
+
+ uic_cmd.command = UIC_CMD_DME_SET;
+ uic_cmd.argument1 = UIC_ARG_MIB(PA_PWRMODE);
+ uic_cmd.argument3 = mode;
+ ret = ufshcd_uic_pwr_ctrl(hba, &uic_cmd);
+
+ return ret;
+}
+
+static
+void ufshcd_prepare_utp_scsi_cmd_upiu(struct ufs_hba *hba,
+ struct scsi_cmd *pccb, u32 upiu_flags)
+{
+ struct utp_upiu_req *ucd_req_ptr = hba->ucd_req_ptr;
+ unsigned int cdb_len;
+
+ /* command descriptor fields */
+ ucd_req_ptr->header.dword_0 =
+ UPIU_HEADER_DWORD(UPIU_TRANSACTION_COMMAND, upiu_flags,
+ pccb->lun, TASK_TAG);
+ ucd_req_ptr->header.dword_1 =
+ UPIU_HEADER_DWORD(UPIU_COMMAND_SET_TYPE_SCSI, 0, 0, 0);
+
+ /* Total EHS length and Data segment length will be zero */
+ ucd_req_ptr->header.dword_2 = 0;
+
+ ucd_req_ptr->sc.exp_data_transfer_len = cpu_to_be32(pccb->datalen);
+
+ cdb_len = min_t(unsigned short, pccb->cmdlen, UFS_CDB_SIZE);
+ memset(ucd_req_ptr->sc.cdb, 0, UFS_CDB_SIZE);
+ memcpy(ucd_req_ptr->sc.cdb, pccb->cmd, cdb_len);
+
+ memset(hba->ucd_rsp_ptr, 0, sizeof(struct utp_upiu_rsp));
+}
+
+static inline void prepare_prdt_desc(struct ufshcd_sg_entry *entry,
+ unsigned char *buf, ulong len)
+{
+ entry->size = cpu_to_le32(len) | GENMASK(1, 0);
+ entry->base_addr = cpu_to_le32(lower_32_bits((unsigned long)buf));
+ entry->upper_addr = cpu_to_le32(upper_32_bits((unsigned long)buf));
+}
+
+static void prepare_prdt_table(struct ufs_hba *hba, struct scsi_cmd *pccb)
+{
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
+ struct ufshcd_sg_entry *prd_table = hba->ucd_prdt_ptr;
+ ulong datalen = pccb->datalen;
+ int table_length;
+ u8 *buf;
+ int i;
+
+ if (!datalen) {
+ req_desc->prd_table_length = 0;
+ return;
+ }
+
+ table_length = DIV_ROUND_UP(pccb->datalen, MAX_PRDT_ENTRY);
+ buf = pccb->pdata;
+ i = table_length;
+ while (--i) {
+ prepare_prdt_desc(&prd_table[table_length - i - 1], buf,
+ MAX_PRDT_ENTRY - 1);
+ buf += MAX_PRDT_ENTRY;
+ datalen -= MAX_PRDT_ENTRY;
+ }
+
+ prepare_prdt_desc(&prd_table[table_length - i - 1], buf, datalen - 1);
+
+ req_desc->prd_table_length = table_length;
+}
+
+static int ufs_scsi_exec(struct udevice *scsi_dev, struct scsi_cmd *pccb)
+{
+ struct ufs_hba *hba = dev_get_uclass_priv(scsi_dev->parent);
+ struct utp_transfer_req_desc *req_desc = hba->utrdl;
+ u32 upiu_flags;
+ int ocs, result = 0;
+ u8 scsi_status;
+
+ ufshcd_prepare_req_desc_hdr(req_desc, &upiu_flags, pccb->dma_dir);
+ ufshcd_prepare_utp_scsi_cmd_upiu(hba, pccb, upiu_flags);
+ prepare_prdt_table(hba, pccb);
+
+ ufshcd_send_command(hba, TASK_TAG);
+
+ ocs = ufshcd_get_tr_ocs(hba);
+ switch (ocs) {
+ case OCS_SUCCESS:
+ result = ufshcd_get_req_rsp(hba->ucd_rsp_ptr);
+ switch (result) {
+ case UPIU_TRANSACTION_RESPONSE:
+ result = ufshcd_get_rsp_upiu_result(hba->ucd_rsp_ptr);
+
+ scsi_status = result & MASK_SCSI_STATUS;
+ if (scsi_status)
+ return -EINVAL;
+
+ break;
+ case UPIU_TRANSACTION_REJECT_UPIU:
+ /* TODO: handle Reject UPIU Response */
+ dev_err(hba->dev,
+ "Reject UPIU not fully implemented\n");
+ return -EINVAL;
+ default:
+ dev_err(hba->dev,
+ "Unexpected request response code = %x\n",
+ result);
+ return -EINVAL;
+ }
+ break;
+ default:
+ dev_err(hba->dev, "OCS error from controller = %x\n", ocs);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static inline int ufshcd_read_desc(struct ufs_hba *hba, enum desc_idn desc_id,
+ int desc_index, u8 *buf, u32 size)
+{
+ return ufshcd_read_desc_param(hba, desc_id, desc_index, 0, buf, size);
+}
+
+static int ufshcd_read_device_desc(struct ufs_hba *hba, u8 *buf, u32 size)
+{
+ return ufshcd_read_desc(hba, QUERY_DESC_IDN_DEVICE, 0, buf, size);
+}
+
+/**
+ * ufshcd_read_string_desc - read string descriptor
+ *
+ */
+int ufshcd_read_string_desc(struct ufs_hba *hba, int desc_index,
+ u8 *buf, u32 size, bool ascii)
+{
+ int err = 0;
+
+ err = ufshcd_read_desc(hba, QUERY_DESC_IDN_STRING, desc_index, buf,
+ size);
+
+ if (err) {
+ dev_err(hba->dev, "%s: reading String Desc failed after %d retries. err = %d\n",
+ __func__, QUERY_REQ_RETRIES, err);
+ goto out;
+ }
+
+ if (ascii) {
+ int desc_len;
+ int ascii_len;
+ int i;
+ u8 *buff_ascii;
+
+ desc_len = buf[0];
+ /* remove header and divide by 2 to move from UTF16 to UTF8 */
+ ascii_len = (desc_len - QUERY_DESC_HDR_SIZE) / 2 + 1;
+ if (size < ascii_len + QUERY_DESC_HDR_SIZE) {
+ dev_err(hba->dev, "%s: buffer allocated size is too small\n",
+ __func__);
+ err = -ENOMEM;
+ goto out;
+ }
+
+ buff_ascii = kmalloc(ascii_len, GFP_KERNEL);
+ if (!buff_ascii) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ /*
+ * the descriptor contains string in UTF16 format
+ * we need to convert to utf-8 so it can be displayed
+ */
+ utf16_to_utf8(buff_ascii,
+ (uint16_t *)&buf[QUERY_DESC_HDR_SIZE], ascii_len);
+
+ /* replace non-printable or non-ASCII characters with spaces */
+ for (i = 0; i < ascii_len; i++)
+ ufshcd_remove_non_printable(&buff_ascii[i]);
+
+ memset(buf + QUERY_DESC_HDR_SIZE, 0,
+ size - QUERY_DESC_HDR_SIZE);
+ memcpy(buf + QUERY_DESC_HDR_SIZE, buff_ascii, ascii_len);
+ buf[QUERY_DESC_LENGTH_OFFSET] = ascii_len + QUERY_DESC_HDR_SIZE;
+ kfree(buff_ascii);
+ }
+out:
+ return err;
+}
+
+static int ufs_get_device_desc(struct ufs_hba *hba,
+ struct ufs_dev_desc *dev_desc)
+{
+ int err;
+ size_t buff_len;
+ u8 model_index;
+ u8 *desc_buf;
+
+ buff_len = max_t(size_t, hba->desc_size.dev_desc,
+ QUERY_DESC_MAX_SIZE + 1);
+ desc_buf = kmalloc(buff_len, GFP_KERNEL);
+ if (!desc_buf) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ err = ufshcd_read_device_desc(hba, desc_buf, hba->desc_size.dev_desc);
+ if (err) {
+ dev_err(hba->dev, "%s: Failed reading Device Desc. err = %d\n",
+ __func__, err);
+ goto out;
+ }
+
+ /*
+ * getting vendor (manufacturerID) and Bank Index in big endian
+ * format
+ */
+ dev_desc->wmanufacturerid = desc_buf[DEVICE_DESC_PARAM_MANF_ID] << 8 |
+ desc_buf[DEVICE_DESC_PARAM_MANF_ID + 1];
+
+ model_index = desc_buf[DEVICE_DESC_PARAM_PRDCT_NAME];
+
+ /* Zero-pad entire buffer for string termination. */
+ memset(desc_buf, 0, buff_len);
+
+ err = ufshcd_read_string_desc(hba, model_index, desc_buf,
+ QUERY_DESC_MAX_SIZE, true/*ASCII*/);
+ if (err) {
+ dev_err(hba->dev, "%s: Failed reading Product Name. err = %d\n",
+ __func__, err);
+ goto out;
+ }
+
+ desc_buf[QUERY_DESC_MAX_SIZE] = '\0';
+ strlcpy(dev_desc->model, (char *)(desc_buf + QUERY_DESC_HDR_SIZE),
+ min_t(u8, desc_buf[QUERY_DESC_LENGTH_OFFSET],
+ MAX_MODEL_LEN));
+
+ /* Null terminate the model string */
+ dev_desc->model[MAX_MODEL_LEN] = '\0';
+
+out:
+ kfree(desc_buf);
+ return err;
+}
+
+/**
+ * ufshcd_get_max_pwr_mode - reads the max power mode negotiated with device
+ */
+static int ufshcd_get_max_pwr_mode(struct ufs_hba *hba)
+{
+ struct ufs_pa_layer_attr *pwr_info = &hba->max_pwr_info.info;
+
+ if (hba->max_pwr_info.is_valid)
+ return 0;
+
+ pwr_info->pwr_tx = FAST_MODE;
+ pwr_info->pwr_rx = FAST_MODE;
+ pwr_info->hs_rate = PA_HS_MODE_B;
+
+ /* Get the connected lane count */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDRXDATALANES),
+ &pwr_info->lane_rx);
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES),
+ &pwr_info->lane_tx);
+
+ if (!pwr_info->lane_rx || !pwr_info->lane_tx) {
+ dev_err(hba->dev, "%s: invalid connected lanes value. rx=%d, tx=%d\n",
+ __func__, pwr_info->lane_rx, pwr_info->lane_tx);
+ return -EINVAL;
+ }
+
+ /*
+ * First, get the maximum gears of HS speed.
+ * If a zero value, it means there is no HSGEAR capability.
+ * Then, get the maximum gears of PWM speed.
+ */
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR), &pwr_info->gear_rx);
+ if (!pwr_info->gear_rx) {
+ ufshcd_dme_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
+ &pwr_info->gear_rx);
+ if (!pwr_info->gear_rx) {
+ dev_err(hba->dev, "%s: invalid max pwm rx gear read = %d\n",
+ __func__, pwr_info->gear_rx);
+ return -EINVAL;
+ }
+ pwr_info->pwr_rx = SLOW_MODE;
+ }
+
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXHSGEAR),
+ &pwr_info->gear_tx);
+ if (!pwr_info->gear_tx) {
+ ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_MAXRXPWMGEAR),
+ &pwr_info->gear_tx);
+ if (!pwr_info->gear_tx) {
+ dev_err(hba->dev, "%s: invalid max pwm tx gear read = %d\n",
+ __func__, pwr_info->gear_tx);
+ return -EINVAL;
+ }
+ pwr_info->pwr_tx = SLOW_MODE;
+ }
+
+ hba->max_pwr_info.is_valid = true;
+ return 0;
+}
+
+static int ufshcd_change_power_mode(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *pwr_mode)
+{
+ int ret;
+
+ /* if already configured to the requested pwr_mode */
+ if (pwr_mode->gear_rx == hba->pwr_info.gear_rx &&
+ pwr_mode->gear_tx == hba->pwr_info.gear_tx &&
+ pwr_mode->lane_rx == hba->pwr_info.lane_rx &&
+ pwr_mode->lane_tx == hba->pwr_info.lane_tx &&
+ pwr_mode->pwr_rx == hba->pwr_info.pwr_rx &&
+ pwr_mode->pwr_tx == hba->pwr_info.pwr_tx &&
+ pwr_mode->hs_rate == hba->pwr_info.hs_rate) {
+ dev_dbg(hba->dev, "%s: power already configured\n", __func__);
+ return 0;
+ }
+
+ /*
+ * Configure attributes for power mode change with below.
+ * - PA_RXGEAR, PA_ACTIVERXDATALANES, PA_RXTERMINATION,
+ * - PA_TXGEAR, PA_ACTIVETXDATALANES, PA_TXTERMINATION,
+ * - PA_HSSERIES
+ */
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXGEAR), pwr_mode->gear_rx);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVERXDATALANES),
+ pwr_mode->lane_rx);
+ if (pwr_mode->pwr_rx == FASTAUTO_MODE || pwr_mode->pwr_rx == FAST_MODE)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), TRUE);
+ else
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_RXTERMINATION), FALSE);
+
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXGEAR), pwr_mode->gear_tx);
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_ACTIVETXDATALANES),
+ pwr_mode->lane_tx);
+ if (pwr_mode->pwr_tx == FASTAUTO_MODE || pwr_mode->pwr_tx == FAST_MODE)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), TRUE);
+ else
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTERMINATION), FALSE);
+
+ if (pwr_mode->pwr_rx == FASTAUTO_MODE ||
+ pwr_mode->pwr_tx == FASTAUTO_MODE ||
+ pwr_mode->pwr_rx == FAST_MODE ||
+ pwr_mode->pwr_tx == FAST_MODE)
+ ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HSSERIES),
+ pwr_mode->hs_rate);
+
+ ret = ufshcd_uic_change_pwr_mode(hba, pwr_mode->pwr_rx << 4 |
+ pwr_mode->pwr_tx);
+
+ if (ret) {
+ dev_err(hba->dev,
+ "%s: power mode change failed %d\n", __func__, ret);
+
+ return ret;
+ }
+
+ /* Copy new Power Mode to power info */
+ memcpy(&hba->pwr_info, pwr_mode, sizeof(struct ufs_pa_layer_attr));
+
+ return ret;
+}
+
+/**
+ * ufshcd_verify_dev_init() - Verify device initialization
+ *
+ */
+static int ufshcd_verify_dev_init(struct ufs_hba *hba)
+{
+ int retries;
+ int err;
+
+ for (retries = NOP_OUT_RETRIES; retries > 0; retries--) {
+ err = ufshcd_exec_dev_cmd(hba, DEV_CMD_TYPE_NOP,
+ NOP_OUT_TIMEOUT);
+ if (!err || err == -ETIMEDOUT)
+ break;
+
+ dev_dbg(hba->dev, "%s: error %d retrying\n", __func__, err);
+ }
+
+ if (err)
+ dev_err(hba->dev, "%s: NOP OUT failed %d\n", __func__, err);
+
+ return err;
+}
+
+/**
+ * ufshcd_complete_dev_init() - checks device readiness
+ */
+static int ufshcd_complete_dev_init(struct ufs_hba *hba)
+{
+ int i;
+ int err;
+ bool flag_res = 1;
+
+ err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_SET_FLAG,
+ QUERY_FLAG_IDN_FDEVICEINIT, NULL);
+ if (err) {
+ dev_err(hba->dev,
+ "%s setting fDeviceInit flag failed with error %d\n",
+ __func__, err);
+ goto out;
+ }
+
+ /* poll for max. 1000 iterations for fDeviceInit flag to clear */
+ for (i = 0; i < 1000 && !err && flag_res; i++)
+ err = ufshcd_query_flag_retry(hba, UPIU_QUERY_OPCODE_READ_FLAG,
+ QUERY_FLAG_IDN_FDEVICEINIT,
+ &flag_res);
+
+ if (err)
+ dev_err(hba->dev,
+ "%s reading fDeviceInit flag failed with error %d\n",
+ __func__, err);
+ else if (flag_res)
+ dev_err(hba->dev,
+ "%s fDeviceInit was not cleared by the device\n",
+ __func__);
+
+out:
+ return err;
+}
+
+static void ufshcd_def_desc_sizes(struct ufs_hba *hba)
+{
+ hba->desc_size.dev_desc = QUERY_DESC_DEVICE_DEF_SIZE;
+ hba->desc_size.pwr_desc = QUERY_DESC_POWER_DEF_SIZE;
+ hba->desc_size.interc_desc = QUERY_DESC_INTERCONNECT_DEF_SIZE;
+ hba->desc_size.conf_desc = QUERY_DESC_CONFIGURATION_DEF_SIZE;
+ hba->desc_size.unit_desc = QUERY_DESC_UNIT_DEF_SIZE;
+ hba->desc_size.geom_desc = QUERY_DESC_GEOMETRY_DEF_SIZE;
+ hba->desc_size.hlth_desc = QUERY_DESC_HEALTH_DEF_SIZE;
+}
+
+int ufs_start(struct ufs_hba *hba)
+{
+ struct ufs_dev_desc card = {0};
+ int ret;
+
+ ret = ufshcd_link_startup(hba);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_verify_dev_init(hba);
+ if (ret)
+ return ret;
+
+ ret = ufshcd_complete_dev_init(hba);
+ if (ret)
+ return ret;
+
+ /* Init check for device descriptor sizes */
+ ufshcd_init_desc_sizes(hba);
+
+ ret = ufs_get_device_desc(hba, &card);
+ if (ret) {
+ dev_err(hba->dev, "%s: Failed getting device info. err = %d\n",
+ __func__, ret);
+
+ return ret;
+ }
+
+ if (ufshcd_get_max_pwr_mode(hba)) {
+ dev_err(hba->dev,
+ "%s: Failed getting max supported power mode\n",
+ __func__);
+ } else {
+ ret = ufshcd_change_power_mode(hba, &hba->max_pwr_info.info);
+ if (ret) {
+ dev_err(hba->dev, "%s: Failed setting power mode, err = %d\n",
+ __func__, ret);
+
+ return ret;
+ }
+
+ printf("Device at %s up at:", hba->dev->name);
+ ufshcd_print_pwr_info(hba);
+ }
+
+ return 0;
+}
+
+int ufshcd_probe(struct udevice *ufs_dev, struct ufs_hba_ops *hba_ops)
+{
+ struct ufs_hba *hba = dev_get_uclass_priv(ufs_dev);
+ struct scsi_platdata *scsi_plat;
+ struct udevice *scsi_dev;
+ int err;
+
+ device_find_first_child(ufs_dev, &scsi_dev);
+ if (!scsi_dev)
+ return -ENODEV;
+
+ scsi_plat = dev_get_uclass_platdata(scsi_dev);
+ scsi_plat->max_id = UFSHCD_MAX_ID;
+ scsi_plat->max_lun = UFS_MAX_LUNS;
+ //scsi_plat->max_bytes_per_req = UFS_MAX_BYTES;
+
+ hba->dev = ufs_dev;
+ hba->ops = hba_ops;
+ hba->mmio_base = (void *)dev_read_addr(ufs_dev);
+
+ /* Set descriptor lengths to specification defaults */
+ ufshcd_def_desc_sizes(hba);
+
+ ufshcd_ops_init(hba);
+
+ /* Read capabilties registers */
+ hba->capabilities = ufshcd_readl(hba, REG_CONTROLLER_CAPABILITIES);
+
+ /* Get UFS version supported by the controller */
+ hba->version = ufshcd_get_ufs_version(hba);
+ if (hba->version != UFSHCI_VERSION_10 &&
+ hba->version != UFSHCI_VERSION_11 &&
+ hba->version != UFSHCI_VERSION_20 &&
+ hba->version != UFSHCI_VERSION_21)
+ dev_err(hba->dev, "invalid UFS version 0x%x\n",
+ hba->version);
+
+ /* Get Interrupt bit mask per version */
+ hba->intr_mask = ufshcd_get_intr_mask(hba);
+
+ /* Allocate memory for host memory space */
+ err = ufshcd_memory_alloc(hba);
+ if (err) {
+ dev_err(hba->dev, "Memory allocation failed\n");
+ return err;
+ }
+
+ /* Configure Local data structures */
+ ufshcd_host_memory_configure(hba);
+
+ /*
+ * In order to avoid any spurious interrupt immediately after
+ * registering UFS controller interrupt handler, clear any pending UFS
+ * interrupt status and disable all the UFS interrupts.
+ */
+ ufshcd_writel(hba, ufshcd_readl(hba, REG_INTERRUPT_STATUS),
+ REG_INTERRUPT_STATUS);
+ ufshcd_writel(hba, 0, REG_INTERRUPT_ENABLE);
+
+ err = ufshcd_hba_enable(hba);
+ if (err) {
+ dev_err(hba->dev, "Host controller enable failed\n");
+ return err;
+ }
+
+ err = ufs_start(hba);
+ if (err)
+ return err;
+
+ return 0;
+}
+
+int ufs_scsi_bind(struct udevice *ufs_dev, struct udevice **scsi_devp)
+{
+ int ret = device_bind_driver(ufs_dev, "ufs_scsi", "ufs_scsi",
+ scsi_devp);
+
+ return ret;
+}
+
+static struct scsi_ops ufs_ops = {
+ .exec = ufs_scsi_exec,
+};
+
+int ufs_probe_dev(int index)
+{
+ struct udevice *dev;
+
+ return uclass_get_device(UCLASS_UFS, index, &dev);
+}
+
+int ufs_probe(void)
+{
+ struct udevice *dev;
+ int ret, i;
+
+ for (i = 0;; i++) {
+ ret = uclass_get_device(UCLASS_UFS, i, &dev);
+ if (ret == -ENODEV)
+ break;
+ }
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ufs_scsi) = {
+ .id = UCLASS_SCSI,
+ .name = "ufs_scsi",
+ .ops = &ufs_ops,
+};
diff --git a/u-boot/drivers/ufs/ufs.h b/u-boot/drivers/ufs/ufs.h
new file mode 100644
index 0000000..8a38832
--- /dev/null
+++ b/u-boot/drivers/ufs/ufs.h
@@ -0,0 +1,917 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef __UFS_H
+#define __UFS_H
+
+#include "unipro.h"
+
+struct udevice;
+
+#define UFS_CDB_SIZE 16
+#define UPIU_TRANSACTION_UIC_CMD 0x1F
+#define UIC_CMD_SIZE (sizeof(u32) * 4)
+#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
+#define UFS_MAX_LUNS 0x7F
+
+enum {
+ TASK_REQ_UPIU_SIZE_DWORDS = 8,
+ TASK_RSP_UPIU_SIZE_DWORDS = 8,
+ ALIGNED_UPIU_SIZE = 512,
+};
+
+/* UFS device power modes */
+enum ufs_dev_pwr_mode {
+ UFS_ACTIVE_PWR_MODE = 1,
+ UFS_SLEEP_PWR_MODE = 2,
+ UFS_POWERDOWN_PWR_MODE = 3,
+};
+
+enum ufs_notify_change_status {
+ PRE_CHANGE,
+ POST_CHANGE,
+};
+
+struct ufs_pa_layer_attr {
+ u32 gear_rx;
+ u32 gear_tx;
+ u32 lane_rx;
+ u32 lane_tx;
+ u32 pwr_rx;
+ u32 pwr_tx;
+ u32 hs_rate;
+};
+
+struct ufs_pwr_mode_info {
+ bool is_valid;
+ struct ufs_pa_layer_attr info;
+};
+
+enum ufs_desc_def_size {
+ QUERY_DESC_DEVICE_DEF_SIZE = 0x40,
+ QUERY_DESC_CONFIGURATION_DEF_SIZE = 0x90,
+ QUERY_DESC_UNIT_DEF_SIZE = 0x23,
+ QUERY_DESC_INTERCONNECT_DEF_SIZE = 0x06,
+ QUERY_DESC_GEOMETRY_DEF_SIZE = 0x48,
+ QUERY_DESC_POWER_DEF_SIZE = 0x62,
+ QUERY_DESC_HEALTH_DEF_SIZE = 0x25,
+};
+
+struct ufs_desc_size {
+ int dev_desc;
+ int pwr_desc;
+ int geom_desc;
+ int interc_desc;
+ int unit_desc;
+ int conf_desc;
+ int hlth_desc;
+};
+
+/*
+ * Request Descriptor Definitions
+ */
+
+/* Transfer request command type */
+enum {
+ UTP_CMD_TYPE_SCSI = 0x0,
+ UTP_CMD_TYPE_UFS = 0x1,
+ UTP_CMD_TYPE_DEV_MANAGE = 0x2,
+};
+
+/* UTP Transfer Request Command Offset */
+#define UPIU_COMMAND_TYPE_OFFSET 28
+
+/* Offset of the response code in the UPIU header */
+#define UPIU_RSP_CODE_OFFSET 8
+
+/* To accommodate UFS2.0 required Command type */
+enum {
+ UTP_CMD_TYPE_UFS_STORAGE = 0x1,
+};
+
+enum {
+ UTP_SCSI_COMMAND = 0x00000000,
+ UTP_NATIVE_UFS_COMMAND = 0x10000000,
+ UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
+ UTP_REQ_DESC_INT_CMD = 0x01000000,
+};
+
+/* UTP Transfer Request Data Direction (DD) */
+enum {
+ UTP_NO_DATA_TRANSFER = 0x00000000,
+ UTP_HOST_TO_DEVICE = 0x02000000,
+ UTP_DEVICE_TO_HOST = 0x04000000,
+};
+
+/* Overall command status values */
+enum {
+ OCS_SUCCESS = 0x0,
+ OCS_INVALID_CMD_TABLE_ATTR = 0x1,
+ OCS_INVALID_PRDT_ATTR = 0x2,
+ OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
+ OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
+ OCS_PEER_COMM_FAILURE = 0x5,
+ OCS_ABORTED = 0x6,
+ OCS_FATAL_ERROR = 0x7,
+ OCS_INVALID_COMMAND_STATUS = 0x0F,
+ MASK_OCS = 0x0F,
+};
+
+/* The maximum length of the data byte count field in the PRDT is 256KB */
+#define PRDT_DATA_BYTE_COUNT_MAX (256 * 1024)
+/* The granularity of the data byte count field in the PRDT is 32-bit */
+#define PRDT_DATA_BYTE_COUNT_PAD 4
+
+#define GENERAL_UPIU_REQUEST_SIZE (sizeof(struct utp_upiu_req))
+#define QUERY_DESC_MAX_SIZE 255
+#define QUERY_DESC_MIN_SIZE 2
+#define QUERY_DESC_HDR_SIZE 2
+#define QUERY_OSF_SIZE (GENERAL_UPIU_REQUEST_SIZE - \
+ (sizeof(struct utp_upiu_header)))
+#define RESPONSE_UPIU_SENSE_DATA_LENGTH 18
+#define UPIU_HEADER_DWORD(byte3, byte2, byte1, byte0)\
+ cpu_to_be32((byte3 << 24) | (byte2 << 16) |\
+ (byte1 << 8) | (byte0))
+/*
+ * UFS Protocol Information Unit related definitions
+ */
+
+/* Task management functions */
+enum {
+ UFS_ABORT_TASK = 0x01,
+ UFS_ABORT_TASK_SET = 0x02,
+ UFS_CLEAR_TASK_SET = 0x04,
+ UFS_LOGICAL_RESET = 0x08,
+ UFS_QUERY_TASK = 0x80,
+ UFS_QUERY_TASK_SET = 0x81,
+};
+
+/* UTP UPIU Transaction Codes Initiator to Target */
+enum {
+ UPIU_TRANSACTION_NOP_OUT = 0x00,
+ UPIU_TRANSACTION_COMMAND = 0x01,
+ UPIU_TRANSACTION_DATA_OUT = 0x02,
+ UPIU_TRANSACTION_TASK_REQ = 0x04,
+ UPIU_TRANSACTION_QUERY_REQ = 0x16,
+};
+
+/* UTP UPIU Transaction Codes Target to Initiator */
+enum {
+ UPIU_TRANSACTION_NOP_IN = 0x20,
+ UPIU_TRANSACTION_RESPONSE = 0x21,
+ UPIU_TRANSACTION_DATA_IN = 0x22,
+ UPIU_TRANSACTION_TASK_RSP = 0x24,
+ UPIU_TRANSACTION_READY_XFER = 0x31,
+ UPIU_TRANSACTION_QUERY_RSP = 0x36,
+ UPIU_TRANSACTION_REJECT_UPIU = 0x3F,
+};
+
+/* UPIU Read/Write flags */
+enum {
+ UPIU_CMD_FLAGS_NONE = 0x00,
+ UPIU_CMD_FLAGS_WRITE = 0x20,
+ UPIU_CMD_FLAGS_READ = 0x40,
+};
+
+/* UPIU Task Attributes */
+enum {
+ UPIU_TASK_ATTR_SIMPLE = 0x00,
+ UPIU_TASK_ATTR_ORDERED = 0x01,
+ UPIU_TASK_ATTR_HEADQ = 0x02,
+ UPIU_TASK_ATTR_ACA = 0x03,
+};
+
+/* UPIU Query request function */
+enum {
+ UPIU_QUERY_FUNC_STANDARD_READ_REQUEST = 0x01,
+ UPIU_QUERY_FUNC_STANDARD_WRITE_REQUEST = 0x81,
+};
+
+/* Offset of the response code in the UPIU header */
+#define UPIU_RSP_CODE_OFFSET 8
+
+enum {
+ MASK_SCSI_STATUS = 0xFF,
+ MASK_TASK_RESPONSE = 0xFF00,
+ MASK_RSP_UPIU_RESULT = 0xFFFF,
+ MASK_QUERY_DATA_SEG_LEN = 0xFFFF,
+ MASK_RSP_UPIU_DATA_SEG_LEN = 0xFFFF,
+ MASK_RSP_EXCEPTION_EVENT = 0x10000,
+ MASK_TM_SERVICE_RESP = 0xFF,
+ MASK_TM_FUNC = 0xFF,
+};
+
+/* UTP QUERY Transaction Specific Fields OpCode */
+enum query_opcode {
+ UPIU_QUERY_OPCODE_NOP = 0x0,
+ UPIU_QUERY_OPCODE_READ_DESC = 0x1,
+ UPIU_QUERY_OPCODE_WRITE_DESC = 0x2,
+ UPIU_QUERY_OPCODE_READ_ATTR = 0x3,
+ UPIU_QUERY_OPCODE_WRITE_ATTR = 0x4,
+ UPIU_QUERY_OPCODE_READ_FLAG = 0x5,
+ UPIU_QUERY_OPCODE_SET_FLAG = 0x6,
+ UPIU_QUERY_OPCODE_CLEAR_FLAG = 0x7,
+ UPIU_QUERY_OPCODE_TOGGLE_FLAG = 0x8,
+};
+
+/* Query response result code */
+enum {
+ QUERY_RESULT_SUCCESS = 0x00,
+ QUERY_RESULT_NOT_READABLE = 0xF6,
+ QUERY_RESULT_NOT_WRITEABLE = 0xF7,
+ QUERY_RESULT_ALREADY_WRITTEN = 0xF8,
+ QUERY_RESULT_INVALID_LENGTH = 0xF9,
+ QUERY_RESULT_INVALID_VALUE = 0xFA,
+ QUERY_RESULT_INVALID_SELECTOR = 0xFB,
+ QUERY_RESULT_INVALID_INDEX = 0xFC,
+ QUERY_RESULT_INVALID_IDN = 0xFD,
+ QUERY_RESULT_INVALID_OPCODE = 0xFE,
+ QUERY_RESULT_GENERAL_FAILURE = 0xFF,
+};
+
+enum {
+ UPIU_COMMAND_SET_TYPE_SCSI = 0x0,
+ UPIU_COMMAND_SET_TYPE_UFS = 0x1,
+ UPIU_COMMAND_SET_TYPE_QUERY = 0x2,
+};
+
+/* Flag idn for Query Requests*/
+enum flag_idn {
+ QUERY_FLAG_IDN_FDEVICEINIT = 0x01,
+ QUERY_FLAG_IDN_PERMANENT_WPE = 0x02,
+ QUERY_FLAG_IDN_PWR_ON_WPE = 0x03,
+ QUERY_FLAG_IDN_BKOPS_EN = 0x04,
+ QUERY_FLAG_IDN_LIFE_SPAN_MODE_ENABLE = 0x05,
+ QUERY_FLAG_IDN_PURGE_ENABLE = 0x06,
+ QUERY_FLAG_IDN_RESERVED2 = 0x07,
+ QUERY_FLAG_IDN_FPHYRESOURCEREMOVAL = 0x08,
+ QUERY_FLAG_IDN_BUSY_RTC = 0x09,
+ QUERY_FLAG_IDN_RESERVED3 = 0x0A,
+ QUERY_FLAG_IDN_PERMANENTLY_DISABLE_FW_UPDATE = 0x0B,
+};
+
+/* Attribute idn for Query requests */
+enum attr_idn {
+ QUERY_ATTR_IDN_BOOT_LU_EN = 0x00,
+ QUERY_ATTR_IDN_RESERVED = 0x01,
+ QUERY_ATTR_IDN_POWER_MODE = 0x02,
+ QUERY_ATTR_IDN_ACTIVE_ICC_LVL = 0x03,
+ QUERY_ATTR_IDN_OOO_DATA_EN = 0x04,
+ QUERY_ATTR_IDN_BKOPS_STATUS = 0x05,
+ QUERY_ATTR_IDN_PURGE_STATUS = 0x06,
+ QUERY_ATTR_IDN_MAX_DATA_IN = 0x07,
+ QUERY_ATTR_IDN_MAX_DATA_OUT = 0x08,
+ QUERY_ATTR_IDN_DYN_CAP_NEEDED = 0x09,
+ QUERY_ATTR_IDN_REF_CLK_FREQ = 0x0A,
+ QUERY_ATTR_IDN_CONF_DESC_LOCK = 0x0B,
+ QUERY_ATTR_IDN_MAX_NUM_OF_RTT = 0x0C,
+ QUERY_ATTR_IDN_EE_CONTROL = 0x0D,
+ QUERY_ATTR_IDN_EE_STATUS = 0x0E,
+ QUERY_ATTR_IDN_SECONDS_PASSED = 0x0F,
+ QUERY_ATTR_IDN_CNTX_CONF = 0x10,
+ QUERY_ATTR_IDN_CORR_PRG_BLK_NUM = 0x11,
+ QUERY_ATTR_IDN_RESERVED2 = 0x12,
+ QUERY_ATTR_IDN_RESERVED3 = 0x13,
+ QUERY_ATTR_IDN_FFU_STATUS = 0x14,
+ QUERY_ATTR_IDN_PSA_STATE = 0x15,
+ QUERY_ATTR_IDN_PSA_DATA_SIZE = 0x16,
+};
+
+/* Descriptor idn for Query requests */
+enum desc_idn {
+ QUERY_DESC_IDN_DEVICE = 0x0,
+ QUERY_DESC_IDN_CONFIGURATION = 0x1,
+ QUERY_DESC_IDN_UNIT = 0x2,
+ QUERY_DESC_IDN_RFU_0 = 0x3,
+ QUERY_DESC_IDN_INTERCONNECT = 0x4,
+ QUERY_DESC_IDN_STRING = 0x5,
+ QUERY_DESC_IDN_RFU_1 = 0x6,
+ QUERY_DESC_IDN_GEOMETRY = 0x7,
+ QUERY_DESC_IDN_POWER = 0x8,
+ QUERY_DESC_IDN_HEALTH = 0x9,
+ QUERY_DESC_IDN_MAX,
+};
+
+enum desc_header_offset {
+ QUERY_DESC_LENGTH_OFFSET = 0x00,
+ QUERY_DESC_DESC_TYPE_OFFSET = 0x01,
+};
+
+struct ufshcd_sg_entry {
+ __le32 base_addr;
+ __le32 upper_addr;
+ __le32 reserved;
+ __le32 size;
+};
+
+#define MAX_BUFF 128
+/**
+ * struct utp_transfer_cmd_desc - UFS Command Descriptor structure
+ * @command_upiu: Command UPIU Frame address
+ * @response_upiu: Response UPIU Frame address
+ * @prd_table: Physical Region Descriptor
+ */
+struct utp_transfer_cmd_desc {
+ u8 command_upiu[ALIGNED_UPIU_SIZE];
+ u8 response_upiu[ALIGNED_UPIU_SIZE];
+ struct ufshcd_sg_entry prd_table[MAX_BUFF];
+};
+
+/**
+ * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
+ * @dword0: Descriptor Header DW0
+ * @dword1: Descriptor Header DW1
+ * @dword2: Descriptor Header DW2
+ * @dword3: Descriptor Header DW3
+ */
+struct request_desc_header {
+ __le32 dword_0;
+ __le32 dword_1;
+ __le32 dword_2;
+ __le32 dword_3;
+};
+
+/**
+ * struct utp_transfer_req_desc - UTRD structure
+ * @header: UTRD header DW-0 to DW-3
+ * @command_desc_base_addr_lo: UCD base address low DW-4
+ * @command_desc_base_addr_hi: UCD base address high DW-5
+ * @response_upiu_length: response UPIU length DW-6
+ * @response_upiu_offset: response UPIU offset DW-6
+ * @prd_table_length: Physical region descriptor length DW-7
+ * @prd_table_offset: Physical region descriptor offset DW-7
+ */
+struct utp_transfer_req_desc {
+ /* DW 0-3 */
+ struct request_desc_header header;
+
+ /* DW 4-5*/
+ __le32 command_desc_base_addr_lo;
+ __le32 command_desc_base_addr_hi;
+
+ /* DW 6 */
+ __le16 response_upiu_length;
+ __le16 response_upiu_offset;
+
+ /* DW 7 */
+ __le16 prd_table_length;
+ __le16 prd_table_offset;
+};
+
+/**
+ * struct utp_upiu_header - UPIU header structure
+ * @dword_0: UPIU header DW-0
+ * @dword_1: UPIU header DW-1
+ * @dword_2: UPIU header DW-2
+ */
+struct utp_upiu_header {
+ __be32 dword_0;
+ __be32 dword_1;
+ __be32 dword_2;
+};
+
+/**
+ * struct utp_upiu_query - upiu request buffer structure for
+ * query request.
+ * @opcode: command to perform B-0
+ * @idn: a value that indicates the particular type of data B-1
+ * @index: Index to further identify data B-2
+ * @selector: Index to further identify data B-3
+ * @reserved_osf: spec reserved field B-4,5
+ * @length: number of descriptor bytes to read/write B-6,7
+ * @value: Attribute value to be written DW-5
+ * @reserved: spec reserved DW-6,7
+ */
+struct utp_upiu_query {
+ __u8 opcode;
+ __u8 idn;
+ __u8 index;
+ __u8 selector;
+ __be16 reserved_osf;
+ __be16 length;
+ __be32 value;
+ __be32 reserved[2];
+};
+
+/**
+ * struct utp_upiu_cmd - Command UPIU structure
+ * @data_transfer_len: Data Transfer Length DW-3
+ * @cdb: Command Descriptor Block CDB DW-4 to DW-7
+ */
+struct utp_upiu_cmd {
+ __be32 exp_data_transfer_len;
+ u8 cdb[UFS_CDB_SIZE];
+};
+
+/*
+ * UTMRD structure.
+ */
+struct utp_task_req_desc {
+ /* DW 0-3 */
+ struct request_desc_header header;
+
+ /* DW 4-11 - Task request UPIU structure */
+ struct utp_upiu_header req_header;
+ __be32 input_param1;
+ __be32 input_param2;
+ __be32 input_param3;
+ __be32 __reserved1[2];
+
+ /* DW 12-19 - Task Management Response UPIU structure */
+ struct utp_upiu_header rsp_header;
+ __be32 output_param1;
+ __be32 output_param2;
+ __be32 __reserved2[3];
+};
+
+/**
+ * struct utp_upiu_req - general upiu request structure
+ * @header:UPIU header structure DW-0 to DW-2
+ * @sc: fields structure for scsi command DW-3 to DW-7
+ * @qr: fields structure for query request DW-3 to DW-7
+ */
+struct utp_upiu_req {
+ struct utp_upiu_header header;
+ union {
+ struct utp_upiu_cmd sc;
+ struct utp_upiu_query qr;
+ struct utp_upiu_query tr;
+ /* use utp_upiu_query to host the 4 dwords of uic command */
+ struct utp_upiu_query uc;
+ };
+};
+
+/**
+ * struct utp_cmd_rsp - Response UPIU structure
+ * @residual_transfer_count: Residual transfer count DW-3
+ * @reserved: Reserved double words DW-4 to DW-7
+ * @sense_data_len: Sense data length DW-8 U16
+ * @sense_data: Sense data field DW-8 to DW-12
+ */
+struct utp_cmd_rsp {
+ __be32 residual_transfer_count;
+ __be32 reserved[4];
+ __be16 sense_data_len;
+ u8 sense_data[RESPONSE_UPIU_SENSE_DATA_LENGTH];
+};
+
+/**
+ * struct utp_upiu_rsp - general upiu response structure
+ * @header: UPIU header structure DW-0 to DW-2
+ * @sr: fields structure for scsi command DW-3 to DW-12
+ * @qr: fields structure for query request DW-3 to DW-7
+ */
+struct utp_upiu_rsp {
+ struct utp_upiu_header header;
+ union {
+ struct utp_cmd_rsp sr;
+ struct utp_upiu_query qr;
+ };
+};
+
+#define MAX_MODEL_LEN 16
+/**
+ * ufs_dev_desc - ufs device details from the device descriptor
+ *
+ * @wmanufacturerid: card details
+ * @model: card model
+ */
+struct ufs_dev_desc {
+ u16 wmanufacturerid;
+ char model[MAX_MODEL_LEN + 1];
+};
+
+/* Device descriptor parameters offsets in bytes*/
+enum device_desc_param {
+ DEVICE_DESC_PARAM_LEN = 0x0,
+ DEVICE_DESC_PARAM_TYPE = 0x1,
+ DEVICE_DESC_PARAM_DEVICE_TYPE = 0x2,
+ DEVICE_DESC_PARAM_DEVICE_CLASS = 0x3,
+ DEVICE_DESC_PARAM_DEVICE_SUB_CLASS = 0x4,
+ DEVICE_DESC_PARAM_PRTCL = 0x5,
+ DEVICE_DESC_PARAM_NUM_LU = 0x6,
+ DEVICE_DESC_PARAM_NUM_WLU = 0x7,
+ DEVICE_DESC_PARAM_BOOT_ENBL = 0x8,
+ DEVICE_DESC_PARAM_DESC_ACCSS_ENBL = 0x9,
+ DEVICE_DESC_PARAM_INIT_PWR_MODE = 0xA,
+ DEVICE_DESC_PARAM_HIGH_PR_LUN = 0xB,
+ DEVICE_DESC_PARAM_SEC_RMV_TYPE = 0xC,
+ DEVICE_DESC_PARAM_SEC_LU = 0xD,
+ DEVICE_DESC_PARAM_BKOP_TERM_LT = 0xE,
+ DEVICE_DESC_PARAM_ACTVE_ICC_LVL = 0xF,
+ DEVICE_DESC_PARAM_SPEC_VER = 0x10,
+ DEVICE_DESC_PARAM_MANF_DATE = 0x12,
+ DEVICE_DESC_PARAM_MANF_NAME = 0x14,
+ DEVICE_DESC_PARAM_PRDCT_NAME = 0x15,
+ DEVICE_DESC_PARAM_SN = 0x16,
+ DEVICE_DESC_PARAM_OEM_ID = 0x17,
+ DEVICE_DESC_PARAM_MANF_ID = 0x18,
+ DEVICE_DESC_PARAM_UD_OFFSET = 0x1A,
+ DEVICE_DESC_PARAM_UD_LEN = 0x1B,
+ DEVICE_DESC_PARAM_RTT_CAP = 0x1C,
+ DEVICE_DESC_PARAM_FRQ_RTC = 0x1D,
+ DEVICE_DESC_PARAM_UFS_FEAT = 0x1F,
+ DEVICE_DESC_PARAM_FFU_TMT = 0x20,
+ DEVICE_DESC_PARAM_Q_DPTH = 0x21,
+ DEVICE_DESC_PARAM_DEV_VER = 0x22,
+ DEVICE_DESC_PARAM_NUM_SEC_WPA = 0x24,
+ DEVICE_DESC_PARAM_PSA_MAX_DATA = 0x25,
+ DEVICE_DESC_PARAM_PSA_TMT = 0x29,
+ DEVICE_DESC_PARAM_PRDCT_REV = 0x2A,
+};
+
+struct ufs_hba;
+
+enum {
+ UFSHCD_MAX_CHANNEL = 0,
+ UFSHCD_MAX_ID = 1,
+};
+
+enum dev_cmd_type {
+ DEV_CMD_TYPE_NOP = 0x0,
+ DEV_CMD_TYPE_QUERY = 0x1,
+};
+
+/**
+ * struct uic_command - UIC command structure
+ * @command: UIC command
+ * @argument1: UIC command argument 1
+ * @argument2: UIC command argument 2
+ * @argument3: UIC command argument 3
+ * @cmd_active: Indicate if UIC command is outstanding
+ * @result: UIC command result
+ * @done: UIC command completion
+ */
+struct uic_command {
+ u32 command;
+ u32 argument1;
+ u32 argument2;
+ u32 argument3;
+ int cmd_active;
+ int result;
+};
+
+/* GenSelectorIndex calculation macros for M-PHY attributes */
+#define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
+#define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
+
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
+ ((sel) & 0xFFFF))
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
+#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
+#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
+
+/* Link Status*/
+enum link_status {
+ UFSHCD_LINK_IS_DOWN = 1,
+ UFSHCD_LINK_IS_UP = 2,
+};
+
+#define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
+ ((sel) & 0xFFFF))
+#define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
+#define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
+#define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
+
+/* UIC Commands */
+enum uic_cmd_dme {
+ UIC_CMD_DME_GET = 0x01,
+ UIC_CMD_DME_SET = 0x02,
+ UIC_CMD_DME_PEER_GET = 0x03,
+ UIC_CMD_DME_PEER_SET = 0x04,
+ UIC_CMD_DME_POWERON = 0x10,
+ UIC_CMD_DME_POWEROFF = 0x11,
+ UIC_CMD_DME_ENABLE = 0x12,
+ UIC_CMD_DME_RESET = 0x14,
+ UIC_CMD_DME_END_PT_RST = 0x15,
+ UIC_CMD_DME_LINK_STARTUP = 0x16,
+ UIC_CMD_DME_HIBER_ENTER = 0x17,
+ UIC_CMD_DME_HIBER_EXIT = 0x18,
+ UIC_CMD_DME_TEST_MODE = 0x1A,
+};
+
+/* UIC Config result code / Generic error code */
+enum {
+ UIC_CMD_RESULT_SUCCESS = 0x00,
+ UIC_CMD_RESULT_INVALID_ATTR = 0x01,
+ UIC_CMD_RESULT_FAILURE = 0x01,
+ UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
+ UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
+ UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
+ UIC_CMD_RESULT_BAD_INDEX = 0x05,
+ UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
+ UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
+ UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
+ UIC_CMD_RESULT_BUSY = 0x09,
+ UIC_CMD_RESULT_DME_FAILURE = 0x0A,
+};
+
+#define MASK_UIC_COMMAND_RESULT 0xFF
+
+/* Host <-> Device UniPro Link state */
+enum uic_link_state {
+ UIC_LINK_OFF_STATE = 0, /* Link powered down or disabled */
+ UIC_LINK_ACTIVE_STATE = 1, /* Link is in Fast/Slow/Sleep state */
+ UIC_LINK_HIBERN8_STATE = 2, /* Link is in Hibernate state */
+};
+
+/* UIC command interfaces for DME primitives */
+#define DME_LOCAL 0
+#define DME_PEER 1
+#define ATTR_SET_NOR 0 /* NORMAL */
+#define ATTR_SET_ST 1 /* STATIC */
+
+int ufshcd_dme_set_attr(struct ufs_hba *hba, u32 attr_sel,
+ u8 attr_set, u32 mib_val, u8 peer);
+int ufshcd_dme_get_attr(struct ufs_hba *hba, u32 attr_sel,
+ u32 *mib_val, u8 peer);
+
+static inline int ufshcd_dme_set(struct ufs_hba *hba, u32 attr_sel,
+ u32 mib_val)
+{
+ return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
+ mib_val, DME_LOCAL);
+}
+
+static inline int ufshcd_dme_get(struct ufs_hba *hba,
+ u32 attr_sel, u32 *mib_val)
+{
+ return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_LOCAL);
+}
+
+static inline int ufshcd_dme_peer_get(struct ufs_hba *hba,
+ u32 attr_sel, u32 *mib_val)
+{
+ return ufshcd_dme_get_attr(hba, attr_sel, mib_val, DME_PEER);
+}
+
+static inline int ufshcd_dme_peer_set(struct ufs_hba *hba, u32 attr_sel,
+ u32 mib_val)
+{
+ return ufshcd_dme_set_attr(hba, attr_sel, ATTR_SET_NOR,
+ mib_val, DME_PEER);
+}
+
+/**
+ * struct ufs_query_req - parameters for building a query request
+ * @query_func: UPIU header query function
+ * @upiu_req: the query request data
+ */
+struct ufs_query_req {
+ u8 query_func;
+ struct utp_upiu_query upiu_req;
+};
+
+/**
+ * struct ufs_query_resp - UPIU QUERY
+ * @response: device response code
+ * @upiu_res: query response data
+ */
+struct ufs_query_res {
+ u8 response;
+ struct utp_upiu_query upiu_res;
+};
+
+/**
+ * struct ufs_query - holds relevant data structures for query request
+ * @request: request upiu and function
+ * @descriptor: buffer for sending/receiving descriptor
+ * @response: response upiu and response
+ */
+struct ufs_query {
+ struct ufs_query_req request;
+ u8 *descriptor;
+ struct ufs_query_res response;
+};
+
+/**
+ * struct ufs_dev_cmd - all assosiated fields with device management commands
+ * @type: device management command type - Query, NOP OUT
+ * @tag_wq: wait queue until free command slot is available
+ */
+struct ufs_dev_cmd {
+ enum dev_cmd_type type;
+ struct ufs_query query;
+};
+
+struct ufs_hba_ops {
+ int (*init)(struct ufs_hba *hba);
+ int (*hce_enable_notify)(struct ufs_hba *hba,
+ enum ufs_notify_change_status);
+ int (*link_startup_notify)(struct ufs_hba *hba,
+ enum ufs_notify_change_status);
+ int (*phy_initialization)(struct ufs_hba *hba);
+};
+
+struct ufs_hba {
+ struct udevice *dev;
+ void __iomem *mmio_base;
+ struct ufs_hba_ops *ops;
+ struct ufs_desc_size desc_size;
+ u32 capabilities;
+ u32 version;
+ u32 intr_mask;
+ u32 quirks;
+/*
+ * If UFS host controller is having issue in processing LCC (Line
+ * Control Command) coming from device then enable this quirk.
+ * When this quirk is enabled, host controller driver should disable
+ * the LCC transmission on UFS device (by clearing TX_LCC_ENABLE
+ * attribute of device to 0).
+ */
+#define UFSHCD_QUIRK_BROKEN_LCC 0x1
+
+ /* Virtual memory reference */
+ struct utp_transfer_cmd_desc *ucdl;
+ struct utp_transfer_req_desc *utrdl;
+ /* TODO: Add Task Manegement Support */
+ struct utp_task_req_desc *utmrdl;
+
+ struct utp_upiu_req *ucd_req_ptr;
+ struct utp_upiu_rsp *ucd_rsp_ptr;
+ struct ufshcd_sg_entry *ucd_prdt_ptr;
+
+ /* Power Mode information */
+ enum ufs_dev_pwr_mode curr_dev_pwr_mode;
+ struct ufs_pa_layer_attr pwr_info;
+ struct ufs_pwr_mode_info max_pwr_info;
+
+ struct ufs_dev_cmd dev_cmd;
+};
+
+static inline int ufshcd_ops_init(struct ufs_hba *hba)
+{
+ if (hba->ops && hba->ops->init)
+ return hba->ops->init(hba);
+
+ return 0;
+}
+
+static inline int ufshcd_ops_hce_enable_notify(struct ufs_hba *hba,
+ bool status)
+{
+ if (hba->ops && hba->ops->hce_enable_notify)
+ return hba->ops->hce_enable_notify(hba, status);
+
+ return 0;
+}
+
+static inline int ufshcd_ops_link_startup_notify(struct ufs_hba *hba,
+ bool status)
+{
+ if (hba->ops && hba->ops->link_startup_notify)
+ return hba->ops->link_startup_notify(hba, status);
+
+ return 0;
+}
+
+/* Controller UFSHCI version */
+enum {
+ UFSHCI_VERSION_10 = 0x00010000, /* 1.0 */
+ UFSHCI_VERSION_11 = 0x00010100, /* 1.1 */
+ UFSHCI_VERSION_20 = 0x00000200, /* 2.0 */
+ UFSHCI_VERSION_21 = 0x00000210, /* 2.1 */
+};
+
+/* Interrupt disable masks */
+enum {
+ /* Interrupt disable mask for UFSHCI v1.0 */
+ INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
+ INTERRUPT_MASK_RW_VER_10 = 0x30000,
+
+ /* Interrupt disable mask for UFSHCI v1.1 */
+ INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
+
+ /* Interrupt disable mask for UFSHCI v2.1 */
+ INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
+};
+
+/* UFSHCI Registers */
+enum {
+ REG_CONTROLLER_CAPABILITIES = 0x00,
+ REG_UFS_VERSION = 0x08,
+ REG_CONTROLLER_DEV_ID = 0x10,
+ REG_CONTROLLER_PROD_ID = 0x14,
+ REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
+ REG_INTERRUPT_STATUS = 0x20,
+ REG_INTERRUPT_ENABLE = 0x24,
+ REG_CONTROLLER_STATUS = 0x30,
+ REG_CONTROLLER_ENABLE = 0x34,
+ REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
+ REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
+ REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
+ REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
+ REG_UIC_ERROR_CODE_DME = 0x48,
+ REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
+ REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
+ REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
+ REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
+ REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
+ REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
+ REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
+ REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
+ REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
+ REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
+ REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
+ REG_UIC_COMMAND = 0x90,
+ REG_UIC_COMMAND_ARG_1 = 0x94,
+ REG_UIC_COMMAND_ARG_2 = 0x98,
+ REG_UIC_COMMAND_ARG_3 = 0x9C,
+
+ UFSHCI_REG_SPACE_SIZE = 0xA0,
+
+ REG_UFS_CCAP = 0x100,
+ REG_UFS_CRYPTOCAP = 0x104,
+
+ UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
+};
+
+/* Controller capability masks */
+enum {
+ MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
+ MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
+ MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
+ MASK_64_ADDRESSING_SUPPORT = 0x01000000,
+ MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
+ MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
+};
+
+/* Interrupt Status 20h */
+#define UTP_TRANSFER_REQ_COMPL 0x1
+#define UIC_DME_END_PT_RESET 0x2
+#define UIC_ERROR 0x4
+#define UIC_TEST_MODE 0x8
+#define UIC_POWER_MODE 0x10
+#define UIC_HIBERNATE_EXIT 0x20
+#define UIC_HIBERNATE_ENTER 0x40
+#define UIC_LINK_LOST 0x80
+#define UIC_LINK_STARTUP 0x100
+#define UTP_TASK_REQ_COMPL 0x200
+#define UIC_COMMAND_COMPL 0x400
+#define DEVICE_FATAL_ERROR 0x800
+#define CONTROLLER_FATAL_ERROR 0x10000
+#define SYSTEM_BUS_FATAL_ERROR 0x20000
+
+#define UFSHCD_UIC_PWR_MASK (UIC_HIBERNATE_ENTER |\
+ UIC_HIBERNATE_EXIT |\
+ UIC_POWER_MODE)
+
+#define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UIC_POWER_MODE)
+
+#define UFSHCD_ERROR_MASK (UIC_ERROR |\
+ DEVICE_FATAL_ERROR |\
+ CONTROLLER_FATAL_ERROR |\
+ SYSTEM_BUS_FATAL_ERROR)
+
+#define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
+ CONTROLLER_FATAL_ERROR |\
+ SYSTEM_BUS_FATAL_ERROR)
+
+/* Host Controller Enable 0x34h */
+#define CONTROLLER_ENABLE 0x1
+#define CONTROLLER_DISABLE 0x0
+/* HCS - Host Controller Status 30h */
+#define DEVICE_PRESENT 0x1
+#define UTP_TRANSFER_REQ_LIST_READY 0x2
+#define UTP_TASK_REQ_LIST_READY 0x4
+#define UIC_COMMAND_READY 0x8
+#define HOST_ERROR_INDICATOR 0x10
+#define DEVICE_ERROR_INDICATOR 0x20
+#define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
+
+#define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
+ UTP_TASK_REQ_LIST_READY |\
+ UIC_COMMAND_READY)
+
+enum {
+ PWR_OK = 0x0,
+ PWR_LOCAL = 0x01,
+ PWR_REMOTE = 0x02,
+ PWR_BUSY = 0x03,
+ PWR_ERROR_CAP = 0x04,
+ PWR_FATAL_ERROR = 0x05,
+};
+
+/* UICCMD - UIC Command */
+#define COMMAND_OPCODE_MASK 0xFF
+#define GEN_SELECTOR_INDEX_MASK 0xFFFF
+
+#define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
+#define RESET_LEVEL 0xFF
+
+#define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
+#define CFG_RESULT_CODE_MASK 0xFF
+#define GENERIC_ERROR_CODE_MASK 0xFF
+
+#define ufshcd_writel(hba, val, reg) \
+ writel((val), (hba)->mmio_base + (reg))
+#define ufshcd_readl(hba, reg) \
+ readl((hba)->mmio_base + (reg))
+
+/* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
+#define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
+
+/* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
+#define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
+
+int ufshcd_probe(struct udevice *dev, struct ufs_hba_ops *hba_ops);
+
+#endif
diff --git a/u-boot/drivers/ufs/ufshcd-dwc.c b/u-boot/drivers/ufs/ufshcd-dwc.c
new file mode 100644
index 0000000..c67bdb8
--- /dev/null
+++ b/u-boot/drivers/ufs/ufshcd-dwc.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * UFS Host driver for Synopsys Designware Core
+ *
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Authors: Joao Pinto <jpinto@synopsys.com>
+ */
+
+#include "ufs.h"
+#include "unipro.h"
+
+#include "ufshcd-dwc.h"
+#include "ufshci-dwc.h"
+
+int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
+ const struct ufshcd_dme_attr_val *v, int n)
+{
+ int ret = 0;
+ int attr_node = 0;
+
+ for (attr_node = 0; attr_node < n; attr_node++) {
+ ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
+ ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
+
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
+
+/**
+ * ufshcd_dwc_program_clk_div()
+ * This function programs the clk divider value. This value is needed to
+ * provide 1 microsecond tick to unipro layer.
+ * @hba: Private Structure pointer
+ * @divider_val: clock divider value to be programmed
+ *
+ */
+static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
+{
+ ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
+}
+
+/**
+ * ufshcd_dwc_link_is_up()
+ * Check if link is up
+ * @hba: private structure pointer
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
+{
+ int dme_result = 0;
+
+ ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result);
+
+ if (dme_result == UFSHCD_LINK_IS_UP)
+ return 0;
+
+ return 1;
+}
+
+/**
+ * ufshcd_dwc_connection_setup()
+ * This function configures both the local side (host) and the peer side
+ * (device) unipro attributes to establish the connection to application/
+ * cport.
+ * This function is not required if the hardware is properly configured to
+ * have this connection setup on reset. But invoking this function does no
+ * harm and should be fine even working with any ufs device.
+ *
+ * @hba: pointer to drivers private data
+ *
+ * Returns 0 on success non-zero value on failure
+ */
+static int ufshcd_dwc_connection_setup(struct ufs_hba *hba)
+{
+ static const struct ufshcd_dme_attr_val setup_attrs[] = {
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL },
+ { UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL },
+ { UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL },
+ { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL },
+ { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL },
+ { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL },
+ { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL },
+ { UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL },
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL },
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER },
+ { UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER },
+ { UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER },
+ { UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER },
+ { UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER },
+ { UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER },
+ { UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER },
+ { UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER },
+ { UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER }
+ };
+
+ return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs));
+}
+
+/**
+ * ufshcd_dwc_link_startup_notify()
+ * UFS Host DWC specific link startup sequence
+ * @hba: private structure pointer
+ * @status: Callback notify status
+ *
+ * Returns 0 on success, non-zero value on failure
+ */
+int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status)
+{
+ int err = 0;
+
+ if (status == PRE_CHANGE) {
+ ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125);
+
+ if (hba->ops->phy_initialization) {
+ err = hba->ops->phy_initialization(hba);
+ if (err) {
+ dev_err(hba->dev, "Phy setup failed (%d)\n",
+ err);
+ goto out;
+ }
+ }
+ } else { /* POST_CHANGE */
+ err = ufshcd_dwc_link_is_up(hba);
+ if (err) {
+ dev_err(hba->dev, "Link is not up\n");
+ goto out;
+ }
+
+ err = ufshcd_dwc_connection_setup(hba);
+ if (err)
+ dev_err(hba->dev, "Connection setup failed (%d)\n",
+ err);
+ }
+
+out:
+ return err;
+}
+EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
+
+MODULE_AUTHOR("Joao Pinto <Joao.Pinto@synopsys.com>");
+MODULE_DESCRIPTION("UFS Host driver for Synopsys Designware Core");
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/u-boot/drivers/ufs/ufshcd-dwc.h b/u-boot/drivers/ufs/ufshcd-dwc.h
new file mode 100644
index 0000000..4268ca2
--- /dev/null
+++ b/u-boot/drivers/ufs/ufshcd-dwc.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS Host driver for Synopsys Designware Core
+ *
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Authors: Joao Pinto <jpinto@synopsys.com>
+ */
+
+#ifndef _UFSHCD_DWC_H
+#define _UFSHCD_DWC_H
+
+struct ufshcd_dme_attr_val {
+ u32 attr_sel;
+ u32 mib_val;
+ u8 peer;
+};
+
+int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
+ enum ufs_notify_change_status status);
+int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
+ const struct ufshcd_dme_attr_val *v, int n);
+#endif /* End of Header */
diff --git a/u-boot/drivers/ufs/ufshci-dwc.h b/u-boot/drivers/ufs/ufshci-dwc.h
new file mode 100644
index 0000000..6c290e2
--- /dev/null
+++ b/u-boot/drivers/ufs/ufshci-dwc.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * UFS Host driver for Synopsys Designware Core
+ *
+ * Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
+ *
+ * Authors: Joao Pinto <jpinto@synopsys.com>
+ */
+
+#ifndef _UFSHCI_DWC_H
+#define _UFSHCI_DWC_H
+
+/* DWC HC UFSHCI specific Registers */
+enum dwc_specific_registers {
+ DWC_UFS_REG_HCLKDIV = 0xFC,
+};
+
+/* Clock Divider Values: Hex equivalent of frequency in MHz */
+enum clk_div_values {
+ DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
+ DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
+ DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
+};
+
+/* Selector Index */
+enum selector_index {
+ SELIND_LN0_TX = 0x00,
+ SELIND_LN1_TX = 0x01,
+ SELIND_LN0_RX = 0x04,
+ SELIND_LN1_RX = 0x05,
+};
+
+#endif /* End of Header */
diff --git a/u-boot/drivers/ufs/unipro.h b/u-boot/drivers/ufs/unipro.h
new file mode 100644
index 0000000..b30b17f
--- /dev/null
+++ b/u-boot/drivers/ufs/unipro.h
@@ -0,0 +1,270 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+#ifndef _UNIPRO_H_
+#define _UNIPRO_H_
+
+/*
+ * M-TX Configuration Attributes
+ */
+#define TX_HIBERN8TIME_CAPABILITY 0x000F
+#define TX_MODE 0x0021
+#define TX_HSRATE_SERIES 0x0022
+#define TX_HSGEAR 0x0023
+#define TX_PWMGEAR 0x0024
+#define TX_AMPLITUDE 0x0025
+#define TX_HS_SLEWRATE 0x0026
+#define TX_SYNC_SOURCE 0x0027
+#define TX_HS_SYNC_LENGTH 0x0028
+#define TX_HS_PREPARE_LENGTH 0x0029
+#define TX_LS_PREPARE_LENGTH 0x002A
+#define TX_HIBERN8_CONTROL 0x002B
+#define TX_LCC_ENABLE 0x002C
+#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
+#define TX_BYPASS_8B10B_ENABLE 0x002E
+#define TX_DRIVER_POLARITY 0x002F
+#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
+#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
+#define TX_LCC_SEQUENCER 0x0032
+#define TX_MIN_ACTIVATETIME 0x0033
+#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
+#define TX_REFCLKFREQ 0x00EB
+#define TX_CFGCLKFREQVAL 0x00EC
+#define CFGEXTRATTR 0x00F0
+#define DITHERCTRL2 0x00F1
+
+/*
+ * M-RX Configuration Attributes
+ */
+#define RX_MODE 0x00A1
+#define RX_HSRATE_SERIES 0x00A2
+#define RX_HSGEAR 0x00A3
+#define RX_PWMGEAR 0x00A4
+#define RX_LS_TERMINATED_ENABLE 0x00A5
+#define RX_HS_UNTERMINATED_ENABLE 0x00A6
+#define RX_ENTER_HIBERN8 0x00A7
+#define RX_BYPASS_8B10B_ENABLE 0x00A8
+#define RX_TERMINATION_FORCE_ENABLE 0x0089
+#define RX_MIN_ACTIVATETIME_CAPABILITY 0x008F
+#define RX_HIBERN8TIME_CAPABILITY 0x0092
+#define RX_REFCLKFREQ 0x00EB
+#define RX_CFGCLKFREQVAL 0x00EC
+#define CFGWIDEINLN 0x00F0
+#define CFGRXCDR8 0x00BA
+#define ENARXDIRECTCFG4 0x00F2
+#define CFGRXOVR8 0x00BD
+#define RXDIRECTCTRL2 0x00C7
+#define ENARXDIRECTCFG3 0x00F3
+#define RXCALCTRL 0x00B4
+#define ENARXDIRECTCFG2 0x00F4
+#define CFGRXOVR4 0x00E9
+#define RXSQCTRL 0x00B5
+#define CFGRXOVR6 0x00BF
+
+#define is_mphy_tx_attr(attr) (attr < RX_MODE)
+#define RX_MIN_ACTIVATETIME_UNIT_US 100
+#define HIBERN8TIME_UNIT_US 100
+
+/*
+ * Common Block Attributes
+ */
+#define TX_GLOBALHIBERNATE UNIPRO_CB_OFFSET(0x002B)
+#define REFCLKMODE UNIPRO_CB_OFFSET(0x00BF)
+#define DIRECTCTRL19 UNIPRO_CB_OFFSET(0x00CD)
+#define DIRECTCTRL10 UNIPRO_CB_OFFSET(0x00E6)
+#define CDIRECTCTRL6 UNIPRO_CB_OFFSET(0x00EA)
+#define RTOBSERVESELECT UNIPRO_CB_OFFSET(0x00F0)
+#define CBDIVFACTOR UNIPRO_CB_OFFSET(0x00F1)
+#define CBDCOCTRL5 UNIPRO_CB_OFFSET(0x00F3)
+#define CBPRGPLL2 UNIPRO_CB_OFFSET(0x00F8)
+#define CBPRGTUNING UNIPRO_CB_OFFSET(0x00FB)
+
+#define UNIPRO_CB_OFFSET(x) (0x8000 | x)
+
+/*
+ * PHY Adpater attributes
+ */
+#define PA_ACTIVETXDATALANES 0x1560
+#define PA_ACTIVERXDATALANES 0x1580
+#define PA_TXTRAILINGCLOCKS 0x1564
+#define PA_PHY_TYPE 0x1500
+#define PA_AVAILTXDATALANES 0x1520
+#define PA_AVAILRXDATALANES 0x1540
+#define PA_MINRXTRAILINGCLOCKS 0x1543
+#define PA_TXPWRSTATUS 0x1567
+#define PA_RXPWRSTATUS 0x1582
+#define PA_TXFORCECLOCK 0x1562
+#define PA_TXPWRMODE 0x1563
+#define PA_LEGACYDPHYESCDL 0x1570
+#define PA_MAXTXSPEEDFAST 0x1521
+#define PA_MAXTXSPEEDSLOW 0x1522
+#define PA_MAXRXSPEEDFAST 0x1541
+#define PA_MAXRXSPEEDSLOW 0x1542
+#define PA_TXLINKSTARTUPHS 0x1544
+#define PA_LOCAL_TX_LCC_ENABLE 0x155E
+#define PA_TXSPEEDFAST 0x1565
+#define PA_TXSPEEDSLOW 0x1566
+#define PA_REMOTEVERINFO 0x15A0
+#define PA_TXGEAR 0x1568
+#define PA_TXTERMINATION 0x1569
+#define PA_HSSERIES 0x156A
+#define PA_PWRMODE 0x1571
+#define PA_RXGEAR 0x1583
+#define PA_RXTERMINATION 0x1584
+#define PA_MAXRXPWMGEAR 0x1586
+#define PA_MAXRXHSGEAR 0x1587
+#define PA_RXHSUNTERMCAP 0x15A5
+#define PA_RXLSTERMCAP 0x15A6
+#define PA_GRANULARITY 0x15AA
+#define PA_PACPREQTIMEOUT 0x1590
+#define PA_PACPREQEOBTIMEOUT 0x1591
+#define PA_HIBERN8TIME 0x15A7
+#define PA_LOCALVERINFO 0x15A9
+#define PA_TACTIVATE 0x15A8
+#define PA_PACPFRAMECOUNT 0x15C0
+#define PA_PACPERRORCOUNT 0x15C1
+#define PA_PHYTESTCONTROL 0x15C2
+#define PA_PWRMODEUSERDATA0 0x15B0
+#define PA_PWRMODEUSERDATA1 0x15B1
+#define PA_PWRMODEUSERDATA2 0x15B2
+#define PA_PWRMODEUSERDATA3 0x15B3
+#define PA_PWRMODEUSERDATA4 0x15B4
+#define PA_PWRMODEUSERDATA5 0x15B5
+#define PA_PWRMODEUSERDATA6 0x15B6
+#define PA_PWRMODEUSERDATA7 0x15B7
+#define PA_PWRMODEUSERDATA8 0x15B8
+#define PA_PWRMODEUSERDATA9 0x15B9
+#define PA_PWRMODEUSERDATA10 0x15BA
+#define PA_PWRMODEUSERDATA11 0x15BB
+#define PA_CONNECTEDTXDATALANES 0x1561
+#define PA_CONNECTEDRXDATALANES 0x1581
+#define PA_LOGICALLANEMAP 0x15A1
+#define PA_SLEEPNOCONFIGTIME 0x15A2
+#define PA_STALLNOCONFIGTIME 0x15A3
+#define PA_SAVECONFIGTIME 0x15A4
+
+#define PA_TACTIVATE_TIME_UNIT_US 10
+#define PA_HIBERN8_TIME_UNIT_US 100
+
+/*Other attributes*/
+#define VS_MPHYCFGUPDT 0xD085
+#define VS_DEBUGOMC 0xD09E
+#define VS_POWERSTATE 0xD083
+
+#define PA_GRANULARITY_MIN_VAL 1
+#define PA_GRANULARITY_MAX_VAL 6
+
+/* PHY Adapter Protocol Constants */
+#define PA_MAXDATALANES 4
+
+/* PA power modes */
+enum {
+ FAST_MODE = 1,
+ SLOW_MODE = 2,
+ FASTAUTO_MODE = 4,
+ SLOWAUTO_MODE = 5,
+ UNCHANGED = 7,
+};
+
+/* PA TX/RX Frequency Series */
+enum {
+ PA_HS_MODE_A = 1,
+ PA_HS_MODE_B = 2,
+};
+
+enum ufs_pwm_gear_tag {
+ UFS_PWM_DONT_CHANGE, /* Don't change Gear */
+ UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
+ UFS_PWM_G2, /* PWM Gear 2 */
+ UFS_PWM_G3, /* PWM Gear 3 */
+ UFS_PWM_G4, /* PWM Gear 4 */
+ UFS_PWM_G5, /* PWM Gear 5 */
+ UFS_PWM_G6, /* PWM Gear 6 */
+ UFS_PWM_G7, /* PWM Gear 7 */
+};
+
+enum ufs_hs_gear_tag {
+ UFS_HS_DONT_CHANGE, /* Don't change Gear */
+ UFS_HS_G1, /* HS Gear 1 (default for reset) */
+ UFS_HS_G2, /* HS Gear 2 */
+ UFS_HS_G3, /* HS Gear 3 */
+};
+
+enum ufs_unipro_ver {
+ UFS_UNIPRO_VER_RESERVED = 0,
+ UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
+ UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
+ UFS_UNIPRO_VER_1_6 = 3, /* UniPro version 1.6 */
+ UFS_UNIPRO_VER_MAX = 4, /* UniPro unsupported version */
+ /* UniPro version field mask in PA_LOCALVERINFO */
+ UFS_UNIPRO_VER_MASK = 0xF,
+};
+
+/*
+ * Data Link Layer Attributes
+ */
+#define DL_TC0TXFCTHRESHOLD 0x2040
+#define DL_FC0PROTTIMEOUTVAL 0x2041
+#define DL_TC0REPLAYTIMEOUTVAL 0x2042
+#define DL_AFC0REQTIMEOUTVAL 0x2043
+#define DL_AFC0CREDITTHRESHOLD 0x2044
+#define DL_TC0OUTACKTHRESHOLD 0x2045
+#define DL_TC1TXFCTHRESHOLD 0x2060
+#define DL_FC1PROTTIMEOUTVAL 0x2061
+#define DL_TC1REPLAYTIMEOUTVAL 0x2062
+#define DL_AFC1REQTIMEOUTVAL 0x2063
+#define DL_AFC1CREDITTHRESHOLD 0x2064
+#define DL_TC1OUTACKTHRESHOLD 0x2065
+#define DL_TXPREEMPTIONCAP 0x2000
+#define DL_TC0TXMAXSDUSIZE 0x2001
+#define DL_TC0RXINITCREDITVAL 0x2002
+#define DL_TC0TXBUFFERSIZE 0x2005
+#define DL_PEERTC0PRESENT 0x2046
+#define DL_PEERTC0RXINITCREVAL 0x2047
+#define DL_TC1TXMAXSDUSIZE 0x2003
+#define DL_TC1RXINITCREDITVAL 0x2004
+#define DL_TC1TXBUFFERSIZE 0x2006
+#define DL_PEERTC1PRESENT 0x2066
+#define DL_PEERTC1RXINITCREVAL 0x2067
+
+/*
+ * Network Layer Attributes
+ */
+#define N_DEVICEID 0x3000
+#define N_DEVICEID_VALID 0x3001
+#define N_TC0TXMAXSDUSIZE 0x3020
+#define N_TC1TXMAXSDUSIZE 0x3021
+
+/*
+ * Transport Layer Attributes
+ */
+#define T_NUMCPORTS 0x4000
+#define T_NUMTESTFEATURES 0x4001
+#define T_CONNECTIONSTATE 0x4020
+#define T_PEERDEVICEID 0x4021
+#define T_PEERCPORTID 0x4022
+#define T_TRAFFICCLASS 0x4023
+#define T_PROTOCOLID 0x4024
+#define T_CPORTFLAGS 0x4025
+#define T_TXTOKENVALUE 0x4026
+#define T_RXTOKENVALUE 0x4027
+#define T_LOCALBUFFERSPACE 0x4028
+#define T_PEERBUFFERSPACE 0x4029
+#define T_CREDITSTOSEND 0x402A
+#define T_CPORTMODE 0x402B
+#define T_TC0TXMAXSDUSIZE 0x4060
+#define T_TC1TXMAXSDUSIZE 0x4061
+
+#ifdef FALSE
+#undef FALSE
+#endif
+
+#ifdef TRUE
+#undef TRUE
+#endif
+
+/* Boolean attribute values */
+enum {
+ FALSE = 0,
+ TRUE,
+};
+
+#endif /* _UNIPRO_H_ */
diff --git a/u-boot/drivers/usb/dwc3/gadget.c b/u-boot/drivers/usb/dwc3/gadget.c
index 0923409..1f8d464 100644
--- a/u-boot/drivers/usb/dwc3/gadget.c
+++ b/u-boot/drivers/usb/dwc3/gadget.c
@@ -2482,7 +2482,6 @@
while (left > 0) {
union dwc3_event event;
- invalidate_dcache_range((uintptr_t)evt->buf, evt->length);
event.raw = *(u32 *) (evt->buf + evt->lpos);
dwc3_process_event_entry(dwc, &event);
@@ -2538,6 +2537,7 @@
u32 reg;
evt = dwc->ev_buffs[buf];
+ dwc3_invalidate_cache((uintptr_t)evt->buf, evt->length);
count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
count &= DWC3_GEVNTCOUNT_MASK;
diff --git a/u-boot/drivers/usb/dwc3/io.h b/u-boot/drivers/usb/dwc3/io.h
index 810980f..d59f8be 100644
--- a/u-boot/drivers/usb/dwc3/io.h
+++ b/u-boot/drivers/usb/dwc3/io.h
@@ -48,6 +48,11 @@
writel(value, base + offs);
}
+static inline void dwc3_invalidate_cache(uintptr_t addr, int length)
+{
+ invalidate_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
+}
+
static inline void dwc3_flush_cache(uintptr_t addr, int length)
{
flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
diff --git a/u-boot/drivers/video/Kconfig b/u-boot/drivers/video/Kconfig
index 27cb8ef..55a27e6 100644
--- a/u-boot/drivers/video/Kconfig
+++ b/u-boot/drivers/video/Kconfig
@@ -14,6 +14,21 @@
option compiles in the video uclass and routes all LCD/video access
through this.
+config SPL_DM_VIDEO
+ bool "Enable driver model support for LCD/video in SPL"
+ depends on DM_VIDEO && SPL
+ help
+ This enables driver model for LCD and video devices in SPL. These support
+ a bitmap display of various sizes and depths which can be drawn on
+ to display a command-line console or splash screen. Enabling this
+ option compiles in the video uclass and routes all LCD/video access
+ through this.
+
+config SPL_VIDEO_BUF
+ hex "SPL video memory buffer for any use"
+ depends on SPL_DM_VIDEO
+ default 0xa200000
+
config BACKLIGHT_PWM
bool "Generic PWM based Backlight Driver"
depends on DM_VIDEO && DM_PWM
@@ -390,6 +405,12 @@
help
This enables library for accessing EDID data from an LCD panel.
+config SPL_I2C_EDID
+ bool "Enable EDID library in SPL"
+ depends on DM_I2C && SPL_DM_VIDEO
+ help
+ This enables library in SPL for accessing EDID data from an LCD panel.
+
config DISPLAY
bool "Enable Display support"
depends on DM
diff --git a/u-boot/drivers/video/Makefile b/u-boot/drivers/video/Makefile
index 60ffa66..6ce2537 100644
--- a/u-boot/drivers/video/Makefile
+++ b/u-boot/drivers/video/Makefile
@@ -5,6 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
+ifndef CONFIG_SPL_BUILD
ifdef CONFIG_DM
obj-$(CONFIG_DISPLAY) += display-uclass.o
obj-$(CONFIG_DM_VIDEO) += backlight-uclass.o
@@ -56,8 +57,11 @@
obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
obj-${CONFIG_EXYNOS_FB} += exynos/
obj-${CONFIG_VIDEO_ROCKCHIP} += rockchip/
-obj-${CONFIG_DRM_ROCKCHIP} += drm/
obj-${CONFIG_ROCKCHIP_EINK} += rk_eink/
obj-y += bridge/
obj-y += sunxi/
+endif
+
+obj-${CONFIG_DRM_ROCKCHIP} += drm/
+
diff --git a/u-boot/drivers/video/drm/Kconfig b/u-boot/drivers/video/drm/Kconfig
index cb070f1..cc27f66 100644
--- a/u-boot/drivers/video/drm/Kconfig
+++ b/u-boot/drivers/video/drm/Kconfig
@@ -28,15 +28,6 @@
help
Driver for Maxim MAX96745 GMSL2 Serializer with eDP1.4a/DP1.4 Input.
-config DRM_MAXIM_MAX96752F
- bool "Maxim max96752F GMSL2 Deserializer"
- depends on DRM_ROCKCHIP
- select I2C_MUX_MAX96752F
- select PINCTRL_MAX96752F
- select GPIO_MAX96752F
- help
- Driver for Maxim MAX96752F GMSL2 Deserializer with Dual LVDS Output.
-
config DRM_MAXIM_MAX96755F
bool "Maxim max96755F GMSL2 Serializer"
depends on DRM_ROCKCHIP
@@ -45,11 +36,19 @@
help
Driver for Maxim MAX96755F GMSL2 Serializer with MIPI-DSI Input.
-config DRM_PANEL_MAXIM_DESERIALIZER
- bool "Maxim deserializer panel driver"
+config DRM_PANEL_ROHM_BU18RL82
+ bool "Rohm BU18RL82-based panels"
depends on DRM_ROCKCHIP
help
- Driver for Maxim deserializer panels.
+ Say Y if you want to enable support for panels based on the
+ Rohm BU18RL82.
+
+config DRM_PANEL_MAXIM_MAX96752F
+ bool "Maxim MAX96752F-based panels"
+ depends on DRM_ROCKCHIP
+ help
+ Say Y if you want to enable support for panels based on the
+ Maxim MAX96752F.
config DRM_ROCKCHIP_PANEL
bool "Rockchip Panel Support"
@@ -216,13 +215,12 @@
Support for Rockchip HDMI/DP Combo PHY HDMI with Samsung
IP block.
-config ROCKCHIP_DRM_TVE
+config DRM_ROCKCHIP_TVE
bool "Rockchip TVE Support"
depends on DRM_ROCKCHIP
help
Choose this option to enable support for Rockchip TVE.
- Rockchip rk322x and rk322xh SoC has TVE can be used, and
- say Y to enable TVE driver.
+ Say Y to enable TVE driver.
config ROCKCHIP_CUBIC_LUT_SIZE
int "Rockchip cubic lut size"
diff --git a/u-boot/drivers/video/drm/Makefile b/u-boot/drivers/video/drm/Makefile
index d5ceeb3..4c28ee1 100644
--- a/u-boot/drivers/video/drm/Makefile
+++ b/u-boot/drivers/video/drm/Makefile
@@ -6,17 +6,18 @@
obj-y += drm_modes.o
-obj-y += rockchip_display.o rockchip_crtc.o rockchip_phy.o rockchip_bridge.o \
+ifndef CONFIG_SPL_BUILD
+obj-y += rockchip_display.o rockchip_display_helper.o rockchip_crtc.o rockchip_phy.o rockchip_bridge.o \
rockchip_vop.o rockchip_vop_reg.o rockchip_vop2.o bmp_helper.o \
- rockchip_connector.o
+ rockchip_connector.o rockchip_post_csc.o
obj-$(CONFIG_DRM_MIPI_DSI) += drm_mipi_dsi.o
obj-$(CONFIG_DRM_DP_HELPER) += drm_dp_helper.o
obj-$(CONFIG_DRM_DSC) += drm_dsc.o
obj-$(CONFIG_DRM_MAXIM_MAX96745) += max96745.o
-obj-$(CONFIG_DRM_MAXIM_MAX96752F) += max96752f.o
obj-$(CONFIG_DRM_MAXIM_MAX96755F) += max96755f.o
-obj-$(CONFIG_DRM_PANEL_MAXIM_DESERIALIZER) += panel-maxim-deserializer.o
+obj-$(CONFIG_DRM_PANEL_ROHM_BU18RL82) += panel-rohm-bu18rl82.o
+obj-$(CONFIG_DRM_PANEL_MAXIM_MAX96752F) += panel-maxim-max96752f.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI) += dw_mipi_dsi.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_MIPI_DSI2) += dw_mipi_dsi2.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_HDMI) += rockchip_dw_hdmi.o dw_hdmi.o
@@ -27,7 +28,7 @@
obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_PHY) += inno_video_phy.o
obj-$(CONFIG_DRM_ROCKCHIP_INNO_VIDEO_COMBO_PHY) += inno_video_combo_phy.o
obj-$(CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX_HDMI) += phy-rockchip-samsung-hdptx-hdmi.o
-obj-$(CONFIG_ROCKCHIP_DRM_TVE) += rockchip_drm_tve.o
+obj-$(CONFIG_DRM_ROCKCHIP_TVE) += rockchip_tve.o
obj-$(CONFIG_DRM_ROCKCHIP_ANALOGIX_DP) += analogix_dp.o analogix_dp_reg.o
obj-$(CONFIG_DRM_ROCKCHIP_DW_DP) += dw-dp.o
obj-$(CONFIG_DRM_ROCKCHIP_LVDS) += rockchip_lvds.o
@@ -37,3 +38,7 @@
obj-$(CONFIG_DRM_ROCKCHIP_RK618) += rk618.o rk618_lvds.o rk618_dsi.o
obj-$(CONFIG_DRM_ROCKCHIP_RK1000) += rk1000.o rk1000_tve.o
obj-$(CONFIG_DRM_ROCKCHIP_SAMSUNG_MIPI_DCPHY) += samsung_mipi_dcphy.o
+else
+obj-y += rockchip_spl_display.o rockchip_display_helper.o rockchip_crtc.o rockchip_connector.o rockchip_post_csc.o rockchip_vop2.o rockchip_phy.o rockchip-inno-hdmi-phy.o rockchip_dw_hdmi.o dw_hdmi.o
+endif
+
diff --git a/u-boot/drivers/video/drm/analogix_dp.c b/u-boot/drivers/video/drm/analogix_dp.c
index 52d5bf1..70cd620 100644
--- a/u-boot/drivers/video/drm/analogix_dp.c
+++ b/u-boot/drivers/video/drm/analogix_dp.c
@@ -943,6 +943,37 @@
.detect = analogix_dp_connector_detect,
};
+static u32 analogix_dp_parse_link_frequencies(struct analogix_dp_device *dp)
+{
+ struct udevice *dev = dp->dev;
+ const struct device_node *endpoint;
+ u64 frequency = 0;
+
+ endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0);
+ if (!endpoint)
+ return 0;
+
+ if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0)
+ return 0;
+
+ if (!frequency)
+ return 0;
+
+ do_div(frequency, 10 * 1000); /* symbol rate kbytes */
+
+ switch (frequency) {
+ case 162000:
+ case 270000:
+ case 540000:
+ break;
+ default:
+ dev_err(dev, "invalid link frequency value: %llu\n", frequency);
+ return 0;
+ }
+
+ return frequency;
+}
+
static int analogix_dp_parse_dt(struct analogix_dp_device *dp)
{
struct udevice *dev = dp->dev;
@@ -956,21 +987,9 @@
dp->video_info.force_stream_valid =
dev_read_bool(dev, "analogix,force-stream-valid");
- max_link_rate = dev_read_u32_default(dev, "max-link-rate", 0);
- if (max_link_rate) {
- switch (max_link_rate) {
- case 1620:
- case 2700:
- case 5400:
- dp->video_info.max_link_rate =
- min_t(u8, dp->video_info.max_link_rate,
- drm_dp_link_rate_to_bw_code(max_link_rate * 100));
- break;
- default:
- dev_err(dev, "invalid max-link-rate %d\n", max_link_rate);
- break;
- }
- }
+ max_link_rate = analogix_dp_parse_link_frequencies(dp);
+ if (max_link_rate && max_link_rate < drm_dp_bw_code_to_link_rate(dp->video_info.max_link_rate))
+ dp->video_info.max_link_rate = drm_dp_link_rate_to_bw_code(max_link_rate);
if (dev_read_prop(dev, "data-lanes", &len)) {
num_lanes = len / sizeof(u32);
@@ -1075,8 +1094,9 @@
.lcdsel_big = 0 | BIT(21),
.lcdsel_lit = BIT(5) | BIT(21),
.chip_type = RK3399_EDP,
+ .ssc = true,
- .max_link_rate = DP_LINK_BW_2_7,
+ .max_link_rate = DP_LINK_BW_5_4,
.max_lane_count = 4,
};
diff --git a/u-boot/drivers/video/drm/drm_modes.c b/u-boot/drivers/video/drm/drm_modes.c
index fabae87..2c35919 100644
--- a/u-boot/drivers/video/drm/drm_modes.c
+++ b/u-boot/drivers/video/drm/drm_modes.c
@@ -60,6 +60,19 @@
}
/**
+ * drm_mode_copy - copy the mode
+ * @dst: mode to overwrite
+ * @src: mode to copy
+ *
+ * Copy an existing mode into another mode, preserving the object id and
+ * list head of the destination mode.
+ */
+void drm_mode_copy(struct drm_display_mode *dst, const struct drm_display_mode *src)
+{
+ *dst = *src;
+}
+
+/**
* drm_mode_destroy - remove a mode
* @mode: mode to remove
*/
@@ -185,6 +198,45 @@
}
/**
+ * drm_display_mode_from_videomode - fill in @dmode using @vm,
+ * @vm: videomode structure to use as source
+ * @dmode: drm_display_mode structure to use as destination
+ *
+ * Fills out @dmode using the display mode specified in @vm.
+ */
+void drm_display_mode_from_videomode(const struct videomode *vm,
+ struct drm_display_mode *dmode)
+{
+ dmode->hdisplay = vm->hactive;
+ dmode->hsync_start = dmode->hdisplay + vm->hfront_porch;
+ dmode->hsync_end = dmode->hsync_start + vm->hsync_len;
+ dmode->htotal = dmode->hsync_end + vm->hback_porch;
+
+ dmode->vdisplay = vm->vactive;
+ dmode->vsync_start = dmode->vdisplay + vm->vfront_porch;
+ dmode->vsync_end = dmode->vsync_start + vm->vsync_len;
+ dmode->vtotal = dmode->vsync_end + vm->vback_porch;
+
+ dmode->clock = vm->pixelclock / 1000;
+
+ dmode->flags = 0;
+ if (vm->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+ dmode->flags |= DRM_MODE_FLAG_PHSYNC;
+ else if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
+ dmode->flags |= DRM_MODE_FLAG_NHSYNC;
+ if (vm->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ dmode->flags |= DRM_MODE_FLAG_PVSYNC;
+ else if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
+ dmode->flags |= DRM_MODE_FLAG_NVSYNC;
+ if (vm->flags & DISPLAY_FLAGS_INTERLACED)
+ dmode->flags |= DRM_MODE_FLAG_INTERLACE;
+ if (vm->flags & DISPLAY_FLAGS_DOUBLESCAN)
+ dmode->flags |= DRM_MODE_FLAG_DBLSCAN;
+ if (vm->flags & DISPLAY_FLAGS_DOUBLECLK)
+ dmode->flags |= DRM_MODE_FLAG_DBLCLK;
+}
+
+/**
* drm_display_mode_to_videomode - fill in @vm using @dmode,
* @dmode: drm_display_mode structure to use as source
* @vm: videomode structure to use as destination
diff --git a/u-boot/drivers/video/drm/dw-dp.c b/u-boot/drivers/video/drm/dw-dp.c
index e6e5b0b..2af2f82 100644
--- a/u-boot/drivers/video/drm/dw-dp.c
+++ b/u-boot/drivers/video/drm/dw-dp.c
@@ -231,6 +231,7 @@
bool force_hpd;
bool force_output;
+ u32 max_link_rate;
};
enum {
@@ -562,7 +563,7 @@
!!(dpcd & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED);
link->revision = link->dpcd[DP_DPCD_REV];
- link->rate = min_t(u32, dp->phy.attrs.max_link_rate * 100,
+ link->rate = min_t(u32, min(dp->max_link_rate, dp->phy.attrs.max_link_rate * 100),
drm_dp_max_link_rate(link->dpcd));
link->lanes = min_t(u8, dp->phy.attrs.bus_width,
drm_dp_max_lane_count(link->dpcd));
@@ -1704,6 +1705,49 @@
return 0;
}
+static u32 dw_dp_parse_link_frequencies(struct dw_dp *dp)
+{
+ struct udevice *dev = dp->dev;
+ const struct device_node *endpoint;
+ u64 frequency = 0;
+
+ endpoint = rockchip_of_graph_get_endpoint_by_regs(dev->node, 1, 0);
+ if (!endpoint)
+ return 0;
+
+ if (of_property_read_u64(endpoint, "link-frequencies", &frequency) < 0)
+ return 0;
+
+ if (!frequency)
+ return 0;
+
+ do_div(frequency, 10 * 1000); /* symbol rate kbytes */
+
+ switch (frequency) {
+ case 162000:
+ case 270000:
+ case 540000:
+ case 810000:
+ break;
+ default:
+ dev_err(dev, "invalid link frequency value: %llu\n", frequency);
+ return 0;
+ }
+
+ return frequency;
+}
+
+static int dw_dp_parse_dt(struct dw_dp *dp)
+{
+ dp->force_hpd = dev_read_bool(dp->dev, "force-hpd");
+
+ dp->max_link_rate = dw_dp_parse_link_frequencies(dp);
+ if (!dp->max_link_rate)
+ dp->max_link_rate = 810000;
+
+ return 0;
+}
+
static int dw_dp_probe(struct udevice *dev)
{
struct dw_dp *dp = dev_get_priv(dev);
@@ -1723,8 +1767,6 @@
return ret;
}
- dp->force_hpd = dev_read_bool(dev, "force-hpd");
-
ret = gpio_request_by_name(dev, "hpd-gpios", 0, &dp->hpd_gpio,
GPIOD_IS_IN);
if (ret && ret != -ENOENT) {
@@ -1736,6 +1778,12 @@
dp->dev = dev;
+ ret = dw_dp_parse_dt(dp);
+ if (ret) {
+ dev_err(dev, "failed to parse DT\n");
+ return ret;
+ }
+
dw_dp_ddc_init(dp);
rockchip_connector_bind(&dp->connector, dev, dp->id, &dw_dp_connector_funcs, NULL,
diff --git a/u-boot/drivers/video/drm/dw_hdmi.c b/u-boot/drivers/video/drm/dw_hdmi.c
index f993a21..a30e4d5 100644
--- a/u-boot/drivers/video/drm/dw_hdmi.c
+++ b/u-boot/drivers/video/drm/dw_hdmi.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <malloc.h>
#include <syscon.h>
+#include <asm/gpio.h>
#include <asm/arch-rockchip/clock.h>
#include <asm/arch/vendor.h>
#include <edid.h>
@@ -27,6 +28,7 @@
#define HDCP_PRIVATE_KEY_SIZE 280
#define HDCP_KEY_SHA_SIZE 20
#define HDMI_HDCP1X_ID 5
+#define HDMI_EDID_BLOCK_LEN 128
/*
* Unless otherwise noted, entries in this table are 100% optimization.
* Values can be obtained from hdmi_compute_n() but that function is
@@ -181,6 +183,7 @@
bool sink_has_audio;
void *regs;
void *grf;
+ void *gpio_base;
struct dw_hdmi_i2c *i2c;
struct {
@@ -203,6 +206,8 @@
bool hdcp1x_enable;
bool output_bus_format_rgb;
+
+ struct gpio_desc hpd_gpiod;
};
static void dw_hdmi_writel(struct dw_hdmi *hdmi, u8 val, int offset)
@@ -409,6 +414,7 @@
{
struct dw_hdmi_i2c *i2c = hdmi->i2c;
int interrupt = 0, i = 20;
+ bool read_edid = false;
if (!i2c->is_regaddr) {
printf("set read register address to 0\n");
@@ -416,14 +422,36 @@
i2c->is_regaddr = true;
}
- while (length--) {
- hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS);
- if (i2c->is_segment)
- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
- HDMI_I2CM_OPERATION);
- else
- hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
- HDMI_I2CM_OPERATION);
+ /* edid reads are in 128 bytes. scdc reads are in 1 byte */
+ if (length == HDMI_EDID_BLOCK_LEN)
+ read_edid = true;
+
+ while (length > 0) {
+ hdmi_writeb(hdmi, i2c->slave_reg, HDMI_I2CM_ADDRESS);
+
+ if (read_edid) {
+ i2c->slave_reg += 8;
+ length -= 8;
+ } else {
+ i2c->slave_reg++;
+ length--;
+ }
+
+ if (i2c->is_segment) {
+ if (read_edid)
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8_EXT,
+ HDMI_I2CM_OPERATION);
+ else
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT,
+ HDMI_I2CM_OPERATION);
+ } else {
+ if (read_edid)
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ8,
+ HDMI_I2CM_OPERATION);
+ else
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ,
+ HDMI_I2CM_OPERATION);
+ }
while (i--) {
udelay(1000);
@@ -439,6 +467,10 @@
if (!interrupt) {
printf("[%s] i2c read reg[0x%02x] no interrupt\n",
__func__, i2c->slave_reg);
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
+ HDMI_I2CM_OPERATION);
+ udelay(1000);
return -EAGAIN;
}
@@ -446,11 +478,19 @@
if (interrupt & HDMI_IH_I2CM_STAT0_ERROR) {
printf("[%s] read reg[0x%02x] data error:0x%02x\n",
__func__, i2c->slave_reg, interrupt);
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
+ HDMI_I2CM_OPERATION);
+ udelay(1000);
return -EIO;
}
i = 20;
- *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
+ if (read_edid)
+ for (i = 0; i < 8; i++)
+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_READ_BUFF0 + i);
+ else
+ *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI);
}
i2c->is_segment = false;
@@ -490,8 +530,22 @@
break;
}
+ if (!interrupt) {
+ printf("[%s] i2c write reg[0x%02x] no interrupt\n",
+ __func__, i2c->slave_reg);
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
+ HDMI_I2CM_OPERATION);
+ udelay(1000);
+ return -EAGAIN;
+ }
+
if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
printf("[%s] write data error\n", __func__);
+ hdmi_writeb(hdmi, 0, HDMI_I2CM_SOFTRSTZ);
+ hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_BUS_CLEAR,
+ HDMI_I2CM_OPERATION);
+ udelay(1000);
return -EIO;
} else if (interrupt & m_I2CM_DONE) {
printf("[%s] write offset %02x success\n",
@@ -959,6 +1013,7 @@
* but it has a vedor phy.
*/
if (phy_type == DW_HDMI_PHY_VENDOR_PHY ||
+ hdmi->dev_type == RK3528_HDMI ||
hdmi->dev_type == RK3328_HDMI ||
hdmi->dev_type == RK3228_HDMI) {
/* Vendor PHYs require support from the glue layer. */
@@ -1042,14 +1097,11 @@
vmode->mpixelclock, vmode->mtmdsclock);
/* Set up HDMI_FC_INVIDCONF
- * fc_invidconf.HDCP_keepout must be set (1'b1)
- * when activate the scrambler feature.
+ * Some display equipments require that the interval
+ * between Video Data and Data island must be at least 58 pixels,
+ * and fc_invidconf.HDCP_keepout set (1'b1) can meet the requirement.
*/
- inv_val = (vmode->mtmdsclock > 340000000 ||
- (hdmi_info->scdc.scrambling.low_rates &&
- hdmi->scramble_low_rates) ?
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE :
- HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE);
+ inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE;
inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ?
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
@@ -1418,13 +1470,8 @@
HDMI_VP_CONF_PR_EN_MASK |
HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF);
- if ((color_depth == 5 && hdmi->previous_mode.htotal % 4) ||
- (color_depth == 6 && hdmi->previous_mode.htotal % 2))
- hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
- HDMI_VP_STUFF);
- else
- hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET,
- HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF);
+ hdmi_modb(hdmi, 0, HDMI_VP_STUFF_IDEFAULT_PHASE_MASK,
+ HDMI_VP_STUFF);
hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP);
@@ -1887,6 +1934,7 @@
hdmi->sample_rate);
}
+#ifndef CONFIG_SPL_BUILD
static int dw_hdmi_hdcp_load_key(struct dw_hdmi *hdmi)
{
int i, j, ret, val;
@@ -1952,6 +2000,7 @@
free(hdcp_keys);
return 0;
}
+#endif
static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi,
const struct drm_display_mode *mode)
@@ -1981,8 +2030,10 @@
hdmi_modb(hdmi, hdmi_dvi, HDMI_A_HDCPCFG0_HDMIDVI_MASK,
HDMI_A_HDCPCFG0);
+#ifndef CONFIG_SPL_BUILD
if (!(hdmi_readb(hdmi, HDMI_HDCPREG_RMSTS) & 0x3f))
dw_hdmi_hdcp_load_key(hdmi);
+#endif
hdmi_modb(hdmi, HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE,
HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK,
@@ -2269,13 +2320,18 @@
{
struct connector_state *conn_state = &state->conn_state;
const struct dw_hdmi_plat_data *pdata =
+#ifdef CONFIG_SPL_BUILD
+ (const struct dw_hdmi_plat_data *)conn->data;
+#else
(const struct dw_hdmi_plat_data *)dev_get_driver_data(conn->dev);
+ ofnode hdmi_node = conn->dev->node;
+ struct device_node *ddc_node;
+ int ret;
+#endif
struct crtc_state *crtc_state = &state->crtc_state;
struct dw_hdmi *hdmi;
struct drm_display_mode *mode_buf;
- ofnode hdmi_node = conn->dev->node;
u32 val;
- struct device_node *ddc_node;
hdmi = malloc(sizeof(struct dw_hdmi));
if (!hdmi)
@@ -2285,13 +2341,28 @@
mode_buf = malloc(MODE_LEN * sizeof(struct drm_display_mode));
if (!mode_buf)
return -ENOMEM;
+
+#ifdef CONFIG_SPL_BUILD
+ hdmi->id = 0;
+ hdmi->regs = (void *)RK3528_HDMI_BASE;
+ hdmi->io_width = 4;
+ hdmi->scramble_low_rates = false;
+ hdmi->hdcp1x_enable = false;
+ hdmi->output_bus_format_rgb = false;
+ conn_state->type = DRM_MODE_CONNECTOR_HDMIA;
+#else
hdmi->id = of_alias_get_id(ofnode_to_np(hdmi_node), "hdmi");
if (hdmi->id < 0)
hdmi->id = 0;
- conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
+#endif
memset(mode_buf, 0, MODE_LEN * sizeof(struct drm_display_mode));
+ hdmi->dev_type = pdata->dev_type;
+ hdmi->plat_data = pdata;
+
+#ifndef CONFIG_SPL_BUILD
hdmi->regs = dev_read_addr_ptr(conn->dev);
hdmi->io_width = ofnode_read_s32_default(hdmi_node, "reg-io-width", -1);
@@ -2309,6 +2380,24 @@
else
hdmi->output_bus_format_rgb = false;
+ ret = dev_read_size(conn->dev, "rockchip,phy-table");
+ if (ret > 0 && hdmi->plat_data->phy_config) {
+ u32 phy_config[ret / 4];
+ int i;
+
+ dev_read_u32_array(conn->dev, "rockchip,phy-table", phy_config, ret / 4);
+
+ for (i = 0; i < ret / 16; i++) {
+ if (phy_config[i * 4] != 0)
+ hdmi->plat_data->phy_config[i].mpixelclock = (u64)phy_config[i * 4];
+ else
+ hdmi->plat_data->phy_config[i].mpixelclock = ~0UL;
+ hdmi->plat_data->phy_config[i].sym_ctr = (u16)phy_config[i * 4 + 1];
+ hdmi->plat_data->phy_config[i].term = (u16)phy_config[i * 4 + 2];
+ hdmi->plat_data->phy_config[i].vlev_ctr = (u16)phy_config[i * 4 + 3];
+ }
+ }
+
ddc_node = of_parse_phandle(ofnode_to_np(hdmi_node), "ddc-i2c-bus", 0);
if (ddc_node) {
uclass_get_device_by_ofnode(UCLASS_I2C, np_to_ofnode(ddc_node),
@@ -2316,6 +2405,7 @@
if (hdmi->adap.i2c_bus)
hdmi->adap.ops = i2c_get_ops(hdmi->adap.i2c_bus);
}
+#endif
hdmi->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (hdmi->grf <= 0) {
@@ -2323,6 +2413,20 @@
__func__, hdmi->grf);
return -ENXIO;
}
+
+#ifdef CONFIG_SPL_BUILD
+ hdmi->gpio_base = (void *)RK3528_GPIO_BASE;
+#else
+ ret = gpio_request_by_name(conn->dev, "hpd-gpios", 0,
+ &hdmi->hpd_gpiod, GPIOD_IS_IN);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get HPD GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+ hdmi->gpio_base = (void *)dev_read_addr_index(conn->dev, 1);
+#endif
+ if (!hdmi->gpio_base)
+ return -ENODEV;
dw_hdmi_set_reg_wr(hdmi);
@@ -2345,24 +2449,28 @@
* Read high and low time from device tree. If not available use
* the default timing scl clock rate is about 99.6KHz.
*/
+#ifdef CONFIG_SPL_BUILD
+ hdmi->i2c->scl_high_ns = 9625;
+ hdmi->i2c->scl_low_ns = 10000;
+#else
hdmi->i2c->scl_high_ns =
ofnode_read_s32_default(hdmi_node,
"ddc-i2c-scl-high-time-ns", 4708);
hdmi->i2c->scl_low_ns =
ofnode_read_s32_default(hdmi_node,
"ddc-i2c-scl-low-time-ns", 4916);
+#endif
dw_hdmi_i2c_init(hdmi);
conn_state->output_if |= VOP_OUTPUT_IF_HDMI0;
conn_state->output_mode = ROCKCHIP_OUT_MODE_AAAA;
- hdmi->dev_type = pdata->dev_type;
- hdmi->plat_data = pdata;
hdmi->edid_data.mode_buf = mode_buf;
hdmi->sample_rate = 48000;
conn->data = hdmi;
- dw_hdmi_set_iomux(hdmi->grf, hdmi->dev_type);
+ dw_hdmi_set_iomux(hdmi->grf, hdmi->gpio_base,
+ &hdmi->hpd_gpiod, hdmi->dev_type);
dw_hdmi_detect_phy(hdmi);
dw_hdmi_dev_init(hdmi);
@@ -2413,7 +2521,7 @@
int rockchip_dw_hdmi_get_timing(struct rockchip_connector *conn, struct display_state *state)
{
- int ret, i;
+ int ret, i, vic;
struct connector_state *conn_state = &state->conn_state;
struct drm_display_mode *mode = &conn_state->mode;
struct dw_hdmi *hdmi = conn->data;
@@ -2439,9 +2547,13 @@
hdmi->sink_has_audio = true;
do_cea_modes(&hdmi->edid_data, def_modes_vic,
sizeof(def_modes_vic));
+ hdmi->edid_data.mode_buf[0].type |= DRM_MODE_TYPE_PREFERRED;
hdmi->edid_data.preferred_mode = &hdmi->edid_data.mode_buf[0];
printf("failed to get edid\n");
}
+#ifdef CONFIG_SPL_BUILD
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, hdmi->id);
+#endif
drm_rk_filter_whitelist(&hdmi->edid_data);
if (hdmi->phy.ops->mode_valid)
hdmi->phy.ops->mode_valid(conn, hdmi, state);
@@ -2452,9 +2564,20 @@
return -EINVAL;
}
- for (i = 0; i < hdmi->edid_data.modes; i++)
+ for (i = 0; i < hdmi->edid_data.modes; i++) {
hdmi->edid_data.mode_buf[i].vrefresh =
drm_mode_vrefresh(&hdmi->edid_data.mode_buf[i]);
+
+ vic = drm_match_cea_mode(&hdmi->edid_data.mode_buf[i]);
+ if (hdmi->edid_data.mode_buf[i].picture_aspect_ratio == HDMI_PICTURE_ASPECT_NONE) {
+ if (vic >= 93 && vic <= 95)
+ hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
+ HDMI_PICTURE_ASPECT_16_9;
+ else if (vic == 98)
+ hdmi->edid_data.mode_buf[i].picture_aspect_ratio =
+ HDMI_PICTURE_ASPECT_256_135;
+ }
+ }
drm_mode_sort(&hdmi->edid_data);
drm_rk_selete_output(&hdmi->edid_data, conn_state, &bus_format,
@@ -2463,7 +2586,6 @@
*mode = *hdmi->edid_data.preferred_mode;
hdmi->vic = drm_match_cea_mode(mode);
- printf("mode:%dx%d\n", mode->hdisplay, mode->vdisplay);
if (state->force_output)
bus_format = state->force_bus_format;
conn_state->bus_format = bus_format;
diff --git a/u-boot/drivers/video/drm/dw_hdmi.h b/u-boot/drivers/video/drm/dw_hdmi.h
index f002dea..3872dae 100644
--- a/u-boot/drivers/video/drm/dw_hdmi.h
+++ b/u-boot/drivers/video/drm/dw_hdmi.h
@@ -1194,6 +1194,7 @@
HDMI_A_VIDPOLCFG_HSYNCPOL_ACTIVE_LOW = 0x0,
/* I2CM_OPERATION field values */
+ HDMI_I2CM_OPERATION_BUS_CLEAR = 0x20,
HDMI_I2CM_OPERATION_WRITE = 0x10,
HDMI_I2CM_OPERATION_READ8_EXT = 0x8,
HDMI_I2CM_OPERATION_READ8 = 0x4,
@@ -1411,6 +1412,7 @@
enum dw_hdmi_devtype dev_type,
bool output_bus_format_rgb);
void inno_dw_hdmi_set_domain(void *grf, int status);
-void dw_hdmi_set_iomux(void *grf, int dev_type);
+void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod,
+ int dev_type);
#endif /* _ROCKCHIP_HDMI_H_ */
diff --git a/u-boot/drivers/video/drm/dw_hdmi_qp.c b/u-boot/drivers/video/drm/dw_hdmi_qp.c
index 7a8b54f..0e28702 100644
--- a/u-boot/drivers/video/drm/dw_hdmi_qp.c
+++ b/u-boot/drivers/video/drm/dw_hdmi_qp.c
@@ -175,6 +175,9 @@
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_UYVY10_1X20:
case MEDIA_BUS_FMT_UYVY12_1X24:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ case MEDIA_BUS_FMT_YUYV10_1X20:
+ case MEDIA_BUS_FMT_YUYV12_1X24:
return true;
default:
@@ -1047,6 +1050,9 @@
/* HDMI Initialization Step B.2 */
hdmi->phy.ops->set_pll(conn, hdmi->rk_hdmi, state);
+ /* Mark yuv422 10bit */
+ if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
+ hdmi_writel(hdmi, BIT(20), VIDEO_INTERFACE_CONFIG0);
rk3588_set_grf_cfg(hdmi->rk_hdmi);
link_cfg = dw_hdmi_rockchip_get_link_cfg(hdmi->rk_hdmi);
@@ -1094,6 +1100,9 @@
hdmi->phy.enabled = true;
printf("%s DVI mode\n", __func__);
}
+
+ /* Mark uboot hdmi is enabled */
+ hdmi_writel(hdmi, BIT(21), VIDEO_INTERFACE_CONFIG0);
return 0;
}
@@ -1239,9 +1248,23 @@
return 0;
}
-int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
+static void rockchip_dw_hdmi_qp_mode_valid(struct dw_hdmi_qp *hdmi)
{
- int ret, i;
+ struct hdmi_edid_data *edid_data = &hdmi->edid_data;
+ int i;
+
+ for (i = 0; i < edid_data->modes; i++) {
+ if (edid_data->mode_buf[i].invalid)
+ continue;
+ if (edid_data->mode_buf[i].clock <= 25000)
+ edid_data->mode_buf[i].invalid = true;
+ }
+}
+
+static int _rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn,
+ struct display_state *state, int edid_status)
+{
+ int i;
struct connector_state *conn_state = &state->conn_state;
struct drm_display_mode *mode = &conn_state->mode;
struct dw_hdmi_qp *hdmi = conn->data;
@@ -1254,14 +1277,13 @@
if (!hdmi)
return -EFAULT;
- ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
- if (!ret) {
+ if (!edid_status) {
hdmi->sink_is_hdmi =
drm_detect_hdmi_monitor(edid);
hdmi->sink_has_audio = drm_detect_monitor_audio(edid);
- ret = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
+ edid_status = drm_add_edid_modes(&hdmi->edid_data, conn_state->edid);
}
- if (ret < 0) {
+ if (edid_status < 0) {
hdmi->sink_is_hdmi = true;
hdmi->sink_has_audio = true;
do_cea_modes(&hdmi->edid_data, def_modes_vic,
@@ -1270,8 +1292,7 @@
printf("failed to get edid\n");
}
drm_rk_filter_whitelist(&hdmi->edid_data);
- if (hdmi->phy.ops->mode_valid)
- hdmi->phy.ops->mode_valid(hdmi->rk_hdmi, state);
+ rockchip_dw_hdmi_qp_mode_valid(hdmi);
drm_mode_max_resolution_filter(&hdmi->edid_data,
&state->crtc_state.max_output);
if (!drm_mode_prune_invalid(&hdmi->edid_data)) {
@@ -1298,15 +1319,17 @@
hdmi->hdmi_data.enc_out_bus_format = bus_format;
switch (bus_format) {
- case MEDIA_BUS_FMT_UYVY10_1X20:
- conn_state->bus_format = MEDIA_BUS_FMT_YUV10_1X30;
+ case MEDIA_BUS_FMT_YUYV10_1X20:
+ conn_state->bus_format = MEDIA_BUS_FMT_YUYV10_1X20;
hdmi->hdmi_data.enc_in_bus_format =
- MEDIA_BUS_FMT_YUV10_1X30;
+ MEDIA_BUS_FMT_YUYV10_1X20;
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
break;
- case MEDIA_BUS_FMT_UYVY8_1X16:
- conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ conn_state->bus_format = MEDIA_BUS_FMT_YUYV8_1X16;
hdmi->hdmi_data.enc_in_bus_format =
- MEDIA_BUS_FMT_YUV8_1X24;
+ MEDIA_BUS_FMT_YUYV8_1X16;
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_YUV422;
break;
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
@@ -1334,6 +1357,21 @@
return 0;
}
+int rockchip_dw_hdmi_qp_get_timing(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct dw_hdmi_qp *hdmi = conn->data;
+ int ret;
+
+ ret = drm_do_get_edid(&hdmi->adap, conn_state->edid);
+
+ if (conn_state->secondary)
+ _rockchip_dw_hdmi_qp_get_timing(conn_state->secondary, state, ret);
+
+ return _rockchip_dw_hdmi_qp_get_timing(conn, state, ret);
+}
+
+
int rockchip_dw_hdmi_qp_detect(struct rockchip_connector *conn, struct display_state *state)
{
int ret;
diff --git a/u-boot/drivers/video/drm/dw_mipi_dsi.c b/u-boot/drivers/video/drm/dw_mipi_dsi.c
index 2a490d1..bf337f7 100644
--- a/u-boot/drivers/video/drm/dw_mipi_dsi.c
+++ b/u-boot/drivers/video/drm/dw_mipi_dsi.c
@@ -1489,6 +1489,21 @@
.max_bit_rate_per_lane = 1500000000UL,
};
+static const u32 rk3562_dsi_grf_reg_fields[MAX_FIELDS] = {
+ [DPIUPDATECFG] = GRF_REG_FIELD(0x05d0, 2, 2),
+ [DPICOLORM] = GRF_REG_FIELD(0x05d0, 1, 1),
+ [DPISHUTDN] = GRF_REG_FIELD(0x05d0, 0, 0),
+ [SKEWCALHS] = GRF_REG_FIELD(0x05d4, 11, 15),
+ [FORCETXSTOPMODE] = GRF_REG_FIELD(0x05d4, 4, 7),
+ [TURNDISABLE] = GRF_REG_FIELD(0x05d4, 2, 2),
+ [FORCERXMODE] = GRF_REG_FIELD(0x05d4, 0, 0),
+};
+
+static const struct dw_mipi_dsi_plat_data rk3562_mipi_dsi_plat_data = {
+ .dsi0_grf_reg_fields = rk3562_dsi_grf_reg_fields,
+ .max_bit_rate_per_lane = 1200000000UL,
+};
+
static const u32 rk3568_dsi0_grf_reg_fields[MAX_FIELDS] = {
[DPIUPDATECFG] = GRF_REG_FIELD(0x0360, 2, 2),
[DPICOLORM] = GRF_REG_FIELD(0x0360, 1, 1),
@@ -1573,6 +1588,10 @@
.data = (ulong)&rk3399_mipi_dsi_plat_data,
},
{
+ .compatible = "rockchip,rk3562-mipi-dsi",
+ .data = (ulong)&rk3562_mipi_dsi_plat_data,
+ },
+ {
.compatible = "rockchip,rk3568-mipi-dsi",
.data = (ulong)&rk3568_mipi_dsi_plat_data,
},
diff --git a/u-boot/drivers/video/drm/dw_mipi_dsi2.c b/u-boot/drivers/video/drm/dw_mipi_dsi2.c
index 1ee8652..42f3314 100644
--- a/u-boot/drivers/video/drm/dw_mipi_dsi2.c
+++ b/u-boot/drivers/video/drm/dw_mipi_dsi2.c
@@ -12,6 +12,7 @@
#include <common.h>
#include <errno.h>
#include <asm/unaligned.h>
+#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/hardware.h>
#include <dm/device.h>
@@ -22,7 +23,6 @@
#include <asm/arch-rockchip/clock.h>
#include <linux/iopoll.h>
-#include "rockchip_bridge.h"
#include "rockchip_display.h"
#include "rockchip_crtc.h"
#include "rockchip_connector.h"
@@ -289,6 +289,7 @@
struct drm_display_mode mode;
bool data_swap;
+ struct gpio_desc te_gpio;
struct mipi_dsi_device *device;
struct mipi_dphy_configure mipi_dphy_cfg;
const struct dw_mipi_dsi2_plat_data *pdata;
@@ -693,42 +694,79 @@
static int dw_mipi_dsi2_connector_pre_init(struct rockchip_connector *conn,
struct display_state *state)
{
+ struct connector_state *conn_state = &state->conn_state;
struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);
struct mipi_dsi_host *host = dev_get_platdata(dsi2->dev);
struct mipi_dsi_device *device;
char name[20];
- struct udevice *dev;
- device = calloc(1, sizeof(struct dw_mipi_dsi2));
- if (!device)
- return -ENOMEM;
+ conn_state->type = DRM_MODE_CONNECTOR_DSI;
- if (conn->bridge)
- dev = conn->bridge->dev;
- else if (conn->panel)
- dev = conn->panel->dev;
- else
- return -ENODEV;
+ if (conn->bridge) {
+ device = dev_get_platdata(conn->bridge->dev);
+ if (!device)
+ return -ENODEV;
- device->dev = dev;
- device->host = host;
- device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
- device->channel = dev_read_u32_default(dev, "reg", 0);
- device->format = dev_read_u32_default(dev, "dsi,format",
- MIPI_DSI_FMT_RGB888);
- device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
- MIPI_DSI_MODE_VIDEO |
- MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_VIDEO_HBP |
- MIPI_DSI_MODE_LPM |
- MIPI_DSI_MODE_EOT_PACKET);
+ device->host = host;
+ sprintf(name, "%s.%d", host->dev->name, device->channel);
+ device_set_name(conn->bridge->dev, name);
+ mipi_dsi_attach(device);
+ }
- sprintf(name, "%s.%d", host->dev->name, device->channel);
- device_set_name(dev, name);
- dsi2->device = device;
- dev->parent_platdata = device;
+ return 0;
+}
- mipi_dsi_attach(dsi2->device);
+static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2)
+{
+ struct udevice *dev = dsi2->device->dev;
+ struct rockchip_cmd_header *header;
+ struct drm_dsc_picture_parameter_set *pps = NULL;
+ u8 *dsc_packed_pps;
+ const void *data;
+ int len;
+
+ dsi2->c_option = dev_read_bool(dev, "phy-c-option");
+ dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable");
+ dsi2->dsc_enable = dev_read_bool(dev, "compressed-data");
+
+ if (dsi2->slave) {
+ dsi2->slave->c_option = dsi2->c_option;
+ dsi2->slave->scrambling_en = dsi2->scrambling_en;
+ dsi2->slave->dsc_enable = dsi2->dsc_enable;
+ }
+
+ dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0);
+ dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0);
+ dsi2->version_major = dev_read_u32_default(dev, "version-major", 0);
+ dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0);
+
+ data = dev_read_prop(dev, "panel-init-sequence", &len);
+ if (!data)
+ return -EINVAL;
+
+ while (len > sizeof(*header)) {
+ header = (struct rockchip_cmd_header *)data;
+ data += sizeof(*header);
+ len -= sizeof(*header);
+
+ if (header->payload_length > len)
+ return -EINVAL;
+
+ if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
+ dsc_packed_pps = calloc(1, header->payload_length);
+ if (!dsc_packed_pps)
+ return -ENOMEM;
+
+ memcpy(dsc_packed_pps, data, header->payload_length);
+ pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
+ break;
+ }
+
+ data += header->payload_length;
+ len -= header->payload_length;
+ }
+
+ dsi2->pps = pps;
return 0;
}
@@ -792,6 +830,13 @@
dsi2->slave->dcphy.phy = phy;
if (phy->funcs && phy->funcs->init)
return phy->funcs->init(phy);
+ }
+
+ dw_mipi_dsi2_get_dsc_params_from_sink(dsi2);
+
+ if (dm_gpio_is_valid(&dsi2->te_gpio)) {
+ cstate->soft_te = true;
+ conn_state->te_gpio = &dsi2->te_gpio;
}
if (dsi2->dsc_enable) {
@@ -905,7 +950,7 @@
static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2)
{
- u32 sys_clk = SYS_CLK / MSEC_PER_SEC;
+ u32 sys_clk = SYS_CLK / USEC_PER_SEC;
u32 esc_clk_div;
u32 val = 0;
@@ -913,7 +958,7 @@
val |= NON_CONTINUOUS_CLK;
/* The Escape clock ranges from 1MHz to 20MHz. */
- esc_clk_div = DIV_ROUND_UP(sys_clk, 10 * 2);
+ esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2);
val |= PHY_LPTX_CLK_DIV(esc_clk_div);
dsi_write(dsi2, DSI2_PHY_CLK_CFG, val);
@@ -1102,6 +1147,41 @@
return 0;
}
+static int dw_mipi_dsi2_connector_mode_valid(struct rockchip_connector *conn,
+ struct display_state *state)
+{
+ struct dw_mipi_dsi2 *dsi2 = dev_get_priv(conn->dev);
+ struct connector_state *conn_state = &state->conn_state;
+ u8 min_pixels = dsi2->slave ? 8 : 4;
+ struct videomode vm;
+
+ drm_display_mode_to_videomode(&conn_state->mode, &vm);
+
+ /*
+ * the minimum region size (HSA,HBP,HACT,HFP) is 4 pixels
+ * which is the ip known issues and limitations.
+ */
+ if (!(vm.hsync_len < min_pixels || vm.hback_porch < min_pixels ||
+ vm.hfront_porch < min_pixels || vm.hactive < min_pixels))
+ return MODE_OK;
+
+ if (vm.hsync_len < min_pixels)
+ vm.hsync_len = min_pixels;
+
+ if (vm.hback_porch < min_pixels)
+ vm.hback_porch = min_pixels;
+
+ if (vm.hfront_porch < min_pixels)
+ vm.hfront_porch = min_pixels;
+
+ if (vm.hactive < min_pixels)
+ vm.hactive = min_pixels;
+
+ drm_display_mode_from_videomode(&vm, &conn_state->mode);
+
+ return MODE_OK;
+}
+
static const struct rockchip_connector_funcs dw_mipi_dsi2_connector_funcs = {
.pre_init = dw_mipi_dsi2_connector_pre_init,
.init = dw_mipi_dsi2_connector_init,
@@ -1109,6 +1189,7 @@
.unprepare = dw_mipi_dsi2_connector_unprepare,
.enable = dw_mipi_dsi2_connector_enable,
.disable = dw_mipi_dsi2_connector_disable,
+ .mode_valid = dw_mipi_dsi2_connector_mode_valid,
};
static int dw_mipi_dsi2_probe(struct udevice *dev)
@@ -1132,6 +1213,13 @@
id = of_alias_get_id(ofnode_to_np(dev->node), "dsi");
if (id < 0)
id = 0;
+
+ ret = gpio_request_by_name(dev, "te-gpios", 0,
+ &dsi2->te_gpio, GPIOD_IS_IN);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get TE GPIO: %d\n", __func__, ret);
+ return ret;
+ }
dsi2->dev = dev;
dsi2->pdata = pdata;
@@ -1185,61 +1273,6 @@
return dw_mipi_dsi2_transfer(dsi2, msg);
}
-static int dw_mipi_dsi2_get_dsc_params_from_sink(struct dw_mipi_dsi2 *dsi2)
-{
- struct udevice *dev = dsi2->device->dev;
- struct rockchip_cmd_header *header;
- struct drm_dsc_picture_parameter_set *pps = NULL;
- u8 *dsc_packed_pps;
- const void *data;
- int len;
-
- dsi2->c_option = dev_read_bool(dev, "phy-c-option");
- dsi2->scrambling_en = dev_read_bool(dev, "scrambling-enable");
- dsi2->dsc_enable = dev_read_bool(dev, "compressed-data");
-
- if (dsi2->slave) {
- dsi2->slave->c_option = dsi2->c_option;
- dsi2->slave->scrambling_en = dsi2->scrambling_en;
- dsi2->slave->dsc_enable = dsi2->dsc_enable;
- }
-
- dsi2->slice_width = dev_read_u32_default(dev, "slice-width", 0);
- dsi2->slice_height = dev_read_u32_default(dev, "slice-height", 0);
- dsi2->version_major = dev_read_u32_default(dev, "version-major", 0);
- dsi2->version_minor = dev_read_u32_default(dev, "version-minor", 0);
-
- data = dev_read_prop(dev, "panel-init-sequence", &len);
- if (!data)
- return -EINVAL;
-
- while (len > sizeof(*header)) {
- header = (struct rockchip_cmd_header *)data;
- data += sizeof(*header);
- len -= sizeof(*header);
-
- if (header->payload_length > len)
- return -EINVAL;
-
- if (header->data_type == MIPI_DSI_PICTURE_PARAMETER_SET) {
- dsc_packed_pps = calloc(1, header->payload_length);
- if (!dsc_packed_pps)
- return -ENOMEM;
-
- memcpy(dsc_packed_pps, data, header->payload_length);
- pps = (struct drm_dsc_picture_parameter_set *)dsc_packed_pps;
- break;
- }
-
- data += header->payload_length;
- len -= header->payload_length;
- }
-
- dsi2->pps = pps;
-
- return 0;
-}
-
static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
@@ -1252,8 +1285,7 @@
dsi2->channel = device->channel;
dsi2->format = device->format;
dsi2->mode_flags = device->mode_flags;
-
- dw_mipi_dsi2_get_dsc_params_from_sink(dsi2);
+ dsi2->device = device;
return 0;
}
@@ -1273,6 +1305,45 @@
return dm_scan_fdt_dev(dev);
}
+static int dw_mipi_dsi2_child_post_bind(struct udevice *dev)
+{
+ struct mipi_dsi_host *host = dev_get_platdata(dev->parent);
+ struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
+ char name[20];
+
+ sprintf(name, "%s.%d", host->dev->name, device->channel);
+ device_set_name(dev, name);
+
+ device->dev = dev;
+ device->host = host;
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
+ device->format = dev_read_u32_default(dev, "dsi,format",
+ MIPI_DSI_FMT_RGB888);
+ device->mode_flags = dev_read_u32_default(dev, "dsi,flags",
+ MIPI_DSI_MODE_VIDEO |
+ MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_VIDEO_HBP |
+ MIPI_DSI_MODE_LPM |
+ MIPI_DSI_MODE_EOT_PACKET);
+ device->channel = dev_read_u32_default(dev, "reg", 0);
+
+ return 0;
+}
+
+static int dw_mipi_dsi2_child_pre_probe(struct udevice *dev)
+{
+ struct mipi_dsi_device *device = dev_get_parent_platdata(dev);
+ int ret;
+
+ ret = mipi_dsi_attach(device);
+ if (ret) {
+ dev_err(dev, "mipi_dsi_attach() failed: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
U_BOOT_DRIVER(dw_mipi_dsi2) = {
.name = "dw_mipi_dsi2",
.id = UCLASS_DISPLAY,
@@ -1280,5 +1351,8 @@
.probe = dw_mipi_dsi2_probe,
.bind = dw_mipi_dsi2_bind,
.priv_auto_alloc_size = sizeof(struct dw_mipi_dsi2),
+ .per_child_platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
.platdata_auto_alloc_size = sizeof(struct mipi_dsi_host),
+ .child_post_bind = dw_mipi_dsi2_child_post_bind,
+ .child_pre_probe = dw_mipi_dsi2_child_pre_probe,
};
diff --git a/u-boot/drivers/video/drm/max96745.c b/u-boot/drivers/video/drm/max96745.c
index c824e01..3750f4d 100644
--- a/u-boot/drivers/video/drm/max96745.c
+++ b/u-boot/drivers/video/drm/max96745.c
@@ -9,41 +9,111 @@
#include <i2c.h>
#include <max96745.h>
#include <video_bridge.h>
+#include <linux/iopoll.h>
#include "rockchip_bridge.h"
#include "rockchip_display.h"
#include "rockchip_panel.h"
-struct max96745_bridge_priv {
- struct gpio_desc lock_gpio;
-};
-
-static bool max96745_bridge_detect(struct rockchip_bridge *bridge)
+static bool max96745_bridge_link_locked(struct udevice *dev)
{
- struct max96745_bridge_priv *priv = dev_get_priv(bridge->dev);
+ int ret;
- if (!dm_gpio_get_value(&priv->lock_gpio))
+ ret = dm_i2c_reg_read(dev->parent, 0x002a);
+ if (ret < 0)
+ return false;
+
+ if (!FIELD_GET(LINK_LOCKED, ret))
return false;
return true;
}
+static bool max96745_bridge_detect(struct rockchip_bridge *bridge)
+{
+ return max96745_bridge_link_locked(bridge->dev);
+}
+
+static void max96745_bridge_enable(struct rockchip_bridge *bridge)
+{
+ struct udevice *dev = bridge->dev;
+ struct drm_display_mode *mode = &bridge->state->conn_state.mode;
+ u8 cxtp, tx_rate;
+ int ret;
+
+ ret = dm_i2c_reg_read(dev->parent, 0x0011);
+ if (ret < 0)
+ return;
+
+ cxtp = FIELD_GET(CXTP_A, ret);
+
+ ret = dm_i2c_reg_read(dev->parent, 0x0028);
+ if (ret < 0)
+ return;
+
+ tx_rate = FIELD_GET(TX_RATE, ret);
+
+ if (!cxtp && mode->clock > 95000 && tx_rate == 1) {
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0028, TX_RATE,
+ FIELD_PREP(TX_RATE, 2));
+ if (ret < 0)
+ return;
+
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0029, RESET_ONESHOT,
+ FIELD_PREP(RESET_ONESHOT, 1));
+ if (ret < 0)
+ return;
+
+ if (readx_poll_timeout(max96745_bridge_link_locked, dev, ret,
+ ret, 200000))
+ dev_err(dev, "%s: GMSL link not locked\n", __func__);
+ }
+}
+
+static void max96745_bridge_post_disable(struct rockchip_bridge *bridge)
+{
+ struct udevice *dev = bridge->dev;
+ u8 cxtp, tx_rate;
+ int ret;
+
+ ret = dm_i2c_reg_read(dev->parent, 0x0011);
+ if (ret < 0)
+ return;
+
+ cxtp = FIELD_GET(CXTP_A, ret);
+
+ ret = dm_i2c_reg_read(dev->parent, 0x0028);
+ if (ret < 0)
+ return;
+
+ tx_rate = FIELD_GET(TX_RATE, ret);
+
+ if (!cxtp && tx_rate == 2) {
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0028, TX_RATE,
+ FIELD_PREP(TX_RATE, 1));
+ if (ret < 0)
+ return;
+
+ ret = dm_i2c_reg_clrset(dev->parent, 0x0029, RESET_ONESHOT,
+ FIELD_PREP(RESET_ONESHOT, 1));
+ if (ret < 0)
+ return;
+
+ if (readx_poll_timeout(max96745_bridge_link_locked, dev, ret,
+ ret, 200000))
+ dev_err(dev, "%s: GMSL link not locked\n", __func__);
+ }
+}
+
static const struct rockchip_bridge_funcs max96745_bridge_funcs = {
- .detect = max96745_bridge_detect,
+ .detect = max96745_bridge_detect,
+ .enable = max96745_bridge_enable,
+ .post_disable = max96745_bridge_post_disable,
};
static int max96745_bridge_probe(struct udevice *dev)
{
- struct max96745_bridge_priv *priv = dev_get_priv(dev);
struct rockchip_bridge *bridge;
- int ret;
-
- ret = gpio_request_by_name(dev, "lock-gpios", 0, &priv->lock_gpio,
- GPIOD_IS_IN);
- if (ret) {
- dev_err(dev, "failed to get lock GPIO: %d\n", ret);
- return ret;
- }
bridge = calloc(1, sizeof(*bridge));
if (!bridge)
@@ -66,5 +136,4 @@
.id = UCLASS_VIDEO_BRIDGE,
.of_match = max96745_bridge_of_match,
.probe = max96745_bridge_probe,
- .priv_auto_alloc_size = sizeof(struct max96745_bridge_priv),
};
diff --git a/u-boot/drivers/video/drm/max96752f.c b/u-boot/drivers/video/drm/max96752f.c
deleted file mode 100644
index e7553d1..0000000
--- a/u-boot/drivers/video/drm/max96752f.c
+++ /dev/null
@@ -1,79 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#include <common.h>
-#include <dm.h>
-#include <errno.h>
-#include <i2c.h>
-#include <linux/media-bus-format.h>
-#include <max96752f.h>
-#include <video_bridge.h>
-
-#include "rockchip_bridge.h"
-#include "rockchip_display.h"
-#include "rockchip_panel.h"
-
-static void max96752f_bridge_pre_enable(struct rockchip_bridge *bridge)
-{
- struct udevice *dev = bridge->dev;
- struct connector_state *conn_state = &bridge->state->conn_state;
- bool oldi_format, oldi_4th_lane;
-
- max96752f_init(dev->parent);
-
- switch (conn_state->bus_format) {
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
- oldi_4th_lane = false;
- oldi_format = 0x0;
- break;
- case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
- oldi_4th_lane = true;
- oldi_format = 0x0;
- break;
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
- oldi_4th_lane = false;
- oldi_format = 0x1;
- break;
- default:
- oldi_4th_lane = false;
- oldi_format = 0x1;
- break;
- }
-
- dm_i2c_reg_clrset(dev->parent, 0x01ce, OLDI_FORMAT | OLDI_4TH_LANE,
- FIELD_PREP(OLDI_4TH_LANE, oldi_4th_lane) |
- FIELD_PREP(OLDI_FORMAT, oldi_format));
-}
-
-static const struct rockchip_bridge_funcs max96752f_bridge_funcs = {
- .pre_enable = max96752f_bridge_pre_enable,
-};
-
-static int max96752f_bridge_probe(struct udevice *dev)
-{
- struct rockchip_bridge *bridge;
-
- bridge = calloc(1, sizeof(*bridge));
- if (!bridge)
- return -ENOMEM;
-
- dev->driver_data = (ulong)bridge;
- bridge->dev = dev;
- bridge->funcs = &max96752f_bridge_funcs;
-
- return 0;
-}
-
-static const struct udevice_id max96752f_bridge_of_match[] = {
- { .compatible = "maxim,max96752f-bridge", },
- { }
-};
-
-U_BOOT_DRIVER(max96752f_bridge) = {
- .name = "max96752f_bridge",
- .id = UCLASS_VIDEO_BRIDGE,
- .of_match = max96752f_bridge_of_match,
- .probe = max96752f_bridge_probe,
-};
diff --git a/u-boot/drivers/video/drm/max96755f.c b/u-boot/drivers/video/drm/max96755f.c
index e09849f..1e0ec08 100644
--- a/u-boot/drivers/video/drm/max96755f.c
+++ b/u-boot/drivers/video/drm/max96755f.c
@@ -9,6 +9,7 @@
#include <i2c.h>
#include <max96755f.h>
#include <video_bridge.h>
+#include <drm/drm_mipi_dsi.h>
#include <dm/of_access.h>
#include <linux/media-bus-format.h>
@@ -21,9 +22,18 @@
struct drm_display_mode *mode = &priv->mode;
u32 hfp, hsa, hbp, hact;
u32 vact, vsa, vfp, vbp;
+ u8 lane_map;
dm_i2c_reg_clrset(priv->dev, 0x0331, NUM_LANES,
FIELD_PREP(NUM_LANES, priv->num_lanes - 1));
+
+ lane_map = (priv->dsi_lane_map[0] & 0xff) << 4 |
+ (priv->dsi_lane_map[1] & 0xff) << 6 |
+ (priv->dsi_lane_map[2] & 0xff) << 0 |
+ (priv->dsi_lane_map[3] & 0xff) << 2;
+
+ dm_i2c_reg_write(priv->dev, 0x0332, lane_map);
+
if (!priv->dpi_deskew_en)
return;
@@ -148,11 +158,26 @@
.detect = max96755f_bridge_detect,
};
+static int max96755f_bridge_bind(struct udevice *dev)
+{
+ struct mipi_dsi_device *device = dev_get_platdata(dev);
+
+ device->dev = dev;
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
+ device->format = dev_read_u32_default(dev, "dsi,format",
+ MIPI_DSI_FMT_RGB888);
+ device->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
+ device->channel = dev_read_u32_default(dev, "reg", 0);
+
+ return 0;
+}
+
static int max96755f_bridge_probe(struct udevice *dev)
{
struct rockchip_bridge *bridge;
struct max96755f_priv *priv = dev_get_priv(dev->parent);
- int ret;
+ const struct device_node *np = ofnode_to_np(dev->node);
+ int i, len, ret;
bridge = calloc(1, sizeof(*bridge));
if (!bridge)
@@ -165,6 +190,24 @@
priv->num_lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
priv->dv_swp_ab = dev_read_bool(dev, "vd-swap-ab");
priv->dpi_deskew_en = dev_read_bool(dev, "dpi-deskew-en");
+
+ for ( i = 0; i < priv->num_lanes; i++)
+ priv->dsi_lane_map[i] = i;
+
+ if (of_find_property(np, "maxim,dsi-lane-map", &len)) {
+ len /= sizeof(u32);
+ if (priv->num_lanes != len) {
+ printf("invalid number of lane map\n");
+ return -EINVAL;
+ }
+ }
+
+ ret = of_read_u32_array(np, "maxim,dsi-lane-map",
+ priv->dsi_lane_map, priv->num_lanes);
+ if (ret) {
+ printf("get dsi lane map failed\n");
+ return -EINVAL;
+ }
ret = gpio_request_by_name(dev, "lock-gpios", 0, &priv->lock_gpio,
GPIOD_IS_IN);
@@ -186,4 +229,6 @@
.id = UCLASS_VIDEO_BRIDGE,
.of_match = max96755f_bridge_of_match,
.probe = max96755f_bridge_probe,
+ .bind = max96755f_bridge_bind,
+ .platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
};
diff --git a/u-boot/drivers/video/drm/panel-maxim-deserializer.c b/u-boot/drivers/video/drm/panel-maxim-deserializer.c
deleted file mode 100644
index 583f6a4..0000000
--- a/u-boot/drivers/video/drm/panel-maxim-deserializer.c
+++ /dev/null
@@ -1,300 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#include <config.h>
-#include <common.h>
-#include <backlight.h>
-#include <errno.h>
-#include <malloc.h>
-#include <video.h>
-
-#include <asm/gpio.h>
-#include <dm/device.h>
-#include <dm/read.h>
-#include <dm/pinctrl.h>
-#include <dm/uclass-id.h>
-#include <linux/media-bus-format.h>
-
-#include "rockchip_display.h"
-#include "rockchip_panel.h"
-
-struct maxim_deserializer_panel;
-
-struct maxim_deserializer_panel_desc {
- const char *name;
- u16 id;
- struct drm_display_mode mode;
- u32 width_mm;
- u32 height_mm;
-
- struct {
- const char *name;
- u8 addr;
- u8 dev_id;
- } deserializer;
-
- void (*prepare)(struct maxim_deserializer_panel *p);
- void (*unprepare)(struct maxim_deserializer_panel *p);
- void (*enable)(struct maxim_deserializer_panel *p);
- void (*disable)(struct maxim_deserializer_panel *p);
-};
-
-struct maxim_deserializer_panel {
- struct udevice *dev;
- struct udevice *backlight;
- struct gpio_desc enable_gpio;
-
- /* the panel desc as detected */
- const struct maxim_deserializer_panel_desc *desc;
-};
-
-static void maxim_max96752f_panel_prepare(struct maxim_deserializer_panel *p)
-{
- pinctrl_select_state(p->dev, p->desc->name ?
- p->desc->name : p->desc->deserializer.name);
-
- dm_i2c_reg_write(p->dev, 0x0002, 0x43);
- dm_i2c_reg_write(p->dev, 0x0140, 0x20);
-
- dm_i2c_reg_write(p->dev, 0x01ce, 0x5e); /* oldi */
- dm_i2c_reg_write(p->dev, 0x020c, 0x84); /* bl_pwm */
- dm_i2c_reg_write(p->dev, 0x0206, 0x83); /* tp_int */
-
- dm_i2c_reg_write(p->dev, 0x0215, 0x90); /* lcd_en */
- mdelay(20);
-}
-
-static void maxim_max96752f_panel_unprepare(struct maxim_deserializer_panel *p)
-{
- dm_i2c_reg_write(p->dev, 0x0215, 0x80); /* lcd_en */
-}
-
-static void maxim_max96752f_panel_enable(struct maxim_deserializer_panel *p)
-{
- dm_i2c_reg_write(p->dev, 0x0227, 0x90); /* lcd_rst */
- mdelay(20);
- dm_i2c_reg_write(p->dev, 0x020f, 0x90); /* tp_rst */
- mdelay(100);
- dm_i2c_reg_write(p->dev, 0x0221, 0x90); /* lcd_stb */
- mdelay(60);
- dm_i2c_reg_write(p->dev, 0x0212, 0x90); /* bl_current_ctl */
- dm_i2c_reg_write(p->dev, 0x0209, 0x90); /* bl_en */
-}
-
-static void maxim_max96752f_panel_disable(struct maxim_deserializer_panel *p)
-{
- dm_i2c_reg_write(p->dev, 0x0209, 0x80); /* bl_en */
- dm_i2c_reg_write(p->dev, 0x0212, 0x80); /* bl_current_ctl */
- dm_i2c_reg_write(p->dev, 0x0221, 0x80); /* lcd_stb */
- dm_i2c_reg_write(p->dev, 0x020f, 0x80); /* tp_rst */
- dm_i2c_reg_write(p->dev, 0x0227, 0x80); /* lcd_rst */
-}
-
-static const struct maxim_deserializer_panel_desc maxim_deserializer_default_panels[] = {
- {
- .deserializer = {
- .name = "max96752f",
- .addr = 0x48,
- .dev_id = 0x82,
- },
-
- .mode = {
- .clock = 148500,
- .hdisplay = 1920,
- .hsync_start = 1920 + 20,
- .hsync_end = 1920 + 20 + 20,
- .htotal = 1920 + 20 + 20 + 20,
- .vdisplay = 1080,
- .vsync_start = 1080 + 250,
- .vsync_end = 1080 + 250 + 2,
- .vtotal = 1080 + 250 + 2 + 8,
- .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
- },
-
- .prepare = maxim_max96752f_panel_prepare,
- .enable = maxim_max96752f_panel_enable,
- .disable = maxim_max96752f_panel_disable,
- .unprepare = maxim_max96752f_panel_unprepare,
- },
-};
-
-static void maxim_deserializer_panel_prepare(struct rockchip_panel *panel)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
-
- if (!p->desc)
- return;
-
- if (p->desc->prepare)
- p->desc->prepare(p);
-}
-
-static void maxim_deserializer_panel_unprepare(struct rockchip_panel *panel)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
-
- if (!p->desc)
- return;
-
- if (p->desc->unprepare)
- p->desc->unprepare(p);
-}
-
-static void maxim_deserializer_panel_enable(struct rockchip_panel *panel)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
-
- if (!p->desc)
- return;
-
- if (p->desc->enable)
- p->desc->enable(p);
-
- if (p->backlight)
- backlight_enable(p->backlight);
-}
-
-static void maxim_deserializer_panel_disable(struct rockchip_panel *panel)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
-
- if (!p->desc)
- return;
-
- if (p->backlight)
- backlight_disable(p->backlight);
-
- if (p->desc->disable)
- p->desc->disable(p);
-}
-
-static u16 maxim_deserializer_panel_get_id(struct maxim_deserializer_panel *p)
-{
- /* TODO */
- return 0;
-}
-
-static int maxim_deserializer_panel_detect(struct maxim_deserializer_panel *p)
-{
- const struct maxim_deserializer_panel_desc *desc = NULL;
- struct udevice *dev = p->dev;
- struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
- u16 id = maxim_deserializer_panel_get_id(p);
- unsigned int i, ret;
-
- if (id) {
- /* TODO */
- } else {
- u8 dev_id;
-
- for (i = 0; i < ARRAY_SIZE(maxim_deserializer_default_panels); i++) {
- chip->chip_addr = maxim_deserializer_default_panels[i].deserializer.addr;
-
- ret = dm_i2c_reg_read(dev, 0x000d);
- if (ret < 0)
- continue;
-
- dev_id = ret;
-
- if (maxim_deserializer_default_panels[i].deserializer.dev_id == dev_id) {
- desc = &maxim_deserializer_default_panels[i];
- break;
- }
- }
- }
-
- if (!desc)
- return -ENODEV;
-
- p->desc = desc;
- chip->chip_addr = desc->deserializer.addr;
-
- return 0;
-}
-
-static int maxim_deserializer_panel_get_mode(struct rockchip_panel *panel,
- struct drm_display_mode *mode)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(panel->dev);
- int ret;
-
- ret = maxim_deserializer_panel_detect(p);
- if (ret)
- return ret;
-
- memcpy(mode, &p->desc->mode, sizeof(struct drm_display_mode));
- mode->vrefresh = drm_mode_vrefresh(mode);
-
- return 0;
-}
-
-static const struct rockchip_panel_funcs maxim_deserializer_panel_funcs = {
- .prepare = maxim_deserializer_panel_prepare,
- .unprepare = maxim_deserializer_panel_unprepare,
- .enable = maxim_deserializer_panel_enable,
- .disable = maxim_deserializer_panel_disable,
- .get_mode = maxim_deserializer_panel_get_mode,
-};
-
-static void maxim_deserializer_panel_power_on(struct maxim_deserializer_panel *p)
-{
- if (dm_gpio_is_valid(&p->enable_gpio)) {
- dm_gpio_set_value(&p->enable_gpio, 1);
- mdelay(500);
- }
-}
-
-static int maxim_deserializer_panel_probe(struct udevice *dev)
-{
- struct maxim_deserializer_panel *p = dev_get_priv(dev);
- struct rockchip_panel *panel;
- int ret;
-
- ret = i2c_set_chip_offset_len(dev, 2);
- if (ret)
- return ret;
-
- p->dev = dev;
-
- ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
- "backlight", &p->backlight);
- if (ret && ret != -ENOENT) {
- dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
- return ret;
- }
-
- ret = gpio_request_by_name(dev, "enable-gpios", 0,
- &p->enable_gpio, GPIOD_IS_OUT);
- if (ret && ret != -ENOENT) {
- dev_err(dev, "%s: Cannot get enable GPIO: %d\n", __func__, ret);
- return ret;
- }
-
- maxim_deserializer_panel_power_on(p);
-
- panel = calloc(1, sizeof(*panel));
- if (!panel)
- return -ENOMEM;
-
- dev->driver_data = (ulong)panel;
- panel->dev = dev;
- panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
- panel->funcs = &maxim_deserializer_panel_funcs;
-
- return 0;
-}
-
-static const struct udevice_id maxim_deserializer_panel_of_match[] = {
- { .compatible = "maxim,deserializer-panel", },
- {}
-};
-
-U_BOOT_DRIVER(maxim_deserializer_panel) = {
- .name = "maxim_deserializer_panel",
- .id = UCLASS_PANEL,
- .of_match = maxim_deserializer_panel_of_match,
- .probe = maxim_deserializer_panel_probe,
- .priv_auto_alloc_size = sizeof(struct maxim_deserializer_panel),
-};
diff --git a/u-boot/drivers/video/drm/panel-maxim-max96752f.c b/u-boot/drivers/video/drm/panel-maxim-max96752f.c
new file mode 100644
index 0000000..0c28231
--- /dev/null
+++ b/u-boot/drivers/video/drm/panel-maxim-max96752f.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Maxim MAX96752F GMSL2 Deserializer
+ *
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+#include <config.h>
+#include <common.h>
+#include <backlight.h>
+#include <errno.h>
+#include <malloc.h>
+#include <video.h>
+
+#include <asm/gpio.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-id.h>
+#include <linux/media-bus-format.h>
+
+#include "rockchip_display.h"
+#include "rockchip_panel.h"
+
+struct max96752f;
+
+struct panel_desc {
+ const char *name;
+ int (*prepare)(struct max96752f *max96752f);
+ int (*unprepare)(struct max96752f *max96752f);
+ int (*enable)(struct max96752f *max96752f);
+ int (*disable)(struct max96752f *max96752f);
+ int (*backlight_enable)(struct max96752f *max96752f);
+ int (*backlight_disable)(struct max96752f *max96752f);
+};
+
+struct max96752f {
+ struct udevice *dev;
+ struct udevice *serializer;
+ struct udevice *backlight;
+
+ const struct panel_desc *desc;
+};
+
+static void max96752f_panel_prepare(struct rockchip_panel *panel)
+{
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = max96752f->desc;
+
+ if (desc->prepare)
+ desc->prepare(max96752f);
+}
+
+static void max96752f_panel_unprepare(struct rockchip_panel *panel)
+{
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = max96752f->desc;
+
+ if (desc->unprepare)
+ desc->unprepare(max96752f);
+}
+
+static void max96752f_panel_enable(struct rockchip_panel *panel)
+{
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = max96752f->desc;
+
+ if (desc->enable)
+ desc->enable(max96752f);
+
+ if (max96752f->backlight)
+ backlight_enable(max96752f->backlight);
+
+ if (desc->backlight_enable)
+ desc->backlight_enable(max96752f);
+}
+
+static void max96752f_panel_disable(struct rockchip_panel *panel)
+{
+ struct max96752f *max96752f = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = max96752f->desc;
+
+ if (desc->backlight_disable)
+ desc->backlight_disable(max96752f);
+
+ if (max96752f->backlight)
+ backlight_disable(max96752f->backlight);
+
+ if (desc->disable)
+ desc->disable(max96752f);
+}
+
+static const struct rockchip_panel_funcs max96752f_panel_funcs = {
+ .prepare = max96752f_panel_prepare,
+ .unprepare = max96752f_panel_unprepare,
+ .enable = max96752f_panel_enable,
+ .disable = max96752f_panel_disable,
+};
+
+static int max96752f_probe(struct udevice *dev)
+{
+ struct max96752f *max96752f = dev_get_priv(dev);
+ struct rockchip_panel *panel;
+ int ret;
+
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret)
+ return ret;
+
+ max96752f->dev = dev;
+ max96752f->serializer = dev->parent->parent;
+ max96752f->desc = (const struct panel_desc *)dev_get_driver_data(dev);
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &max96752f->backlight);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
+ return ret;
+ }
+
+ panel = calloc(1, sizeof(*panel));
+ if (!panel)
+ return -ENOMEM;
+
+ dev->driver_data = (ulong)panel;
+ panel->dev = dev;
+ panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ panel->funcs = &max96752f_panel_funcs;
+
+ return 0;
+}
+
+#define maxim_serializer_write(max96752f, reg, val) do { \
+ int ret; \
+ ret = dm_i2c_reg_write(max96752f->serializer, \
+ reg, val); \
+ if (ret) \
+ return ret; \
+ } while (0)
+
+#define maxim_deserializer_write(max96752f, reg, val) do { \
+ int ret; \
+ ret = dm_i2c_reg_write(max96752f->dev, \
+ reg, val); \
+ if (ret) \
+ return ret; \
+ } while (0)
+
+static int boe_av156fht_l83_panel_prepare(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0002, 0x43);
+ maxim_deserializer_write(max96752f, 0x0140, 0x20);
+
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e); /* oldi */
+ maxim_deserializer_write(max96752f, 0x020c, 0x84); /* bl_pwm */
+ maxim_deserializer_write(max96752f, 0x0206, 0x83); /* tp_int */
+
+ maxim_deserializer_write(max96752f, 0x0215, 0x90); /* lcd_en */
+ mdelay(20);
+
+ return 0;
+}
+
+static int boe_av156fht_l83_panel_unprepare(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0215, 0x80); /* lcd_en */
+
+ return 0;
+}
+
+static int boe_av156fht_l83_panel_enable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0227, 0x90); /* lcd_rst */
+ mdelay(20);
+ maxim_deserializer_write(max96752f, 0x020f, 0x90); /* tp_rst */
+ mdelay(100);
+ maxim_deserializer_write(max96752f, 0x0221, 0x90); /* lcd_stb */
+ mdelay(60);
+ maxim_deserializer_write(max96752f, 0x0212, 0x90); /* bl_current_ctl */
+ maxim_deserializer_write(max96752f, 0x0209, 0x90); /* bl_en */
+
+ return 0;
+}
+
+static int boe_av156fht_l83_panel_disable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0209, 0x80); /* bl_en */
+ maxim_deserializer_write(max96752f, 0x0212, 0x80); /* bl_current_ctl */
+ maxim_deserializer_write(max96752f, 0x0221, 0x80); /* lcd_stb */
+ maxim_deserializer_write(max96752f, 0x020f, 0x80); /* tp_rst */
+ maxim_deserializer_write(max96752f, 0x0227, 0x80); /* lcd_rst */
+
+ return 0;
+}
+
+static int boe_av156fht_l83_panel_backlight_enable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0212, 0x90); /* bl_current_ctl */
+ maxim_deserializer_write(max96752f, 0x0209, 0x90); /* bl_en */
+
+ return 0;
+}
+
+static int boe_av156fht_l83_panel_backlight_disable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0209, 0x80); /* bl_en */
+ maxim_deserializer_write(max96752f, 0x0212, 0x80); /* bl_current_ctl */
+
+ return 0;
+}
+
+static const struct panel_desc boe_av156fht_l83 = {
+ .name = "boe-av156fht-l83",
+ .prepare = boe_av156fht_l83_panel_prepare,
+ .unprepare = boe_av156fht_l83_panel_unprepare,
+ .enable = boe_av156fht_l83_panel_enable,
+ .disable = boe_av156fht_l83_panel_disable,
+ .backlight_enable = boe_av156fht_l83_panel_backlight_enable,
+ .backlight_disable = boe_av156fht_l83_panel_backlight_disable,
+};
+
+static int hannstar_hsd123jpw3_a15_prepare(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0002, 0x43);
+ maxim_deserializer_write(max96752f, 0x0140, 0x20);
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e);
+
+ maxim_deserializer_write(max96752f, 0x0203, 0x83); /* GPIO1 <- TP_INT */
+ maxim_deserializer_write(max96752f, 0x0206, 0x84); /* GPIO2 -> TP_RST */
+ maxim_deserializer_write(max96752f, 0x0224, 0x84); /* GPIO12 -> LCD_BL_PWM */
+
+ return 0;
+}
+
+static int hannstar_hsd123jpw3_a15_unprepare(struct max96752f *max96752f)
+{
+ return 0;
+}
+
+static int hannstar_hsd123jpw3_a15_enable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0221, 0x10); /* GPIO11 -> LCD_RESET */
+ mdelay(20);
+
+ return 0;
+}
+
+static int hannstar_hsd123jpw3_a15_disable(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0221, 0x00); /* GPIO11 -> LCD_RESET */
+ mdelay(20);
+
+ return 0;
+}
+
+static const struct panel_desc hannstar_hsd123jpw3_a15 = {
+ .name = "hannstar,hsd123jpw3-a15",
+ .prepare = hannstar_hsd123jpw3_a15_prepare,
+ .unprepare = hannstar_hsd123jpw3_a15_unprepare,
+ .enable = hannstar_hsd123jpw3_a15_enable,
+ .disable = hannstar_hsd123jpw3_a15_disable,
+};
+
+static int ogm_101fhbllm01_prepare(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x01ce, 0x5e);
+
+ maxim_deserializer_write(max96752f, 0x0203, 0x84); /* GPIO1 -> BL_PWM */
+ maxim_deserializer_write(max96752f, 0x0206, 0x84); /* GPIO2 -> TP_RST */
+ maxim_deserializer_write(max96752f, 0x0209, 0x83); /* GPIO3 <- TP_INT */
+
+ maxim_deserializer_write(max96752f, 0x0001, 0x02);
+
+ return 0;
+}
+
+static int ogm_101fhbllm01_unprepare(struct max96752f *max96752f)
+{
+ maxim_deserializer_write(max96752f, 0x0001, 0x01);
+
+ return 0;
+}
+
+static const struct panel_desc ogm_101fhbllm01 = {
+ .name = "ogm,101fhbllm01",
+ .prepare = ogm_101fhbllm01_prepare,
+ .unprepare = ogm_101fhbllm01_unprepare,
+};
+
+static const struct udevice_id max96752f_of_match[] = {
+ { .compatible = "boe,av156fht-l83", .data = (ulong)&boe_av156fht_l83 },
+ { .compatible = "hannstar,hsd123jpw3-a15", .data = (ulong)&hannstar_hsd123jpw3_a15 },
+ { .compatible = "ogm,101fhbllm01", .data = (ulong)&ogm_101fhbllm01 },
+ {}
+};
+
+U_BOOT_DRIVER(max96752f) = {
+ .name = "max96752f",
+ .id = UCLASS_PANEL,
+ .of_match = max96752f_of_match,
+ .probe = max96752f_probe,
+ .priv_auto_alloc_size = sizeof(struct max96752f),
+};
diff --git a/u-boot/drivers/video/drm/panel-rohm-bu18rl82.c b/u-boot/drivers/video/drm/panel-rohm-bu18rl82.c
new file mode 100644
index 0000000..24792ad
--- /dev/null
+++ b/u-boot/drivers/video/drm/panel-rohm-bu18rl82.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Rohm BU18RL82-based panel driver
+ *
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ */
+
+#include <config.h>
+#include <common.h>
+#include <backlight.h>
+#include <errno.h>
+#include <malloc.h>
+#include <video.h>
+
+#include <asm/gpio.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass-id.h>
+#include <linux/media-bus-format.h>
+
+#include "rockchip_display.h"
+#include "rockchip_panel.h"
+
+struct bu18rl82;
+
+struct panel_desc {
+ const char *name;
+ int (*prepare)(struct bu18rl82 *rl82);
+ int (*unprepare)(struct bu18rl82 *rl82);
+ int (*enable)(struct bu18rl82 *rl82);
+ int (*disable)(struct bu18rl82 *rl82);
+ int (*backlight_enable)(struct bu18rl82 *rl82);
+ int (*backlight_disable)(struct bu18rl82 *rl82);
+};
+
+struct bu18rl82 {
+ struct udevice *dev;
+ struct udevice *backlight;
+ const struct panel_desc *desc;
+};
+
+static void bu18rl82_panel_prepare(struct rockchip_panel *panel)
+{
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = rl82->desc;
+
+ if (desc->prepare)
+ desc->prepare(rl82);
+}
+
+static void bu18rl82_panel_unprepare(struct rockchip_panel *panel)
+{
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = rl82->desc;
+
+ if (desc->unprepare)
+ desc->unprepare(rl82);
+}
+
+static void bu18rl82_panel_enable(struct rockchip_panel *panel)
+{
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = rl82->desc;
+
+ if (desc->enable)
+ desc->enable(rl82);
+
+ if (rl82->backlight)
+ backlight_enable(rl82->backlight);
+
+ if (desc->backlight_enable)
+ desc->backlight_enable(rl82);
+}
+
+static void bu18rl82_panel_disable(struct rockchip_panel *panel)
+{
+ struct bu18rl82 *rl82 = dev_get_priv(panel->dev);
+ const struct panel_desc *desc = rl82->desc;
+
+ if (desc->backlight_disable)
+ desc->backlight_disable(rl82);
+
+ if (rl82->backlight)
+ backlight_disable(rl82->backlight);
+
+ if (desc->disable)
+ desc->disable(rl82);
+}
+
+static const struct rockchip_panel_funcs bu18rl82_panel_funcs = {
+ .prepare = bu18rl82_panel_prepare,
+ .unprepare = bu18rl82_panel_unprepare,
+ .enable = bu18rl82_panel_enable,
+ .disable = bu18rl82_panel_disable,
+};
+
+static int bu18rl82_probe(struct udevice *dev)
+{
+ struct bu18rl82 *rl82 = dev_get_priv(dev);
+ struct rockchip_panel *panel;
+ int ret;
+
+ ret = i2c_set_chip_offset_len(dev, 2);
+ if (ret)
+ return ret;
+
+ rl82->dev = dev;
+ rl82->desc = (const struct panel_desc *)dev_get_driver_data(dev);
+
+ ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
+ "backlight", &rl82->backlight);
+ if (ret && ret != -ENOENT) {
+ dev_err(dev, "%s: Cannot get backlight: %d\n", __func__, ret);
+ return ret;
+ }
+
+ panel = calloc(1, sizeof(*panel));
+ if (!panel)
+ return -ENOMEM;
+
+ dev->driver_data = (ulong)panel;
+ panel->dev = dev;
+ panel->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ panel->funcs = &bu18rl82_panel_funcs;
+
+ return 0;
+}
+
+#define rohm_deserializer_write(rl82, reg, val) do { \
+ int ret; \
+ ret = dm_i2c_reg_write(rl82->dev, reg, val); \
+ if (ret) { \
+ dev_err(rl82->dev, \
+ "failed to set register 0x%04x\n", \
+ reg); \
+ return ret; \
+ } \
+ } while (0)
+
+static int csot_mg1561b01_prepare(struct bu18rl82 *rl82)
+{
+ const struct reg_sequence {
+ u16 reg;
+ u8 def;
+ } regs[] = {
+ { 0x0011, 0x03 }, { 0x0012, 0x03 },
+ { 0x001f, 0x02 }, { 0x0020, 0x02 },
+ { 0x0031, 0x41 }, { 0x0032, 0x41 },
+ { 0x0073, 0x80 }, { 0x0074, 0x07 },
+ { 0x007b, 0x38 }, { 0x007c, 0x04 },
+ { 0x0079, 0x0a },
+ { 0x0429, 0x0a }, { 0x045d, 0x01 },
+ { 0x0529, 0x0a }, { 0x055d, 0x01 },
+ { 0x060a, 0xb0 }, { 0x060b, 0xff }, { 0x060c, 0xff },
+ { 0x0644, 0x18 }, { 0x0645, 0x01 }, { 0x0646, 0x2d },
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(regs); i++)
+ rohm_deserializer_write(rl82, regs[i].reg, regs[i].def);
+
+ /* BL_PWM - GPIO0 */
+ rohm_deserializer_write(rl82, 0x0057, 0x00);
+ rohm_deserializer_write(rl82, 0x0058, 0x02);
+
+ /* TP_INT - GPIO3 */
+ rohm_deserializer_write(rl82, 0x0060, 0x08);
+ rohm_deserializer_write(rl82, 0x042e, 0x05);
+
+ /* TP_RST - GPIO4 */
+ rohm_deserializer_write(rl82, 0x0063, 0x00);
+ rohm_deserializer_write(rl82, 0x0064, 0x01);
+
+ return 0;
+}
+
+static int csot_mg1561b01_unprepare(struct bu18rl82 *rl82)
+{
+ /* TP_RST - GPIO4 */
+ rohm_deserializer_write(rl82, 0x0064, 0x00);
+
+ return 0;
+}
+
+static int csot_mg1561b01_enable(struct bu18rl82 *rl82)
+{
+ rohm_deserializer_write(rl82, 0x0091, 0x03);
+ rohm_deserializer_write(rl82, 0x0090, 0x01);
+
+ return 0;
+}
+
+static int csot_mg1561b01_disable(struct bu18rl82 *rl82)
+{
+ rohm_deserializer_write(rl82, 0x0090, 0x00);
+ rohm_deserializer_write(rl82, 0x0091, 0x00);
+
+ return 0;
+}
+
+static int csot_mg1561b01_backlight_enable(struct bu18rl82 *rl82)
+{
+ /* BL_EN - GPIO1 */
+ rohm_deserializer_write(rl82, 0x005a, 0x00);
+ rohm_deserializer_write(rl82, 0x005b, 0x01);
+
+ return 0;
+}
+
+static int csot_mg1561b01_backlight_disable(struct bu18rl82 *rl82)
+{
+ /* BL_EN - GPIO1 */
+ rohm_deserializer_write(rl82, 0x005b, 0x00);
+
+ return 0;
+}
+
+static const struct panel_desc csot_mg1561b01 = {
+ .name = "csot,mg1561b01",
+ .prepare = csot_mg1561b01_prepare,
+ .unprepare = csot_mg1561b01_unprepare,
+ .enable = csot_mg1561b01_enable,
+ .disable = csot_mg1561b01_disable,
+ .backlight_enable = csot_mg1561b01_backlight_enable,
+ .backlight_disable = csot_mg1561b01_backlight_disable,
+};
+
+static int touch_china_v123awf3_r1_prepare(struct bu18rl82 *rl82)
+{
+ const struct reg_sequence {
+ u16 reg;
+ u8 def;
+ } regs[] = {
+ { 0x0011, 0x03 }, { 0x0012, 0x03 },
+ { 0x001f, 0x02 }, { 0x0020, 0x02 },
+ { 0x0031, 0x48 }, { 0x0032, 0x48 },
+ { 0x0073, 0x80 }, { 0x0074, 0x07 },
+ { 0x007b, 0xd0 }, { 0x007c, 0x02 },
+ { 0x0079, 0x0a },
+ { 0x0429, 0x0a }, { 0x045d, 0x01 },
+ { 0x0529, 0x0a }, { 0x055d, 0x01 },
+ { 0x060a, 0xb0 }, { 0x060b, 0xff }, { 0x060c, 0xff },
+ { 0x0644, 0x90 }, { 0x0646, 0xd2 },
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(regs); i++)
+ rohm_deserializer_write(rl82, regs[i].reg, regs[i].def);
+
+ /* TP_INT - GPIO4 */
+ rohm_deserializer_write(rl82, 0x0063, 0x08);
+ rohm_deserializer_write(rl82, 0x042f, 0x06);
+
+ /* TP_RST - GPIO3 */
+ rohm_deserializer_write(rl82, 0x0060, 0x00);
+ rohm_deserializer_write(rl82, 0x0061, 0x00);
+
+ /* LCD_BIAS_EN - GPIO2 */
+ rohm_deserializer_write(rl82, 0x005d, 0x00);
+ rohm_deserializer_write(rl82, 0x005e, 0x01);
+ mdelay(6);
+
+ return 0;
+}
+
+static int touch_china_v123awf3_r1_unprepare(struct bu18rl82 *rl82)
+{
+ /* LCD_BIAS_EN - GPIO2 */
+ rohm_deserializer_write(rl82, 0x005e, 0x00);
+
+ return 0;
+}
+
+static int touch_china_v123awf3_r1_enable(struct bu18rl82 *rl82)
+{
+ rohm_deserializer_write(rl82, 0x0091, 0x03);
+ rohm_deserializer_write(rl82, 0x0090, 0x01);
+
+ /* RSEX - GPIO5 */
+ rohm_deserializer_write(rl82, 0x0066, 0x00);
+ rohm_deserializer_write(rl82, 0x0067, 0x01);
+ /* TP_RST - GPIO3 */
+ rohm_deserializer_write(rl82, 0x0060, 0x00);
+ rohm_deserializer_write(rl82, 0x0061, 0x01);
+ mdelay(20);
+ /* LCD_PON - GPIO1 */
+ rohm_deserializer_write(rl82, 0x005a, 0x00);
+ rohm_deserializer_write(rl82, 0x005b, 0x01);
+
+ return 0;
+}
+
+static int touch_china_v123awf3_r1_disable(struct bu18rl82 *rl82)
+{
+ rohm_deserializer_write(rl82, 0x0090, 0x00);
+ rohm_deserializer_write(rl82, 0x0091, 0x00);
+
+ /* LCD_PON - GPIO1 */
+ rohm_deserializer_write(rl82, 0x005b, 0x00);
+ mdelay(100);
+ /* TP_RST - GPIO3 */
+ rohm_deserializer_write(rl82, 0x0061, 0x00);
+ /* RSEX - GPIO5 */
+ rohm_deserializer_write(rl82, 0x0067, 0x00);
+
+ return 0;
+}
+
+static int touch_china_v123awf3_r1_backlight_enable(struct bu18rl82 *rl82)
+{
+ /* BL_PWM - GPIO0 */
+ rohm_deserializer_write(rl82, 0x0057, 0x00);
+ rohm_deserializer_write(rl82, 0x0058, 0x02);
+
+ return 0;
+}
+
+static int touch_china_v123awf3_r1_backlight_disable(struct bu18rl82 *rl82)
+{
+ /* BL_PWM - GPIO0 */
+ rohm_deserializer_write(rl82, 0x0058, 0x00);
+
+ return 0;
+}
+
+static const struct panel_desc touch_china_v123awf3_r1 = {
+ .name = "touch-china,v123awf3-r1",
+ .prepare = touch_china_v123awf3_r1_prepare,
+ .unprepare = touch_china_v123awf3_r1_unprepare,
+ .enable = touch_china_v123awf3_r1_enable,
+ .disable = touch_china_v123awf3_r1_disable,
+ .backlight_enable = touch_china_v123awf3_r1_backlight_enable,
+ .backlight_disable = touch_china_v123awf3_r1_backlight_disable,
+};
+
+static const struct udevice_id bu18rl82_of_match[] = {
+ { .compatible = "csot,mg1561b01", .data = (ulong)&csot_mg1561b01 },
+ { .compatible = "touch-china,v123awf3-r1", .data = (ulong)&touch_china_v123awf3_r1 },
+ {}
+};
+
+U_BOOT_DRIVER(panel_rohm_bu18rl82) = {
+ .name = "panel-rohm-bu18rl82",
+ .id = UCLASS_PANEL,
+ .of_match = bu18rl82_of_match,
+ .probe = bu18rl82_probe,
+ .priv_auto_alloc_size = sizeof(struct bu18rl82),
+};
diff --git a/u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c b/u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c
index 4a00253..f964ddb 100644
--- a/u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c
+++ b/u-boot/drivers/video/drm/phy-rockchip-samsung-hdptx-hdmi.c
@@ -1278,9 +1278,9 @@
hdptx_write(hdptx, CMN_REG0043, 0x00);
hdptx_write(hdptx, CMN_REG0044, 0x46);
hdptx_write(hdptx, CMN_REG0045, 0x24);
- hdptx_write(hdptx, CMN_REG0046, 0xff);
+ hdptx_write(hdptx, CMN_REG0046, 0xdd);
hdptx_write(hdptx, CMN_REG0047, 0x00);
- hdptx_write(hdptx, CMN_REG0048, 0x44);
+ hdptx_write(hdptx, CMN_REG0048, 0x11);
hdptx_write(hdptx, CMN_REG0049, 0xfa);
hdptx_write(hdptx, CMN_REG004A, 0x08);
hdptx_write(hdptx, CMN_REG004B, 0x00);
@@ -1457,6 +1457,13 @@
hdptx_write(hdptx, LANE_REG0616, 0x02);
hdptx_write(hdptx, LANE_REG061B, 0x01);
hdptx_write(hdptx, LANE_REG061E, 0x08);
+
+ /* fix Inter-Pair Skew exceed the limits */
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
+ hdptx_write(hdptx, LANE_REG061E, 0x0a);
+
hdptx_write(hdptx, LANE_REG061F, 0x15);
hdptx_write(hdptx, LANE_REG0620, 0xa0);
@@ -1705,6 +1712,33 @@
hdptx_write(hdptx, LANE_REG061F, 0x15);
hdptx_write(hdptx, LANE_REG0620, 0xa0);
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
+ hdptx_write(hdptx, LANE_REG061E, 0x02);
+
+ hdptx_write(hdptx, LANE_REG0303, 0x2f);
+ hdptx_write(hdptx, LANE_REG0403, 0x2f);
+ hdptx_write(hdptx, LANE_REG0503, 0x2f);
+ hdptx_write(hdptx, LANE_REG0603, 0x2f);
+ hdptx_write(hdptx, LANE_REG0305, 0x03);
+ hdptx_write(hdptx, LANE_REG0405, 0x03);
+ hdptx_write(hdptx, LANE_REG0505, 0x03);
+ hdptx_write(hdptx, LANE_REG0605, 0x03);
+ hdptx_write(hdptx, LANE_REG0306, 0xfc);
+ hdptx_write(hdptx, LANE_REG0406, 0xfc);
+ hdptx_write(hdptx, LANE_REG0506, 0xfc);
+ hdptx_write(hdptx, LANE_REG0606, 0xfc);
+
+ hdptx_write(hdptx, LANE_REG0305, 0x4f);
+ hdptx_write(hdptx, LANE_REG0405, 0x4f);
+ hdptx_write(hdptx, LANE_REG0505, 0x4f);
+ hdptx_write(hdptx, LANE_REG0605, 0x4f);
+ hdptx_write(hdptx, LANE_REG0304, 0x14);
+ hdptx_write(hdptx, LANE_REG0404, 0x14);
+ hdptx_write(hdptx, LANE_REG0504, 0x14);
+ hdptx_write(hdptx, LANE_REG0604, 0x14);
+
return hdptx_post_enable_lane(hdptx);
}
@@ -1774,6 +1808,33 @@
hdptx_write(hdptx, LANE_REG061B, 0x01);
hdptx_write(hdptx, LANE_REG061F, 0x15);
hdptx_write(hdptx, LANE_REG0620, 0xa0);
+
+ hdptx_write(hdptx, LANE_REG031E, 0x02);
+ hdptx_write(hdptx, LANE_REG041E, 0x02);
+ hdptx_write(hdptx, LANE_REG051E, 0x02);
+ hdptx_write(hdptx, LANE_REG061E, 0x02);
+
+ hdptx_write(hdptx, LANE_REG0303, 0x2f);
+ hdptx_write(hdptx, LANE_REG0403, 0x2f);
+ hdptx_write(hdptx, LANE_REG0503, 0x2f);
+ hdptx_write(hdptx, LANE_REG0603, 0x2f);
+ hdptx_write(hdptx, LANE_REG0305, 0x03);
+ hdptx_write(hdptx, LANE_REG0405, 0x03);
+ hdptx_write(hdptx, LANE_REG0505, 0x03);
+ hdptx_write(hdptx, LANE_REG0605, 0x03);
+ hdptx_write(hdptx, LANE_REG0306, 0xfc);
+ hdptx_write(hdptx, LANE_REG0406, 0xfc);
+ hdptx_write(hdptx, LANE_REG0506, 0xfc);
+ hdptx_write(hdptx, LANE_REG0606, 0xfc);
+
+ hdptx_write(hdptx, LANE_REG0305, 0x4f);
+ hdptx_write(hdptx, LANE_REG0405, 0x4f);
+ hdptx_write(hdptx, LANE_REG0505, 0x4f);
+ hdptx_write(hdptx, LANE_REG0605, 0x4f);
+ hdptx_write(hdptx, LANE_REG0304, 0x14);
+ hdptx_write(hdptx, LANE_REG0404, 0x14);
+ hdptx_write(hdptx, LANE_REG0504, 0x14);
+ hdptx_write(hdptx, LANE_REG0604, 0x14);
return hdptx_post_enable_lane(hdptx);
}
@@ -1951,12 +2012,14 @@
subnode = ofnode_find_subnode(parent->node, "clk-port");
if (!ofnode_valid(subnode)) {
- printf("%s: no subnode for %s", __func__, parent->name);
+ free(str);
+ printf("%s: no subnode for %s\n", __func__, parent->name);
return -ENXIO;
}
ret = device_bind_driver_to_node(parent, "clk_hdptx", str, subnode, &child);
if (ret) {
+ free(str);
printf("%s: clk-port cannot bind its driver\n", __func__);
return ret;
}
@@ -2019,18 +2082,6 @@
new_rate = rate;
priv->rate = rate;
}
- }
- } else {
- if (!hdptx_ropll_cmn_config(hdptx, rate)) {
- new_rate = rate;
- priv->rate = rate;
- }
- }
-
- if (rate > (HDMI20_MAX_RATE / 100)) {
- if (!hdptx_lcpll_cmn_config(hdptx, rate)) {
- new_rate = rate;
- priv->rate = rate;
}
} else {
if (!hdptx_ropll_cmn_config(hdptx, rate)) {
diff --git a/u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c b/u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c
index 71c710f..1f60e1f 100644
--- a/u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c
+++ b/u-boot/drivers/video/drm/rockchip-inno-hdmi-phy.c
@@ -3,6 +3,7 @@
* (C) Copyright 2008-2016 Fuzhou Rockchip Electronics Co., Ltd
*/
+#include <clk-uclass.h>
#include <config.h>
#include <common.h>
#include <errno.h>
@@ -11,7 +12,9 @@
#include <fdtdec.h>
#include <fdt_support.h>
#include <asm/unaligned.h>
+#include <asm/arch/clock.h>
#include <dm/device.h>
+#include <dm/lists.h>
#include <dm/read.h>
#include <asm/io.h>
#include <linux/list.h>
@@ -20,6 +23,7 @@
#include "rockchip_display.h"
#include "rockchip_crtc.h"
+#include "rockchip_connector.h"
#include "rockchip_phy.h"
#define INNO_HDMI_PHY_TIMEOUT_LOOP_COUNT 1000
@@ -145,7 +149,8 @@
enum inno_hdmi_phy_type {
INNO_HDMI_PHY_RK3228,
- INNO_HDMI_PHY_RK3328
+ INNO_HDMI_PHY_RK3328,
+ INNO_HDMI_PHY_RK3528
};
struct inno_hdmi_phy_drv_data;
@@ -214,6 +219,14 @@
const void *data;
};
+struct clk_inno_hdmi {
+ struct udevice *dev;
+ ulong rate;
+};
+
+/* global variables are used to pass reource from phy drivers to clk driver */
+static struct inno_hdmi_phy *g_inno;
+
static const struct pre_pll_config pre_pll_cfg_table[] = {
{ 27000000, 27000000, 1, 90, 3, 2, 2, 10, 3, 3, 4, 0, 0},
{ 27000000, 33750000, 1, 90, 1, 3, 3, 10, 3, 3, 4, 0, 0},
@@ -249,9 +262,13 @@
{33750000, 1, 10, 2, 4},
{74250000, 1, 40, 8, 1},
{74250000, 18, 80, 8, 2},
+ {74250000, 1, 20, 4, 8},
{148500000, 2, 40, 4, 3},
+ {148500000, 1, 10, 2, 8},
{297000000, 4, 40, 2, 3},
+ {297000000, 2, 20, 2, 8},
{594000000, 8, 40, 1, 3},
+ {594000000, 4, 20, 1, 8},
{ ~0UL, 0, 0, 0, 0}
};
@@ -292,6 +309,30 @@
594000000, {
0x10, 0x1a, 0x1a, 0x1a, 0x07, 0x15, 0x08, 0x08, 0x08,
0x00, 0xac, 0xcc, 0xcc, 0xcc,
+ },
+ }, {
+ ~0UL, {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ },
+ }
+};
+
+static const struct phy_config rk3528_phy_cfg[] = {
+ /* tmdsclk bias-clk bias-data voltage-clk voltage-data pre-emphasis-data */
+ { 165000000, {
+ 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ },
+ }, {
+ 340000000, {
+ 0x03, 0x04, 0x0c, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
+ },
+ }, {
+ 594000000, {
+ 0x02, 0x08, 0x0d, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00,
},
}, {
~0UL, {
@@ -398,7 +439,11 @@
static int inno_hdmi_phy_power_on(struct rockchip_phy *phy)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
+#endif
const struct post_pll_config *cfg = post_pll_cfg_table;
const struct phy_config *phy_cfg = inno->plat_data->phy_cfg_table;
u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
@@ -420,6 +465,8 @@
else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3228 &&
tmdsclock <= 33750000)
chipversion = 4;
+ else if (inno->plat_data->dev_type == INNO_HDMI_PHY_RK3528)
+ chipversion = 8;
printf("tmdsclock = %d; chipversion = %d\n", tmdsclock, chipversion);
@@ -444,7 +491,11 @@
static int inno_hdmi_phy_power_off(struct rockchip_phy *phy)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
+#endif
if (inno->plat_data->ops->power_off)
inno->plat_data->ops->power_off(inno);
@@ -858,6 +909,229 @@
return rate;
}
+static int
+inno_hdmi_phy_rk3528_power_on(struct inno_hdmi_phy *inno,
+ const struct post_pll_config *cfg,
+ const struct phy_config *phy_cfg)
+{
+ u32 val;
+ u64 temp;
+ u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, inno->pixclock);
+
+ /* Power off post PLL */
+ inno_update_bits(inno, 0xaa, 1, 0);
+
+ val = cfg->prediv;
+ inno_write(inno, 0xab, val);
+
+ if (cfg->postdiv == 1) {
+ inno_write(inno, 0xad, 0x8);
+ inno_write(inno, 0xaa, 2);
+ } else {
+ val = (cfg->postdiv / 2) - 1;
+ inno_write(inno, 0xad, val);
+ inno_write(inno, 0xaa, 0x0e);
+ }
+
+ val = cfg->fbdiv & 0xff;
+ inno_write(inno, 0xac, val);
+ val = (cfg->fbdiv >> 8) & BIT(0);
+ inno_update_bits(inno, 0xad, BIT(4), val);
+
+ /* current bias clk/data 2 */
+ val = phy_cfg->regs[0] << 4 | phy_cfg->regs[1];
+ inno_write(inno, 0xbf, val);
+
+ /* current bias data 1/0 */
+ val = phy_cfg->regs[1] << 4 | phy_cfg->regs[1];
+ inno_write(inno, 0xc0, val);
+
+ /* output voltage */
+ inno_write(inno, 0xb5, phy_cfg->regs[2]);
+ inno_write(inno, 0xb6, phy_cfg->regs[3]);
+ inno_write(inno, 0xb7, phy_cfg->regs[3]);
+ inno_write(inno, 0xb8, phy_cfg->regs[3]);
+
+ /* pre-emphasis */
+ inno_write(inno, 0xbb, phy_cfg->regs[4]);
+ inno_write(inno, 0xbc, phy_cfg->regs[4]);
+ inno_write(inno, 0xbd, phy_cfg->regs[4]);
+
+ /* enable LDO */
+ inno_write(inno, 0xb4, 0x7);
+
+ /* enable serializer */
+ inno_write(inno, 0xbe, 0x70);
+
+ inno_write(inno, 0xb2, 0x0f);
+
+ for (val = 0; val < 5; val++) {
+ if (inno_read(inno, 0xaf) & 1)
+ break;
+ udelay(1000);
+ }
+ if (!(inno_read(inno, 0xaf) & 1)) {
+ dev_err(inno->dev, "HDMI PHY Post PLL unlock\n");
+ return -ETIMEDOUT;
+ }
+
+ /* set termination resistance */
+ if (phy_cfg->tmdsclock > 340000000) {
+ inno_write(inno, 0xc7, 0x76);
+ inno_write(inno, 0xc5, 0x83);
+ inno_write(inno, 0xc8, 0x00);
+ inno_write(inno, 0xc9, 0x2f);
+ inno_write(inno, 0xca, 0x2f);
+ inno_write(inno, 0xcb, 0x2f);
+ } else {
+ inno_write(inno, 0xc7, 0x76);
+ inno_write(inno, 0xc5, 0x83);
+ inno_write(inno, 0xc8, 0x00);
+ inno_write(inno, 0xc9, 0x0f);
+ inno_write(inno, 0xca, 0x0f);
+ inno_write(inno, 0xcb, 0x0f);
+ }
+
+
+ /* set TMDS sync detection counter length */
+ temp = 47520000000UL / tmdsclock;
+ inno_write(inno, 0xd8, (temp >> 8) & 0xff);
+ inno_write(inno, 0xd9, temp & 0xff);
+
+ if (phy_cfg->tmdsclock > 340000000)
+ mdelay(100);
+ /* set pdata_en to 0/1 */
+ inno_update_bits(inno, 0x02, 1, 0);
+ inno_update_bits(inno, 0x02, 1, 1);
+
+ /* Enable PHY IRQ */
+ inno_write(inno, 0x05, 0x22);
+ inno_write(inno, 0x07, 0x22);
+ inno_write(inno, 0xcc, 0x0f);
+
+ return 0;
+}
+
+static void inno_hdmi_phy_rk3528_power_off(struct inno_hdmi_phy *inno)
+{
+ /* Power off driver */
+ inno_write(inno, 0xb2, 0);
+ /* Power off band gap */
+ inno_update_bits(inno, 0xb0, 4, 0);
+ /* Power off post pll */
+ inno_update_bits(inno, 0xaa, 1, 1);
+
+ /* Disable PHY IRQ */
+ inno_write(inno, 0x05, 0);
+ inno_write(inno, 0x07, 0);
+}
+
+static void inno_hdmi_phy_rk3528_init(struct inno_hdmi_phy *inno)
+{
+ /*
+ * Use phy internal register control
+ * rxsense/poweron/pllpd/pdataen signal.
+ */
+ inno_write(inno, 0x02, 0x81);
+}
+
+static int
+inno_hdmi_phy_rk3528_pre_pll_update(struct inno_hdmi_phy *inno,
+ const struct pre_pll_config *cfg)
+{
+ u32 val;
+
+ inno_update_bits(inno, 0xb0, 4, 4);
+ inno_write(inno, 0xcc, 0x0f);
+
+ /* Power on PLL */
+ inno_update_bits(inno, 0xa0, 1, 0);
+ /* Configure pre-pll */
+ inno_update_bits(inno, 0xa0, 2, (cfg->vco_div_5_en & 1) << 1);
+ inno_write(inno, 0xa1, cfg->prediv);
+ if (cfg->fracdiv)
+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xc0;
+ else
+ val = ((cfg->fbdiv >> 8) & 0x0f) | 0xf0;
+ inno_write(inno, 0xa2, val);
+ inno_write(inno, 0xa3, cfg->fbdiv & 0xff);
+ val = (cfg->pclk_div_a & 0x1f) |
+ ((cfg->pclk_div_b & 3) << 5);
+ inno_write(inno, 0xa5, val);
+ val = (cfg->pclk_div_d & 0x1f) |
+ ((cfg->pclk_div_c & 3) << 5);
+ inno_write(inno, 0xa6, val);
+ val = ((cfg->tmds_div_a & 3) << 4) |
+ ((cfg->tmds_div_b & 3) << 2) |
+ (cfg->tmds_div_c & 3);
+ inno_write(inno, 0xa4, val);
+
+ if (cfg->fracdiv) {
+ val = cfg->fracdiv & 0xff;
+ inno_write(inno, 0xd3, val);
+ val = (cfg->fracdiv >> 8) & 0xff;
+ inno_write(inno, 0xd2, val);
+ val = (cfg->fracdiv >> 16) & 0xff;
+ inno_write(inno, 0xd1, val);
+ } else {
+ inno_write(inno, 0xd3, 0);
+ inno_write(inno, 0xd2, 0);
+ inno_write(inno, 0xd1, 0);
+ }
+
+ /* Wait for PLL lock */
+ for (val = 0; val < 5; val++) {
+ if (inno_read(inno, 0xa9) & 1)
+ break;
+ udelay(1000);
+ }
+ if (val == 5) {
+ dev_err(inno->dev, "Pre-PLL unlock\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static unsigned long
+inno_hdmi_rk3528_phy_pll_recalc_rate(struct inno_hdmi_phy *inno,
+ unsigned long parent_rate)
+{
+ unsigned long frac;
+ u8 nd, no_a, no_b, no_d;
+ u16 nf;
+ u64 vco = parent_rate;
+
+ nd = inno_read(inno, 0xa1) & 0x3f;
+ nf = ((inno_read(inno, 0xa2) & 0x0f) << 8) | inno_read(inno, 0xa3);
+ vco *= nf;
+ if ((inno_read(inno, 0xa2) & 0x30) == 0) {
+ frac = inno_read(inno, 0xd3) |
+ (inno_read(inno, 0xd2) << 8) |
+ (inno_read(inno, 0xd1) << 16);
+ vco += DIV_ROUND_CLOSEST(parent_rate * frac, (1 << 24));
+ }
+ if (inno_read(inno, 0xa0) & 2) {
+ do_div(vco, nd * 5);
+ } else {
+ no_a = inno_read(inno, 0xa5) & 0x1f;
+ no_b = ((inno_read(inno, 0xa5) >> 5) & 7) + 2;
+ no_d = inno_read(inno, 0xa6) & 0x1f;
+ if (no_a == 1)
+ do_div(vco, nd * no_b * no_d * 2);
+ else
+ do_div(vco, nd * no_a * no_d * 2);
+ }
+
+ frac = vco;
+ inno->pixclock = DIV_ROUND_CLOSEST(frac, 1000) * 1000;
+
+ dev_dbg(inno->dev, "%s rate %lu\n", __func__, inno->pixclock);
+
+ return frac;
+}
+
+#ifndef CONFIG_SPL_BUILD
#define PHY_TAB_LEN 60
static
@@ -889,6 +1163,7 @@
return 0;
}
+#endif
static const struct inno_hdmi_phy_ops rk3228_hdmi_phy_ops = {
.init = inno_hdmi_phy_rk3228_init,
@@ -905,6 +1180,14 @@
.recalc_rate = inno_hdmi_3328_phy_pll_recalc_rate,
};
+static const struct inno_hdmi_phy_ops rk3528_hdmi_phy_ops = {
+ .init = inno_hdmi_phy_rk3528_init,
+ .power_on = inno_hdmi_phy_rk3528_power_on,
+ .power_off = inno_hdmi_phy_rk3528_power_off,
+ .pre_pll_update = inno_hdmi_phy_rk3528_pre_pll_update,
+ .recalc_rate = inno_hdmi_rk3528_phy_pll_recalc_rate,
+};
+
static const struct inno_hdmi_phy_drv_data rk3228_hdmi_phy_drv_data = {
.dev_type = INNO_HDMI_PHY_RK3228,
.ops = &rk3228_hdmi_phy_ops,
@@ -917,6 +1200,12 @@
.phy_cfg_table = rk3328_phy_cfg,
};
+static const struct inno_hdmi_phy_drv_data rk3528_hdmi_phy_drv_data = {
+ .dev_type = INNO_HDMI_PHY_RK3528,
+ .ops = &rk3528_hdmi_phy_ops,
+ .phy_cfg_table = rk3528_phy_cfg,
+};
+
static const struct rockchip_inno_data inno_hdmi_phy_of_match[] = {
{ .compatible = "rockchip,rk3228-hdmi-phy",
.data = &rk3228_hdmi_phy_drv_data
@@ -924,26 +1213,41 @@
{ .compatible = "rockchip,rk3328-hdmi-phy",
.data = &rk3328_hdmi_phy_drv_data
},
+ { .compatible = "rockchip,rk3528-hdmi-phy",
+ .data = &rk3528_hdmi_phy_drv_data
+ },
{}
};
static int inno_hdmi_phy_init(struct rockchip_phy *phy)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct udevice *dev = phy->dev;
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
- int i, val, phy_table_size, ret;
- const char *name;
+ int val, phy_table_size, ret;
u32 *phy_config;
+#endif
+ int i;
+ const char *name;
- inno->node = dev->node;
-
+#ifdef CONFIG_SPL_BUILD
+ inno->regs = (void *)RK3528_HDMIPHY_BASE;
+#else
inno->regs = dev_read_addr_ptr(dev);
+ inno->node = dev->node;
+#endif
if (!inno->regs) {
printf("%s: failed to get phy address\n", __func__);
return -ENOMEM;
}
+#ifdef CONFIG_SPL_BUILD
+ name = "rockchip,rk3528-hdmi-phy";
+#else
name = dev_read_string(dev, "compatible");
+#endif
for (i = 0; i < ARRAY_SIZE(inno_hdmi_phy_of_match); i++) {
if (!strcmp(name, inno_hdmi_phy_of_match[i].compatible)) {
inno->plat_data = inno_hdmi_phy_of_match[i].data;
@@ -951,6 +1255,7 @@
}
}
+#ifndef CONFIG_SPL_BUILD
dev_read_prop(dev, "rockchip,phy-table", &val);
if (val >= 0) {
@@ -986,6 +1291,7 @@
} else {
printf("use default hdmi phy table\n");
}
+#endif
if (i >= ARRAY_SIZE(inno_hdmi_phy_of_match))
return 0;
@@ -1002,8 +1308,16 @@
static unsigned long inno_hdmi_phy_set_pll(struct rockchip_phy *phy,
unsigned long rate)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
+#endif
+#ifdef CONFIG_SPL_BUILD
+ if (!inno)
+ inno = g_inno;
+#endif
inno_hdmi_phy_clk_prepare(inno);
inno_hdmi_phy_clk_is_prepared(inno);
inno_hdmi_phy_clk_set_rate(inno, rate);
@@ -1013,7 +1327,11 @@
static int
inno_hdmi_phy_set_bus_width(struct rockchip_phy *phy, u32 bus_width)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
+#endif
inno->bus_width = bus_width;
@@ -1023,7 +1341,11 @@
static long
inno_hdmi_phy_clk_round_rate(struct rockchip_phy *phy, unsigned long rate)
{
+#ifdef CONFIG_SPL_BUILD
+ struct inno_hdmi_phy *inno = (struct inno_hdmi_phy *)phy->data;
+#else
struct inno_hdmi_phy *inno = dev_get_priv(phy->dev);
+#endif
int i;
const struct pre_pll_config *cfg = pre_pll_cfg_table;
u32 tmdsclock = inno_hdmi_phy_get_tmdsclk(inno, rate);
@@ -1082,9 +1404,26 @@
.compatible = "rockchip,rk3228-hdmi-phy",
.data = (ulong)&inno_hdmi_phy_driver_data,
},
+ {
+ .compatible = "rockchip,rk3528-hdmi-phy",
+ .data = (ulong)&inno_hdmi_phy_driver_data,
+ },
{}
};
+#ifdef CONFIG_SPL_BUILD
+int inno_spl_hdmi_phy_probe(struct display_state *state)
+{
+ struct inno_hdmi_phy *inno = malloc(sizeof(struct inno_hdmi_phy));
+
+ memset(inno, 0, sizeof(*inno));
+ g_inno = inno;
+
+ state->conn_state.connector->phy = &inno_hdmi_phy_driver_data;
+ state->conn_state.connector->phy->data = (void *)inno;
+ return 0;
+}
+#else
static int inno_hdmi_phy_probe(struct udevice *dev)
{
struct inno_hdmi_phy *inno = dev_get_priv(dev);
@@ -1094,6 +1433,32 @@
inno->dev = dev;
phy->dev = dev;
+ g_inno = inno;
+ dev->driver_data = (ulong)&inno_hdmi_phy_driver_data;
+ phy = &inno_hdmi_phy_driver_data;
+
+ return 0;
+}
+#endif
+
+static int rockchip_inno_phy_hdmi_bind(struct udevice *parent)
+{
+ struct udevice *child;
+ ofnode subnode;
+ int ret;
+
+ subnode = ofnode_find_subnode(parent->node, "clk-port");
+ if (!ofnode_valid(subnode)) {
+ printf("%s: no subnode for %s\n", __func__, parent->name);
+ return -ENXIO;
+ }
+
+ ret = device_bind_driver_to_node(parent, "clk_inno_hdmi", "inno_hdmi_pll_clk", subnode, &child);
+ if (ret) {
+ printf("%s: clk-port cannot bind its driver\n", __func__);
+ return ret;
+ }
+
return 0;
}
@@ -1101,6 +1466,57 @@
.name = "inno_hdmi_phy",
.id = UCLASS_PHY,
.of_match = inno_hdmi_phy_ids,
+#ifndef CONFIG_SPL_BUILD
.probe = inno_hdmi_phy_probe,
+#endif
+ .bind = rockchip_inno_phy_hdmi_bind,
.priv_auto_alloc_size = sizeof(struct inno_hdmi_phy),
};
+
+
+static ulong inno_hdmi_clk_get_rate(struct clk *clk)
+{
+ struct clk_inno_hdmi *priv = dev_get_priv(clk->dev);
+
+ return priv->rate;
+}
+
+static ulong inno_hdmi_clk_set_rate(struct clk *clk, ulong rate)
+{
+ struct clk_inno_hdmi *priv = dev_get_priv(clk->dev);
+ int ret;
+
+ inno_hdmi_phy_clk_prepare(g_inno);
+ inno_hdmi_phy_clk_is_prepared(g_inno);
+ ret = inno_hdmi_phy_clk_set_rate(g_inno, rate);
+ if (ret < 0) {
+ printf("inno hdmi set rate failed ret:%d\n", ret);
+ return ret;
+ }
+
+ priv->rate = g_inno->pixclock;
+
+ return priv->rate;
+}
+
+static const struct clk_ops inno_hdmi_clk_ops = {
+ .get_rate = inno_hdmi_clk_get_rate,
+ .set_rate = inno_hdmi_clk_set_rate,
+};
+
+static int inno_hdmi_clk_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+/*
+ * In order for other display interfaces to use hdmiphy as source
+ * for dclk, hdmiphy must register a virtual clock driver
+ */
+U_BOOT_DRIVER(clk_inno_hdmi) = {
+ .name = "clk_inno_hdmi",
+ .id = UCLASS_CLK,
+ .priv_auto_alloc_size = sizeof(struct clk_inno_hdmi),
+ .ops = &inno_hdmi_clk_ops,
+ .probe = inno_hdmi_clk_probe,
+};
diff --git a/u-boot/drivers/video/drm/rockchip_connector.c b/u-boot/drivers/video/drm/rockchip_connector.c
index fb7adfa..2eb8319 100644
--- a/u-boot/drivers/video/drm/rockchip_connector.c
+++ b/u-boot/drivers/video/drm/rockchip_connector.c
@@ -15,6 +15,19 @@
#include "rockchip_connector.h"
#include "rockchip_phy.h"
+#ifdef CONFIG_SPL_BUILD
+int rockchip_connector_bind(struct rockchip_connector *conn, struct udevice *dev, int id,
+ const struct rockchip_connector_funcs *funcs, void *data, int type)
+{
+ conn->id = id;
+ conn->funcs = funcs;
+ conn->data = data;
+ conn->type = type;
+
+ return 0;
+}
+
+#else
static LIST_HEAD(rockchip_connector_list);
int rockchip_connector_bind(struct rockchip_connector *conn, struct udevice *dev, int id,
@@ -105,21 +118,6 @@
return ret;
}
-int rockchip_connector_deinit(struct display_state *state)
-{
- struct rockchip_connector *conn;
-
- conn = state->conn_state.connector;
- if (conn->funcs->deinit) {
- conn->funcs->deinit(conn, state);
- if (state->conn_state.secondary) {
- conn = state->conn_state.secondary;
- conn->funcs->deinit(conn, state);
- }
- }
-
- return 0;
-}
static bool rockchip_connector_path_detect(struct rockchip_connector *conn,
struct display_state *state)
@@ -322,3 +320,20 @@
return 0;
}
+#endif
+
+int rockchip_connector_deinit(struct display_state *state)
+{
+ struct rockchip_connector *conn;
+
+ conn = state->conn_state.connector;
+ if (conn->funcs->deinit) {
+ conn->funcs->deinit(conn, state);
+ if (state->conn_state.secondary) {
+ conn = state->conn_state.secondary;
+ conn->funcs->deinit(conn, state);
+ }
+ }
+
+ return 0;
+}
diff --git a/u-boot/drivers/video/drm/rockchip_connector.h b/u-boot/drivers/video/drm/rockchip_connector.h
index 39a81e4..8c2ff75 100644
--- a/u-boot/drivers/video/drm/rockchip_connector.h
+++ b/u-boot/drivers/video/drm/rockchip_connector.h
@@ -7,6 +7,17 @@
#ifndef _ROCKCHIP_CONNECTOR_H_
#define _ROCKCHIP_CONNECTOR_H_
+#ifdef CONFIG_SPL_BUILD
+struct rockchip_connector {
+ struct rockchip_phy *phy;
+ int id;
+ int type;
+ bool hpd;
+
+ const struct rockchip_connector_funcs *funcs;
+ void *data;
+};
+#else
#include "rockchip_bridge.h"
#include "rockchip_panel.h"
@@ -18,10 +29,123 @@
struct list_head head;
int id;
int type;
+ bool hpd;
const struct rockchip_connector_funcs *funcs;
void *data;
};
+#endif
+
+/**
+ * enum drm_bus_flags - bus_flags info for &drm_display_info
+ *
+ * This enum defines signal polarities and clock edge information for signals on
+ * a bus as bitmask flags.
+ *
+ * The clock edge information is conveyed by two sets of symbols,
+ * DRM_BUS_FLAGS_*_DRIVE_\* and DRM_BUS_FLAGS_*_SAMPLE_\*. When this enum is
+ * used to describe a bus from the point of view of the transmitter, the
+ * \*_DRIVE_\* flags should be used. When used from the point of view of the
+ * receiver, the \*_SAMPLE_\* flags should be used. The \*_DRIVE_\* and
+ * \*_SAMPLE_\* flags alias each other, with the \*_SAMPLE_POSEDGE and
+ * \*_SAMPLE_NEGEDGE flags being equal to \*_DRIVE_NEGEDGE and \*_DRIVE_POSEDGE
+ * respectively. This simplifies code as signals are usually sampled on the
+ * opposite edge of the driving edge. Transmitters and receivers may however
+ * need to take other signal timings into account to convert between driving
+ * and sample edges.
+ */
+enum drm_bus_flags {
+ /**
+ * @DRM_BUS_FLAG_DE_LOW:
+ *
+ * The Data Enable signal is active low
+ */
+ DRM_BUS_FLAG_DE_LOW = BIT(0),
+
+ /**
+ * @DRM_BUS_FLAG_DE_HIGH:
+ *
+ * The Data Enable signal is active high
+ */
+ DRM_BUS_FLAG_DE_HIGH = BIT(1),
+
+ /**
+ * @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE:
+ *
+ * Data is driven on the rising edge of the pixel clock
+ */
+ DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = BIT(2),
+
+ /**
+ * @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE:
+ *
+ * Data is driven on the falling edge of the pixel clock
+ */
+ DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = BIT(3),
+
+ /**
+ * @DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE:
+ *
+ * Data is sampled on the rising edge of the pixel clock
+ */
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
+
+ /**
+ * @DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE:
+ *
+ * Data is sampled on the falling edge of the pixel clock
+ */
+ DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
+
+ /**
+ * @DRM_BUS_FLAG_DATA_MSB_TO_LSB:
+ *
+ * Data is transmitted MSB to LSB on the bus
+ */
+ DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4),
+
+ /**
+ * @DRM_BUS_FLAG_DATA_LSB_TO_MSB:
+ *
+ * Data is transmitted LSB to MSB on the bus
+ */
+ DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5),
+
+ /**
+ * @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE:
+ *
+ * Sync signals are driven on the rising edge of the pixel clock
+ */
+ DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = BIT(6),
+
+ /**
+ * @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE:
+ *
+ * Sync signals are driven on the falling edge of the pixel clock
+ */
+ DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = BIT(7),
+
+ /**
+ * @DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE:
+ *
+ * Sync signals are sampled on the rising edge of the pixel clock
+ */
+ DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
+
+ /**
+ * @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE:
+ *
+ * Sync signals are sampled on the falling edge of the pixel clock
+ */
+ DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
+
+ /**
+ * @DRM_BUS_FLAG_SHARP_SIGNALS:
+ *
+ * Set if the Sharp-specific signals (SPL, CLS, PS, REV) must be used
+ */
+ DRM_BUS_FLAG_SHARP_SIGNALS = BIT(8),
+};
struct rockchip_connector_funcs {
/*
diff --git a/u-boot/drivers/video/drm/rockchip_crtc.c b/u-boot/drivers/video/drm/rockchip_crtc.c
index 1e7376d..447bbf6 100644
--- a/u-boot/drivers/video/drm/rockchip_crtc.c
+++ b/u-boot/drivers/video/drm/rockchip_crtc.c
@@ -20,6 +20,7 @@
#include "rockchip_crtc.h"
#include "rockchip_connector.h"
+#ifndef CONFIG_SPL_BUILD
static const struct udevice_id rockchip_vp_ids[] = {
{ .compatible = "rockchip-vp" },
{ }
@@ -111,6 +112,16 @@
.data = &rk3328_vop,
};
+static const struct rockchip_crtc rk3528_vop_data = {
+ .funcs = &rockchip_vop2_funcs,
+ .data = &rk3528_vop,
+};
+
+static const struct rockchip_crtc rk3562_vop_data = {
+ .funcs = &rockchip_vop2_funcs,
+ .data = &rk3562_vop,
+};
+
static const struct rockchip_crtc rk3568_vop_data = {
.funcs = &rockchip_vop2_funcs,
.data = &rk3568_vop,
@@ -174,6 +185,12 @@
.compatible = "rockchip,rk3328-vop",
.data = (ulong)&rk3328_vop_data,
}, {
+ .compatible = "rockchip,rk3528-vop",
+ .data = (ulong)&rk3528_vop_data,
+ }, {
+ .compatible = "rockchip,rk3562-vop",
+ .data = (ulong)&rk3562_vop_data,
+ }, {
.compatible = "rockchip,rk3568-vop",
.data = (ulong)&rk3568_vop_data,
}, {
@@ -186,6 +203,13 @@
{
struct udevice *child;
int ret;
+
+ /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
+ ret = clk_set_defaults(dev);
+ if (ret) {
+ dev_err(dev, "%s clk_set_defaults failed %d\n", __func__, ret);
+ return ret;
+ }
for (device_find_first_child(dev, &child);
child;
@@ -237,3 +261,19 @@
.id = UCLASS_VIDEO_CRTC,
.name = "CRTC",
};
+
+#else
+static struct rockchip_crtc rk3528_vop_data = {
+ .funcs = &rockchip_vop2_funcs,
+ .data = &rk3528_vop,
+};
+
+int rockchip_spl_vop_probe(struct crtc_state *crtc_state)
+{
+
+ crtc_state->crtc = &rk3528_vop_data;
+
+ return 0;
+}
+#endif
+
diff --git a/u-boot/drivers/video/drm/rockchip_crtc.h b/u-boot/drivers/video/drm/rockchip_crtc.h
index b28e8dd..1078f8c 100644
--- a/u-boot/drivers/video/drm/rockchip_crtc.h
+++ b/u-boot/drivers/video/drm/rockchip_crtc.h
@@ -44,7 +44,11 @@
int (*send_mcu_cmd)(struct display_state *state, u32 type, u32 value);
int (*check)(struct display_state *state);
int (*mode_valid)(struct display_state *state);
+ int (*mode_fixup)(struct display_state *state);
int (*plane_check)(struct display_state *state);
+ int (*regs_dump)(struct display_state *state);
+ int (*active_regs_dump)(struct display_state *state);
+ int (*apply_soft_te)(struct display_state *state);
};
struct vop_data;
@@ -67,6 +71,8 @@
extern const struct vop_data rv1106_vop;
extern const struct vop_data rv1108_vop;
extern const struct vop_data rv1126_vop;
+extern const struct vop2_data rk3528_vop;
+extern const struct vop2_data rk3562_vop;
extern const struct vop2_data rk3568_vop;
extern const struct vop2_data rk3588_vop;
#endif
diff --git a/u-boot/drivers/video/drm/rockchip_display.c b/u-boot/drivers/video/drm/rockchip_display.c
index b6e8774..96ef65e 100644
--- a/u-boot/drivers/video/drm/rockchip_display.c
+++ b/u-boot/drivers/video/drm/rockchip_display.c
@@ -57,7 +57,7 @@
static unsigned long cubic_lut_memory_start;
static unsigned long memory_end;
static struct base2_info base_parameter;
-static uint32_t crc32_table[256];
+static u32 align_size = PAGE_SIZE;
/*
* the phy types are used by different connectors in public.
@@ -75,41 +75,6 @@
int public_phy_type;
bool phy_init;
};
-
-void rockchip_display_make_crc32_table(void)
-{
- uint32_t c;
- int n, k;
- unsigned long poly; /* polynomial exclusive-or pattern */
- /* terms of polynomial defining this crc (except x^32): */
- static const char p[] = {0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
-
- /* make exclusive-or pattern from polynomial (0xedb88320L) */
- poly = 0L;
- for (n = 0; n < sizeof(p) / sizeof(char); n++)
- poly |= 1L << (31 - p[n]);
-
- for (n = 0; n < 256; n++) {
- c = (unsigned long)n;
- for (k = 0; k < 8; k++)
- c = c & 1 ? poly ^ (c >> 1) : c >> 1;
- crc32_table[n] = cpu_to_le32(c);
- }
-}
-
-uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length)
-{
- int i;
- uint32_t crc;
- crc = 0xFFFFFFFF;
-
- for (i = 0; i < length; i++) {
- crc = crc32_table[(crc ^ *data) & 0xff] ^ (crc >> 8);
- data++;
- }
-
- return crc ^ 0xffffffff;
-}
int rockchip_get_baseparameter(void)
{
@@ -152,6 +117,7 @@
struct base2_disp_header *disp_header;
int i = 0, offset = -1;
u32 crc_val;
+ u32 base2_length;
void *base_parameter_addr = (void *)&base_parameter;
for (i = 0; i < 8; i++) {
@@ -178,11 +144,23 @@
if (strncasecmp(disp_info->disp_head_flag, "DISP", 4))
return NULL;
- crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, sizeof(struct base2_disp_info) - 4);
-
- if (crc_val != disp_info->crc) {
- printf("error: connector type[%d], id[%d] disp info crc check error\n", type, id);
- return NULL;
+ if (base_parameter.major_version == 3 && base_parameter.minor_version == 0) {
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info,
+ sizeof(struct base2_disp_info) - 4);
+ if (crc_val != disp_info->crc2) {
+ printf("error: connector type[%d], id[%d] disp info crc2 check error\n",
+ type, id);
+ return NULL;
+ }
+ } else {
+ base2_length = sizeof(struct base2_disp_info) - sizeof(struct csc_info) -
+ sizeof(struct acm_data) - 10 * 1024 - 4;
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, base2_length - 4);
+ if (crc_val != disp_info->crc) {
+ printf("error: connector type[%d], id[%d] disp info crc check error\n",
+ type, id);
+ return NULL;
+ }
}
return disp_info;
@@ -253,9 +231,9 @@
static void init_display_buffer(ulong base)
{
- memory_start = base + DRM_ROCKCHIP_FB_SIZE;
+ memory_start = ALIGN(base + DRM_ROCKCHIP_FB_SIZE, align_size);
memory_end = memory_start;
- cubic_lut_memory_start = memory_start + MEMORY_POOL_SIZE;
+ cubic_lut_memory_start = ALIGN(memory_start + MEMORY_POOL_SIZE, align_size);
}
void *get_display_buffer(int size)
@@ -340,38 +318,15 @@
return 0;
}
-int drm_mode_vrefresh(const struct drm_display_mode *mode)
-{
- int refresh = 0;
- unsigned int calc_val;
-
- if (mode->vrefresh > 0) {
- refresh = mode->vrefresh;
- } else if (mode->htotal > 0 && mode->vtotal > 0) {
- int vtotal;
-
- vtotal = mode->vtotal;
- /* work out vrefresh the value will be x1000 */
- calc_val = (mode->clock * 1000);
- calc_val /= mode->htotal;
- refresh = (calc_val + vtotal / 2) / vtotal;
-
- if (mode->flags & DRM_MODE_FLAG_INTERLACE)
- refresh *= 2;
- if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
- refresh /= 2;
- if (mode->vscan > 1)
- refresh /= mode->vscan;
- }
- return refresh;
-}
-
-int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode)
+int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode, u32 *bus_flags)
{
int hactive, vactive, pixelclock;
int hfront_porch, hback_porch, hsync_len;
int vfront_porch, vback_porch, vsync_len;
int val, flags = 0;
+
+#define FDT_GET_BOOL(val, name) \
+ val = ofnode_read_bool(node, name);
#define FDT_GET_INT(val, name) \
val = ofnode_read_s32_default(node, name, -1); \
@@ -396,8 +351,18 @@
flags |= val ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
FDT_GET_INT(val, "vsync-active");
flags |= val ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
+
+ FDT_GET_BOOL(val, "interlaced");
+ flags |= val ? DRM_MODE_FLAG_INTERLACE : 0;
+ FDT_GET_BOOL(val, "doublescan");
+ flags |= val ? DRM_MODE_FLAG_DBLSCAN : 0;
+ FDT_GET_BOOL(val, "doubleclk");
+ flags |= val ? DISPLAY_FLAGS_DOUBLECLK : 0;
+
+ FDT_GET_INT(val, "de-active");
+ *bus_flags |= val ? DRM_BUS_FLAG_DE_HIGH : DRM_BUS_FLAG_DE_LOW;
FDT_GET_INT(val, "pixelclk-active");
- flags |= val ? DRM_MODE_FLAG_PPIXDATA : 0;
+ *bus_flags |= val ? DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE : DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
FDT_GET_INT_DEFAULT(val, "screen-rotate", 0);
if (val == DRM_MODE_FLAG_XMIRROR) {
@@ -425,11 +390,13 @@
return 0;
}
-static int display_get_force_timing_from_dts(ofnode node, struct drm_display_mode *mode)
+static int display_get_force_timing_from_dts(ofnode node,
+ struct drm_display_mode *mode,
+ u32 *bus_flags)
{
int ret = 0;
- ret = rockchip_ofnode_get_display_mode(node, mode);
+ ret = rockchip_ofnode_get_display_mode(node, mode, bus_flags);
if (ret) {
mode->clock = 74250;
@@ -456,14 +423,24 @@
}
static int display_get_timing_from_dts(struct rockchip_panel *panel,
- struct drm_display_mode *mode)
+ struct drm_display_mode *mode,
+ u32 *bus_flags)
{
struct ofnode_phandle_args args;
- ofnode dt, timing;
+ ofnode dt, timing, mcu_panel;
int ret;
+ mcu_panel = dev_read_subnode(panel->dev, "mcu-panel");
dt = dev_read_subnode(panel->dev, "display-timings");
if (ofnode_valid(dt)) {
+ ret = ofnode_parse_phandle_with_args(dt, "native-mode", NULL,
+ 0, 0, &args);
+ if (ret)
+ return ret;
+
+ timing = args.node;
+ } else if (ofnode_valid(mcu_panel)) {
+ dt = ofnode_find_subnode(mcu_panel, "display-timings");
ret = ofnode_parse_phandle_with_args(dt, "native-mode", NULL,
0, 0, &args);
if (ret)
@@ -479,163 +456,26 @@
return -ENXIO;
}
- rockchip_ofnode_get_display_mode(timing, mode);
+ rockchip_ofnode_get_display_mode(timing, mode, bus_flags);
+
+ if (IS_ENABLED(CONFIG_ROCKCHIP_RK3568) || IS_ENABLED(CONFIG_ROCKCHIP_RK3588)) {
+ if (mode->hdisplay % 4) {
+ int old_hdisplay = mode->hdisplay;
+ int align = 4 - (mode->hdisplay % 4);
+
+ mode->hdisplay += align;
+ mode->hsync_start += align;
+ mode->hsync_end += align;
+ mode->htotal += align;
+
+ ofnode_write_u32_array(timing, "hactive", (u32 *)&mode->hdisplay, 1);
+
+ printf("WARN: hactive need to be aligned with 4-pixel, %d -> %d\n",
+ old_hdisplay, mode->hdisplay);
+ }
+ }
return 0;
-}
-
-/**
- * drm_mode_max_resolution_filter - mark modes out of vop max resolution
- * @edid_data: structure store mode list
- * @max_output: vop max output resolution
- */
-void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
- struct vop_rect *max_output)
-{
- int i;
-
- for (i = 0; i < edid_data->modes; i++) {
- if (edid_data->mode_buf[i].hdisplay > max_output->width ||
- edid_data->mode_buf[i].vdisplay > max_output->height)
- edid_data->mode_buf[i].invalid = true;
- }
-}
-
-/**
- * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
- * @p: mode
- * @adjust_flags: a combination of adjustment flags
- *
- * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
- *
- * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
- * interlaced modes.
- * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
- * buffers containing two eyes (only adjust the timings when needed, eg. for
- * "frame packing" or "side by side full").
- * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
- * be performed for doublescan and vscan > 1 modes respectively.
- */
-void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
-{
- if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
- return;
-
- if (p->flags & DRM_MODE_FLAG_DBLCLK)
- p->crtc_clock = 2 * p->clock;
- else
- p->crtc_clock = p->clock;
- p->crtc_hdisplay = p->hdisplay;
- p->crtc_hsync_start = p->hsync_start;
- p->crtc_hsync_end = p->hsync_end;
- p->crtc_htotal = p->htotal;
- p->crtc_hskew = p->hskew;
- p->crtc_vdisplay = p->vdisplay;
- p->crtc_vsync_start = p->vsync_start;
- p->crtc_vsync_end = p->vsync_end;
- p->crtc_vtotal = p->vtotal;
-
- if (p->flags & DRM_MODE_FLAG_INTERLACE) {
- if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
- p->crtc_vdisplay /= 2;
- p->crtc_vsync_start /= 2;
- p->crtc_vsync_end /= 2;
- p->crtc_vtotal /= 2;
- }
- }
-
- if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
- if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
- p->crtc_vdisplay *= 2;
- p->crtc_vsync_start *= 2;
- p->crtc_vsync_end *= 2;
- p->crtc_vtotal *= 2;
- }
- }
-
- if (!(adjust_flags & CRTC_NO_VSCAN)) {
- if (p->vscan > 1) {
- p->crtc_vdisplay *= p->vscan;
- p->crtc_vsync_start *= p->vscan;
- p->crtc_vsync_end *= p->vscan;
- p->crtc_vtotal *= p->vscan;
- }
- }
-
- if (adjust_flags & CRTC_STEREO_DOUBLE) {
- unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
-
- switch (layout) {
- case DRM_MODE_FLAG_3D_FRAME_PACKING:
- p->crtc_clock *= 2;
- p->crtc_vdisplay += p->crtc_vtotal;
- p->crtc_vsync_start += p->crtc_vtotal;
- p->crtc_vsync_end += p->crtc_vtotal;
- p->crtc_vtotal += p->crtc_vtotal;
- break;
- }
- }
-
- p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
- p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
- p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
- p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
-}
-
-/**
- * drm_mode_is_420_only - if a given videomode can be only supported in YCBCR420
- * output format
- *
- * @connector: drm connector under action.
- * @mode: video mode to be tested.
- *
- * Returns:
- * true if the mode can be supported in YCBCR420 format
- * false if not.
- */
-bool drm_mode_is_420_only(const struct drm_display_info *display,
- struct drm_display_mode *mode)
-{
- u8 vic = drm_match_cea_mode(mode);
-
- return test_bit(vic, display->hdmi.y420_vdb_modes);
-}
-
-/**
- * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
- * output format also (along with RGB/YCBCR444/422)
- *
- * @display: display under action.
- * @mode: video mode to be tested.
- *
- * Returns:
- * true if the mode can be support YCBCR420 format
- * false if not.
- */
-bool drm_mode_is_420_also(const struct drm_display_info *display,
- struct drm_display_mode *mode)
-{
- u8 vic = drm_match_cea_mode(mode);
-
- return test_bit(vic, display->hdmi.y420_cmdb_modes);
-}
-
-/**
- * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
- * output format
- *
- * @display: display under action.
- * @mode: video mode to be tested.
- *
- * Returns:
- * true if the mode can be supported in YCBCR420 format
- * false if not.
- */
-bool drm_mode_is_420(const struct drm_display_info *display,
- struct drm_display_mode *mode)
-{
- return drm_mode_is_420_only(display, mode) ||
- drm_mode_is_420_also(display, mode);
}
static int display_get_timing(struct display_state *state)
@@ -649,7 +489,7 @@
return panel->funcs->get_mode(panel, mode);
if (dev_of_valid(panel->dev) &&
- !display_get_timing_from_dts(panel, mode)) {
+ !display_get_timing_from_dts(panel, mode, &conn_state->bus_flags)) {
printf("Using display timing dts\n");
return 0;
}
@@ -730,6 +570,47 @@
return ret;
}
+static int display_mode_valid(struct display_state *state)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct rockchip_connector *conn = conn_state->connector;
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
+ struct crtc_state *crtc_state = &state->crtc_state;
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
+ int ret;
+
+ if (conn_funcs->mode_valid && state->enabled_at_spl == false) {
+ ret = conn_funcs->mode_valid(conn, state);
+ if (ret)
+ return ret;
+ }
+
+ if (crtc_funcs->mode_valid) {
+ ret = crtc_funcs->mode_valid(state);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int display_mode_fixup(struct display_state *state)
+{
+ struct crtc_state *crtc_state = &state->crtc_state;
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
+ int ret;
+
+ if (crtc_funcs->mode_fixup) {
+ ret = crtc_funcs->mode_fixup(state);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int display_init(struct display_state *state)
{
struct connector_state *conn_state = &state->conn_state;
@@ -741,7 +622,9 @@
const char *compatible;
int ret = 0;
static bool __print_once = false;
-
+#ifdef CONFIG_SPL_BUILD
+ struct spl_display_info *spl_disp_info = (struct spl_display_info *)CONFIG_SPL_VIDEO_BUF;
+#endif
if (!__print_once) {
__print_once = true;
printf("Rockchip UBOOT DRM driver version: %s\n", DRIVER_VERSION);
@@ -755,6 +638,12 @@
return -ENXIO;
}
+#ifdef CONFIG_SPL_BUILD
+ if (state->conn_state.type == DRM_MODE_CONNECTOR_HDMIA)
+ state->enabled_at_spl = spl_disp_info->enabled == 1 ? true : false;
+ if (state->enabled_at_spl)
+ printf("HDMI enabled at SPL\n");
+#endif
if (crtc_state->crtc->active && !crtc_state->ports_node &&
memcmp(&crtc_state->crtc->active_mode, &conn_state->mode,
sizeof(struct drm_display_mode))) {
@@ -773,14 +662,16 @@
return ret;
}
- ret = rockchip_connector_init(state);
- if (ret)
- goto deinit;
+ if (state->enabled_at_spl == false) {
+ ret = rockchip_connector_init(state);
+ if (ret)
+ goto deinit;
+ }
/*
* support hotplug, but not connect;
*/
-#ifdef CONFIG_ROCKCHIP_DRM_TVE
+#ifdef CONFIG_DRM_ROCKCHIP_TVE
if (crtc->hdmi_hpd && conn_state->type == DRM_MODE_CONNECTOR_TV) {
printf("hdmi plugin ,skip tve\n");
goto deinit;
@@ -793,14 +684,27 @@
#endif
ret = rockchip_connector_detect(state);
-#if defined(CONFIG_ROCKCHIP_DRM_TVE) || defined(CONFIG_DRM_ROCKCHIP_RK1000)
+#if defined(CONFIG_DRM_ROCKCHIP_TVE) || defined(CONFIG_DRM_ROCKCHIP_RK1000)
if (conn_state->type == DRM_MODE_CONNECTOR_HDMIA)
crtc->hdmi_hpd = ret;
+ if (state->enabled_at_spl)
+ crtc->hdmi_hpd = true;
#endif
if (!ret && !state->force_output)
goto deinit;
- if (conn->panel) {
+ ret = 0;
+ if (state->enabled_at_spl == true) {
+#ifdef CONFIG_SPL_BUILD
+ struct drm_display_mode *mode = &conn_state->mode;
+
+ memcpy(mode, &spl_disp_info->mode, sizeof(*mode));
+ conn_state->bus_format = spl_disp_info->bus_format;
+
+ printf("%s get display mode from spl:%dx%d, bus format:0x%x\n",
+ conn->dev->name, mode->hdisplay, mode->vdisplay, conn_state->bus_format);
+#endif
+ } else if (conn->panel) {
ret = display_get_timing(state);
if (!ret)
conn_state->bpc = conn->panel->bpc;
@@ -853,10 +757,15 @@
if (state->force_output)
display_use_force_mode(state);
+ if (display_mode_valid(state))
+ goto deinit;
+
/* rk356x series drive mipi pixdata on posedge */
compatible = dev_read_string(conn->dev, "compatible");
- if (!strcmp(compatible, "rockchip,rk3568-mipi-dsi"))
- conn_state->mode.flags |= DRM_MODE_FLAG_PPIXDATA;
+ if (!strcmp(compatible, "rockchip,rk3568-mipi-dsi")) {
+ conn_state->bus_flags &= ~DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE;
+ conn_state->bus_flags |= DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE;
+ }
printf("%s: %s detailed mode clock %u kHz, flags[%x]\n"
" H: %04d %04d %04d %04d\n"
@@ -871,20 +780,13 @@
mode->vsync_end, mode->vtotal,
conn_state->bus_format);
- drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
-
- if (conn_state->secondary) {
- mode->crtc_clock *= 2;
- mode->crtc_hdisplay *= 2;
- mode->crtc_hsync_start *= 2;
- mode->crtc_hsync_end *= 2;
- mode->crtc_htotal *= 2;
- }
+ if (display_mode_fixup(state))
+ goto deinit;
if (conn->bridge)
rockchip_bridge_mode_set(conn->bridge, &conn_state->mode);
- if (crtc_funcs->init) {
+ if (crtc_funcs->init && state->enabled_at_spl == false) {
ret = crtc_funcs->init(state);
if (ret)
goto deinit;
@@ -955,12 +857,17 @@
if (crtc_funcs->prepare)
crtc_funcs->prepare(state);
- rockchip_connector_pre_enable(state);
+ if (state->enabled_at_spl == false)
+ rockchip_connector_pre_enable(state);
if (crtc_funcs->enable)
crtc_funcs->enable(state);
- rockchip_connector_enable(state);
+ if (state->enabled_at_spl == false)
+ rockchip_connector_enable(state);
+
+ if (crtc_state->soft_te)
+ crtc_funcs->apply_soft_te(state);
state->is_enable = true;
@@ -990,54 +897,6 @@
state->is_init = 0;
return 0;
-}
-
-static int display_rect_calc_scale(int src, int dst)
-{
- int scale = 0;
-
- if (WARN_ON(src < 0 || dst < 0))
- return -EINVAL;
-
- if (dst == 0)
- return 0;
-
- src <<= 16;
-
- if (src > (dst << 16))
- return DIV_ROUND_UP(src, dst);
- else
- scale = src / dst;
-
- return scale;
-}
-
-int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
- int min_hscale, int max_hscale)
-{
- int hscale = display_rect_calc_scale(src->w, dst->w);
-
- if (hscale < 0 || dst->w == 0)
- return hscale;
-
- if (hscale < min_hscale || hscale > max_hscale)
- return -ERANGE;
-
- return hscale;
-}
-
-int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
- int min_vscale, int max_vscale)
-{
- int vscale = display_rect_calc_scale(src->h, dst->h);
-
- if (vscale < 0 || dst->h == 0)
- return vscale;
-
- if (vscale < min_vscale || vscale > max_vscale)
- return -ERANGE;
-
- return vscale;
}
static int display_check(struct display_state *state)
@@ -1074,38 +933,6 @@
return 0;
check_fail:
- state->is_init = false;
- return ret;
-}
-
-static int display_mode_valid(struct display_state *state)
-{
- struct connector_state *conn_state = &state->conn_state;
- struct rockchip_connector *conn = conn_state->connector;
- const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
- struct crtc_state *crtc_state = &state->crtc_state;
- const struct rockchip_crtc *crtc = crtc_state->crtc;
- const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
- int ret;
-
- if (!state->is_init)
- return 0;
-
- if (conn_funcs->mode_valid) {
- ret = conn_funcs->mode_valid(conn, state);
- if (ret)
- goto invalid_mode;
- }
-
- if (crtc_funcs->mode_valid) {
- ret = crtc_funcs->mode_valid(state);
- if (ret)
- goto invalid_mode;
- }
-
- return 0;
-
-invalid_mode:
state->is_init = false;
return ret;
}
@@ -1170,7 +997,6 @@
}
}
- display_mode_valid(state);
display_check(state);
display_set_plane(state);
display_enable(state);
@@ -1213,14 +1039,22 @@
return 0;
}
-static int get_crtc_mcu_mode(struct crtc_state *crtc_state)
+static int get_crtc_mcu_mode(struct crtc_state *crtc_state, struct device_node *port_node,
+ bool is_ports_node)
{
- ofnode mcu_node;
+ ofnode mcu_node, vp_node;
int total_pixel, cs_pst, cs_pend, rw_pst, rw_pend;
- mcu_node = dev_read_subnode(crtc_state->dev, "mcu-timing");
- if (!ofnode_valid(mcu_node))
- return -ENODEV;
+ if (is_ports_node) {
+ vp_node = np_to_ofnode(port_node);
+ mcu_node = ofnode_find_subnode(vp_node, "mcu-timing");
+ if (!ofnode_valid(mcu_node))
+ return -ENODEV;
+ } else {
+ mcu_node = dev_read_subnode(crtc_state->dev, "mcu-timing");
+ if (!ofnode_valid(mcu_node))
+ return -ENODEV;
+ }
#define FDT_GET_MCU_INT(val, name) \
do { \
@@ -1464,6 +1298,35 @@
return ret;
}
+int rockchip_vop_dump(const char *cmd)
+{
+ struct display_state *state;
+ struct crtc_state *crtc_state;
+ struct rockchip_crtc *crtc;
+ const struct rockchip_crtc_funcs *crtc_funcs;
+ int ret = -EINVAL;
+
+ list_for_each_entry(state, &rockchip_display_list, head) {
+ if (!state->is_init)
+ continue;
+ crtc_state = &state->crtc_state;
+ crtc = crtc_state->crtc;
+ crtc_funcs = crtc->funcs;
+
+ if (!cmd)
+ ret = crtc_funcs->active_regs_dump(state);
+ else if (!strcmp(cmd, "a") || !strcmp(cmd, "all"))
+ ret = crtc_funcs->regs_dump(state);
+ if (!ret)
+ break;
+ }
+
+ if (ret)
+ ret = CMD_RET_USAGE;
+
+ return ret;
+}
+
enum {
PORT_DIR_IN,
PORT_DIR_OUT,
@@ -1505,13 +1368,12 @@
return ofnode_to_np(parent);
}
-static const struct device_node *rockchip_of_graph_get_remote_node(ofnode node, int port,
- int endpoint)
+const struct device_node *
+rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint)
{
const struct device_node *port_node;
ofnode ep;
u32 reg;
- uint phandle;
port_node = rockchip_of_graph_get_port_by_id(node, port);
if (!port_node)
@@ -1527,7 +1389,21 @@
if (!ofnode_valid(ep))
return NULL;
- if (ofnode_read_u32(ep, "remote-endpoint", &phandle))
+ return ofnode_to_np(ep);
+}
+
+static const struct device_node *
+rockchip_of_graph_get_remote_node(ofnode node, int port, int endpoint)
+{
+ const struct device_node *ep_node;
+ ofnode ep;
+ uint phandle;
+
+ ep_node = rockchip_of_graph_get_endpoint_by_regs(node, port, endpoint);
+ if (!ep_node)
+ return NULL;
+
+ if (ofnode_read_u32(np_to_ofnode(ep_node), "remote-endpoint", &phandle))
return NULL;
ep = ofnode_get_by_phandle(phandle);
@@ -1611,6 +1487,10 @@
struct rockchip_bridge **bridge)
{
int ret = 0;
+
+ if (*panel)
+ return 0;
+
*panel = NULL;
*bridge = NULL;
@@ -1952,7 +1832,9 @@
if (s->force_output) {
timing_node = ofnode_find_subnode(node, "force_timing");
- ret = display_get_force_timing_from_dts(timing_node, &s->force_mode);
+ ret = display_get_force_timing_from_dts(timing_node,
+ &s->force_mode,
+ &s->conn_state.bus_flags);
if (ofnode_read_u32(node, "force-bus-format", &s->force_bus_format))
s->force_bus_format = MEDIA_BUS_FMT_RGB888_1X24;
}
@@ -2002,10 +1884,11 @@
s->crtc_state.crtc->vps[vp_id].plane_mask = ret;
s->crtc_state.crtc->assign_plane |= true;
s->crtc_state.crtc->vps[vp_id].primary_plane_id =
- ofnode_read_u32_default(vp_node, "rockchip,primary-plane", -1);
+ ofnode_read_u32_default(vp_node, "rockchip,primary-plane", U8_MAX);
printf("get vp%d plane mask:0x%x, primary id:%d, cursor_plane:%d, from dts\n",
vp_id,
s->crtc_state.crtc->vps[vp_id].plane_mask,
+ s->crtc_state.crtc->vps[vp_id].primary_plane_id == U8_MAX ? -1 :
s->crtc_state.crtc->vps[vp_id].primary_plane_id,
cursor_plane);
}
@@ -2020,7 +1903,7 @@
}
}
- get_crtc_mcu_mode(&s->crtc_state);
+ get_crtc_mcu_mode(&s->crtc_state, port_node, is_ports_node);
ret = ofnode_read_u32_default(s->crtc_state.node,
"rockchip,dual-channel-swap", 0);
@@ -2061,27 +1944,41 @@
const struct rockchip_crtc *crtc;
struct display_state *s;
int offset;
+ int ret;
const struct device_node *np;
const char *path;
+ const char *cacm_header;
+ u64 aligned_memory_size;
if (fdt_node_offset_by_compatible(blob, 0, "rockchip,drm-logo") >= 0) {
- list_for_each_entry(s, &rockchip_display_list, head)
- load_bmp_logo(&s->logo, s->klogo_name);
+ list_for_each_entry(s, &rockchip_display_list, head) {
+ ret = load_bmp_logo(&s->logo, s->klogo_name);
+ if (ret < 0) {
+ s->is_klogo_valid = false;
+ printf("VP%d fail to load kernel logo\n", s->crtc_state.crtc_id);
+ } else {
+ s->is_klogo_valid = true;
+ }
+ }
if (!get_display_size())
return;
+ aligned_memory_size = (u64)ALIGN(get_display_size(), align_size);
offset = fdt_update_reserved_memory(blob, "rockchip,drm-logo",
(u64)memory_start,
- (u64)get_display_size());
+ aligned_memory_size);
if (offset < 0)
printf("failed to reserve drm-loader-logo memory\n");
- offset = fdt_update_reserved_memory(blob, "rockchip,drm-cubic-lut",
- (u64)cubic_lut_memory_start,
- (u64)get_cubic_memory_size());
- if (offset < 0)
- printf("failed to reserve drm-cubic-lut memory\n");
+ if (get_cubic_memory_size()) {
+ aligned_memory_size = (u64)ALIGN(get_cubic_memory_size(), align_size);
+ offset = fdt_update_reserved_memory(blob, "rockchip,drm-cubic-lut",
+ (u64)cubic_lut_memory_start,
+ aligned_memory_size);
+ if (offset < 0)
+ printf("failed to reserve drm-cubic-lut memory\n");
+ }
} else {
printf("can't found rockchip,drm-logo, use rockchip,fb-logo\n");
/* Compatible with rkfb display, only need reserve memory */
@@ -2097,7 +1994,14 @@
}
list_for_each_entry(s, &rockchip_display_list, head) {
- if (!s->is_init)
+ /*
+ * If plane mask is not set in dts, fixup dts to assign it
+ * whether crtc is initialized or not.
+ */
+ if (s->crtc_state.crtc->funcs->fixup_dts && !s->crtc_state.crtc->assign_plane)
+ s->crtc_state.crtc->funcs->fixup_dts(s, blob);
+
+ if (!s->is_init || !s->is_klogo_valid)
continue;
conn = s->conn_state.connector;
@@ -2123,9 +2027,6 @@
printf("failed to get exist crtc\n");
continue;
}
-
- if (crtc_funcs->fixup_dts)
- crtc_funcs->fixup_dts(s, blob);
np = ofnode_to_np(s->node);
path = np->full_name;
@@ -2155,10 +2056,37 @@
FDT_SET_U32("overscan,bottom_margin", s->conn_state.overscan.bottom_margin);
if (s->conn_state.disp_info) {
+ cacm_header = (const char*)&s->conn_state.disp_info->cacm_header;
+
FDT_SET_U32("bcsh,brightness", s->conn_state.disp_info->bcsh_info.brightness);
FDT_SET_U32("bcsh,contrast", s->conn_state.disp_info->bcsh_info.contrast);
FDT_SET_U32("bcsh,saturation", s->conn_state.disp_info->bcsh_info.saturation);
FDT_SET_U32("bcsh,hue", s->conn_state.disp_info->bcsh_info.hue);
+
+ if (!strncasecmp(cacm_header, "CACM", 4)) {
+ FDT_SET_U32("post_csc,hue",
+ s->conn_state.disp_info->csc_info.hue);
+ FDT_SET_U32("post_csc,saturation",
+ s->conn_state.disp_info->csc_info.saturation);
+ FDT_SET_U32("post_csc,contrast",
+ s->conn_state.disp_info->csc_info.contrast);
+ FDT_SET_U32("post_csc,brightness",
+ s->conn_state.disp_info->csc_info.brightness);
+ FDT_SET_U32("post_csc,r_gain",
+ s->conn_state.disp_info->csc_info.r_gain);
+ FDT_SET_U32("post_csc,g_gain",
+ s->conn_state.disp_info->csc_info.g_gain);
+ FDT_SET_U32("post_csc,b_gain",
+ s->conn_state.disp_info->csc_info.b_gain);
+ FDT_SET_U32("post_csc,r_offset",
+ s->conn_state.disp_info->csc_info.r_offset);
+ FDT_SET_U32("post_csc,g_offset",
+ s->conn_state.disp_info->csc_info.g_offset);
+ FDT_SET_U32("post_csc,b_offset",
+ s->conn_state.disp_info->csc_info.b_offset);
+ FDT_SET_U32("post_csc,csc_enable",
+ s->conn_state.disp_info->csc_info.csc_enable);
+ }
}
if (s->conn_state.disp_info->cubic_lut_data.size &&
@@ -2213,6 +2141,19 @@
return 0;
}
+static int do_rockchip_vop_dump(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret;
+
+ if (argc < 1 || argc > 2)
+ return CMD_RET_USAGE;
+
+ ret = rockchip_vop_dump(argv[1]);
+
+ return ret;
+}
+
U_BOOT_CMD(
rockchip_show_logo, 1, 1, do_rockchip_logo_show,
"load and display log from resource partition",
@@ -2224,3 +2165,9 @@
"load and display bmp from resource partition",
" <bmp_name>"
);
+
+U_BOOT_CMD(
+ vop_dump, 2, 1, do_rockchip_vop_dump,
+ "dump vop regs",
+ " [a/all]"
+);
diff --git a/u-boot/drivers/video/drm/rockchip_display.h b/u-boot/drivers/video/drm/rockchip_display.h
index 4d45e9d..8447871 100644
--- a/u-boot/drivers/video/drm/rockchip_display.h
+++ b/u-boot/drivers/video/drm/rockchip_display.h
@@ -7,22 +7,37 @@
#ifndef _ROCKCHIP_DISPLAY_H
#define _ROCKCHIP_DISPLAY_H
+#ifdef CONFIG_SPL_BUILD
+#include <linux/hdmi.h>
+#include <linux/media-bus-format.h>
+#else
#include <bmp_layout.h>
-#include <drm_modes.h>
#include <edid.h>
+#endif
+#include <drm_modes.h>
#include <dm/ofnode.h>
#include <drm/drm_dsc.h>
+#include <spl_display.h>
+#include <clk.h>
/*
- * major: IP major vertion, used for IP structure
+ * major: IP major version, used for IP structure
* minor: big feature change under same structure
+ * build: RTL current SVN number
*/
-#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
-#define VOP_MAJOR(version) ((version) >> 8)
-#define VOP_MINOR(version) ((version) & 0xff)
+#define VOP_VERSION(major, minor) ((major) << 8 | (minor))
+#define VOP_MAJOR(version) ((version) >> 8)
+#define VOP_MINOR(version) ((version) & 0xff)
-#define VOP_VERSION_RK3568 VOP_VERSION(0x40, 0x15)
-#define VOP_VERSION_RK3588 VOP_VERSION(0x40, 0x17)
+#define VOP2_VERSION(major, minor, build) ((major) << 24 | (minor) << 16 | (build))
+#define VOP2_MAJOR(version) (((version) >> 24) & 0xff)
+#define VOP2_MINOR(version) (((version) >> 16) & 0xff)
+#define VOP2_BUILD(version) ((version) & 0xffff)
+
+#define VOP_VERSION_RK3528 VOP2_VERSION(0x50, 0x17, 0x1263)
+#define VOP_VERSION_RK3562 VOP2_VERSION(0x50, 0x17, 0x4350)
+#define VOP_VERSION_RK3568 VOP2_VERSION(0x40, 0x15, 0x8023)
+#define VOP_VERSION_RK3588 VOP2_VERSION(0x40, 0x17, 0x6786)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE BIT(0)
#define ROCKCHIP_OUTPUT_DUAL_CHANNEL_ODD_EVEN_MODE BIT(1)
@@ -66,6 +81,7 @@
#define ROCKCHIP_OUT_MODE_P565 2
#define ROCKCHIP_OUT_MODE_BT656 5
#define ROCKCHIP_OUT_MODE_S888 8
+#define ROCKCHIP_OUT_MODE_YUV422 9
#define ROCKCHIP_OUT_MODE_S888_DUMMY 12
#define ROCKCHIP_OUT_MODE_YUV420 14
/* for use special outface */
@@ -141,6 +157,7 @@
void *private;
ofnode node;
struct device_node *ports_node; /* if (ports_node) it's vop2; */
+ struct clk dclk;
int crtc_id;
int format;
@@ -160,6 +177,7 @@
bool post_y2r_en;
bool bcsh_en;
bool splice_mode;
+ bool soft_te;
u8 splice_crtc_id;
u8 dsc_id;
u8 dsc_enable;
@@ -198,6 +216,7 @@
struct overscan overscan;
u8 edid[EDID_SIZE * 4];
int bus_format;
+ u32 bus_flags;
int output_mode;
int type;
int output_if;
@@ -223,6 +242,8 @@
u64 dsc_cds_clk;
struct rockchip_dsc_sink_cap dsc_sink_cap;
struct drm_dsc_picture_parameter_set pps;
+
+ struct gpio_desc *te_gpio;
struct {
u32 *lut;
@@ -268,7 +289,9 @@
int enable;
int is_init;
int is_enable;
+ bool is_klogo_valid;
bool force_output;
+ bool enabled_at_spl;
struct drm_display_mode force_mode;
u32 force_bus_format;
};
@@ -282,11 +305,22 @@
void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
struct vop_rect *max_output);
unsigned long get_cubic_lut_buffer(int crtc_id);
-int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode);
+int rockchip_ofnode_get_display_mode(ofnode node, struct drm_display_mode *mode,
+ u32 *bus_flags);
+void rockchip_display_make_crc32_table(void);
+uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length);
+void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags);
int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
int min_hscale, int max_hscale);
int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
int min_vscale, int max_vscale);
+const struct device_node *
+rockchip_of_graph_get_endpoint_by_regs(ofnode node, int port, int endpoint);
+#ifdef CONFIG_SPL_BUILD
+int rockchip_spl_vop_probe(struct crtc_state *crtc_state);
+int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state);
+int inno_spl_hdmi_phy_probe(struct display_state *state);
+#endif
#endif
diff --git a/u-boot/drivers/video/drm/rockchip_display_helper.c b/u-boot/drivers/video/drm/rockchip_display_helper.c
new file mode 100644
index 0000000..da34f4d
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_display_helper.c
@@ -0,0 +1,279 @@
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <linux/hdmi.h>
+#include <linux/compat.h>
+#include "rockchip_display.h"
+#include <spl_display.h>
+
+#define RK_BLK_SIZE 512
+#define BMP_PROCESSED_FLAG 8399
+
+static uint32_t crc32_table[256];
+
+void rockchip_display_make_crc32_table(void)
+{
+ uint32_t c;
+ int n, k;
+ unsigned long poly; /* polynomial exclusive-or pattern */
+ /* terms of polynomial defining this crc (except x^32): */
+ static const char p[] = {0, 1, 2, 4, 5, 7, 8, 10, 11, 12, 16, 22, 23, 26};
+
+ /* make exclusive-or pattern from polynomial (0xedb88320L) */
+ poly = 0L;
+ for (n = 0; n < sizeof(p) / sizeof(char); n++)
+ poly |= 1L << (31 - p[n]);
+
+ for (n = 0; n < 256; n++) {
+ c = (unsigned long)n;
+ for (k = 0; k < 8; k++)
+ c = c & 1 ? poly ^ (c >> 1) : c >> 1;
+ crc32_table[n] = cpu_to_le32(c);
+ }
+}
+
+uint32_t rockchip_display_crc32c_cal(unsigned char *data, int length)
+{
+ int i;
+ uint32_t crc;
+ crc = 0xFFFFFFFF;
+
+ for (i = 0; i < length; i++) {
+ crc = crc32_table[(crc ^ *data) & 0xff] ^ (crc >> 8);
+ data++;
+ }
+
+ return crc ^ 0xffffffff;
+}
+
+/**
+ * drm_mode_max_resolution_filter - mark modes out of vop max resolution
+ * @edid_data: structure store mode list
+ * @max_output: vop max output resolution
+ */
+void drm_mode_max_resolution_filter(struct hdmi_edid_data *edid_data,
+ struct vop_rect *max_output)
+{
+ int i;
+
+ for (i = 0; i < edid_data->modes; i++) {
+ if (edid_data->mode_buf[i].hdisplay > max_output->width ||
+ edid_data->mode_buf[i].vdisplay > max_output->height)
+ edid_data->mode_buf[i].invalid = true;
+ }
+}
+
+int drm_mode_vrefresh(const struct drm_display_mode *mode)
+{
+ int refresh = 0;
+ unsigned int calc_val;
+
+ if (mode->vrefresh > 0) {
+ refresh = mode->vrefresh;
+ } else if (mode->htotal > 0 && mode->vtotal > 0) {
+ int vtotal;
+
+ vtotal = mode->vtotal;
+ /* work out vrefresh the value will be x1000 */
+ calc_val = (mode->clock * 1000);
+ calc_val /= mode->htotal;
+ refresh = (calc_val + vtotal / 2) / vtotal;
+
+ if (mode->flags & DRM_MODE_FLAG_INTERLACE)
+ refresh *= 2;
+ if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
+ refresh /= 2;
+ if (mode->vscan > 1)
+ refresh /= mode->vscan;
+ }
+ return refresh;
+}
+
+/**
+ * drm_mode_set_crtcinfo - set CRTC modesetting timing parameters
+ * @p: mode
+ * @adjust_flags: a combination of adjustment flags
+ *
+ * Setup the CRTC modesetting timing parameters for @p, adjusting if necessary.
+ *
+ * - The CRTC_INTERLACE_HALVE_V flag can be used to halve vertical timings of
+ * interlaced modes.
+ * - The CRTC_STEREO_DOUBLE flag can be used to compute the timings for
+ * buffers containing two eyes (only adjust the timings when needed, eg. for
+ * "frame packing" or "side by side full").
+ * - The CRTC_NO_DBLSCAN and CRTC_NO_VSCAN flags request that adjustment *not*
+ * be performed for doublescan and vscan > 1 modes respectively.
+ */
+void drm_mode_set_crtcinfo(struct drm_display_mode *p, int adjust_flags)
+{
+ if ((p == NULL) || ((p->type & DRM_MODE_TYPE_CRTC_C) == DRM_MODE_TYPE_BUILTIN))
+ return;
+
+ if (p->flags & DRM_MODE_FLAG_DBLCLK)
+ p->crtc_clock = 2 * p->clock;
+ else
+ p->crtc_clock = p->clock;
+ p->crtc_hdisplay = p->hdisplay;
+ p->crtc_hsync_start = p->hsync_start;
+ p->crtc_hsync_end = p->hsync_end;
+ p->crtc_htotal = p->htotal;
+ p->crtc_hskew = p->hskew;
+ p->crtc_vdisplay = p->vdisplay;
+ p->crtc_vsync_start = p->vsync_start;
+ p->crtc_vsync_end = p->vsync_end;
+ p->crtc_vtotal = p->vtotal;
+
+ if (p->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (adjust_flags & CRTC_INTERLACE_HALVE_V) {
+ p->crtc_vdisplay /= 2;
+ p->crtc_vsync_start /= 2;
+ p->crtc_vsync_end /= 2;
+ p->crtc_vtotal /= 2;
+ }
+ }
+
+ if (!(adjust_flags & CRTC_NO_DBLSCAN)) {
+ if (p->flags & DRM_MODE_FLAG_DBLSCAN) {
+ p->crtc_vdisplay *= 2;
+ p->crtc_vsync_start *= 2;
+ p->crtc_vsync_end *= 2;
+ p->crtc_vtotal *= 2;
+ }
+ }
+
+ if (!(adjust_flags & CRTC_NO_VSCAN)) {
+ if (p->vscan > 1) {
+ p->crtc_vdisplay *= p->vscan;
+ p->crtc_vsync_start *= p->vscan;
+ p->crtc_vsync_end *= p->vscan;
+ p->crtc_vtotal *= p->vscan;
+ }
+ }
+
+ if (adjust_flags & CRTC_STEREO_DOUBLE) {
+ unsigned int layout = p->flags & DRM_MODE_FLAG_3D_MASK;
+
+ switch (layout) {
+ case DRM_MODE_FLAG_3D_FRAME_PACKING:
+ p->crtc_clock *= 2;
+ p->crtc_vdisplay += p->crtc_vtotal;
+ p->crtc_vsync_start += p->crtc_vtotal;
+ p->crtc_vsync_end += p->crtc_vtotal;
+ p->crtc_vtotal += p->crtc_vtotal;
+ break;
+ }
+ }
+
+ p->crtc_vblank_start = min(p->crtc_vsync_start, p->crtc_vdisplay);
+ p->crtc_vblank_end = max(p->crtc_vsync_end, p->crtc_vtotal);
+ p->crtc_hblank_start = min(p->crtc_hsync_start, p->crtc_hdisplay);
+ p->crtc_hblank_end = max(p->crtc_hsync_end, p->crtc_htotal);
+}
+
+/**
+ * drm_mode_is_420_only - if a given videomode can be only supported in YCBCR420
+ * output format
+ *
+ * @connector: drm connector under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be supported in YCBCR420 format
+ * false if not.
+ */
+static bool drm_mode_is_420_only(const struct drm_display_info *display,
+ struct drm_display_mode *mode)
+{
+ u8 vic = drm_match_cea_mode(mode);
+
+ return test_bit(vic, display->hdmi.y420_vdb_modes);
+}
+
+/**
+ * drm_mode_is_420_also - if a given videomode can be supported in YCBCR420
+ * output format also (along with RGB/YCBCR444/422)
+ *
+ * @display: display under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be support YCBCR420 format
+ * false if not.
+ */
+static bool drm_mode_is_420_also(const struct drm_display_info *display,
+ struct drm_display_mode *mode)
+{
+ u8 vic = drm_match_cea_mode(mode);
+
+ return test_bit(vic, display->hdmi.y420_cmdb_modes);
+}
+
+/**
+ * drm_mode_is_420 - if a given videomode can be supported in YCBCR420
+ * output format
+ *
+ * @display: display under action.
+ * @mode: video mode to be tested.
+ *
+ * Returns:
+ * true if the mode can be supported in YCBCR420 format
+ * false if not.
+ */
+bool drm_mode_is_420(const struct drm_display_info *display,
+ struct drm_display_mode *mode)
+{
+ return drm_mode_is_420_only(display, mode) ||
+ drm_mode_is_420_also(display, mode);
+}
+
+static int display_rect_calc_scale(int src, int dst)
+{
+ int scale = 0;
+
+ if (WARN_ON(src < 0 || dst < 0))
+ return -EINVAL;
+
+ if (dst == 0)
+ return 0;
+
+ src <<= 16;
+
+ if (src > (dst << 16))
+ return DIV_ROUND_UP(src, dst);
+ else
+ scale = src / dst;
+
+ return scale;
+}
+
+int display_rect_calc_hscale(struct display_rect *src, struct display_rect *dst,
+ int min_hscale, int max_hscale)
+{
+ int hscale = display_rect_calc_scale(src->w, dst->w);
+
+ if (hscale < 0 || dst->w == 0)
+ return hscale;
+
+ if (hscale < min_hscale || hscale > max_hscale)
+ return -ERANGE;
+
+ return hscale;
+}
+
+int display_rect_calc_vscale(struct display_rect *src, struct display_rect *dst,
+ int min_vscale, int max_vscale)
+{
+ int vscale = display_rect_calc_scale(src->h, dst->h);
+
+ if (vscale < 0 || dst->h == 0)
+ return vscale;
+
+ if (vscale < min_vscale || vscale > max_vscale)
+ return -ERANGE;
+
+ return vscale;
+}
+
diff --git a/u-boot/drivers/video/drm/rockchip_drm_tve.c b/u-boot/drivers/video/drm/rockchip_drm_tve.c
deleted file mode 100644
index a159bfe..0000000
--- a/u-boot/drivers/video/drm/rockchip_drm_tve.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
- */
-#include <common.h>
-#include <malloc.h>
-#include <fdtdec.h>
-#include <fdt_support.h>
-#include <asm/io.h>
-#include <linux/media-bus-format.h>
-#include <asm/arch-rockchip/clock.h>
-#include <dm/device.h>
-#include <dm/read.h>
-#include <dm/uclass-internal.h>
-#include <linux/fb.h>
-#include <edid.h>
-#include <syscon.h>
-#include <boot_rkimg.h>
-#include <mapmem.h>
-#include <misc.h>
-#include "rockchip_drm_tve.h"
-#include "rockchip_display.h"
-#include "rockchip_crtc.h"
-#include "rockchip_connector.h"
-#include "rockchip_phy.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct drm_tve tve_s;
-
-#define tve_writel(offset, v) writel(v, tve_s.reg_phy_base + offset)
-#define tve_readl(offset) readl(tve_s.reg_phy_base + offset)
-
-#define tve_dac_writel(offset, v) writel(v, tve_s.vdacbase + offset)
-#define tve_dac_readl(offset) readl(tve_s.vdacbase + offset)
-
-#define RK322X_VDAC_STANDARD 0x15
-
-#define TVE_REG_NUM 0x28
-
-static const struct drm_display_mode tve_modes[] = {
- /* 0 - 720x576i@50Hz */
- { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
- 816, 864, 576, 580, 586, 625, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 50, },
- /* 1 - 720x480i@60Hz */
- { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
- 815, 858, 480, 480, 486, 525, 0,
- DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
- DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
- .vrefresh = 60, },
-};
-
-static void dac_enable(int enable)
-{
- u32 mask, val = 0;
- u32 grfreg = 0;
-
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
- tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve_s.daclevel));
- tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0));
-#endif
- if (enable) {
- mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
-#if defined(CONFIG_ROCKCHIP_RK3128)
- val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve_s.daclevel);
- grfreg = GRF_TVE_CON0;
-#elif defined(CONFIG_ROCKCHIP_RK3036)
- val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve_s.daclevel);
- grfreg = GRF_SOC_CON3;
-#endif
- val |= mask << 16;
-
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
- val = v_CUR_REG(tve_s.dac1level) |
- v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
-#endif
- } else {
- mask = m_VBG_EN | m_DAC_EN;
- val = 0;
-#if defined(CONFIG_ROCKCHIP_RK3128)
- grfreg = GRF_TVE_CON0;
-#elif defined(CONFIG_ROCKCHIP_RK3036)
- grfreg = GRF_SOC_CON3;
-#endif
- val |= mask << 16;
-
-#if defined(CONFIG_ROCKCHIP_RK322X) || defined(CONFIG_ROCKCHIP_RK3328)
- val = v_CUR_REG(tve_s.dac1level) |
- m_DR_PWR_DOWN | m_BG_PWR_DOWN;
- #endif
- }
-
- if (grfreg)
- writel(val, tve_s.grf + grfreg);
- else if (tve_s.vdacbase)
- tve_dac_writel(VDAC_VDAC1, val);
-}
-
-static void tve_set_mode(int mode)
-{
- if (tve_s.soctype != SOC_RK322X &&
- tve_s.soctype != SOC_RK322XH) {
- tve_writel(TV_RESET, v_RESET(1));
- udelay(100);
- tve_writel(TV_RESET, v_RESET(0));
- }
-
- if (tve_s.soctype == SOC_RK3036)
- tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
- v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
- v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
- else
- tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
- v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
- v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3));
-
- tve_writel(TV_LUMA_FILTER0, tve_s.lumafilter0);
- tve_writel(TV_LUMA_FILTER1, tve_s.lumafilter1);
- tve_writel(TV_LUMA_FILTER2, tve_s.lumafilter2);
-
- if (mode == TVOUT_CVBS_NTSC) {
- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) |
- v_Y_AGC_PULSE_ON(1) | v_Y_VIDEO_ON(1) |
- v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) |
- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
- tve_writel(TV_SATURATION, 0x0052543C);
- if (tve_s.test_mode)
- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
- else
- tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
-
- tve_writel(TV_FREQ_SC, 0x21F07BD7);
- tve_writel(TV_SYNC_TIMING, 0x00C07a81);
- tve_writel(TV_ADJ_TIMING, 0x96B40000);
- tve_writel(TV_ACT_ST, 0x001500D6);
- tve_writel(TV_ACT_TIMING, 0x169800FC | (1 << 12) | (1 << 28));
-
- } else if (mode == TVOUT_CVBS_PAL) {
- tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) |
- v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
- v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
- tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) |
- v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
-
- tve_writel(TV_SATURATION, tve_s.saturation);
- tve_writel(TV_BRIGHTNESS_CONTRAST, tve_s.brightcontrast);
-
- tve_writel(TV_FREQ_SC, 0x2A098ACB);
- tve_writel(TV_SYNC_TIMING, 0x00C28381);
- tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80);
- tve_writel(TV_ACT_ST, 0x001500F6);
- tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
-
- tve_writel(TV_ADJ_TIMING, tve_s.adjtiming);
- tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
- }
-}
-
-static u8 rk_get_vdac_value(void)
-{
- u8 value = 0;
-#ifdef CONFIG_ROCKCHIP_EFUSE
-#if defined(CONFIG_ROCKCHIP_RK322X)
- struct udevice *dev;
- u32 regs[2] = {0};
- u8 fuses[1];
- ofnode node;
- int ret;
-
- ret = uclass_get_device_by_driver(UCLASS_MISC,
- DM_GET_DRIVER(rockchip_efuse), &dev);
- if (ret) {
- printf("%s: no misc-device found\n", __func__);
- return -EINVAL;
- }
-
- node = dev_read_subnode(dev, "tve_dac");
- if (!ofnode_valid(node))
- return -EINVAL;
-
- ret = ofnode_read_u32_array(node, "reg", regs, 2);
- if (ret) {
- printf("Cannot get efuse reg\n");
- return -EINVAL;
- }
-
- ret = misc_read(dev, regs[0], &fuses, regs[1]);
- if (ret) {
- printf("%s: misc_read failed\n", __func__);
- return 0;
- }
-
- value = fuses[0];
- value = (value >> 3) & 0x1f;
-#endif
-#endif /* CONFIG_RK_EFUSE */
- if (value > 0)
- value += 5;
- TVEDBG("%s value = 0x%x\n", __func__, value);
-
- return value;
-}
-
-static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state)
-{
- int node = 0;
- int dac_value, getvdac;
- fdt_addr_t addr;
-
- tve_s.grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
- if (tve_s.grf <= 0) {
- printf("%s:Get syscon grf failed (ret=%p)\n",
- __func__, tve_s.grf);
- return -ENXIO;
- }
-
-#if defined(CONFIG_ROCKCHIP_RK3036)
- addr = dev_read_addr_index(conn->dev, 0);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- tve_s.reg_phy_base = (void *)addr;
- tve_s.soctype = SOC_RK3036;
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
- "rockchip,rk3036-tve");
- if (node < 0) {
- printf("can't find dts node for rk3036-tve\n");
- goto err;
- }
-#elif defined(CONFIG_ROCKCHIP_RK3128)
- addr = dev_read_addr_index(conn->dev, 0);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- tve_s.reg_phy_base = (void *)addr;
- tve_s.soctype = SOC_RK312X;
- tve_s.saturation = 0;
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
- "rockchip,rk312x-tve");
- if (node < 0) {
- printf("can't find dts node for rk312x-tve\n");
- goto err;
- }
-#elif defined(CONFIG_ROCKCHIP_RK322X)
- addr = dev_read_addr_index(conn->dev, 0);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- tve_s.reg_phy_base = (void *)addr;
- tve_s.soctype = SOC_RK322X;
- tve_s.saturation = 0;
-
- addr = dev_read_addr_index(conn->dev, 1);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
- tve_s.vdacbase = (void *)addr;
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
- "rockchip,rk3328-tve");
- if (node < 0) {
- printf("can't find dts node for rk322x-tve\n");
- goto err;
- }
-#elif defined(CONFIG_ROCKCHIP_RK3328)
- addr = dev_read_addr_index(conn->dev, 0);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
-
- tve_s.reg_phy_base = (void *)addr;
- tve_s.soctype = SOC_RK322XH;
-
- addr = dev_read_addr_index(conn->dev, 1);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
- tve_s.vdacbase = (void *)addr;
-
- node = fdt_node_offset_by_compatible(gd->fdt_blob, 0,
- "rockchip,rk3328-tve");
- if (node < 0) {
- printf("can't find dts node for rk322xh-tve\n");
- goto err;
- }
-#endif
-
- if (!fdtdec_get_is_enabled(gd->fdt_blob, node)) {
- printf("tve is disabled\n");
- goto err;
- }
-
- if (tve_s.soctype == SOC_RK312X)
- tve_s.test_mode = fdtdec_get_int(gd->fdt_blob, node,
- "test_mode", 0);
-
- tve_s.preferred_mode = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,tvemode", -1);
- if (tve_s.preferred_mode < 0) {
- tve_s.preferred_mode = 0;
- } else if (tve_s.preferred_mode > 1) {
- printf("tve mode value invalid\n");
- goto err;
- }
-
- tve_s.saturation = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,saturation", 0);
- if (tve_s.saturation == 0) {
- printf("tve saturation err\n");
- goto err;
- }
-
- tve_s.brightcontrast = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,brightcontrast", 0);
- if (tve_s.brightcontrast == 0) {
- printf("tve brightcontrast err\n");
- goto err;
- }
-
- tve_s.adjtiming = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,adjtiming", 0);
- if (tve_s.adjtiming == 0) {
- printf("tve adjtiming err\n");
- goto err;
- }
-
- tve_s.lumafilter0 = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,lumafilter0", 0);
- if (tve_s.lumafilter0 == 0) {
- printf("tve lumafilter0 err\n");
- goto err;
- }
-
- tve_s.lumafilter1 = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,lumafilter1", 0);
- if (tve_s.lumafilter1 == 0) {
- printf("tve lumafilter1 err\n");
- goto err;
- }
-
- tve_s.lumafilter2 = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,lumafilter2", 0);
- if (tve_s.lumafilter2 == 0) {
- printf("tve lumafilter2 err\n");
- goto err;
- }
-
- dac_value = fdtdec_get_int(gd->fdt_blob, node, "rockchip,daclevel", 0);
- if (dac_value == 0) {
- printf("tve dac_value err\n");
- goto err;
- }
-
- tve_s.daclevel = dac_value;
- if (tve_s.soctype == SOC_RK322X) {
- getvdac = rk_get_vdac_value();
- if (getvdac > 0) {
- tve_s.daclevel =
- dac_value + getvdac - RK322X_VDAC_STANDARD;
- if (tve_s.daclevel > 0x3f ||
- tve_s.daclevel < 0) {
- printf("rk322x daclevel error!\n");
- tve_s.daclevel = dac_value;
- }
- } else if (getvdac < 0) {
- printf("get rk322x daclevel error\n");
- goto err;
- }
- }
-
- if (tve_s.soctype == SOC_RK322X ||
- tve_s.soctype == SOC_RK322XH) {
- tve_s.dac1level = fdtdec_get_int(gd->fdt_blob, node,
- "rockchip,dac1level", 0);
- if (tve_s.dac1level == 0) {
- printf("rk322x dac1level error!\n");
- goto err;
- }
- }
- TVEDBG("tve_s.test_mode = 0x%x\n", tve_s.test_mode);
- TVEDBG("tve_s.saturation = 0x%x\n", tve_s.saturation);
- TVEDBG("tve_s.brightcontrast = 0x%x\n", tve_s.brightcontrast);
- TVEDBG("tve_s.adjtiming = 0x%x\n", tve_s.adjtiming);
- TVEDBG("tve_s.lumafilter0 = 0x%x\n", tve_s.lumafilter0);
- TVEDBG("tve_s.lumafilter1 = 0x%x\n", tve_s.lumafilter1);
- TVEDBG("tve_s.lumafilter2 = 0x%x\n", tve_s.lumafilter2);
- TVEDBG("tve_s.daclevel = 0x%x\n", tve_s.daclevel);
-
- return 0;
-
-err:
- dac_enable(0);
- return -ENODEV;
-}
-
-static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state)
-{
- struct connector_state *conn_state = &state->conn_state;
- struct drm_display_mode *mode = &conn_state->mode;
- int tve_type;
-
-#ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY
- /* set inno hdmi phy clk. */
- rockchip_phy_set_pll(conn->phy, 27000000);
-#endif
- if (mode->vdisplay == 576)
- tve_type = TVOUT_CVBS_PAL;
- else
- tve_type = TVOUT_CVBS_NTSC;
- dac_enable(0);
- tve_set_mode(tve_type);
- dac_enable(1);
-
- return 0;
-}
-
-static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state)
-{
- dac_enable(0);
-}
-
-static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state)
-{
- return 0;
-}
-
-static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state)
-{
- dac_enable(0);
- return 0;
-}
-
-static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state)
-{
- return 1;
-}
-
-static void drm_tve_selete_output(struct overscan *overscan,
- struct drm_display_mode *mode)
-{
- int ret, i, screen_size;
- struct base_screen_info *screen_info = NULL;
- struct base_disp_info base_parameter;
- struct drm_display_mode modes[2];
- const struct base_overscan *scan;
- char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
- struct blk_desc *dev_desc;
- disk_partition_t part_info;
- int max_scan = 100;
- int min_scan = 50;
-
- overscan->left_margin = max_scan;
- overscan->right_margin = max_scan;
- overscan->top_margin = max_scan;
- overscan->bottom_margin = max_scan;
-
- for (i = 0; i < 2; i++) {
- modes[i] = tve_modes[i];
- if (i == tve_s.preferred_mode)
- modes[i].type |= DRM_MODE_TYPE_PREFERRED;
- }
- *mode = modes[tve_s.preferred_mode];
-
- dev_desc = rockchip_get_bootdev();
- if (!dev_desc) {
- printf("%s: Could not find device\n", __func__);
- return;
- }
-
- if (part_get_info_by_name(dev_desc, "baseparameter", &part_info) < 0) {
- printf("Could not find baseparameter partition\n");
- return;
- }
-
- ret = blk_dread(dev_desc, part_info.start, 1,
- (void *)baseparameter_buf);
- if (ret < 0) {
- printf("read baseparameter failed\n");
- return;
- }
-
- memcpy(&base_parameter, baseparameter_buf, sizeof(base_parameter));
- scan = &base_parameter.scan;
-
- screen_size = sizeof(base_parameter.screen_list) /
- sizeof(base_parameter.screen_list[0]);
-
- for (i = 0; i < screen_size; i++) {
- if (base_parameter.screen_list[i].type ==
- DRM_MODE_CONNECTOR_TV) {
- screen_info = &base_parameter.screen_list[i];
- break;
- }
- }
-
- if (scan->leftscale < min_scan && scan->leftscale > 0)
- overscan->left_margin = min_scan;
- else if (scan->leftscale < max_scan)
- overscan->left_margin = scan->leftscale;
-
- if (scan->rightscale < min_scan && scan->rightscale > 0)
- overscan->right_margin = min_scan;
- else if (scan->rightscale < max_scan)
- overscan->right_margin = scan->rightscale;
-
- if (scan->topscale < min_scan && scan->topscale > 0)
- overscan->top_margin = min_scan;
- else if (scan->topscale < max_scan)
- overscan->top_margin = scan->topscale;
-
- if (scan->bottomscale < min_scan && scan->bottomscale > 0)
- overscan->bottom_margin = min_scan;
- else if (scan->bottomscale < max_scan)
- overscan->bottom_margin = scan->bottomscale;
-
- if (screen_info &&
- (screen_info->mode.hdisplay == 720 &&
- screen_info->mode.vdisplay == 576 &&
- screen_info->mode.hsync_start == 753 &&
- screen_info->mode.hsync_end == 816))
- *mode = modes[0];
- else if (screen_info &&
- screen_info->mode.vdisplay == 480 &&
- screen_info->mode.vsync_start == 480 &&
- screen_info->mode.vsync_end == 486)
- *mode = modes[1];
-
- if (screen_info)
- printf("base_parameter.mode:%dx%d\n",
- screen_info->mode.hdisplay,
- screen_info->mode.vdisplay);
-}
-
-static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state)
-{
- struct connector_state *conn_state = &state->conn_state;
- struct drm_display_mode *mode = &conn_state->mode;
-
- conn_state->output_mode = ROCKCHIP_OUT_MODE_P888;
- conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
- drm_tve_selete_output(&conn_state->overscan, mode);
-
- return 0;
-}
-
-const struct rockchip_connector_funcs rockchip_drm_tve_funcs = {
- .init = rockchip_drm_tve_init,
- .deinit = rockchip_drm_tve_deinit,
- .prepare = rockchip_drm_tve_prepare,
- .enable = rockchip_drm_tve_enable,
- .disable = rockchip_drm_tve_disable,
- .get_timing = rockchip_drm_tve_get_timing,
- .detect = rockchip_drm_tve_detect,
-};
-
-static int rockchip_drm_tve_probe(struct udevice *dev)
-{
- struct rockchip_connector *conn = dev_get_priv(dev);
-
- rockchip_connector_bind(conn, dev, 0, &rockchip_drm_tve_funcs, NULL,
- DRM_MODE_CONNECTOR_TV);
-
- return 0;
-}
-
-static const struct udevice_id rockchip_drm_tve_ids[] = {
- {
- .compatible = "rockchip,rk3328-tve",
- }, {}
-};
-
-U_BOOT_DRIVER(rockchip_drm_tve) = {
- .name = "rockchip_drm_tve",
- .id = UCLASS_DISPLAY,
- .of_match = rockchip_drm_tve_ids,
- .probe = rockchip_drm_tve_probe,
- .priv_auto_alloc_size = sizeof(struct rockchip_connector),
-};
diff --git a/u-boot/drivers/video/drm/rockchip_drm_tve.h b/u-boot/drivers/video/drm/rockchip_drm_tve.h
deleted file mode 100644
index 2d504a6..0000000
--- a/u-boot/drivers/video/drm/rockchip_drm_tve.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * SPDX-License-Identifier: GPL-2.0+
- * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
- */
-#ifndef __ROCKCHIP_DRM_TVE_H__
-#define __ROCKCHIP_DRM_TVE_H__
-
-#include <lcd.h>
-
-#define TV_CTRL (0x00)
- #define m_CVBS_MODE BIT(24)
- #define m_CLK_UPSTREAM_EN (3 << 18)
- #define m_TIMING_EN (3 << 16)
- #define m_LUMA_FILTER_GAIN (3 << 9)
- #define m_LUMA_FILTER_BW BIT(8)
- #define m_CSC_PATH (3 << 1)
-
- #define v_CVBS_MODE(x) ((x & 1) << 24)
- #define v_CLK_UPSTREAM_EN(x) ((x & 3) << 18)
- #define v_TIMING_EN(x) ((x & 3) << 16)
- #define v_LUMA_FILTER_GAIN(x) ((x & 3) << 9)
- #define v_LUMA_FILTER_UPSAMPLE(x) ((x & 1) << 8)
- #define v_CSC_PATH(x) ((x & 3) << 1)
-
-#define TV_SYNC_TIMING (0x04)
-#define TV_ACT_TIMING (0x08)
-#define TV_ADJ_TIMING (0x0c)
-#define TV_FREQ_SC (0x10)
-#define TV_LUMA_FILTER0 (0x14)
-#define TV_LUMA_FILTER1 (0x18)
-#define TV_LUMA_FILTER2 (0x1C)
-#define TV_ACT_ST (0x34)
-#define TV_ROUTING (0x38)
- #define m_DAC_SENSE_EN BIT(27)
- #define m_Y_IRE_7_5 BIT(19)
- #define m_Y_AGC_PULSE_ON BIT(15)
- #define m_Y_VIDEO_ON BIT(11)
- #define m_Y_SYNC_ON BIT(7)
- #define m_YPP_MODE BIT(3)
- #define m_MONO_EN BIT(2)
- #define m_PIC_MODE BIT(1)
-
- #define v_DAC_SENSE_EN(x) ((x & 1) << 27)
- #define v_Y_IRE_7_5(x) ((x & 1) << 19)
- #define v_Y_AGC_PULSE_ON(x) ((x & 1) << 15)
- #define v_Y_VIDEO_ON(x) ((x & 1) << 11)
- #define v_Y_SYNC_ON(x) ((x & 1) << 7)
- #define v_YPP_MODE(x) ((x & 1) << 3)
- #define v_MONO_EN(x) ((x & 1) << 2)
- #define v_PIC_MODE(x) ((x & 1) << 1)
-
-#define TV_SYNC_ADJUST (0x50)
-#define TV_STATUS (0x54)
-#define TV_RESET (0x68)
- #define m_RESET BIT(1)
- #define v_RESET(x) ((x & 1) << 1)
-#define TV_SATURATION (0x78)
-#define TV_BW_CTRL (0x8C)
- #define m_CHROMA_BW (3 << 4)
- #define m_COLOR_DIFF_BW (0xf)
-
- enum {
- BP_FILTER_PASS = 0,
- BP_FILTER_NTSC,
- BP_FILTER_PAL,
- };
- enum {
- COLOR_DIFF_FILTER_OFF = 0,
- COLOR_DIFF_FILTER_BW_0_6,
- COLOR_DIFF_FILTER_BW_1_3,
- COLOR_DIFF_FILTER_BW_2_0
- };
-
- #define v_CHROMA_BW(x) ((3 & x) << 4)
- #define v_COLOR_DIFF_BW(x) (0xF & x)
-
-#define TV_BRIGHTNESS_CONTRAST (0x90)
-
-#define m_EXTREF_EN BIT(0)
-#define m_VBG_EN BIT(1)
-#define m_DAC_EN BIT(2)
-#define m_SENSE_EN BIT(3)
-#define m_BIAS_EN (7 << 4)
-#define m_DAC_GAIN (0x3f << 7)
-#define v_DAC_GAIN(x) ((x & 0x3f) << 7)
-
-#define VDAC_VDAC0 (0x00)
- #define m_RST_ANA BIT(7)
- #define m_RST_DIG BIT(6)
-
- #define v_RST_ANA(x) ((x & 1) << 7)
- #define v_RST_DIG(x) ((x & 1) << 6)
-#define VDAC_VDAC1 (0x280)
- #define m_CUR_REG (0xf << 4)
- #define m_DR_PWR_DOWN BIT(1)
- #define m_BG_PWR_DOWN BIT(0)
-
- #define v_CUR_REG(x) ((x & 0xf) << 4)
- #define v_DR_PWR_DOWN(x) ((x & 1) << 1)
- #define v_BG_PWR_DOWN(x) ((x & 1) << 0)
-#define VDAC_VDAC2 (0x284)
- #define m_CUR_CTR (0X3f)
-
- #define v_CUR_CTR(x) ((x & 0X3f))
-#define VDAC_VDAC3 (0x288)
- #define m_CAB_EN BIT(5)
- #define m_CAB_REF BIT(4)
- #define m_CAB_FLAG BIT(0)
-
- #define v_CAB_EN(x) ((x & 1) << 5)
- #define v_CAB_REF(x) ((x & 1) << 4)
- #define v_CAB_FLAG(x) ((x & 1) << 0)
-
-enum {
- TVOUT_CVBS_NTSC = 0,
- TVOUT_CVBS_PAL,
-};
-
-enum {
- SOC_RK3036 = 0,
- SOC_RK312X,
- SOC_RK322X,
- SOC_RK322XH
-};
-
-struct drm_tve {
- void *reg_phy_base;
- int soctype;
- int test_mode;
- int saturation;
- void *vdacbase;
- int brightcontrast;
- int adjtiming;
- int lumafilter0;
- int lumafilter1;
- int lumafilter2;
- int daclevel;
- int dac1level;
- int preferred_mode;
- void *grf;
-};
-
-#define RK30_TVE_REGBASE 0x10118000 + 0x200
-#define MAX_TVE_COUNT 2
-
-#ifdef TVEDEBUG
-#define TVEDBG(format, ...) \
- printf("TVE: " format, ## __VA_ARGS__)
-#else
-#define TVEDBG(format, ...)
-#endif
-
-#endif /* __ROCKCHIP_DRM_TVE_H__*/
diff --git a/u-boot/drivers/video/drm/rockchip_dw_hdmi.c b/u-boot/drivers/video/drm/rockchip_dw_hdmi.c
index 3a3169c..6e6139f 100644
--- a/u-boot/drivers/video/drm/rockchip_dw_hdmi.c
+++ b/u-boot/drivers/video/drm/rockchip_dw_hdmi.c
@@ -7,6 +7,7 @@
#include <common.h>
#include <boot_rkimg.h>
#include <asm/io.h>
+#include <asm/gpio.h>
#include <dm/of_access.h>
#include <dm/device.h>
#include <linux/dw_hdmi.h>
@@ -35,6 +36,19 @@
#define RK3328_GRF_SOC_CON2 0x0408
#define RK3328_GRF_SOC_CON3 0x040c
#define RK3328_GRF_SOC_CON4 0x0410
+
+#define RK3528_GPIO0A_IOMUX_SEL_H 0x4
+#define RK3528_GPIO0A_PULL 0x200
+#define RK3528_DDC_PULL (0xf00 << 16)
+#define RK3528_VO_GRF_HDMI_MASK 0x60014
+#define RK3528_HDMI_SNKDET_SEL ((BIT(6) << 16) | BIT(6))
+#define RK3528_HDMI_SNKDET BIT(21)
+#define RK3528_HDMI_CECIN_MSK ((BIT(2) << 16) | BIT(2))
+#define RK3528_HDMI_SDAIN_MSK ((BIT(1) << 16) | BIT(1))
+#define RK3528_HDMI_SCLIN_MSK ((BIT(0) << 16) | BIT(0))
+
+#define RK3528_GPIO_SWPORT_DR_L 0x0000
+#define RK3528_GPIO0_A2_DR ((BIT(2) << 16) | BIT(2))
#define RK3568_GRF_VO_CON1 0x0364
#define RK3568_HDMI_SDAIN_MSK ((1 << 15) | (1 << (15 + 16)))
@@ -177,7 +191,7 @@
}
};
-static const struct dw_hdmi_phy_config rockchip_phy_config[] = {
+static struct dw_hdmi_phy_config rockchip_phy_config[] = {
/*pixelclk symbol term vlev*/
{ 74250000, 0x8009, 0x0004, 0x0272},
{ 165000000, 0x802b, 0x0004, 0x0209},
@@ -334,19 +348,23 @@
enum dw_hdmi_devtype dev_type,
bool output_bus_format_rgb)
{
- int ret, i, screen_size;
- struct base_disp_info base_parameter;
struct base2_disp_info *base2_parameter = conn_state->disp_info;
const struct base_overscan *scan;
struct base_screen_info *screen_info = NULL;
struct base2_screen_info *screen_info2 = NULL;
int max_scan = 100;
int min_scan = 51;
+#ifdef CONFIG_SPL_BUILD
+ int i, screen_size;
+#else
+ int ret, i, screen_size;
int offset = 0;
bool found = false;
struct blk_desc *dev_desc;
disk_partition_t part_info;
char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ struct base_disp_info base_parameter;
+#endif
overscan->left_margin = max_scan;
overscan->right_margin = max_scan;
@@ -358,6 +376,27 @@
else
*bus_format = MEDIA_BUS_FMT_YUV8_1X24;
+#ifdef CONFIG_SPL_BUILD
+ scan = &base2_parameter->overscan_info;
+ screen_size = sizeof(base2_parameter->screen_info) /
+ sizeof(base2_parameter->screen_info[0]);
+
+ for (i = 0; i < screen_size; i++) {
+ if (base2_parameter->screen_info[i].type ==
+ DRM_MODE_CONNECTOR_HDMIA) {
+ screen_info2 =
+ &base2_parameter->screen_info[i];
+ break;
+ }
+ }
+ screen_info = malloc(sizeof(*screen_info));
+
+ screen_info->type = screen_info2->type;
+ screen_info->mode = screen_info2->resolution;
+ screen_info->format = screen_info2->format;
+ screen_info->depth = screen_info2->depthc;
+ screen_info->feature = screen_info2->feature;
+#else
if (!base2_parameter) {
dev_desc = rockchip_get_bootdev();
if (!dev_desc) {
@@ -422,6 +461,7 @@
screen_info->depth = screen_info2->depthc;
screen_info->feature = screen_info2->feature;
}
+#endif
if (scan->leftscale < min_scan && scan->leftscale > 0)
overscan->left_margin = min_scan;
@@ -443,7 +483,9 @@
else if (scan->bottomscale < max_scan && scan->bottomscale > 0)
overscan->bottom_margin = scan->bottomscale;
+#ifndef CONFIG_SPL_BUILD
null_basep:
+#endif
if (screen_info)
printf("base_parameter.mode:%dx%d\n",
@@ -463,8 +505,15 @@
writel(RK3328_IO_3V_DOMAIN, grf + RK3328_GRF_SOC_CON4);
}
-void dw_hdmi_set_iomux(void *grf, int dev_type)
+void dw_hdmi_set_iomux(void *grf, void *gpio_base, struct gpio_desc *hpd_gpiod,
+ int dev_type)
{
+ u32 val = 0;
+ int i = 400;
+#ifdef CONFIG_SPL_BUILD
+ void *gpio0_ioc = (void *)RK3528_GPIO0_IOC_BASE;
+#endif
+
switch (dev_type) {
case RK3328_HDMI:
writel(RK3328_IO_DDC_IN_MSK, grf + RK3328_GRF_SOC_CON2);
@@ -473,6 +522,49 @@
case RK3228_HDMI:
writel(RK3228_IO_3V_DOMAIN, grf + RK3228_GRF_SOC_CON6);
writel(RK3228_IO_DDC_IN_MSK, grf + RK3228_GRF_SOC_CON2);
+ break;
+ case RK3528_HDMI:
+ writel(RK3528_HDMI_SDAIN_MSK | RK3528_HDMI_SCLIN_MSK |
+ RK3528_HDMI_SNKDET_SEL,
+ grf + RK3528_VO_GRF_HDMI_MASK);
+
+#ifdef CONFIG_SPL_BUILD
+ val = (0x11 << 16) | 0x11;
+ writel(val, gpio0_ioc + RK3528_GPIO0A_IOMUX_SEL_H);
+
+ writel(RK3528_DDC_PULL, gpio0_ioc + RK3528_GPIO0A_PULL);
+
+ /* gpio0_a2's input enable is controlled by gpio output data bit */
+ writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
+
+ while (i--) {
+ val = readl(gpio_base + 0x70) & BIT(2);
+ if (val)
+ break;
+ mdelay(5);
+ }
+#else
+ writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
+
+ /* gpio0_a2's input enable is controlled by gpio output data bit */
+ writel(RK3528_GPIO0_A2_DR, gpio_base + RK3528_GPIO_SWPORT_DR_L);
+
+ if (dm_gpio_is_valid(hpd_gpiod)) {
+ while (i--) {
+ val = dm_gpio_get_value(hpd_gpiod);
+ if (val)
+ break;
+ mdelay(5);
+ }
+ }
+#endif
+
+ if (val)
+ val = RK3528_HDMI_SNKDET | BIT(5);
+ else
+ val = RK3528_HDMI_SNKDET;
+ writel(val, grf + RK3528_VO_GRF_HDMI_MASK);
+
break;
case RK3568_HDMI:
writel(RK3568_HDMI_SDAIN_MSK | RK3568_HDMI_SCLIN_MSK,
@@ -544,6 +636,14 @@
.dev_type = RK3399_HDMI,
};
+const struct dw_hdmi_plat_data rk3528_hdmi_drv_data = {
+ .vop_sel_bit = 0,
+ .grf_vop_sel_reg = 0,
+ .phy_ops = &inno_dw_hdmi_phy_ops,
+ .phy_name = "inno_dw_hdmi_phy2",
+ .dev_type = RK3528_HDMI,
+};
+
const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
.vop_sel_bit = 0,
.grf_vop_sel_reg = 0,
@@ -554,6 +654,19 @@
.dev_type = RK3568_HDMI,
};
+#ifdef CONFIG_SPL_BUILD
+int rockchip_spl_dw_hdmi_probe(struct connector_state *conn_state)
+{
+ conn_state->connector = malloc(sizeof(struct rockchip_connector));
+
+ memset(conn_state->connector, 0, sizeof(*conn_state->connector));
+ rockchip_connector_bind(conn_state->connector, NULL, 0, &rockchip_dw_hdmi_funcs,
+ (void *)&rk3528_hdmi_drv_data,
+ DRM_MODE_CONNECTOR_HDMIA);
+
+ return 0;
+}
+#else
static int rockchip_dw_hdmi_probe(struct udevice *dev)
{
int id;
@@ -568,9 +681,13 @@
return 0;
}
+#endif
static const struct udevice_id rockchip_dw_hdmi_ids[] = {
{
+ .compatible = "rockchip,rk3528-dw-hdmi",
+ .data = (ulong)&rk3528_hdmi_drv_data,
+ }, {
.compatible = "rockchip,rk3568-dw-hdmi",
.data = (ulong)&rk3568_hdmi_drv_data,
}, {
@@ -598,6 +715,8 @@
.name = "rockchip_dw_hdmi",
.id = UCLASS_DISPLAY,
.of_match = rockchip_dw_hdmi_ids,
+#ifndef CONFIG_SPL_BUILD
.probe = rockchip_dw_hdmi_probe,
+#endif
.priv_auto_alloc_size = sizeof(struct rockchip_connector),
};
diff --git a/u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c b/u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c
index 13c8f47..32dc484 100644
--- a/u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c
+++ b/u-boot/drivers/video/drm/rockchip_dw_hdmi_qp.c
@@ -50,6 +50,7 @@
#define RK3588_GRF_VO1_CON3 0x000c
#define RK3588_COLOR_FORMAT_MASK 0xf
+#define RK3588_YUV422 0x1
#define RK3588_YUV444 0x2
#define RK3588_YUV420 0x3
#define RK3588_COMPRESSED_DATA 0xb
@@ -348,6 +349,9 @@
case MEDIA_BUS_FMT_UYVY8_1X16:
case MEDIA_BUS_FMT_UYVY10_1X20:
case MEDIA_BUS_FMT_UYVY12_1X24:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ case MEDIA_BUS_FMT_YUYV10_1X20:
+ case MEDIA_BUS_FMT_YUYV12_1X24:
return true;
default:
@@ -375,18 +379,21 @@
case MEDIA_BUS_FMT_RGB888_1X24:
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_UYVY8_1X16:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
return 8;
case MEDIA_BUS_FMT_RGB101010_1X30:
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYVY10_1X20:
+ case MEDIA_BUS_FMT_YUYV10_1X20:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
return 10;
case MEDIA_BUS_FMT_RGB121212_1X36:
case MEDIA_BUS_FMT_YUV12_1X36:
case MEDIA_BUS_FMT_UYVY12_1X24:
+ case MEDIA_BUS_FMT_YUYV12_1X24:
case MEDIA_BUS_FMT_UYYVYY12_0_5X36:
return 12;
@@ -834,12 +841,8 @@
if (screen_info && screen_info->depth == 10)
color_depth = screen_info->depth;
- if (mode->clock >= 600000) {
+ if (mode->clock >= 600000)
color_format = DRM_HDMI_OUTPUT_YCBCR420;
- } else if (mode->clock >= 340000) {
- if (drm_mode_is_420(info, mode))
- color_format = DRM_HDMI_OUTPUT_YCBCR420;
- }
if (color_format == DRM_HDMI_OUTPUT_YCBCR422 || color_depth == 8)
tmdsclock = pixclock;
@@ -876,7 +879,7 @@
case DRM_HDMI_OUTPUT_YCBCR444:
return MEDIA_BUS_FMT_YUV10_1X30;
case DRM_HDMI_OUTPUT_YCBCR422:
- return MEDIA_BUS_FMT_UYVY10_1X20;
+ return MEDIA_BUS_FMT_YUYV10_1X20;
case DRM_HDMI_OUTPUT_YCBCR420:
return MEDIA_BUS_FMT_UYYVYY10_0_5X30;
default:
@@ -887,7 +890,7 @@
case DRM_HDMI_OUTPUT_YCBCR444:
return MEDIA_BUS_FMT_YUV8_1X24;
case DRM_HDMI_OUTPUT_YCBCR422:
- return MEDIA_BUS_FMT_UYVY8_1X16;
+ return MEDIA_BUS_FMT_YUYV8_1X16;
case DRM_HDMI_OUTPUT_YCBCR420:
return MEDIA_BUS_FMT_UYYVYY8_0_5X24;
default:
@@ -1081,7 +1084,7 @@
if (hdmi_bus_fmt_is_yuv420(*bus_format))
hdmi->bus_width /= 2;
- if (color_depth == 10)
+ if (color_depth == 10 && !hdmi_bus_fmt_is_yuv422(*bus_format))
hdmi->bus_width |= COLOR_DEPTH_10BIT;
}
@@ -1154,6 +1157,10 @@
case MEDIA_BUS_FMT_YUV10_1X30:
val = HIWORD_UPDATE(RK3588_YUV444, RK3588_COLOR_FORMAT_MASK);
break;
+ case MEDIA_BUS_FMT_YUYV10_1X20:
+ case MEDIA_BUS_FMT_YUYV8_1X16:
+ val = HIWORD_UPDATE(RK3588_YUV422, RK3588_COLOR_FORMAT_MASK);
+ break;
default:
dev_err(hdmi->dev, "can't set correct color format\n");
return;
@@ -1162,7 +1169,7 @@
if (hdmi->link_cfg.dsc_mode)
val = HIWORD_UPDATE(RK3588_COMPRESSED_DATA, RK3588_COLOR_FORMAT_MASK);
- if (depth == 8)
+ if (depth == 8 || bus_format == MEDIA_BUS_FMT_YUYV10_1X20)
val |= HIWORD_UPDATE(RK3588_8BPC, RK3588_COLOR_DEPTH_MASK);
else
val |= HIWORD_UPDATE(RK3588_10BPC, RK3588_COLOR_DEPTH_MASK);
diff --git a/u-boot/drivers/video/drm/rockchip_lvds.c b/u-boot/drivers/video/drm/rockchip_lvds.c
index ffacd49..d7acbe4 100644
--- a/u-boot/drivers/video/drm/rockchip_lvds.c
+++ b/u-boot/drivers/video/drm/rockchip_lvds.c
@@ -59,6 +59,9 @@
#define RK3368_LVDS_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
#define RK3368_LVDS_P2S_EN(x) HIWORD_UPDATE(x, 6, 6)
+#define RK3562_GRF_VO_CON0 0x05d0
+#define RK3562_GRF_VO_CON1 0x05d4
+
#define RK3568_GRF_VO_CON0 0x0360
#define RK3568_LVDS1_SELECT(x) HIWORD_UPDATE(x, 13, 12)
#define RK3568_LVDS1_MSBSEL(x) HIWORD_UPDATE(x, 11, 11)
@@ -307,6 +310,25 @@
.disable = rk3368_lvds_disable,
};
+static void rk3562_lvds_enable(struct rockchip_lvds *lvds, int pipe)
+{
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON1,
+ RK3568_LVDS0_MODE_EN(1) | RK3568_LVDS0_P2S_EN(1) |
+ RK3568_LVDS0_DCLK_INV_SEL(1));
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON0,
+ RK3568_LVDS0_SELECT(lvds->format) | RK3568_LVDS0_MSBSEL(1));
+}
+
+static void rk3562_lvds_disable(struct rockchip_lvds *lvds)
+{
+ regmap_write(lvds->grf, RK3562_GRF_VO_CON1, RK3568_LVDS0_MODE_EN(0));
+}
+
+static const struct rockchip_lvds_funcs rk3562_lvds_funcs = {
+ .enable = rk3562_lvds_enable,
+ .disable = rk3562_lvds_disable,
+};
+
static void rk3568_lvds_enable(struct rockchip_lvds *lvds, int pipe)
{
regmap_write(lvds->grf, RK3568_GRF_VO_CON2,
@@ -344,6 +366,10 @@
.data = (ulong)&rk3368_lvds_funcs,
},
{
+ .compatible = "rockchip,rk3562-lvds",
+ .data = (ulong)&rk3562_lvds_funcs,
+ },
+ {
.compatible = "rockchip,rk3568-lvds",
.data = (ulong)&rk3568_lvds_funcs,
},
diff --git a/u-boot/drivers/video/drm/rockchip_panel.c b/u-boot/drivers/video/drm/rockchip_panel.c
index 570bc99..5203371 100755
--- a/u-boot/drivers/video/drm/rockchip_panel.c
+++ b/u-boot/drivers/video/drm/rockchip_panel.c
@@ -12,6 +12,7 @@
#include <malloc.h>
#include <video.h>
#include <backlight.h>
+#include <spi.h>
#include <asm/gpio.h>
#include <dm/device.h>
#include <dm/read.h>
@@ -65,6 +66,7 @@
bool enabled;
struct udevice *power_supply;
struct udevice *backlight;
+ struct spi_slave *spi_slave;
struct gpio_desc enable_gpio;
struct gpio_desc reset_gpio;
struct gpio_desc edp_bl_on;
@@ -197,24 +199,48 @@
{
struct rockchip_panel_priv *priv = dev_get_priv(panel->dev);
int i;
+ int ret;
if (!cmds)
return -EINVAL;
+ if (priv->spi_slave) {
+ ret = spi_claim_bus(priv->spi_slave);
+ if (ret) {
+ printf("%s: Failed to claim spi bus: %d\n", __func__, ret);
+ return -EINVAL;
+ }
+ }
+
for (i = 0; i < cmds->cmd_cnt; i++) {
struct rockchip_cmd_desc *desc = &cmds->cmds[i];
int value = 0;
+ u16 mask = 0;
+ u16 data = 0;
- if (desc->header.payload_length == 2)
- value = (desc->payload[0] << 8) | desc->payload[1];
- else
- value = desc->payload[0];
- rockchip_panel_write_spi_cmds(priv,
- desc->header.data_type, value);
+ if (priv->spi_slave) {
+ mask = desc->header.data_type ? 0x100 : 0;
+ data = (mask | desc->payload[0]) << 7;;
+ data = ((data & 0xff) << 8) | (data >> 8);
+ value = mask | desc->payload[0];
+ ret = spi_xfer(priv->spi_slave, 9, &data, NULL, SPI_XFER_ONCE);
+ if (ret)
+ printf("%s: Failed to xfer spi cmd 0x%x: %d\n",
+ __func__, desc->payload[0], ret);
+ } else {
+ if (desc->header.payload_length == 2)
+ value = (desc->payload[0] << 8) | desc->payload[1];
+ else
+ value = desc->payload[0];
+ rockchip_panel_write_spi_cmds(priv, desc->header.data_type, value);
+ }
if (desc->header.delay_ms)
mdelay(desc->header.delay_ms);
}
+
+ if (priv->spi_slave)
+ spi_release_bus(priv->spi_slave);
return 0;
}
@@ -336,21 +362,24 @@
if (dm_gpio_is_valid(&priv->edp_bl_en))
dm_gpio_set_value(&priv->edp_bl_en, 1);
-
+
if (dm_gpio_is_valid(&priv->enable_gpio))
dm_gpio_set_value(&priv->enable_gpio, 1);
-
+
if (plat->delay.prepare)
mdelay(plat->delay.prepare);
-
+
if (dm_gpio_is_valid(&priv->reset_gpio))
dm_gpio_set_value(&priv->reset_gpio, 1);
+
+ if (plat->delay.reset)
+ mdelay(plat->delay.reset);
mdelay(50);
if (dm_gpio_is_valid(&priv->reset_gpio))
dm_gpio_set_value(&priv->reset_gpio, 0);
-
- mdelay(200);
+ mdelay(200);
+
if (plat->delay.init)
mdelay(plat->delay.init);
@@ -556,7 +585,7 @@
printf("%s: Cannot get reset GPIO: %d\n", __func__, ret);
return ret;
}
-
+
ret = gpio_request_by_name(dev, "lvds-gpio0", 0,
&priv->lvds_gpio0, GPIOD_IS_OUT);
if (ret && ret != -ENOENT) {
@@ -584,7 +613,7 @@
printf("%s: Cannot get lvds-gpio3: %d\n", __func__, ret);
return ret;
}
-
+
ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev,
"backlight", &priv->backlight);
if (ret && ret != -ENOENT) {
@@ -606,31 +635,47 @@
priv->cmd_type = get_panel_cmd_type(cmd_type);
if (priv->cmd_type == CMD_TYPE_SPI) {
- ret = gpio_request_by_name(dev, "spi-sdi-gpios", 0,
- &priv->spi_sdi_gpio, GPIOD_IS_OUT);
- if (ret && ret != -ENOENT) {
- printf("%s: Cannot get spi sdi GPIO: %d\n",
- __func__, ret);
- return ret;
+ ofnode parent = ofnode_get_parent(dev->node);
+
+ if (ofnode_valid(parent)) {
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct udevice *spi = dev_get_parent(dev);
+
+ if (spi->seq < 0) {
+ printf("%s: Failed to get spi bus num\n", __func__);
+ return -EINVAL;
+ }
+
+ priv->spi_slave = spi_setup_slave(spi->seq, plat->cs, plat->max_hz,
+ plat->mode);
+ if (!priv->spi_slave) {
+ printf("%s: Failed to setup spi slave: %d\n", __func__, ret);
+ return -EINVAL;
+ }
+ } else {
+ ret = gpio_request_by_name(dev, "spi-sdi-gpios", 0,
+ &priv->spi_sdi_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get spi sdi GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+ ret = gpio_request_by_name(dev, "spi-scl-gpios", 0,
+ &priv->spi_scl_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get spi scl GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+ ret = gpio_request_by_name(dev, "spi-cs-gpios", 0,
+ &priv->spi_cs_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get spi cs GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+ dm_gpio_set_value(&priv->spi_sdi_gpio, 1);
+ dm_gpio_set_value(&priv->spi_scl_gpio, 1);
+ dm_gpio_set_value(&priv->spi_cs_gpio, 1);
+ dm_gpio_set_value(&priv->reset_gpio, 0);
}
- ret = gpio_request_by_name(dev, "spi-scl-gpios", 0,
- &priv->spi_scl_gpio, GPIOD_IS_OUT);
- if (ret && ret != -ENOENT) {
- printf("%s: Cannot get spi scl GPIO: %d\n",
- __func__, ret);
- return ret;
- }
- ret = gpio_request_by_name(dev, "spi-cs-gpios", 0,
- &priv->spi_cs_gpio, GPIOD_IS_OUT);
- if (ret && ret != -ENOENT) {
- printf("%s: Cannot get spi cs GPIO: %d\n",
- __func__, ret);
- return ret;
- }
- dm_gpio_set_value(&priv->spi_sdi_gpio, 1);
- dm_gpio_set_value(&priv->spi_scl_gpio, 1);
- dm_gpio_set_value(&priv->spi_cs_gpio, 1);
- dm_gpio_set_value(&priv->reset_gpio, 0);
}
panel = calloc(1, sizeof(*panel));
@@ -649,6 +694,7 @@
static const struct udevice_id rockchip_panel_ids[] = {
{ .compatible = "simple-panel", },
{ .compatible = "simple-panel-dsi", },
+ { .compatible = "simple-panel-spi", },
{}
};
diff --git a/u-boot/drivers/video/drm/rockchip_post_csc.c b/u-boot/drivers/video/drm/rockchip_post_csc.c
new file mode 100755
index 0000000..2409103
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_post_csc.c
@@ -0,0 +1,1587 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ * Author: Zhang yubing <yubing.zhang@rock-chips.com>
+ */
+
+#include <stdio.h>
+#include <linux/errno.h>
+
+#include "rockchip_post_csc.h"
+
+#define PQ_CSC_HUE_TABLE_NUM 256
+#define PQ_CSC_MODE_COEF_COMMENT_LEN 32
+#define PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH 10
+#define PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM (1 << PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH)
+
+#define PQ_CALC_ENHANCE_BIT 6
+/* csc convert coef fixed-point num bit width */
+#define PQ_CSC_PARAM_FIX_BIT_WIDTH 10
+/* csc convert coef half fixed-point num bit width */
+#define PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH (PQ_CSC_PARAM_FIX_BIT_WIDTH - 1)
+/* csc convert coef fixed-point num */
+#define PQ_CSC_PARAM_FIX_NUM (1 << PQ_CSC_PARAM_FIX_BIT_WIDTH)
+#define PQ_CSC_PARAM_HALF_FIX_NUM (1 << PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH)
+/* csc input param bit width */
+#define PQ_CSC_IN_PARAM_NORM_BIT_WIDTH 9
+/* csc input param normalization coef */
+#define PQ_CSC_IN_PARAM_NORM_COEF (1 << PQ_CSC_IN_PARAM_NORM_BIT_WIDTH)
+
+/* csc hue table range [0,255] */
+#define PQ_CSC_HUE_TABLE_DIV_COEF 2
+/* csc brightness offset */
+#define PQ_CSC_BRIGHTNESS_OFFSET 256
+
+/* dc coef base bit width */
+#define PQ_CSC_DC_COEF_BASE_BIT_WIDTH 10
+/* input dc coef offset for 10bit data */
+#define PQ_CSC_DC_IN_OFFSET 64
+/* input and output dc coef offset for 10bit data u,v */
+#define PQ_CSC_DC_IN_OUT_DEFAULT 512
+/* r,g,b color temp div coef, range [-128,128] for 10bit data */
+#define PQ_CSC_TEMP_OFFSET_DIV_COEF 2
+
+#define MAX(a, b) ((a) > (b) ? (a) : (b))
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+#define CLIP(x, min_v, max_v) MIN(MAX(x, min_v), max_v)
+
+enum rk_pq_csc_mode {
+ RK_PQ_CSC_YUV2RGB_601 = 0, /* YCbCr_601 LIMIT-> RGB FULL */
+ RK_PQ_CSC_YUV2RGB_709, /* YCbCr_709 LIMIT-> RGB FULL */
+ RK_PQ_CSC_RGB2YUV_601, /* RGB FULL->YCbCr_601 LIMIT */
+ RK_PQ_CSC_RGB2YUV_709, /* RGB FULL->YCbCr_709 LIMIT */
+ RK_PQ_CSC_YUV2YUV_709_601, /* YCbCr_709 LIMIT->YCbCr_601 LIMIT */
+ RK_PQ_CSC_YUV2YUV_601_709, /* YCbCr_601 LIMIT->YCbCr_709 LIMIT */
+ RK_PQ_CSC_YUV2YUV, /* YCbCr LIMIT->YCbCr LIMIT */
+ RK_PQ_CSC_YUV2RGB_601_FULL, /* YCbCr_601 FULL-> RGB FULL */
+ RK_PQ_CSC_YUV2RGB_709_FULL, /* YCbCr_709 FULL-> RGB FULL */
+ RK_PQ_CSC_RGB2YUV_601_FULL, /* RGB FULL->YCbCr_601 FULL */
+ RK_PQ_CSC_RGB2YUV_709_FULL, /* RGB FULL->YCbCr_709 FULL */
+ RK_PQ_CSC_YUV2YUV_709_601_FULL, /* YCbCr_709 FULL->YCbCr_601 FULL */
+ RK_PQ_CSC_YUV2YUV_601_709_FULL, /* YCbCr_601 FULL->YCbCr_709 FULL */
+ RK_PQ_CSC_YUV2YUV_FULL, /* YCbCr FULL->YCbCr FULL */
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, /* YCbCr LIMIT->YCbCr FULL */
+ RK_PQ_CSC_YUV2YUV_601_709_LIMIT2FULL, /* YCbCr 601 LIMIT->YCbCr 709 FULL */
+ RK_PQ_CSC_YUV2YUV_709_601_LIMIT2FULL, /* YCbCr 709 LIMIT->YCbCr 601 FULL */
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, /* YCbCr FULL->YCbCr LIMIT */
+ RK_PQ_CSC_YUV2YUV_601_709_FULL2LIMIT, /* YCbCr 601 FULL->YCbCr 709 LIMIT */
+ RK_PQ_CSC_YUV2YUV_709_601_FULL2LIMIT, /* YCbCr 709 FULL->YCbCr 601 LIMIT */
+ RK_PQ_CSC_YUV2RGBL_601, /* YCbCr_601 LIMIT-> RGB LIMIT */
+ RK_PQ_CSC_YUV2RGBL_709, /* YCbCr_709 LIMIT-> RGB LIMIT */
+ RK_PQ_CSC_RGBL2YUV_601, /* RGB LIMIT->YCbCr_601 LIMIT */
+ RK_PQ_CSC_RGBL2YUV_709, /* RGB LIMIT->YCbCr_709 LIMIT */
+ RK_PQ_CSC_YUV2RGBL_601_FULL, /* YCbCr_601 FULL-> RGB LIMIT */
+ RK_PQ_CSC_YUV2RGBL_709_FULL, /* YCbCr_709 FULL-> RGB LIMIT */
+ RK_PQ_CSC_RGBL2YUV_601_FULL, /* RGB LIMIT->YCbCr_601 FULL */
+ RK_PQ_CSC_RGBL2YUV_709_FULL, /* RGB LIMIT->YCbCr_709 FULL */
+ RK_PQ_CSC_RGB2RGBL, /* RGB FULL->RGB LIMIT */
+ RK_PQ_CSC_RGBL2RGB, /* RGB LIMIT->RGB FULL */
+ RK_PQ_CSC_RGBL2RGBL, /* RGB LIMIT->RGB LIMIT */
+ RK_PQ_CSC_RGB2RGB, /* RGB FULL->RGB FULL */
+ RK_PQ_CSC_YUV2RGB_2020, /* YUV 2020 FULL->RGB 2020 FULL */
+ RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, /* BT2020RGBLIMIT -> BT2020YUVFULL */
+ RK_PQ_CSC_RGB2YUV2020_LIMIT, /* BT2020RGBLIMIT -> BT2020YUVLIMIT */
+ RK_PQ_CSC_RGB2YUV2020_FULL2LIMIT, /* BT2020RGBFULL -> BT2020YUVLIMIT */
+ RK_PQ_CSC_RGB2YUV2020_FULL, /* BT2020RGBFULL -> BT2020YUVFULL */
+};
+
+enum color_space_type {
+ OPTM_CS_E_UNKNOWN = 0,
+ OPTM_CS_E_ITU_R_BT_709 = 1,
+ OPTM_CS_E_FCC = 4,
+ OPTM_CS_E_ITU_R_BT_470_2_BG = 5,
+ OPTM_CS_E_SMPTE_170_M = 6,
+ OPTM_CS_E_SMPTE_240_M = 7,
+ OPTM_CS_E_XV_YCC_709 = OPTM_CS_E_ITU_R_BT_709,
+ OPTM_CS_E_XV_YCC_601 = 8,
+ OPTM_CS_E_RGB = 9,
+ OPTM_CS_E_XV_YCC_2020 = 10,
+ OPTM_CS_E_RGB_2020 = 11,
+};
+
+enum vop_csc_format {
+ CSC_BT601L,
+ CSC_BT709L,
+ CSC_BT601F,
+ CSC_BT2020,
+ CSC_BT709L_13BIT,
+ CSC_BT709F_13BIT,
+ CSC_BT2020L_13BIT,
+ CSC_BT2020F_13BIT,
+};
+
+struct rk_pq_csc_coef {
+ s32 csc_coef00;
+ s32 csc_coef01;
+ s32 csc_coef02;
+ s32 csc_coef10;
+ s32 csc_coef11;
+ s32 csc_coef12;
+ s32 csc_coef20;
+ s32 csc_coef21;
+ s32 csc_coef22;
+};
+
+struct rk_pq_csc_ventor {
+ s32 csc_offset0;
+ s32 csc_offset1;
+ s32 csc_offset2;
+};
+
+struct rk_pq_csc_dc_coef {
+ s32 csc_in_dc0;
+ s32 csc_in_dc1;
+ s32 csc_in_dc2;
+ s32 csc_out_dc0;
+ s32 csc_out_dc1;
+ s32 csc_out_dc2;
+};
+
+/* color space param */
+struct rk_csc_colorspace_info {
+ enum color_space_type input_color_space;
+ enum color_space_type output_color_space;
+ bool in_full_range;
+ bool out_full_range;
+};
+
+struct rk_csc_mode_coef {
+ enum rk_pq_csc_mode csc_mode;
+ char c_csc_comment[PQ_CSC_MODE_COEF_COMMENT_LEN];
+ const struct rk_pq_csc_coef *pst_csc_coef;
+ const struct rk_pq_csc_dc_coef *pst_csc_dc_coef;
+ struct rk_csc_colorspace_info st_csc_color_info;
+};
+
+/*
+ *CSC matrix
+ */
+/* xv_ycc BT.601 limit(i.e. SD) -> RGB full */
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full = {
+ 1196, 0, 1639,
+ 1196, -402, -835,
+ 1196, 2072, 0
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full = {
+ -64, -512, -512,
+ 0, 0, 0
+};
+
+/* BT.709 limit(i.e. HD) -> RGB full */
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_limit_to_rgb_full = {
+ 1196, 0, 1841,
+ 1196, -219, -547,
+ 1196, 2169, 0
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_full = {
+ -64, -512, -512,
+ 0, 0, 0
+};
+
+/* RGB full-> YUV601 (i.e. SD) limit */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_xv_yccsdy_cb_cr = {
+ 262, 515, 100,
+ -151, -297, 448,
+ 448, -376, -73
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr = {
+ 0, 0, 0,
+ 64, 512, 512
+};
+
+/* RGB full-> YUV709 (i.e. SD) limit */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_hdy_cb_cr = {
+ 186, 627, 63,
+ -103, -346, 448,
+ 448, -407, -41
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_hdy_cb_cr = {
+ 0, 0, 0,
+ 64, 512, 512
+};
+
+/* BT.709 (i.e. HD) -> to xv_ycc BT.601 (i.e. SD) */
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr = {
+ 1024, 104, 201,
+ 0, 1014, -113,
+ 0, -74, 1007
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr = {
+ -64, -512, -512,
+ 64, 512, 512
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full = {
+ 0, -512, -512,
+ 0, 512, 512
+};
+
+/* xv_ycc BT.601 (i.e. SD) -> to BT.709 (i.e. HD) */
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr = {
+ 1024, -121, -218,
+ 0, 1043, 117,
+ 0, 77, 1050
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr = {
+ -64, -512, -512,
+ 64, 512, 512
+};
+
+/* xv_ycc BT.601 full(i.e. SD) -> RGB full */
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_rgb_full = {
+ 1024, 0, 1436,
+ 1024, -352, -731,
+ 1024, 1815, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_full = {
+ 0, -512, -512,
+ 0, 0, 0
+};
+
+/* BT.709 full(i.e. HD) -> RGB full */
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_rgb_full = {
+ 1024, 0, 1613,
+ 1024, -192, -479,
+ 1024, 1900, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_rgb_full = {
+ 0, -512, -512,
+ 0, 0, 0
+};
+
+/* RGB full-> YUV601 full(i.e. SD) */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_xv_yccsdy_cb_cr_full = {
+ 306, 601, 117,
+ -173, -339, 512,
+ 512, -429, -83
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr_full = {
+ 0, 0, 0,
+ 0, 512, 512
+};
+
+/* RGB full-> YUV709 full (i.e. SD) */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_to_hdy_cb_cr_full = {
+ 218, 732, 74,
+ -117, -395, 512,
+ 512, -465, -47
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_to_hdy_cb_cr_full = {
+ 0, 0, 0,
+ 0, 512, 512
+};
+
+/* limit -> full */
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full = {
+ 1196, 0, 0,
+ 0, 1169, 0,
+ 0, 0, 1169
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full = {
+ -64, -512, -512,
+ 0, 512, 512
+};
+
+/* 601 limit -> 709 full */
+static const struct rk_pq_csc_coef rk_csc_table_identity_601_limit_to_709_full = {
+ 1196, -138, -249,
+ 0, 1191, 134,
+ 0, 88, 1199
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_601_limit_to_709_full = {
+ -64, -512, -512,
+ 0, 512, 512
+};
+
+/* 709 limit -> 601 full */
+static const struct rk_pq_csc_coef rk_csc_table_identity_709_limit_to_601_full = {
+ 1196, 119, 229,
+ 0, 1157, -129,
+ 0, -85, 1150
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_709_limit_to_601_full = {
+ -64, -512, -512,
+ 0, 512, 512
+};
+
+/* full -> limit */
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit = {
+ 877, 0, 0,
+ 0, 897, 0,
+ 0, 0, 897
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit = {
+ 0, -512, -512,
+ 64, 512, 512
+};
+
+/* 601 full -> 709 limit */
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit = {
+ 877, -106, -191,
+ 0, 914, 103,
+ 0, 67, 920
+};
+static const struct rk_pq_csc_dc_coef
+rk_dc_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit = {
+ 0, -512, -512,
+ 64, 512, 512
+};
+
+/* 709 full -> 601 limit */
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit = {
+ 877, 91, 176,
+ 0, 888, -99,
+ 0, -65, 882
+};
+static const struct rk_pq_csc_dc_coef
+rk_dc_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit = {
+ 0, -512, -512,
+ 64, 512, 512
+};
+
+/* xv_ycc BT.601 limit(i.e. SD) -> RGB limit */
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit = {
+ 1024, 0, 1404,
+ 1024, -344, -715,
+ 1024, 1774, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit = {
+ -64, -512, -512,
+ 64, 64, 64
+};
+
+/* BT.709 limit(i.e. HD) -> RGB limit */
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_limit_to_rgb_limit = {
+ 1024, 0, 1577,
+ 1024, -188, -469,
+ 1024, 1858, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_limit = {
+ -64, -512, -512,
+ 64, 64, 64
+};
+
+/* RGB limit-> YUV601 (i.e. SD) limit */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr = {
+ 306, 601, 117,
+ -177, -347, 524,
+ 524, -439, -85
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr = {
+ -64, -64, -64,
+ 64, 512, 512
+};
+
+/* RGB limit -> YUV709 (i.e. SD) limit */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_hdy_cb_cr = {
+ 218, 732, 74,
+ -120, -404, 524,
+ 524, -476, -48
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_hdy_cb_cr = {
+ -64, -64, -64,
+ 64, 512, 512
+};
+
+/* xv_ycc BT.601 full(i.e. SD) -> RGB limit */
+static const struct rk_pq_csc_coef rk_csc_table_xv_yccsdy_cb_cr_to_rgb_limit = {
+ 877, 0, 1229,
+ 877, -302, -626,
+ 877, 1554, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_limit = {
+ 0, -512, -512,
+ 64, 64, 64
+};
+
+/* BT.709 full(i.e. HD) -> RGB limit */
+static const struct rk_pq_csc_coef rk_csc_table_hdy_cb_cr_to_rgb_limit = {
+ 877, 0, 1381,
+ 877, -164, -410,
+ 877, 1627, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_hdy_cb_cr_to_rgb_limit = {
+ 0, -512, -512,
+ 64, 64, 64
+};
+
+/* RGB limit-> YUV601 full(i.e. SD) */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full = {
+ 358, 702, 136,
+ -202, -396, 598,
+ 598, -501, -97
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full = {
+ -64, -64, -64,
+ 0, 512, 512
+};
+
+/* RGB limit-> YUV709 full (i.e. SD) */
+static const struct rk_pq_csc_coef rk_csc_table_rgb_limit_to_hdy_cb_cr_full = {
+ 254, 855, 86,
+ -137, -461, 598,
+ 598, -543, -55
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_rgb_limit_to_hdy_cb_cr_full = {
+ -64, -64, -64,
+ 0, 512, 512
+};
+
+/* RGB full -> RGB limit */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_to_rgb_limit = {
+ 877, 0, 0,
+ 0, 877, 0,
+ 0, 0, 877
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb_limit = {
+ 0, 0, 0,
+ 64, 64, 64
+};
+
+/* RGB limit -> RGB full */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_rgb = {
+ 1196, 0, 0,
+ 0, 1196, 0,
+ 0, 0, 1196
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_rgb = {
+ -64, -64, -64,
+ 0, 0, 0
+};
+
+/* RGB limit/full -> RGB limit/full */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_to_rgb = {
+ 1024, 0, 0,
+ 0, 1024, 0,
+ 0, 0, 1024
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb1 = {
+ -64, -64, -64,
+ 64, 64, 64
+};
+
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_to_rgb2 = {
+ 0, 0, 0,
+ 0, 0, 0
+};
+
+static const struct rk_pq_csc_coef rk_csc_table_identity_yuv_to_rgb_2020 = {
+ 1024, 0, 1510,
+ 1024, -169, -585,
+ 1024, 1927, 0
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_yuv_to_rgb_2020 = {
+ 0, -512, -512,
+ 0, 0, 0
+};
+
+/* 2020 RGB LIMIT ->YUV LIMIT */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_yuv_limit_2020 = {
+ 269, 694, 61,
+ -146, -377, 524,
+ 524, -482, -42
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_yuv_limit_2020 = {
+ -64, -64, -64,
+ 64, 512, 512
+};
+
+/* 2020 RGB LIMIT ->YUV FULL */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_limit_to_yuv_full_2020 = {
+ 314, 811, 71,
+ -167, -431, 598,
+ 598, -550, -48
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_limit_to_yuv_full_2020 = {
+ -64, -64, -64,
+ 0, 512, 512
+};
+
+/* 2020 RGB FULL ->YUV LIMIT */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_full_to_yuv_limit_2020 = {
+ 230, 595, 52,
+ -125, -323, 448,
+ 448, -412, -36
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_full_to_yuv_limit_2020 = {
+ 0, 0, 0,
+ 64, 512, 512
+};
+
+/* 2020 RGB FULL ->YUV FULL */
+static const struct rk_pq_csc_coef rk_csc_table_identity_rgb_full_to_yuv_full_2020 = {
+ 269, 694, 61,
+ -143, -369, 512,
+ 512, -471, -41
+};
+static const struct rk_pq_csc_dc_coef rk_dc_csc_table_identity_rgb_full_to_yuv_full_2020 = {
+ 0, 0, 0,
+ 0, 512, 512
+};
+
+/* identity matrix */
+static const struct rk_pq_csc_coef rk_csc_table_identity_y_cb_cr_to_y_cb_cr = {
+ 1024, 0, 0,
+ 0, 1024, 0,
+ 0, 0, 1024
+};
+
+/* 10bit Hue Sin Look Up Table -> range[-30, 30] */
+static const s32 g_hue_sin_table[PQ_CSC_HUE_TABLE_NUM] = {
+ 512, 508, 505, 501, 497, 494, 490, 486,
+ 483, 479, 475, 472, 468, 464, 460, 457,
+ 453, 449, 445, 442, 438, 434, 430, 426,
+ 423, 419, 415, 411, 407, 403, 400, 396,
+ 392, 388, 384, 380, 376, 372, 369, 365,
+ 361, 357, 353, 349, 345, 341, 337, 333,
+ 329, 325, 321, 317, 313, 309, 305, 301,
+ 297, 293, 289, 285, 281, 277, 273, 269,
+ 265, 261, 257, 253, 249, 245, 241, 237,
+ 233, 228, 224, 220, 216, 212, 208, 204,
+ 200, 196, 192, 187, 183, 179, 175, 171,
+ 167, 163, 159, 154, 150, 146, 142, 138,
+ 134, 130, 125, 121, 117, 113, 109, 105,
+ 100, 96, 92, 88, 84, 80, 75, 71,
+ 67, 63, 59, 54, 50, 46, 42, 38,
+ 34, 29, 25, 21, 17, 13, 8, 4,
+ 0, -4, -8, -13, -17, -21, -25, -29,
+ -34, -38, -42, -46, -50, -54, -59, -63,
+ -67, -71, -75, -80, -84, -88, -92, -96,
+ -100, -105, -109, -113, -117, -121, -125, -130,
+ -134, -138, -142, -146, -150, -154, -159, -163,
+ -167, -171, -175, -179, -183, -187, -192, -196,
+ -200, -204, -208, -212, -216, -220, -224, -228,
+ -233, -237, -241, -245, -249, -253, -257, -261,
+ -265, -269, -273, -277, -281, -285, -289, -293,
+ -297, -301, -305, -309, -313, -317, -321, -325,
+ -329, -333, -337, -341, -345, -349, -353, -357,
+ -361, -365, -369, -372, -376, -380, -384, -388,
+ -392, -396, -400, -403, -407, -411, -415, -419,
+ -423, -426, -430, -434, -438, -442, -445, -449,
+ -453, -457, -460, -464, -468, -472, -475, -479,
+ -483, -486, -490, -494, -497, -501, -505, -508,
+};
+
+/* 10bit Hue Cos Look Up Table -> range[-30, 30] */
+static const s32 g_hue_cos_table[PQ_CSC_HUE_TABLE_NUM] = {
+ 887, 889, 891, 893, 895, 897, 899, 901,
+ 903, 905, 907, 909, 911, 913, 915, 917,
+ 919, 920, 922, 924, 926, 928, 929, 931,
+ 933, 935, 936, 938, 940, 941, 943, 945,
+ 946, 948, 949, 951, 953, 954, 956, 957,
+ 959, 960, 962, 963, 964, 966, 967, 969,
+ 970, 971, 973, 974, 975, 976, 978, 979,
+ 980, 981, 983, 984, 985, 986, 987, 988,
+ 989, 990, 992, 993, 994, 995, 996, 997,
+ 998, 998, 999, 1000, 1001, 1002, 1003, 1004,
+ 1005, 1005, 1006, 1007, 1008, 1008, 1009, 1010,
+ 1011, 1011, 1012, 1013, 1013, 1014, 1014, 1015,
+ 1015, 1016, 1016, 1017, 1017, 1018, 1018, 1019,
+ 1019, 1020, 1020, 1020, 1021, 1021, 1021, 1022,
+ 1022, 1022, 1022, 1023, 1023, 1023, 1023, 1023,
+ 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
+ 1024, 1024, 1024, 1024, 1024, 1024, 1024, 1024,
+ 1023, 1023, 1023, 1023, 1023, 1022, 1022, 1022,
+ 1022, 1021, 1021, 1021, 1020, 1020, 1020, 1019,
+ 1019, 1018, 1018, 1017, 1017, 1016, 1016, 1015,
+ 1015, 1014, 1014, 1013, 1013, 1012, 1011, 1011,
+ 1010, 1009, 1008, 1008, 1007, 1006, 1005, 1005,
+ 1004, 1003, 1002, 1001, 1000, 999, 998, 998,
+ 997, 996, 995, 994, 993, 992, 990, 989,
+ 988, 987, 986, 985, 984, 983, 981, 980,
+ 979, 978, 976, 975, 974, 973, 971, 970,
+ 969, 967, 966, 964, 963, 962, 960, 959,
+ 957, 956, 954, 953, 951, 949, 948, 946,
+ 945, 943, 941, 940, 938, 936, 935, 933,
+ 931, 929, 928, 926, 924, 922, 920, 919,
+ 917, 915, 913, 911, 909, 907, 905, 903,
+ 901, 899, 897, 895, 893, 891, 889, 887
+};
+
+/*
+ *CSC Param Struct
+ */
+static const struct rk_csc_mode_coef g_mode_csc_coef[] = {
+ {
+ RK_PQ_CSC_YUV2RGB_601, "YUV601 L->RGB F",
+ &rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGB_709, "YUV709 L->RGB F",
+ &rk_csc_table_hdy_cb_cr_limit_to_rgb_full,
+ &rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV_601, "RGB F->YUV601 L",
+ &rk_csc_table_rgb_to_xv_yccsdy_cb_cr,
+ &rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV_709, "RGB F->YUV709 L",
+ &rk_csc_table_rgb_to_hdy_cb_cr,
+ &rk_dc_csc_table_rgb_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_709_601, "YUV709 L->YUV601 L",
+ &rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_601_709, "YUV601 L->YUV709 L",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV, "YUV L->YUV L",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGB_601_FULL, "YUV601 F->RGB F",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_rgb_full,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGB_709_FULL, "YUV709 F->RGB F",
+ &rk_csc_table_hdy_cb_cr_to_rgb_full,
+ &rk_dc_csc_table_hdy_cb_cr_to_rgb_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV_601_FULL, "RGB F->YUV601 F",
+ &rk_csc_table_rgb_to_xv_yccsdy_cb_cr_full,
+ &rk_dc_csc_table_rgb_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV_709_FULL, "RGB F->YUV709 F",
+ &rk_csc_table_rgb_to_hdy_cb_cr_full,
+ &rk_dc_csc_table_rgb_to_hdy_cb_cr_full,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_709_601_FULL, "YUV709 F->YUV601 F",
+ &rk_csc_table_hdy_cb_cr_to_xv_yccsdy_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_601_709_FULL, "YUV601 F->YUV709 F",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV F->YUV F",
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV L->YUV F",
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_601_709_LIMIT2FULL, "YUV601 L->YUV709 F",
+ &rk_csc_table_identity_601_limit_to_709_full,
+ &rk_dc_csc_table_identity_601_limit_to_709_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_709_601_LIMIT2FULL, "YUV709 L->YUV601 F",
+ &rk_csc_table_identity_709_limit_to_601_full,
+ &rk_dc_csc_table_identity_709_limit_to_601_full,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV F->YUV L",
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_ITU_R_BT_709, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_601_709_FULL2LIMIT, "YUV601 F->YUV709 L",
+ &rk_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit,
+ &rk_dc_csc_table_identity_y_cb_cr_601_full_to_y_cb_cr_709_limit,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_ITU_R_BT_709, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_709_601_FULL2LIMIT, "YUV709 F->YUV601 L",
+ &rk_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit,
+ &rk_dc_csc_table_identity_y_cb_cr_709_full_to_y_cb_cr_601_limit,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_XV_YCC_601, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGBL_601, "YUV601 L->RGB L",
+ &rk_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_limit_to_rgb_limit,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGBL_709, "YUV709 L->RGB L",
+ &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit,
+ &rk_dc_csc_table_hdy_cb_cr_limit_to_rgb_limit,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2YUV_601, "RGB L->YUV601 L",
+ &rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr,
+ &rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2YUV_709, "RGB L->YUV709 L",
+ &rk_csc_table_rgb_limit_to_hdy_cb_cr,
+ &rk_dc_csc_table_rgb_limit_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGBL_601_FULL, "YUV601 F->RGB L",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_rgb_limit,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_rgb_limit,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_RGB, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGBL_709_FULL, "YUV709 F->RGB L",
+ &rk_csc_table_hdy_cb_cr_to_rgb_limit,
+ &rk_dc_csc_table_hdy_cb_cr_to_rgb_limit,
+ {
+ OPTM_CS_E_ITU_R_BT_709, OPTM_CS_E_RGB, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2YUV_601_FULL, "RGB L->YUV601 F",
+ &rk_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full,
+ &rk_dc_csc_table_rgb_limit_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_XV_YCC_601, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2YUV_709_FULL, "RGB L->YUV709 F",
+ &rk_csc_table_rgb_limit_to_hdy_cb_cr_full,
+ &rk_dc_csc_table_rgb_limit_to_hdy_cb_cr_full,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_ITU_R_BT_709, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2RGBL, "RGB F->RGB L",
+ &rk_csc_table_identity_rgb_to_rgb_limit,
+ &rk_dc_csc_table_identity_rgb_to_rgb_limit,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2RGB, "RGB L->RGB F",
+ &rk_csc_table_identity_rgb_limit_to_rgb,
+ &rk_dc_csc_table_identity_rgb_limit_to_rgb,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2RGBL, "RGB L->RGB L",
+ &rk_csc_table_identity_rgb_to_rgb,
+ &rk_dc_csc_table_identity_rgb_to_rgb1,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2RGB, "RGB F->RGB F",
+ &rk_csc_table_identity_rgb_to_rgb,
+ &rk_dc_csc_table_identity_rgb_to_rgb2,
+ {
+ OPTM_CS_E_RGB, OPTM_CS_E_RGB, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2RGB_2020, "YUV2020 F->RGB2020 F",
+ &rk_csc_table_identity_yuv_to_rgb_2020,
+ &rk_dc_csc_table_identity_yuv_to_rgb_2020,
+ {
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_RGB_2020, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV2020_LIMIT2FULL, "RGB2020 L->YUV2020 F",
+ &rk_csc_table_identity_rgb_limit_to_yuv_full_2020,
+ &rk_dc_csc_table_identity_rgb_limit_to_yuv_full_2020,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV2020_LIMIT, "RGB2020 L->YUV2020 L",
+ &rk_csc_table_identity_rgb_limit_to_yuv_limit_2020,
+ &rk_dc_csc_table_identity_rgb_limit_to_yuv_limit_2020,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV2020_FULL2LIMIT, "RGB2020 F->YUV2020 L",
+ &rk_csc_table_identity_rgb_full_to_yuv_limit_2020,
+ &rk_dc_csc_table_identity_rgb_full_to_yuv_limit_2020,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2YUV2020_FULL, "RGB2020 F->YUV2020 F",
+ &rk_csc_table_identity_rgb_full_to_yuv_full_2020,
+ &rk_dc_csc_table_identity_rgb_full_to_yuv_full_2020,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_XV_YCC_2020, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV, "YUV 601 L->YUV 601 L",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV 601 F->YUV 601 F",
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV 601 L->YUV 601 F",
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV 601 F->YUV 601 L",
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ {
+ OPTM_CS_E_XV_YCC_601, OPTM_CS_E_XV_YCC_601, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV, "YUV 2020 L->YUV 2020 L",
+ &rk_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ &rk_dc_csc_table_xv_yccsdy_cb_cr_to_hdy_cb_cr,
+ {
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL, "YUV 2020 F->YUV 2020 F",
+ &rk_csc_table_identity_y_cb_cr_to_y_cb_cr,
+ &rk_dc_csc_table_hdy_cb_cr_full_to_xv_yccsdy_cb_cr_full,
+ {
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, true, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_LIMIT2FULL, "YUV 2020 L->YUV 2020 F",
+ &rk_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ &rk_dc_csc_table_identity_y_cb_cr_limit_to_y_cb_cr_full,
+ {
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_YUV2YUV_FULL2LIMIT, "YUV 2020 F->YUV 2020 L",
+ &rk_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ &rk_dc_csc_table_identity_y_cb_cr_full_to_y_cb_cr_limit,
+ {
+ OPTM_CS_E_XV_YCC_2020, OPTM_CS_E_XV_YCC_2020, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2RGBL, "RGB 2020 F->RGB 2020 L",
+ &rk_csc_table_identity_rgb_to_rgb_limit,
+ &rk_dc_csc_table_identity_rgb_to_rgb_limit,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, true, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2RGB, "RGB 2020 L->RGB 2020 F",
+ &rk_csc_table_identity_rgb_limit_to_rgb,
+ &rk_dc_csc_table_identity_rgb_limit_to_rgb,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, false, true
+ }
+ },
+ {
+ RK_PQ_CSC_RGBL2RGBL, "RGB 2020 L->RGB 2020 L",
+ &rk_csc_table_identity_rgb_to_rgb,
+ &rk_dc_csc_table_identity_rgb_to_rgb1,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, false, false
+ }
+ },
+ {
+ RK_PQ_CSC_RGB2RGB, "RGB 2020 F->RGB 2020 F",
+ &rk_csc_table_identity_rgb_to_rgb,
+ &rk_dc_csc_table_identity_rgb_to_rgb2,
+ {
+ OPTM_CS_E_RGB_2020, OPTM_CS_E_RGB_2020, true, true
+ }
+ },
+};
+
+struct csc_mapping {
+ enum vop_csc_format csc_format;
+ enum color_space_type rgb_color_space;
+ enum color_space_type yuv_color_space;
+ bool rgb_full_range;
+ bool yuv_full_range;
+};
+
+static const struct csc_mapping csc_mapping_table[] = {
+ {
+ CSC_BT601L,
+ OPTM_CS_E_RGB,
+ OPTM_CS_E_XV_YCC_601,
+ true,
+ false,
+ },
+ {
+ CSC_BT709L,
+ OPTM_CS_E_RGB,
+ OPTM_CS_E_XV_YCC_709,
+ true,
+ false,
+ },
+ {
+ CSC_BT601F,
+ OPTM_CS_E_RGB,
+ OPTM_CS_E_XV_YCC_601,
+ true,
+ true,
+ },
+ {
+ CSC_BT2020,
+ OPTM_CS_E_RGB_2020,
+ OPTM_CS_E_XV_YCC_2020,
+ true,
+ true,
+ },
+ {
+ CSC_BT709L_13BIT,
+ OPTM_CS_E_RGB,
+ OPTM_CS_E_XV_YCC_709,
+ true,
+ false,
+ },
+ {
+ CSC_BT709F_13BIT,
+ OPTM_CS_E_RGB,
+ OPTM_CS_E_XV_YCC_709,
+ true,
+ true,
+ },
+ {
+ CSC_BT2020L_13BIT,
+ OPTM_CS_E_RGB_2020,
+ OPTM_CS_E_XV_YCC_2020,
+ true,
+ false,
+ },
+ {
+ CSC_BT2020F_13BIT,
+ OPTM_CS_E_RGB_2020,
+ OPTM_CS_E_XV_YCC_2020,
+ true,
+ true,
+ },
+};
+
+static const struct rk_pq_csc_coef r2y_for_y2y = {
+ 306, 601, 117,
+ -151, -296, 446,
+ 630, -527, -102,
+};
+
+static const struct rk_pq_csc_coef y2r_for_y2y = {
+ 1024, -0, 1167,
+ 1024, -404, -594,
+ 1024, 2081, -1,
+};
+
+static const struct rk_pq_csc_coef rgb_input_swap_matrix = {
+ 0, 0, 1,
+ 1, 0, 0,
+ 0, 1, 0,
+};
+
+static const struct rk_pq_csc_coef yuv_output_swap_matrix = {
+ 0, 0, 1,
+ 1, 0, 0,
+ 0, 1, 0,
+};
+
+static int csc_get_mode_index(int post_csc_mode, bool is_input_yuv, bool is_output_yuv)
+{
+ const struct rk_csc_colorspace_info *colorspace_info;
+ enum color_space_type input_color_space;
+ enum color_space_type output_color_space;
+ bool is_input_full_range;
+ bool is_output_full_range;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(csc_mapping_table); i++) {
+ if (post_csc_mode == csc_mapping_table[i].csc_format) {
+ input_color_space = is_input_yuv ? csc_mapping_table[i].yuv_color_space :
+ csc_mapping_table[i].rgb_color_space;
+ is_input_full_range = is_input_yuv ? csc_mapping_table[i].yuv_full_range :
+ csc_mapping_table[i].rgb_full_range;
+ output_color_space = is_output_yuv ? csc_mapping_table[i].yuv_color_space :
+ csc_mapping_table[i].rgb_color_space;
+ is_output_full_range = is_output_yuv ? csc_mapping_table[i].yuv_full_range :
+ csc_mapping_table[i].rgb_full_range;
+ break;
+ }
+ }
+ if (i >= ARRAY_SIZE(csc_mapping_table))
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(g_mode_csc_coef); i++) {
+ colorspace_info = &g_mode_csc_coef[i].st_csc_color_info;
+ if (colorspace_info->input_color_space == input_color_space &&
+ colorspace_info->output_color_space == output_color_space &&
+ colorspace_info->in_full_range == is_input_full_range &&
+ colorspace_info->out_full_range == is_output_full_range)
+ return i;
+ }
+
+ return -EINVAL;
+}
+
+static void csc_matrix_multiply(struct rk_pq_csc_coef *dst, const struct rk_pq_csc_coef *m0,
+ const struct rk_pq_csc_coef *m1)
+{
+ dst->csc_coef00 = m0->csc_coef00 * m1->csc_coef00 +
+ m0->csc_coef01 * m1->csc_coef10 +
+ m0->csc_coef02 * m1->csc_coef20;
+
+ dst->csc_coef01 = m0->csc_coef00 * m1->csc_coef01 +
+ m0->csc_coef01 * m1->csc_coef11 +
+ m0->csc_coef02 * m1->csc_coef21;
+
+ dst->csc_coef02 = m0->csc_coef00 * m1->csc_coef02 +
+ m0->csc_coef01 * m1->csc_coef12 +
+ m0->csc_coef02 * m1->csc_coef22;
+
+ dst->csc_coef10 = m0->csc_coef10 * m1->csc_coef00 +
+ m0->csc_coef11 * m1->csc_coef10 +
+ m0->csc_coef12 * m1->csc_coef20;
+
+ dst->csc_coef11 = m0->csc_coef10 * m1->csc_coef01 +
+ m0->csc_coef11 * m1->csc_coef11 +
+ m0->csc_coef12 * m1->csc_coef21;
+
+ dst->csc_coef12 = m0->csc_coef10 * m1->csc_coef02 +
+ m0->csc_coef11 * m1->csc_coef12 +
+ m0->csc_coef12 * m1->csc_coef22;
+
+ dst->csc_coef20 = m0->csc_coef20 * m1->csc_coef00 +
+ m0->csc_coef21 * m1->csc_coef10 +
+ m0->csc_coef22 * m1->csc_coef20;
+
+ dst->csc_coef21 = m0->csc_coef20 * m1->csc_coef01 +
+ m0->csc_coef21 * m1->csc_coef11 +
+ m0->csc_coef22 * m1->csc_coef21;
+
+ dst->csc_coef22 = m0->csc_coef20 * m1->csc_coef02 +
+ m0->csc_coef21 * m1->csc_coef12 +
+ m0->csc_coef22 * m1->csc_coef22;
+}
+
+static void csc_matrix_ventor_multiply(struct rk_pq_csc_ventor *dst,
+ const struct rk_pq_csc_coef *m0,
+ const struct rk_pq_csc_ventor *v0)
+{
+ dst->csc_offset0 = m0->csc_coef00 * v0->csc_offset0 +
+ m0->csc_coef01 * v0->csc_offset1 +
+ m0->csc_coef02 * v0->csc_offset2;
+
+ dst->csc_offset1 = m0->csc_coef10 * v0->csc_offset0 +
+ m0->csc_coef11 * v0->csc_offset1 +
+ m0->csc_coef12 * v0->csc_offset2;
+
+ dst->csc_offset2 = m0->csc_coef20 * v0->csc_offset0 +
+ m0->csc_coef21 * v0->csc_offset1 +
+ m0->csc_coef22 * v0->csc_offset2;
+}
+
+static void csc_matrix_element_left_shift(struct rk_pq_csc_coef *m, int n)
+{
+ m->csc_coef00 = m->csc_coef00 >> n;
+ m->csc_coef01 = m->csc_coef01 >> n;
+ m->csc_coef02 = m->csc_coef02 >> n;
+ m->csc_coef10 = m->csc_coef10 >> n;
+ m->csc_coef11 = m->csc_coef11 >> n;
+ m->csc_coef12 = m->csc_coef12 >> n;
+ m->csc_coef20 = m->csc_coef20 >> n;
+ m->csc_coef21 = m->csc_coef21 >> n;
+ m->csc_coef22 = m->csc_coef22 >> n;
+}
+
+static struct rk_pq_csc_coef create_rgb_gain_matrix(s32 r_gain, s32 g_gain, s32 b_gain)
+{
+ struct rk_pq_csc_coef m;
+
+ m.csc_coef00 = r_gain;
+ m.csc_coef01 = 0;
+ m.csc_coef02 = 0;
+
+ m.csc_coef10 = 0;
+ m.csc_coef11 = g_gain;
+ m.csc_coef12 = 0;
+
+ m.csc_coef20 = 0;
+ m.csc_coef21 = 0;
+ m.csc_coef22 = b_gain;
+
+ return m;
+}
+
+static struct rk_pq_csc_coef create_contrast_matrix(s32 contrast)
+{
+ struct rk_pq_csc_coef m;
+
+ m.csc_coef00 = contrast;
+ m.csc_coef01 = 0;
+ m.csc_coef02 = 0;
+
+ m.csc_coef10 = 0;
+ m.csc_coef11 = contrast;
+ m.csc_coef12 = 0;
+
+ m.csc_coef20 = 0;
+ m.csc_coef21 = 0;
+ m.csc_coef22 = contrast;
+
+ return m;
+}
+
+static struct rk_pq_csc_coef create_hue_matrix(s32 hue)
+{
+ struct rk_pq_csc_coef m;
+ s32 hue_idx;
+ s32 sin_hue;
+ s32 cos_hue;
+
+ hue_idx = CLIP(hue / PQ_CSC_HUE_TABLE_DIV_COEF, 0, PQ_CSC_HUE_TABLE_NUM - 1);
+ sin_hue = g_hue_sin_table[hue_idx];
+ cos_hue = g_hue_cos_table[hue_idx];
+
+ m.csc_coef00 = 1024;
+ m.csc_coef01 = 0;
+ m.csc_coef02 = 0;
+
+ m.csc_coef10 = 0;
+ m.csc_coef11 = cos_hue;
+ m.csc_coef12 = sin_hue;
+
+ m.csc_coef20 = 0;
+ m.csc_coef21 = -sin_hue;
+ m.csc_coef22 = cos_hue;
+
+ return m;
+}
+
+static struct rk_pq_csc_coef create_saturation_matrix(s32 saturation)
+{
+ struct rk_pq_csc_coef m;
+
+ m.csc_coef00 = 512;
+ m.csc_coef01 = 0;
+ m.csc_coef02 = 0;
+
+ m.csc_coef10 = 0;
+ m.csc_coef11 = saturation;
+ m.csc_coef12 = 0;
+
+ m.csc_coef20 = 0;
+ m.csc_coef21 = 0;
+ m.csc_coef22 = saturation;
+
+ return m;
+}
+
+static int csc_calc_adjust_output_coef(bool is_input_yuv, bool is_output_yuv,
+ struct csc_info *csc_input_cfg,
+ const struct rk_csc_mode_coef *csc_mode_cfg,
+ struct rk_pq_csc_coef *out_matrix,
+ struct rk_pq_csc_ventor *out_dc)
+{
+ struct rk_pq_csc_coef gain_matrix;
+ struct rk_pq_csc_coef contrast_matrix;
+ struct rk_pq_csc_coef hue_matrix;
+ struct rk_pq_csc_coef saturation_matrix;
+ struct rk_pq_csc_coef temp0, temp1;
+ const struct rk_pq_csc_coef *r2y_matrix;
+ const struct rk_pq_csc_coef *y2r_matrix;
+ struct rk_pq_csc_ventor dc_in_ventor;
+ struct rk_pq_csc_ventor dc_out_ventor;
+ struct rk_pq_csc_ventor v;
+ const struct rk_csc_colorspace_info *color_info;
+ s32 contrast, saturation, brightness;
+ s32 r_gain, g_gain, b_gain;
+ s32 r_offset, g_offset, b_offset;
+ s32 dc_in_offset, dc_out_offset;
+
+ contrast = csc_input_cfg->contrast * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
+ saturation = csc_input_cfg->saturation * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
+ r_gain = csc_input_cfg->r_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
+ g_gain = csc_input_cfg->g_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
+ b_gain = csc_input_cfg->b_gain * PQ_CSC_PARAM_FIX_NUM / PQ_CSC_IN_PARAM_NORM_COEF;
+ r_offset = ((s32)csc_input_cfg->r_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
+ g_offset = ((s32)csc_input_cfg->g_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
+ b_offset = ((s32)csc_input_cfg->b_offset - PQ_CSC_BRIGHTNESS_OFFSET) /
+ PQ_CSC_TEMP_OFFSET_DIV_COEF;
+
+ gain_matrix = create_rgb_gain_matrix(r_gain, g_gain, b_gain);
+ contrast_matrix = create_contrast_matrix(contrast);
+ hue_matrix = create_hue_matrix(csc_input_cfg->hue);
+ saturation_matrix = create_saturation_matrix(saturation);
+
+ color_info = &csc_mode_cfg->st_csc_color_info;
+ brightness = (s32)csc_input_cfg->brightness - PQ_CSC_BRIGHTNESS_OFFSET;
+ dc_in_offset = color_info->in_full_range ? 0 : -PQ_CSC_DC_IN_OFFSET;
+ dc_out_offset = color_info->out_full_range ? 0 : PQ_CSC_DC_IN_OFFSET;
+
+ /*
+ * M0 = hue_matrix * saturation_matrix,
+ * M1 = gain_matrix * constrast_matrix,
+ */
+
+ if (is_input_yuv && is_output_yuv) {
+ /*
+ * yuv2yuv: output = T * M0 * N_r2y * M1 * N_y2r,
+ * so output = T * hue_matrix * saturation_matrix *
+ * N_r2y * gain_matrix * contrast_matrix * N_y2r
+ */
+ r2y_matrix = &r2y_for_y2y;
+ y2r_matrix = &y2r_for_y2y;
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &hue_matrix);
+ /*
+ * The value bits width is 32 bit, so every time 2 matirx multifly,
+ * left shift is necessary to avoid overflow. For enhancing the
+ * calculator precision, PQ_CALC_ENHANCE_BIT bits is reserved and
+ * left shift before get the final result.
+ */
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH -
+ PQ_CALC_ENHANCE_BIT);
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp0, &temp1, r2y_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp1, &temp0, &gain_matrix);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp0, &temp1, &contrast_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(out_matrix, &temp0, y2r_matrix);
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
+ PQ_CALC_ENHANCE_BIT);
+
+ dc_in_ventor.csc_offset0 = dc_in_offset;
+ dc_in_ventor.csc_offset1 = -PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_in_ventor.csc_offset2 = -PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset;
+ dc_out_ventor.csc_offset1 = PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_out_ventor.csc_offset2 = PQ_CSC_DC_IN_OUT_DEFAULT;
+ } else if (is_input_yuv && !is_output_yuv) {
+ /*
+ * yuv2rgb: output = M1 * T * M0,
+ * so output = gain_matrix * contrast_matrix * T *
+ * hue_matrix * saturation_matrix
+ */
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &hue_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH -
+ PQ_CALC_ENHANCE_BIT);
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp0, &contrast_matrix, &temp1);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(out_matrix, &gain_matrix, &temp0);
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH +
+ PQ_CALC_ENHANCE_BIT);
+
+ dc_in_ventor.csc_offset0 = dc_in_offset;
+ dc_in_ventor.csc_offset1 = -PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_in_ventor.csc_offset2 = -PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset + r_offset;
+ dc_out_ventor.csc_offset1 = brightness + dc_out_offset + g_offset;
+ dc_out_ventor.csc_offset2 = brightness + dc_out_offset + b_offset;
+ } else if (!is_input_yuv && is_output_yuv) {
+ /*
+ * rgb2yuv: output = M0 * T * M1,
+ * so output = hue_matrix * saturation_matrix * T *
+ * gain_matrix * contrast_matrix
+ */
+ csc_matrix_multiply(&temp0, csc_mode_cfg->pst_csc_coef, &gain_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH -
+ PQ_CALC_ENHANCE_BIT);
+ csc_matrix_multiply(&temp1, &temp0, &contrast_matrix);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp0, &saturation_matrix, &temp1);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(out_matrix, &hue_matrix, &temp0);
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
+ PQ_CALC_ENHANCE_BIT);
+
+ dc_in_ventor.csc_offset0 = dc_in_offset;
+ dc_in_ventor.csc_offset1 = dc_in_offset;
+ dc_in_ventor.csc_offset2 = dc_in_offset;
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset;
+ dc_out_ventor.csc_offset1 = PQ_CSC_DC_IN_OUT_DEFAULT;
+ dc_out_ventor.csc_offset2 = PQ_CSC_DC_IN_OUT_DEFAULT;
+ } else {
+ /*
+ * rgb2rgb: output = T * M1 * N_y2r * M0 * N_r2y,
+ * so output = T * gain_matrix * contrast_matrix *
+ * N_y2r * hue_matrix * saturation_matrix * N_r2y
+ */
+ if (!color_info->in_full_range && color_info->out_full_range) {
+ r2y_matrix = &rk_csc_table_rgb_limit_to_hdy_cb_cr;
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_full;
+ } else if (color_info->in_full_range && !color_info->out_full_range) {
+ r2y_matrix = &rk_csc_table_rgb_to_hdy_cb_cr;
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit;
+ } else if (color_info->in_full_range && color_info->out_full_range) {
+ r2y_matrix = &rk_csc_table_rgb_to_hdy_cb_cr_full;
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_to_rgb_full;
+ } else {
+ r2y_matrix = &rk_csc_table_rgb_limit_to_hdy_cb_cr;
+ y2r_matrix = &rk_csc_table_hdy_cb_cr_limit_to_rgb_limit;
+ }
+
+ csc_matrix_multiply(&temp0, &contrast_matrix, y2r_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH -
+ PQ_CALC_ENHANCE_BIT);
+ csc_matrix_multiply(&temp1, &gain_matrix, &temp0);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp0, &temp1, &hue_matrix);
+ csc_matrix_element_left_shift(&temp0, PQ_CSC_PARAM_FIX_BIT_WIDTH);
+ csc_matrix_multiply(&temp1, &temp0, &saturation_matrix);
+ csc_matrix_element_left_shift(&temp1, PQ_CSC_PARAM_HALF_FIX_BIT_WIDTH);
+ csc_matrix_multiply(out_matrix, &temp1, r2y_matrix);
+ csc_matrix_element_left_shift(out_matrix, PQ_CSC_PARAM_FIX_BIT_WIDTH +
+ PQ_CALC_ENHANCE_BIT);
+
+ if (color_info->in_full_range && color_info->out_full_range)
+ out_matrix->csc_coef00 += 1;
+
+ dc_in_ventor.csc_offset0 = dc_in_offset;
+ dc_in_ventor.csc_offset1 = dc_in_offset;
+ dc_in_ventor.csc_offset2 = dc_in_offset;
+ dc_out_ventor.csc_offset0 = brightness + dc_out_offset + r_offset;
+ dc_out_ventor.csc_offset1 = brightness + dc_out_offset + g_offset;
+ dc_out_ventor.csc_offset2 = brightness + dc_out_offset + b_offset;
+ }
+
+ csc_matrix_ventor_multiply(&v, out_matrix, &dc_in_ventor);
+ out_dc->csc_offset0 = v.csc_offset0 + dc_out_ventor.csc_offset0 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+ out_dc->csc_offset1 = v.csc_offset1 + dc_out_ventor.csc_offset1 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+ out_dc->csc_offset2 = v.csc_offset2 + dc_out_ventor.csc_offset2 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+
+ return 0;
+}
+
+static int csc_calc_default_output_coef(const struct rk_csc_mode_coef *csc_mode_cfg,
+ struct rk_pq_csc_coef *out_matrix,
+ struct rk_pq_csc_ventor *out_dc)
+{
+ const struct rk_pq_csc_coef *csc_coef;
+ const struct rk_pq_csc_dc_coef *csc_dc_coef;
+ struct rk_pq_csc_ventor dc_in_ventor;
+ struct rk_pq_csc_ventor dc_out_ventor;
+ struct rk_pq_csc_ventor v;
+
+ csc_coef = csc_mode_cfg->pst_csc_coef;
+ csc_dc_coef = csc_mode_cfg->pst_csc_dc_coef;
+
+ out_matrix->csc_coef00 = csc_coef->csc_coef00;
+ out_matrix->csc_coef01 = csc_coef->csc_coef01;
+ out_matrix->csc_coef02 = csc_coef->csc_coef02;
+ out_matrix->csc_coef10 = csc_coef->csc_coef10;
+ out_matrix->csc_coef11 = csc_coef->csc_coef11;
+ out_matrix->csc_coef12 = csc_coef->csc_coef12;
+ out_matrix->csc_coef20 = csc_coef->csc_coef20;
+ out_matrix->csc_coef21 = csc_coef->csc_coef21;
+ out_matrix->csc_coef22 = csc_coef->csc_coef22;
+
+ dc_in_ventor.csc_offset0 = csc_dc_coef->csc_in_dc0;
+ dc_in_ventor.csc_offset1 = csc_dc_coef->csc_in_dc1;
+ dc_in_ventor.csc_offset2 = csc_dc_coef->csc_in_dc2;
+ dc_out_ventor.csc_offset0 = csc_dc_coef->csc_out_dc0;
+ dc_out_ventor.csc_offset1 = csc_dc_coef->csc_out_dc1;
+ dc_out_ventor.csc_offset2 = csc_dc_coef->csc_out_dc2;
+
+ csc_matrix_ventor_multiply(&v, csc_coef, &dc_in_ventor);
+ out_dc->csc_offset0 = v.csc_offset0 + dc_out_ventor.csc_offset0 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+ out_dc->csc_offset1 = v.csc_offset1 + dc_out_ventor.csc_offset1 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+ out_dc->csc_offset2 = v.csc_offset2 + dc_out_ventor.csc_offset2 *
+ PQ_CSC_SIMPLE_MAT_PARAM_FIX_NUM;
+
+ return 0;
+}
+
+static inline s32 pq_csc_simple_round(s32 x, s32 n)
+{
+ s32 value = 0;
+
+ if (n == 0)
+ return x;
+
+ value = (abs(x) + (1 << (n - 1))) >> (n);
+ return (((x) >= 0) ? value : -value);
+}
+
+static void rockchip_swap_color_channel(bool is_input_yuv, bool is_output_yuv,
+ struct post_csc_coef *csc_simple_coef,
+ struct rk_pq_csc_coef *out_matrix,
+ struct rk_pq_csc_ventor *out_dc)
+{
+ struct rk_pq_csc_coef tmp_matrix;
+ struct rk_pq_csc_ventor tmp_v;
+
+ if (!is_input_yuv) {
+ memcpy(&tmp_matrix, out_matrix, sizeof(struct rk_pq_csc_coef));
+ csc_matrix_multiply(out_matrix, &tmp_matrix, &rgb_input_swap_matrix);
+ }
+
+ if (is_output_yuv) {
+ memcpy(&tmp_matrix, out_matrix, sizeof(struct rk_pq_csc_coef));
+ memcpy(&tmp_v, out_dc, sizeof(struct rk_pq_csc_ventor));
+ csc_matrix_multiply(out_matrix, &yuv_output_swap_matrix, &tmp_matrix);
+ csc_matrix_ventor_multiply(out_dc, &yuv_output_swap_matrix, &tmp_v);
+ }
+
+ csc_simple_coef->csc_coef00 = out_matrix->csc_coef00;
+ csc_simple_coef->csc_coef01 = out_matrix->csc_coef01;
+ csc_simple_coef->csc_coef02 = out_matrix->csc_coef02;
+ csc_simple_coef->csc_coef10 = out_matrix->csc_coef10;
+ csc_simple_coef->csc_coef11 = out_matrix->csc_coef11;
+ csc_simple_coef->csc_coef12 = out_matrix->csc_coef12;
+ csc_simple_coef->csc_coef20 = out_matrix->csc_coef20;
+ csc_simple_coef->csc_coef21 = out_matrix->csc_coef21;
+ csc_simple_coef->csc_coef22 = out_matrix->csc_coef22;
+ csc_simple_coef->csc_dc0 = out_dc->csc_offset0;
+ csc_simple_coef->csc_dc1 = out_dc->csc_offset1;
+ csc_simple_coef->csc_dc2 = out_dc->csc_offset2;
+}
+
+int rockchip_calc_post_csc(struct csc_info *csc_cfg, struct post_csc_coef *csc_simple_coef,
+ int csc_mode, bool is_input_yuv, bool is_output_yuv)
+{
+ int ret = 0;
+ struct rk_pq_csc_coef out_matrix;
+ struct rk_pq_csc_ventor out_dc;
+ const struct rk_csc_mode_coef *csc_mode_cfg;
+ int bit_num = PQ_CSC_SIMPLE_MAT_PARAM_FIX_BIT_WIDTH;
+
+ ret = csc_get_mode_index(csc_mode, is_input_yuv, is_output_yuv);
+ if (ret < 0) {
+ printf("invalid csc_mode:%d\n", csc_mode);
+ return ret;
+ }
+
+ csc_mode_cfg = &g_mode_csc_coef[ret];
+
+ if (csc_cfg)
+ ret = csc_calc_adjust_output_coef(is_input_yuv, is_output_yuv, csc_cfg,
+ csc_mode_cfg, &out_matrix, &out_dc);
+ else
+ ret = csc_calc_default_output_coef(csc_mode_cfg, &out_matrix, &out_dc);
+
+ rockchip_swap_color_channel(is_input_yuv, is_output_yuv, csc_simple_coef, &out_matrix,
+ &out_dc);
+
+ csc_simple_coef->csc_dc0 = pq_csc_simple_round(csc_simple_coef->csc_dc0, bit_num);
+ csc_simple_coef->csc_dc1 = pq_csc_simple_round(csc_simple_coef->csc_dc1, bit_num);
+ csc_simple_coef->csc_dc2 = pq_csc_simple_round(csc_simple_coef->csc_dc2, bit_num);
+ csc_simple_coef->range_type = csc_mode_cfg->st_csc_color_info.out_full_range;
+
+ return ret;
+}
diff --git a/u-boot/drivers/video/drm/rockchip_post_csc.h b/u-boot/drivers/video/drm/rockchip_post_csc.h
new file mode 100755
index 0000000..f11e808
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_post_csc.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (C) Rockchip Electronics Co.Ltd
+ * Author:
+ * Zhang Yubing <yubing.zhang@rock-chips.com>
+ */
+
+#ifndef _ROCKCHIP_POST_CSC_H
+#define _ROCKCHIP_POST_CSC_H
+
+#include <linux/kernel.h>
+#include <edid.h>
+
+struct post_csc_coef {
+ s32 csc_coef00;
+ s32 csc_coef01;
+ s32 csc_coef02;
+ s32 csc_coef10;
+ s32 csc_coef11;
+ s32 csc_coef12;
+ s32 csc_coef20;
+ s32 csc_coef21;
+ s32 csc_coef22;
+
+ s32 csc_dc0;
+ s32 csc_dc1;
+ s32 csc_dc2;
+
+ u32 range_type;
+};
+
+int rockchip_calc_post_csc(struct csc_info *csc, struct post_csc_coef *csc_coef,
+ int csc_mode, bool is_input_yuv, bool is_output_yuv);
+
+#endif
diff --git a/u-boot/drivers/video/drm/rockchip_rgb.c b/u-boot/drivers/video/drm/rockchip_rgb.c
index 53fb862..2b3b85c 100644
--- a/u-boot/drivers/video/drm/rockchip_rgb.c
+++ b/u-boot/drivers/video/drm/rockchip_rgb.c
@@ -13,11 +13,14 @@
#include <dm/read.h>
#include <dm/pinctrl.h>
#include <linux/media-bus-format.h>
+#include <asm/gpio.h>
+#include <backlight.h>
#include "rockchip_display.h"
#include "rockchip_crtc.h"
#include "rockchip_connector.h"
#include "rockchip_phy.h"
+#include "rockchip_panel.h"
#define HIWORD_UPDATE(v, h, l) (((v) << (l)) | (GENMASK(h, l) << 16))
@@ -48,6 +51,9 @@
#define RK3368_GRF_SOC_CON15 0x043c
#define RK3368_FORCE_JETAG(v) HIWORD_UPDATE(v, 13, 13)
+#define RK3562_GRF_IOC_VO_IO_CON 0x10500
+#define RK3562_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
+
#define RK3568_GRF_VO_CON1 0X0364
#define RK3568_RGB_DATA_BYPASS(v) HIWORD_UPDATE(v, 6, 6)
@@ -67,6 +73,64 @@
struct rockchip_phy *phy;
const struct rockchip_rgb_funcs *funcs;
};
+
+struct mcu_cmd_header {
+ u8 data_type;
+ u8 delay;
+ u8 payload_length;
+} __packed;
+
+struct mcu_cmd_desc {
+ struct mcu_cmd_header header;
+ const u8 *payload;
+};
+
+struct mcu_cmd_seq {
+ struct mcu_cmd_desc *cmds;
+ unsigned int cmd_cnt;
+};
+
+struct rockchip_mcu_panel_desc {
+ struct mcu_cmd_seq *init_seq;
+ struct mcu_cmd_seq *exit_seq;
+
+ struct {
+ unsigned int width;
+ unsigned int height;
+ } size;
+
+ struct {
+ unsigned int prepare;
+ unsigned int enable;
+ unsigned int disable;
+ unsigned int unprepare;
+ unsigned int reset;
+ unsigned int init;
+ } delay;
+
+ unsigned int bpc;
+ u32 bus_format;
+ u32 bus_flags;
+ bool power_invert;
+};
+
+struct rockchip_mcu_panel {
+ struct rockchip_panel base;
+ struct rockchip_mcu_panel_desc *desc;
+ struct udevice *power_supply;
+ struct udevice *backlight;
+
+ struct gpio_desc enable_gpio;
+ struct gpio_desc reset_gpio;
+
+ bool prepared;
+ bool enabled;
+};
+
+static inline struct rockchip_mcu_panel *to_rockchip_mcu_panel(struct rockchip_panel *panel)
+{
+ return container_of(panel, struct rockchip_mcu_panel, base);
+}
static int rockchip_rgb_connector_prepare(struct rockchip_connector *conn,
struct display_state *state)
@@ -170,9 +234,254 @@
.unprepare = rockchip_rgb_connector_unprepare,
};
+static int rockchip_mcu_panel_send_cmds(struct display_state *state,
+ struct mcu_cmd_seq *cmds)
+{
+ int i;
+
+ if (!cmds)
+ return -EINVAL;
+
+ display_send_mcu_cmd(state, MCU_SETBYPASS, 1);
+ for (i = 0; i < cmds->cmd_cnt; i++) {
+ struct mcu_cmd_desc *desc = &cmds->cmds[i];
+ int value = 0;
+
+ value = desc->payload[0];
+ display_send_mcu_cmd(state, desc->header.data_type, value);
+
+ if (desc->header.delay)
+ mdelay(desc->header.delay);
+ }
+ display_send_mcu_cmd(state, MCU_SETBYPASS, 0);
+
+ return 0;
+}
+
+static void rockchip_mcu_panel_prepare(struct rockchip_panel *panel)
+{
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
+ int ret;
+
+ if (mcu_panel->prepared)
+ return;
+
+ if (dm_gpio_is_valid(&mcu_panel->enable_gpio))
+ dm_gpio_set_value(&mcu_panel->enable_gpio, 1);
+
+ if (mcu_panel->desc->delay.prepare)
+ mdelay(mcu_panel->desc->delay.prepare);
+
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 1);
+
+ if (mcu_panel->desc->delay.reset)
+ mdelay(mcu_panel->desc->delay.reset);
+
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 0);
+
+ if (mcu_panel->desc->delay.init)
+ mdelay(mcu_panel->desc->delay.init);
+
+ if (mcu_panel->desc->init_seq) {
+ ret = rockchip_mcu_panel_send_cmds(panel->state, mcu_panel->desc->init_seq);
+ if (ret)
+ printf("failed to send mcu panel init cmds: %d\n", ret);
+ }
+
+ mcu_panel->prepared = true;
+}
+
+static void rockchip_mcu_panel_unprepare(struct rockchip_panel *panel)
+{
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
+ int ret;
+
+ if (!mcu_panel->prepared)
+ return;
+
+ if (mcu_panel->desc->exit_seq) {
+ ret = rockchip_mcu_panel_send_cmds(panel->state, mcu_panel->desc->exit_seq);
+ if (ret)
+ printf("failed to send mcu panel exit cmds: %d\n", ret);
+ }
+
+ if (dm_gpio_is_valid(&mcu_panel->reset_gpio))
+ dm_gpio_set_value(&mcu_panel->reset_gpio, 1);
+
+ if (dm_gpio_is_valid(&mcu_panel->enable_gpio))
+ dm_gpio_set_value(&mcu_panel->enable_gpio, 0);
+
+ if (mcu_panel->desc->delay.unprepare)
+ mdelay(mcu_panel->desc->delay.unprepare);
+
+ mcu_panel->prepared = false;
+}
+
+static void rockchip_mcu_panel_enable(struct rockchip_panel *panel)
+{
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
+
+ if (mcu_panel->enabled)
+ return;
+
+ if (mcu_panel->desc->delay.enable)
+ mdelay(mcu_panel->desc->delay.enable);
+
+ if (mcu_panel->backlight)
+ backlight_enable(mcu_panel->backlight);
+
+ mcu_panel->enabled = true;
+}
+
+static void rockchip_mcu_panel_disable(struct rockchip_panel *panel)
+{
+ struct rockchip_mcu_panel *mcu_panel = to_rockchip_mcu_panel(panel);
+
+ if (!mcu_panel->enabled)
+ return;
+
+ if (mcu_panel->backlight)
+ backlight_disable(mcu_panel->backlight);
+
+ if (mcu_panel->desc->delay.disable)
+ mdelay(mcu_panel->desc->delay.disable);
+
+ mcu_panel->enabled = false;
+}
+
+static const struct rockchip_panel_funcs rockchip_mcu_panel_funcs = {
+ .prepare = rockchip_mcu_panel_prepare,
+ .unprepare = rockchip_mcu_panel_unprepare,
+ .enable = rockchip_mcu_panel_enable,
+ .disable = rockchip_mcu_panel_disable,
+};
+
+static int rockchip_mcu_panel_parse_cmds(const u8 *data, int length,
+ struct mcu_cmd_seq *pcmds)
+{
+ int len;
+ const u8 *buf;
+ const struct mcu_cmd_header *header;
+ int i, cnt = 0;
+
+ /* scan commands */
+ cnt = 0;
+ buf = data;
+ len = length;
+ while (len > sizeof(*header)) {
+ header = (const struct mcu_cmd_header *)buf;
+ buf += sizeof(*header) + header->payload_length;
+ len -= sizeof(*header) + header->payload_length;
+ cnt++;
+ }
+
+ pcmds->cmds = calloc(cnt, sizeof(struct mcu_cmd_desc));
+ if (!pcmds->cmds)
+ return -ENOMEM;
+
+ pcmds->cmd_cnt = cnt;
+
+ buf = data;
+ len = length;
+ for (i = 0; i < cnt; i++) {
+ struct mcu_cmd_desc *desc = &pcmds->cmds[i];
+
+ header = (const struct mcu_cmd_header *)buf;
+ length -= sizeof(*header);
+ buf += sizeof(*header);
+ desc->header.data_type = header->data_type;
+ desc->header.delay = header->delay;
+ desc->header.payload_length = header->payload_length;
+ desc->payload = buf;
+ buf += header->payload_length;
+ length -= header->payload_length;
+ }
+
+ return 0;
+}
+
+static int rockchip_mcu_panel_init(struct rockchip_mcu_panel *mcu_panel, ofnode mcu_panel_node)
+{
+ const void *data;
+ int len;
+ int ret;
+
+ ret = gpio_request_by_name_nodev(mcu_panel_node, "enable-gpios", 0,
+ &mcu_panel->enable_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get mcu panel enable GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name_nodev(mcu_panel_node, "reset-gpios", 0,
+ &mcu_panel->reset_gpio, GPIOD_IS_OUT);
+ if (ret && ret != -ENOENT) {
+ printf("%s: Cannot get mcu panel reset GPIO: %d\n", __func__, ret);
+ return ret;
+ }
+
+ mcu_panel->desc = malloc(sizeof(struct rockchip_mcu_panel_desc));
+ if (!mcu_panel->desc)
+ return -ENOMEM;
+
+ mcu_panel->desc->power_invert = ofnode_read_bool(mcu_panel_node, "power-invert");
+
+ mcu_panel->desc->delay.prepare = ofnode_read_u32_default(mcu_panel_node, "prepare-delay-ms", 0);
+ mcu_panel->desc->delay.unprepare = ofnode_read_u32_default(mcu_panel_node, "unprepare-delay-ms", 0);
+ mcu_panel->desc->delay.enable = ofnode_read_u32_default(mcu_panel_node, "enable-delay-ms", 0);
+ mcu_panel->desc->delay.disable = ofnode_read_u32_default(mcu_panel_node, "disable-delay-ms", 0);
+ mcu_panel->desc->delay.init = ofnode_read_u32_default(mcu_panel_node, "init-delay-ms", 0);
+ mcu_panel->desc->delay.reset = ofnode_read_u32_default(mcu_panel_node, "reset-delay-ms", 0);
+
+ mcu_panel->desc->bus_format = ofnode_read_u32_default(mcu_panel_node, "bus-format",
+ MEDIA_BUS_FMT_RBG888_1X24);
+ mcu_panel->desc->bpc = ofnode_read_u32_default(mcu_panel_node, "bpc", 8);
+
+ data = ofnode_get_property(mcu_panel_node, "panel-init-sequence", &len);
+ if (data) {
+ mcu_panel->desc->init_seq = calloc(1, sizeof(*mcu_panel->desc->init_seq));
+ if (!mcu_panel->desc->init_seq)
+ return -ENOMEM;
+
+ ret = rockchip_mcu_panel_parse_cmds(data, len, mcu_panel->desc->init_seq);
+ if (ret) {
+ printf("failed to parse panel init sequence\n");
+ goto free_on_cmds;
+ }
+ }
+
+ data = ofnode_get_property(mcu_panel_node, "panel-exit-sequence", &len);
+ if (data) {
+ mcu_panel->desc->exit_seq = calloc(1, sizeof(*mcu_panel->desc->exit_seq));
+ if (!mcu_panel->desc->exit_seq) {
+ ret = -ENOMEM;
+ goto free_on_cmds;
+ }
+
+ ret = rockchip_mcu_panel_parse_cmds(data, len, mcu_panel->desc->exit_seq);
+ if (ret) {
+ printf("failed to parse panel exit sequence\n");
+ goto free_cmds;
+ }
+ }
+
+ return 0;
+
+free_cmds:
+ free(mcu_panel->desc->exit_seq);
+free_on_cmds:
+ free(mcu_panel->desc->init_seq);
+ return ret;
+}
+
static int rockchip_rgb_probe(struct udevice *dev)
{
struct rockchip_rgb *rgb = dev_get_priv(dev);
+ ofnode mcu_panel_node;
+ int phandle;
+ int ret;
rgb->dev = dev;
rgb->funcs = (const struct rockchip_rgb_funcs *)dev_get_driver_data(dev);
@@ -181,6 +490,45 @@
rgb->id = of_alias_get_id(ofnode_to_np(dev->node), "rgb");
if (rgb->id < 0)
rgb->id = 0;
+
+ mcu_panel_node = dev_read_subnode(dev, "mcu-panel");
+ if (ofnode_valid(mcu_panel_node) && ofnode_is_available(mcu_panel_node)) {
+ struct rockchip_mcu_panel *mcu_panel;
+
+ mcu_panel = malloc(sizeof(struct rockchip_mcu_panel));
+ if (!mcu_panel) {
+ printf("failed to alloc mcu_panel data\n");
+ return -ENOMEM;
+ }
+
+ ret = rockchip_mcu_panel_init(mcu_panel, mcu_panel_node);
+ if (ret < 0) {
+ printf("failed to init mcu_panel: %d\n", ret);
+ return ret;
+ }
+
+ phandle = ofnode_read_u32_default(mcu_panel_node, "backlight", -1);
+ if (phandle < 0) {
+ printf("failed to find backlight phandle\n");
+ return -EINVAL;
+ }
+
+ ret = uclass_get_device_by_phandle_id(UCLASS_PANEL_BACKLIGHT, phandle,
+ &mcu_panel->backlight);
+ if (ret && ret != -ENOENT) {
+ printf("%s: failed to get backlight device: %d\n", __func__, ret);
+ return ret;
+ }
+
+ mcu_panel->base.dev = dev;
+ mcu_panel->base.bus_format = mcu_panel->desc->bus_format;
+ mcu_panel->base.bpc = mcu_panel->desc->bpc;
+ mcu_panel->base.funcs = &rockchip_mcu_panel_funcs;
+ mcu_panel->enabled = false;
+ mcu_panel->prepared = false;
+
+ rgb->connector.panel = &mcu_panel->base;
+ }
rockchip_connector_bind(&rgb->connector, dev, rgb->id, &rockchip_rgb_connector_funcs,
NULL, DRM_MODE_CONNECTOR_LVDS);
@@ -260,6 +608,16 @@
.prepare = rk3368_rgb_prepare,
};
+static void rk3562_rgb_prepare(struct rockchip_rgb *rgb, int pipe)
+{
+ regmap_write(rgb->grf, RK3562_GRF_IOC_VO_IO_CON,
+ RK3562_RGB_DATA_BYPASS(rgb->data_sync_bypass));
+}
+
+static const struct rockchip_rgb_funcs rk3562_rgb_funcs = {
+ .prepare = rk3562_rgb_prepare,
+};
+
static void rk3568_rgb_prepare(struct rockchip_rgb *rgb, int pipe)
{
regmap_write(rgb->grf, RK3568_GRF_VO_CON1, RK3568_RGB_DATA_BYPASS(rgb->data_sync_bypass));
@@ -296,6 +654,10 @@
.data = (ulong)&rk3368_rgb_funcs,
},
{
+ .compatible = "rockchip,rk3562-rgb",
+ .data = (ulong)&rk3562_rgb_funcs,
+ },
+ {
.compatible = "rockchip,rk3568-rgb",
.data = (ulong)&rk3568_rgb_funcs,
},
diff --git a/u-boot/drivers/video/drm/rockchip_spl_display.c b/u-boot/drivers/video/drm/rockchip_spl_display.c
new file mode 100644
index 0000000..c66815a
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_spl_display.c
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <mp_boot.h>
+#include <spl.h>
+#include <part.h>
+#include <drm_modes.h>
+#include <spl_display.h>
+#include <linux/hdmi.h>
+
+#include "rockchip_display.h"
+#include "rockchip_crtc.h"
+#include "rockchip_connector.h"
+#include "rockchip_phy.h"
+
+static struct base2_info base_parameter;
+
+struct display_state *rockchip_spl_display_drv_probe(void)
+{
+ struct display_state *state = malloc(sizeof(struct display_state));
+ if (!state)
+ return NULL;
+
+ memset(state, 0, sizeof(*state));
+
+ rockchip_spl_vop_probe(&state->crtc_state);
+ rockchip_spl_dw_hdmi_probe(&state->conn_state);
+ inno_spl_hdmi_phy_probe(state);
+
+ return state;
+}
+
+static int rockchip_spl_display_init(struct display_state *state)
+{
+ struct crtc_state *crtc_state = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct rockchip_connector *conn = conn_state->connector;
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
+ struct drm_display_mode *mode = &state->conn_state.mode;
+ int ret = 0;
+
+ if (!crtc_funcs) {
+ printf("failed to find crtc functions\n");
+ return -ENXIO;
+ }
+
+ if (crtc_funcs->preinit) {
+ ret = crtc_funcs->preinit(state);
+ if (ret)
+ return ret;
+ }
+
+ rockchip_display_make_crc32_table();
+ if (conn_funcs->pre_init) {
+ ret = conn_funcs->pre_init(conn, state);
+ if (ret)
+ return ret;
+ }
+
+ if (conn_funcs->init) {
+ ret = conn_funcs->init(conn, state);
+ if (ret)
+ goto deinit;
+ }
+
+ if (conn->phy)
+ rockchip_phy_init(conn->phy);
+
+ if (conn_funcs->detect) {
+ conn->hpd = conn_funcs->detect(conn, state);
+ if (!conn->hpd)
+ goto deinit;
+ }
+
+ if (conn_funcs->get_timing) {
+ ret = conn_funcs->get_timing(conn, state);
+ if (ret)
+ goto deinit;
+ }
+
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+ if (crtc_funcs->init) {
+ ret = crtc_funcs->init(state);
+ if (ret)
+ goto deinit;
+ }
+
+ return 0;
+
+deinit:
+ rockchip_connector_deinit(state);
+ return ret;
+}
+
+static int rockchip_spl_display_post_enable(struct display_state *state)
+{
+ struct crtc_state *crtc_state = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct rockchip_connector *conn = conn_state->connector;
+ const struct rockchip_crtc *crtc = crtc_state->crtc;
+ const struct rockchip_crtc_funcs *crtc_funcs = crtc->funcs;
+ const struct rockchip_connector_funcs *conn_funcs = conn->funcs;
+
+ if (crtc_funcs->enable)
+ crtc_funcs->enable(state);
+ state->crtc_state.crtc->active = true;
+
+ if (conn_funcs->enable)
+ conn_funcs->enable(conn, state);
+
+ return 0;
+}
+
+static void rockchip_spl_display_transmit_info_to_uboot(struct display_state *state)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct spl_display_info *spl_disp_info = (struct spl_display_info *)CONFIG_SPL_VIDEO_BUF;
+
+ /* transmit mode and bus_format to uboot */
+ memcpy(&spl_disp_info->mode, &conn_state->mode, sizeof(conn_state->mode));
+ spl_disp_info->bus_format = state->conn_state.bus_format;
+ spl_disp_info->enabled = 1;
+ flush_dcache_all();
+}
+
+int spl_init_display(struct task_data *data)
+{
+ struct display_state *state = NULL;
+ struct drm_display_mode *mode;
+ int ret = 0;
+
+ state = rockchip_spl_display_drv_probe();
+ if (!state) {
+ printf("rockchip_spl_display_drv_probe failed\n");
+ return -1;
+ }
+
+ ret = rockchip_spl_display_init(state);
+ if (ret) {
+ printf("rockchip_spl_display_init failed ret:%d\n", ret);
+ return -1;
+ }
+
+ if (!state->conn_state.connector->hpd) {
+ printf("HDMI is unplug and exit\n");
+ return 0;
+ }
+
+ ret = rockchip_spl_display_post_enable(state);
+ if (ret) {
+ printf("rockchip_spl_display_post_enable failed ret:%d\n", ret);
+ return -1;
+ }
+
+ rockchip_spl_display_transmit_info_to_uboot(state);
+
+ mode = &state->conn_state.mode;
+ printf("SPL enable hdmi, detailed mode clock %u kHz, flags[%x]\n"
+ " H: %04d %04d %04d %04d\n"
+ " V: %04d %04d %04d %04d\n"
+ "bus_format: %x\n",
+ mode->clock, mode->flags,
+ mode->hdisplay, mode->hsync_start,
+ mode->hsync_end, mode->htotal,
+ mode->vdisplay, mode->vsync_start,
+ mode->vsync_end, mode->vtotal,
+ state->conn_state.bus_format);
+
+ return ret;
+}
+
+struct base2_disp_info *rockchip_get_disp_info(int type, int id)
+{
+ struct base2_disp_info *disp_info;
+ struct base2_disp_header *disp_header;
+ int i = 0, offset = -1;
+ u32 crc_val;
+ u32 base2_length;
+ void *base_parameter_addr = (void *)&base_parameter;
+#ifdef CONFIG_MP_BOOT
+ void *bp_addr = (void *)CONFIG_SPL_VIDEO_BUF;
+ ulong ret;
+
+ /* make sure the baseparameter is ready */
+ ret = mpb_post(6);
+ printf("SPL read baseparameter %s\n", ret < 0 ? "failed" : "success");
+ memcpy(&base_parameter, bp_addr, sizeof(base_parameter));
+#endif
+ for (i = 0; i < 8; i++) {
+ disp_header = &base_parameter.disp_header[i];
+ if (disp_header->connector_type == type &&
+ disp_header->connector_id == id) {
+ printf("disp info %d, type:%d, id:%d\n", i, type, id);
+ offset = disp_header->offset;
+ break;
+ }
+ }
+
+ if (offset < 0)
+ return NULL;
+ disp_info = base_parameter_addr + offset;
+ if (disp_info->screen_info[0].type != type ||
+ disp_info->screen_info[0].id != id) {
+ printf("base2_disp_info couldn't be found, screen_info type[%d] or id[%d] mismatched\n",
+ disp_info->screen_info[0].type,
+ disp_info->screen_info[0].id);
+ return NULL;
+ }
+
+ if (strncasecmp(disp_info->disp_head_flag, "DISP", 4))
+ return NULL;
+
+ if (base_parameter.major_version == 3 && base_parameter.minor_version == 0) {
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info,
+ sizeof(struct base2_disp_info) - 4);
+ if (crc_val != disp_info->crc2) {
+ printf("error: connector type[%d], id[%d] disp info crc2 check error\n",
+ type, id);
+ return NULL;
+ }
+ } else {
+ base2_length = sizeof(struct base2_disp_info) - sizeof(struct csc_info) -
+ sizeof(struct acm_data) - 10 * 1024 - 4;
+ crc_val = rockchip_display_crc32c_cal((unsigned char *)disp_info, base2_length - 4);
+ if (crc_val != disp_info->crc) {
+ printf("error: connector type[%d], id[%d] disp info crc check error\n",
+ type, id);
+ return NULL;
+ }
+ }
+
+ return disp_info;
+}
+
+int spl_load_baseparamter(struct task_data *data)
+{
+ struct spl_load_info *info = &data->info;
+ ulong addr = CONFIG_SPL_VIDEO_BUF;
+ disk_partition_t part;
+
+ debug("== Baseparam: start\n");
+
+ if (part_get_info_by_name(info->dev, "baseparameter", &part) < 0) {
+ printf("No baseparameter partition\n");
+ return -ENOENT;
+ } else {
+ if (info->read(info, part.start, part.size, (void *)addr) != part.size)
+ return -EIO;
+ else
+ flush_dcache_range(addr, addr + part.size * info->bl_len);
+ }
+
+ debug("== Baseparam: load OK\n");
+
+ return 0;
+}
+
diff --git a/u-boot/drivers/video/drm/rockchip_tve.c b/u-boot/drivers/video/drm/rockchip_tve.c
new file mode 100644
index 0000000..9664549
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_tve.c
@@ -0,0 +1,848 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
+ */
+#include <common.h>
+#include <malloc.h>
+#include <fdtdec.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <linux/media-bus-format.h>
+#include <asm/arch-rockchip/clock.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <dm/uclass-internal.h>
+#include <linux/fb.h>
+#include <edid.h>
+#include <syscon.h>
+#include <boot_rkimg.h>
+#include <mapmem.h>
+#include <misc.h>
+
+#include "rockchip_display.h"
+#include "rockchip_crtc.h"
+#include "rockchip_connector.h"
+#include "rockchip_phy.h"
+#include "rockchip_tve.h"
+
+#define RK322X_VDAC_STANDARD 0x15
+
+static const struct drm_display_mode tve_modes[] = {
+ /* 0 - 720x576i@50Hz */
+ { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
+ 816, 864, 576, 580, 586, 625, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 50, },
+ /* 1 - 720x480i@60Hz */
+ { DRM_MODE(DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
+ 815, 858, 480, 483, 486, 525, 0,
+ DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
+ DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
+ .vrefresh = 60, },
+};
+
+struct env_config {
+ u32 offset;
+ u32 value;
+};
+
+static struct env_config ntsc_bt656_config[] = {
+ { BT656_DECODER_CROP, 0x00000000 },
+ { BT656_DECODER_SIZE, 0x01e002d0 },
+ { BT656_DECODER_HTOTAL_HS_END, 0x035a003e },
+ { BT656_DECODER_VACT_ST_HACT_ST, 0x00160069 },
+ { BT656_DECODER_VTOTAL_VS_END, 0x020d0003 },
+ { BT656_DECODER_VS_ST_END_F1, 0x01060109 },
+ { BT656_DECODER_DBG_REG, 0x024002d0 },
+ { BT656_DECODER_CTRL, 0x00000009 },
+};
+
+static struct env_config ntsc_tve_config[] = {
+ { TVE_MODE_CTRL, 0x000af906 },
+ { TVE_HOR_TIMING1, 0x00c07a81 },
+ { TVE_HOR_TIMING2, 0x169810fc },
+ { TVE_HOR_TIMING3, 0x96b40000 },
+ { TVE_SUB_CAR_FRQ, 0x21f07bd7 },
+ { TVE_IMAGE_POSITION, 0x001500d6 },
+ { TVE_ROUTING, 0x10088880 },
+ { TVE_SYNC_ADJUST, 0x00000000 },
+ { TVE_STATUS, 0x00000000 },
+ { TVE_CTRL, 0x00000000 },
+ { TVE_INTR_STATUS, 0x00000000 },
+ { TVE_INTR_EN, 0x00000000 },
+ { TVE_INTR_CLR, 0x00000000 },
+ { TVE_COLOR_BUSRT_SAT, 0x0052543c },
+ { TVE_CHROMA_BANDWIDTH, 0x00000002 },
+ { TVE_BRIGHTNESS_CONTRAST, 0x00008300 },
+ { TVE_CLAMP, 0x00000000 },
+};
+
+static struct env_config pal_bt656_config[] = {
+ { BT656_DECODER_CROP, 0x00000000 },
+ { BT656_DECODER_SIZE, 0x024002d0 },
+ { BT656_DECODER_HTOTAL_HS_END, 0x0360003f },
+ { BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f },
+ { BT656_DECODER_VTOTAL_VS_END, 0x02710003 },
+ { BT656_DECODER_VS_ST_END_F1, 0x0138013b },
+ { BT656_DECODER_DBG_REG, 0x024002d0 },
+ { BT656_DECODER_CTRL, 0x00000009 },
+};
+
+static struct env_config pal_tve_config[] = {
+ { TVE_MODE_CTRL, 0x010ab906 },
+ { TVE_HOR_TIMING1, 0x00c28381 },
+ { TVE_HOR_TIMING2, 0x267d111d },
+ { TVE_HOR_TIMING3, 0x66c00880 },
+ { TVE_SUB_CAR_FRQ, 0x2a098acb },
+ { TVE_IMAGE_POSITION, 0x001500f6 },
+ { TVE_ROUTING, 0x10008882 },
+ { TVE_SYNC_ADJUST, 0x00000000 },
+ { TVE_STATUS, 0x000000b0 },
+ { TVE_CTRL, 0x00000000 },
+ { TVE_INTR_STATUS, 0x00000000 },
+ { TVE_INTR_EN, 0x00000000 },
+ { TVE_INTR_CLR, 0x00000000 },
+ { TVE_COLOR_BUSRT_SAT, 0x00356245 },
+ { TVE_CHROMA_BANDWIDTH, 0x00000022 },
+ { TVE_BRIGHTNESS_CONTRAST, 0x0000aa00 },
+ { TVE_CLAMP, 0x00000000 },
+};
+
+#define BT656_ENV_CONFIG_SIZE (sizeof(ntsc_bt656_config) / sizeof(struct env_config))
+#define TVE_ENV_CONFIG_SIZE (sizeof(ntsc_tve_config) / sizeof(struct env_config))
+
+#define tve_writel(offset, v) writel(v, tve->reg_base + offset)
+#define tve_readl(offset) readl(tve->reg_base + offset)
+
+#define tve_dac_writel(offset, v) writel(v, tve->vdac_base + offset)
+#define tve_dac_readl(offset) readl(tve->vdac_base + offset)
+
+#define tve_grf_writel(offset, v) writel(v, tve->grf + offset)
+#define tve_grf_readl(offset, v) readl(tve->grf + offset)
+
+struct rockchip_tve_data {
+ int input_format;
+ int soc_type;
+};
+
+struct rockchip_tve {
+ struct rockchip_connector connector;
+ struct udevice *dev;
+ void *reg_base;
+ void *vdac_base;
+ int soc_type;
+ int input_format;
+ int tv_format;
+ int test_mode;
+ int saturation;
+ int brightcontrast;
+ int adjtiming;
+ int lumafilter0;
+ int lumafilter1;
+ int lumafilter2;
+ int lumafilter3;
+ int lumafilter4;
+ int lumafilter5;
+ int lumafilter6;
+ int lumafilter7;
+ int daclevel;
+ int dac1level;
+ int preferred_mode;
+ int upsample_mode;
+ void *grf;
+};
+
+static void tve_write_block(struct rockchip_tve *tve, struct env_config *config, int len)
+{
+ int i;
+
+ for (i = 0; i < len; i++)
+ tve_writel(config[i].offset, config[i].value);
+}
+
+static void tve_set_mode(struct rockchip_tve *tve)
+{
+ struct env_config *bt656_cfg, *tve_cfg;
+ int mode = tve->tv_format;
+
+ if (tve->soc_type == SOC_RK3528) {
+ tve_writel(TVE_LUMA_FILTER1, tve->lumafilter0);
+ tve_writel(TVE_LUMA_FILTER2, tve->lumafilter1);
+ tve_writel(TVE_LUMA_FILTER3, tve->lumafilter2);
+ tve_writel(TVE_LUMA_FILTER4, tve->lumafilter3);
+ tve_writel(TVE_LUMA_FILTER5, tve->lumafilter4);
+ tve_writel(TVE_LUMA_FILTER6, tve->lumafilter5);
+ tve_writel(TVE_LUMA_FILTER7, tve->lumafilter6);
+ tve_writel(TVE_LUMA_FILTER8, tve->lumafilter7);
+ } else {
+ if (tve->input_format == INPUT_FORMAT_RGB)
+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
+ v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
+ v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(0));
+ else
+ tve_writel(TV_CTRL, v_CVBS_MODE(mode) | v_CLK_UPSTREAM_EN(2) |
+ v_TIMING_EN(2) | v_LUMA_FILTER_GAIN(0) |
+ v_LUMA_FILTER_UPSAMPLE(1) | v_CSC_PATH(3));
+
+ tve_writel(TV_LUMA_FILTER0, tve->lumafilter0);
+ tve_writel(TV_LUMA_FILTER1, tve->lumafilter1);
+ tve_writel(TV_LUMA_FILTER2, tve->lumafilter2);
+ }
+
+ if (mode == TVOUT_CVBS_NTSC) {
+ TVEDBG("tve set ntsc mode\n");
+
+ if (tve->soc_type == SOC_RK3528) {
+ bt656_cfg = ntsc_bt656_config;
+ tve_cfg = ntsc_tve_config;
+
+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
+ } else {
+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(1) |
+ v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
+ v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_NTSC) |
+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
+ tve_writel(TV_SATURATION, 0x0042543C);
+ if (tve->test_mode)
+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00008300);
+ else
+ tve_writel(TV_BRIGHTNESS_CONTRAST, 0x00007900);
+
+ tve_writel(TV_FREQ_SC, 0x21F07BD7);
+ tve_writel(TV_SYNC_TIMING, 0x00C07a81);
+ tve_writel(TV_ADJ_TIMING, 0x96B40000 | 0x70);
+ tve_writel(TV_ACT_ST, 0x001500D6);
+ tve_writel(TV_ACT_TIMING, 0x069800FC | (1 << 12) | (1 << 28));
+ }
+ } else if (mode == TVOUT_CVBS_PAL) {
+ TVEDBG("tve set pal mode\n");
+
+ if (tve->soc_type == SOC_RK3528) {
+ bt656_cfg = pal_bt656_config;
+ tve_cfg = pal_tve_config;
+
+ tve_write_block(tve, bt656_cfg, BT656_ENV_CONFIG_SIZE);
+ tve_write_block(tve, tve_cfg, TVE_ENV_CONFIG_SIZE);
+ } else {
+ tve_writel(TV_ROUTING, v_DAC_SENSE_EN(0) | v_Y_IRE_7_5(0) |
+ v_Y_AGC_PULSE_ON(0) | v_Y_VIDEO_ON(1) |
+ v_YPP_MODE(1) | v_Y_SYNC_ON(1) | v_PIC_MODE(mode));
+ tve_writel(TV_BW_CTRL, v_CHROMA_BW(BP_FILTER_PAL) |
+ v_COLOR_DIFF_BW(COLOR_DIFF_FILTER_BW_1_3));
+
+ tve_writel(TV_SATURATION, tve->saturation);
+ tve_writel(TV_BRIGHTNESS_CONTRAST, tve->brightcontrast);
+
+ tve_writel(TV_FREQ_SC, 0x2A098ACB);
+ tve_writel(TV_SYNC_TIMING, 0x00C28381);
+ tve_writel(TV_ADJ_TIMING, (0xc << 28) | 0x06c00800 | 0x80);
+ tve_writel(TV_ACT_ST, 0x001500F6);
+ tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
+
+ tve_writel(TV_ADJ_TIMING, tve->adjtiming);
+ tve_writel(TV_ACT_TIMING, 0x0694011D | (1 << 12) | (2 << 28));
+ }
+ }
+
+ if (tve->soc_type == SOC_RK3528) {
+ u32 upsample_mode = 0;
+ u32 mask = 0;
+ u32 val = 0;
+ bool upsample_en;
+
+ upsample_en = tve->upsample_mode ? 1 : 0;
+ if (upsample_en)
+ upsample_mode = tve->upsample_mode - 1;
+ mask = m_TVE_DCLK_POL | m_TVE_DCLK_EN | m_DCLK_UPSAMPLE_2X4X |
+ m_DCLK_UPSAMPLE_EN | m_TVE_MODE | m_TVE_EN;
+ val = v_TVE_DCLK_POL(0) | v_TVE_DCLK_EN(1) | v_DCLK_UPSAMPLE_2X4X(upsample_mode) |
+ v_DCLK_UPSAMPLE_EN(upsample_en) | v_TVE_MODE(tve->tv_format) | v_TVE_EN(1);
+
+ tve_grf_writel(RK3528_VO_GRF_CVBS_CON, (mask << 16) | val);
+ }
+}
+
+static void dac_init(struct rockchip_tve *tve)
+{
+ tve_dac_writel(VDAC_VDAC1, v_CUR_REG(tve->dac1level) |
+ m_DR_PWR_DOWN | m_BG_PWR_DOWN);
+ tve_dac_writel(VDAC_VDAC2, v_CUR_CTR(tve->daclevel));
+ tve_dac_writel(VDAC_VDAC3, v_CAB_EN(0));
+}
+
+static void dac_enable(struct rockchip_tve *tve, bool enable)
+{
+ u32 mask = 0;
+ u32 val = 0;
+ u32 grfreg = 0;
+ u32 offset = 0;
+
+ if (enable) {
+ TVEDBG("tve enable\n");
+
+ if (tve->soc_type == SOC_RK3036) {
+ mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
+ val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
+ grfreg = RK3036_GRF_SOC_CON3;
+ } else if (tve->soc_type == SOC_RK312X) {
+ mask = m_VBG_EN | m_DAC_EN | m_DAC_GAIN;
+ val = m_VBG_EN | m_DAC_EN | v_DAC_GAIN(tve->daclevel);
+ grfreg = RK312X_GRF_TVE_CON;
+ } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+ val = v_CUR_REG(tve->dac1level) | v_DR_PWR_DOWN(0) | v_BG_PWR_DOWN(0);
+ } else if (tve->soc_type == SOC_RK3528) {
+ /*
+ * Reset the vdac
+ */
+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(0) | v_DIGITAL_RST(0));
+ mdelay(20);
+ tve_dac_writel(VDAC_CLK_RST, v_ANALOG_RST(1) | v_DIGITAL_RST(1));
+
+ tve_dac_writel(VDAC_CURRENT_CTRL, v_OUT_CURRENT(0xd2));
+
+ val = v_REF_VOLTAGE(7) | v_DAC_PWN(1) | v_BIAS_PWN(1);
+ offset = VDAC_PWM_REF_CTRL;
+ }
+ } else {
+ TVEDBG("tve disable\n");
+
+ if (tve->soc_type == SOC_RK312X) {
+ mask = m_VBG_EN | m_DAC_EN;
+ grfreg = RK312X_GRF_TVE_CON;
+ } else if (tve->soc_type == SOC_RK3036) {
+ mask = m_VBG_EN | m_DAC_EN;
+ grfreg = RK3036_GRF_SOC_CON3;
+ } else if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+ val = v_CUR_REG(tve->dac1level) | m_DR_PWR_DOWN | m_BG_PWR_DOWN;
+ offset = VDAC_VDAC1;
+ } else if (tve->soc_type == SOC_RK3528) {
+ val = v_DAC_PWN(0) | v_BIAS_PWN(0);
+ offset = VDAC_PWM_REF_CTRL;
+ }
+ }
+
+ if (grfreg)
+ tve_grf_writel(grfreg, (mask << 16) | val);
+ else if (tve->vdac_base)
+ tve_dac_writel(offset, val);
+}
+
+static u8 rk_get_vdac_value(void)
+{
+ u8 value = 0;
+#ifdef CONFIG_ROCKCHIP_EFUSE
+#if defined(CONFIG_ROCKCHIP_RK322X)
+ struct udevice *dev;
+ u32 regs[2] = {0};
+ u8 fuses[1];
+ ofnode node;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC, DM_GET_DRIVER(rockchip_efuse), &dev);
+ if (ret) {
+ printf("%s: no misc-device found\n", __func__);
+ return -EINVAL;
+ }
+
+ node = dev_read_subnode(dev, "tve_dac");
+ if (!ofnode_valid(node))
+ return -EINVAL;
+
+ ret = ofnode_read_u32_array(node, "reg", regs, 2);
+ if (ret) {
+ printf("Cannot get efuse reg\n");
+ return -EINVAL;
+ }
+
+ ret = misc_read(dev, regs[0], &fuses, regs[1]);
+ if (ret) {
+ printf("%s: misc_read failed\n", __func__);
+ return 0;
+ }
+
+ value = fuses[0];
+ value = (value >> 3) & 0x1f;
+#endif
+#endif /* CONFIG_RK_EFUSE */
+ if (value > 0)
+ value += 5;
+ TVEDBG("%s value = 0x%x\n", __func__, value);
+
+ return value;
+}
+
+static int tve_parse_dt(struct rockchip_tve *tve)
+{
+ tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1);
+ if (tve->preferred_mode < 0) {
+ tve->preferred_mode = 0;
+ } else if (tve->preferred_mode > 1) {
+ printf("tve mode value invalid\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0);
+ if (tve->lumafilter0 == 0) {
+ printf("tve get lumafilter0 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0);
+ if (tve->lumafilter1 == 0) {
+ printf("tve get lumafilter1 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0);
+ if (tve->lumafilter2 == 0) {
+ printf("tve get lumafilter2 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter3 = dev_read_u32_default(tve->dev, "rockchip,lumafilter3", 0);
+ if (tve->lumafilter3 == 0) {
+ printf("tve get lumafilter3 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter4 = dev_read_u32_default(tve->dev, "rockchip,lumafilter4", 0);
+ if (tve->lumafilter4 == 0) {
+ printf("tve get lumafilter4 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter5 = dev_read_u32_default(tve->dev, "rockchip,lumafilter5", 0);
+ if (tve->lumafilter5 == 0) {
+ printf("tve get lumafilter5 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter6 = dev_read_u32_default(tve->dev, "rockchip,lumafilter6", 0);
+ if (tve->lumafilter6 == 0) {
+ printf("tve get lumafilter6 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter7 = dev_read_u32_default(tve->dev, "rockchip,lumafilter7", 0);
+ if (tve->lumafilter7 == 0) {
+ printf("tve get lumafilter7 err\n");
+ return -EINVAL;
+ }
+
+ tve->upsample_mode = dev_read_u32_default(tve->dev, "rockchip,tve-upsample", -1);
+ if (tve->upsample_mode < 0 || tve->upsample_mode > DCLK_UPSAMPLEx4) {
+ printf("tve get upsample_mode err\n");
+ return -EINVAL;
+ }
+
+ TVEDBG("tve->preferred_mode = 0x%x\n", tve->preferred_mode);
+ TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0);
+ TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1);
+ TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2);
+ TVEDBG("tve->lumafilter3 = 0x%x\n", tve->lumafilter3);
+ TVEDBG("tve->lumafilter4 = 0x%x\n", tve->lumafilter4);
+ TVEDBG("tve->lumafilter5 = 0x%x\n", tve->lumafilter5);
+ TVEDBG("tve->lumafilter6 = 0x%x\n", tve->lumafilter6);
+ TVEDBG("tve->lumafilter7 = 0x%x\n", tve->lumafilter7);
+ TVEDBG("tve->upsample_mode = 0x%x\n", tve->upsample_mode);
+
+ return 0;
+}
+
+static int tve_parse_dt_legacy(struct rockchip_tve *tve)
+{
+ int dac_value, getvdac;
+
+ if (tve->soc_type == SOC_RK312X)
+ tve->test_mode = dev_read_u32_default(tve->dev, "test_mode", 0);
+
+ tve->preferred_mode = dev_read_u32_default(tve->dev, "rockchip,tvemode", -1);
+ if (tve->preferred_mode < 0) {
+ tve->preferred_mode = 0;
+ } else if (tve->preferred_mode > 1) {
+ printf("tve mode value invalid\n");
+ return -EINVAL;
+ }
+
+ tve->saturation = dev_read_u32_default(tve->dev, "rockchip,saturation", 0);
+ if (tve->saturation == 0) {
+ printf("tve get saturation err\n");
+ return -EINVAL;
+ }
+
+ tve->brightcontrast = dev_read_u32_default(tve->dev, "rockchip,brightcontrast", 0);
+ if (tve->brightcontrast == 0) {
+ printf("tve get brightcontrast err\n");
+ return -EINVAL;
+ }
+
+ tve->adjtiming = dev_read_u32_default(tve->dev, "rockchip,adjtiming", 0);
+ if (tve->adjtiming == 0) {
+ printf("tve get adjtiming err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter0 = dev_read_u32_default(tve->dev, "rockchip,lumafilter0", 0);
+ if (tve->lumafilter0 == 0) {
+ printf("tve get lumafilter0 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter1 = dev_read_u32_default(tve->dev, "rockchip,lumafilter1", 0);
+ if (tve->lumafilter1 == 0) {
+ printf("tve get lumafilter1 err\n");
+ return -EINVAL;
+ }
+
+ tve->lumafilter2 = dev_read_u32_default(tve->dev, "rockchip,lumafilter2", 0);
+ if (tve->lumafilter2 == 0) {
+ printf("tve get lumafilter2 err\n");
+ return -EINVAL;
+ }
+
+ dac_value = dev_read_u32_default(tve->dev, "rockchip,daclevel", 0);
+ if (dac_value == 0) {
+ printf("tve get dac_value err\n");
+ return -EINVAL;
+ }
+
+ tve->daclevel = dac_value;
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+ getvdac = rk_get_vdac_value();
+ if (getvdac > 0) {
+ tve->daclevel = dac_value + getvdac - RK322X_VDAC_STANDARD;
+ if (tve->daclevel > 0x3f || tve->daclevel < 0) {
+ printf("rk322x daclevel error!\n");
+ tve->daclevel = dac_value;
+ }
+ } else if (getvdac < 0) {
+ printf("get rk322x daclevel error\n");
+ return -EINVAL;
+ }
+ }
+
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328) {
+ tve->dac1level = dev_read_u32_default(tve->dev, "rockchip,dac1level", 0);
+ if (tve->dac1level == 0) {
+ printf("rk322x dac1level error!\n");
+ return -EINVAL;
+ }
+ }
+
+ TVEDBG("tve->test_mode = 0x%x\n", tve->test_mode);
+ TVEDBG("tve->saturation = 0x%x\n", tve->saturation);
+ TVEDBG("tve->brightcontrast = 0x%x\n", tve->brightcontrast);
+ TVEDBG("tve->adjtiming = 0x%x\n", tve->adjtiming);
+ TVEDBG("tve->lumafilter0 = 0x%x\n", tve->lumafilter0);
+ TVEDBG("tve->lumafilter1 = 0x%x\n", tve->lumafilter1);
+ TVEDBG("tve->lumafilter2 = 0x%x\n", tve->lumafilter2);
+ TVEDBG("tve->daclevel = 0x%x\n", tve->daclevel);
+
+ return 0;
+}
+
+static int rockchip_drm_tve_init(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
+ struct connector_state *conn_state = &state->conn_state;
+ fdt_addr_t addr;
+ int ret;
+
+ conn_state->output_mode = ROCKCHIP_OUT_MODE_P888;
+ conn_state->bus_format = MEDIA_BUS_FMT_YUV8_1X24;
+ if (tve->soc_type == SOC_RK3528)
+ conn_state->output_if |= VOP_OUTPUT_IF_BT656;
+ conn_state->color_space = V4L2_COLORSPACE_SMPTE170M;
+
+ conn_state->disp_info = rockchip_get_disp_info(conn_state->type, 0);
+
+ if (tve->soc_type == SOC_RK3528)
+ ret = tve_parse_dt(tve);
+ else
+ ret = tve_parse_dt_legacy(tve);
+ if (ret) {
+ printf("tve parse dts error\n");
+ return -EINVAL;
+ }
+
+ addr = dev_read_addr_index(conn->dev, 0);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("failed to get tve reg_base\n");
+ return -EINVAL;
+ }
+ tve->reg_base = (void *)addr;
+
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328 ||
+ tve->soc_type == SOC_RK3528) {
+ addr = dev_read_addr_index(conn->dev, 1);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("failed to get tve vdac_base\n");
+ return -EINVAL;
+ }
+ tve->vdac_base = (void *)addr;
+ }
+
+ tve->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
+ if (tve->soc_type == SOC_RK322X || tve->soc_type == SOC_RK3328)
+ dac_init(tve);
+
+ return 0;
+}
+
+static int rockchip_drm_tve_enable(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+
+#ifdef CONFIG_ROCKCHIP_INNO_HDMI_PHY
+ /* set inno hdmi phy clk. */
+ if (tve->soc_type != SOC_RK3528)
+ rockchip_phy_set_pll(conn->phy, 27000000);
+#endif
+ if (mode->vdisplay == 576)
+ tve->tv_format = TVOUT_CVBS_PAL;
+ else
+ tve->tv_format = TVOUT_CVBS_NTSC;
+
+ tve_set_mode(tve);
+ mdelay(1000);
+ dac_enable(tve, true);
+
+ return 0;
+}
+
+static void rockchip_drm_tve_deinit(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
+
+ dac_enable(tve, false);
+}
+
+static int rockchip_drm_tve_prepare(struct rockchip_connector *conn, struct display_state *state)
+{
+ return 0;
+}
+
+static int rockchip_drm_tve_disable(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
+
+ dac_enable(tve, false);
+
+ return 0;
+}
+
+static int rockchip_drm_tve_detect(struct rockchip_connector *conn, struct display_state *state)
+{
+ return 1;
+}
+
+static void tve_select_output(struct rockchip_tve *tve, struct connector_state *conn_state,
+ struct drm_display_mode *mode)
+{
+ int ret, i, screen_size;
+ struct base_screen_info *screen_info = NULL;
+ struct base2_screen_info *screen_info2 = NULL;
+ struct base_disp_info base_parameter;
+ struct base2_disp_info *base2_parameter = conn_state->disp_info;
+ struct drm_display_mode modes[2];
+ const struct base_overscan *scan;
+ struct overscan *overscan = &conn_state->overscan;
+ char baseparameter_buf[8 * RK_BLK_SIZE] __aligned(ARCH_DMA_MINALIGN);
+ struct blk_desc *dev_desc;
+ disk_partition_t part_info;
+ int max_scan = 100;
+ int min_scan = 50;
+ int offset = 0;
+ bool found = false;
+
+ for (i = 0; i < 2; i++) {
+ modes[i] = tve_modes[i];
+ if (i == tve->preferred_mode)
+ modes[i].type |= DRM_MODE_TYPE_PREFERRED;
+ }
+ *mode = modes[tve->preferred_mode];
+
+ if (!base2_parameter) {
+ dev_desc = rockchip_get_bootdev();
+ if (!dev_desc) {
+ printf("%s: Could not find device\n", __func__);
+ goto null_basep;
+ }
+
+ ret = part_get_info_by_name(dev_desc, "baseparameter",
+ &part_info);
+ if (ret < 0) {
+ printf("Could not find baseparameter partition\n");
+ goto null_basep;
+ }
+
+read_aux:
+ ret = blk_dread(dev_desc, part_info.start + offset, 1,
+ (void *)baseparameter_buf);
+ if (ret < 0) {
+ printf("read baseparameter failed\n");
+ goto null_basep;
+ }
+
+ memcpy(&base_parameter, baseparameter_buf,
+ sizeof(base_parameter));
+ scan = &base_parameter.scan;
+
+ screen_size = sizeof(base_parameter.screen_list) /
+ sizeof(base_parameter.screen_list[0]);
+
+ for (i = 0; i < screen_size; i++) {
+ if (base_parameter.screen_list[i].type ==
+ DRM_MODE_CONNECTOR_TV) {
+ found = true;
+ screen_info = &base_parameter.screen_list[i];
+ break;
+ }
+ }
+
+ if (!found && !offset) {
+ printf("cvbs info isn't saved in main block\n");
+ offset += 16;
+ goto read_aux;
+ }
+ } else {
+ scan = &base2_parameter->overscan_info;
+ screen_size = sizeof(base2_parameter->screen_info) /
+ sizeof(base2_parameter->screen_info[0]);
+
+ for (i = 0; i < screen_size; i++) {
+ if (base2_parameter->screen_info[i].type ==
+ DRM_MODE_CONNECTOR_TV) {
+ screen_info2 =
+ &base2_parameter->screen_info[i];
+ break;
+ }
+ }
+ screen_info = malloc(sizeof(*screen_info));
+
+ screen_info->type = screen_info2->type;
+ screen_info->mode = screen_info2->resolution;
+ screen_info->format = screen_info2->format;
+ screen_info->depth = screen_info2->depthc;
+ screen_info->feature = screen_info2->feature;
+ }
+
+ if (scan->leftscale < min_scan && scan->leftscale > 0)
+ overscan->left_margin = min_scan;
+ else if (scan->leftscale < max_scan && scan->leftscale > 0)
+ overscan->left_margin = scan->leftscale;
+
+ if (scan->rightscale < min_scan && scan->rightscale > 0)
+ overscan->right_margin = min_scan;
+ else if (scan->rightscale < max_scan && scan->rightscale > 0)
+ overscan->right_margin = scan->rightscale;
+
+ if (scan->topscale < min_scan && scan->topscale > 0)
+ overscan->top_margin = min_scan;
+ else if (scan->topscale < max_scan && scan->topscale > 0)
+ overscan->top_margin = scan->topscale;
+
+ if (scan->bottomscale < min_scan && scan->bottomscale > 0)
+ overscan->bottom_margin = min_scan;
+ else if (scan->bottomscale < max_scan && scan->bottomscale > 0)
+ overscan->bottom_margin = scan->bottomscale;
+
+null_basep:
+
+ if (screen_info)
+ printf("cvbs base_parameter.mode:%dx%d\n",
+ screen_info->mode.hdisplay,
+ screen_info->mode.vdisplay);
+
+ if (screen_info &&
+ (screen_info->mode.hdisplay == 720 &&
+ screen_info->mode.vdisplay == 576))
+ *mode = modes[0];
+ else if (screen_info &&
+ (screen_info->mode.hdisplay == 720 &&
+ screen_info->mode.vdisplay == 480))
+ *mode = modes[1];
+}
+
+static int rockchip_drm_tve_get_timing(struct rockchip_connector *conn, struct display_state *state)
+{
+ struct rockchip_tve *tve = dev_get_priv(conn->dev);
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+
+ tve_select_output(tve, conn_state, mode);
+
+ return 0;
+}
+
+const struct rockchip_connector_funcs rockchip_drm_tve_funcs = {
+ .init = rockchip_drm_tve_init,
+ .deinit = rockchip_drm_tve_deinit,
+ .prepare = rockchip_drm_tve_prepare,
+ .enable = rockchip_drm_tve_enable,
+ .disable = rockchip_drm_tve_disable,
+ .get_timing = rockchip_drm_tve_get_timing,
+ .detect = rockchip_drm_tve_detect,
+};
+
+static int rockchip_drm_tve_probe(struct udevice *dev)
+{
+ struct rockchip_tve *tve = dev_get_priv(dev);
+ const struct rockchip_tve_data *data;
+
+ tve->dev = dev;
+ data = (const struct rockchip_tve_data *)dev_get_driver_data(dev);
+ tve->soc_type = data->soc_type;
+ tve->input_format = data->input_format;
+
+ rockchip_connector_bind(&tve->connector, dev, 0, &rockchip_drm_tve_funcs, NULL, DRM_MODE_CONNECTOR_TV);
+
+ return 0;
+}
+
+static const struct rockchip_tve_data rk3036_tve = {
+ .soc_type = SOC_RK3036,
+ .input_format = INPUT_FORMAT_RGB,
+};
+
+static const struct rockchip_tve_data rk312x_tve = {
+ .soc_type = SOC_RK312X,
+ .input_format = INPUT_FORMAT_RGB,
+};
+
+static const struct rockchip_tve_data rk322x_tve = {
+ .soc_type = SOC_RK322X,
+ .input_format = INPUT_FORMAT_YUV,
+};
+
+static const struct rockchip_tve_data rk3328_tve = {
+ .soc_type = SOC_RK3328,
+ .input_format = INPUT_FORMAT_YUV,
+};
+
+static const struct rockchip_tve_data rk3528_tve = {
+ .soc_type = SOC_RK3528,
+ .input_format = INPUT_FORMAT_YUV,
+};
+
+static const struct udevice_id rockchip_drm_tve_ids[] = {
+ { .compatible = "rockchip,rk3036-tve", .data = (ulong)&rk3036_tve },
+ { .compatible = "rockchip,rk312x-tve", .data = (ulong)&rk312x_tve },
+ { .compatible = "rockchip,rk322x-tve", .data = (ulong)&rk322x_tve },
+ { .compatible = "rockchip,rk3328-tve", .data = (ulong)&rk3328_tve },
+ { .compatible = "rockchip,rk3528-tve", .data = (ulong)&rk3528_tve },
+};
+
+U_BOOT_DRIVER(rockchip_drm_tve) = {
+ .name = "rockchip_drm_tve",
+ .id = UCLASS_DISPLAY,
+ .of_match = rockchip_drm_tve_ids,
+ .probe = rockchip_drm_tve_probe,
+ .priv_auto_alloc_size = sizeof(struct rockchip_tve),
+};
diff --git a/u-boot/drivers/video/drm/rockchip_tve.h b/u-boot/drivers/video/drm/rockchip_tve.h
new file mode 100644
index 0000000..5cf5f21
--- /dev/null
+++ b/u-boot/drivers/video/drm/rockchip_tve.h
@@ -0,0 +1,253 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ * (C) Copyright 2008-2015 Fuzhou Rockchip Electronics Co., Ltd
+ */
+#ifndef __ROCKCHIP_TVE_H__
+#define __ROCKCHIP_TVE_H__
+
+#define RK3036_GRF_SOC_CON3 0x0154
+#define RK312X_GRF_TVE_CON 0x0170
+ #define m_EXTREF_EN BIT(0)
+ #define m_VBG_EN BIT(1)
+ #define m_DAC_EN BIT(2)
+ #define m_SENSE_EN BIT(3)
+ #define m_BIAS_EN (7 << 4)
+ #define m_DAC_GAIN (0x3f << 7)
+ #define v_DAC_GAIN(x) (((x) & 0x3f) << 7)
+
+#define TV_CTRL (0x00)
+ #define m_CVBS_MODE BIT(24)
+ #define m_CLK_UPSTREAM_EN (3 << 18)
+ #define m_TIMING_EN (3 << 16)
+ #define m_LUMA_FILTER_GAIN (3 << 9)
+ #define m_LUMA_FILTER_BW BIT(8)
+ #define m_CSC_PATH (3 << 1)
+
+ #define v_CVBS_MODE(x) (((x) & 1) << 24)
+ #define v_CLK_UPSTREAM_EN(x) (((x) & 3) << 18)
+ #define v_TIMING_EN(x) (((x) & 3) << 16)
+ #define v_LUMA_FILTER_GAIN(x) (((x) & 3) << 9)
+ #define v_LUMA_FILTER_UPSAMPLE(x) (((x) & 1) << 8)
+ #define v_CSC_PATH(x) (((x) & 3) << 1)
+
+#define TV_SYNC_TIMING (0x04)
+#define TV_ACT_TIMING (0x08)
+#define TV_ADJ_TIMING (0x0c)
+#define TV_FREQ_SC (0x10)
+#define TV_LUMA_FILTER0 (0x14)
+#define TV_LUMA_FILTER1 (0x18)
+#define TV_LUMA_FILTER2 (0x1C)
+#define TV_ACT_ST (0x34)
+#define TV_ROUTING (0x38)
+ #define m_DAC_SENSE_EN BIT(27)
+ #define m_Y_IRE_7_5 BIT(19)
+ #define m_Y_AGC_PULSE_ON BIT(15)
+ #define m_Y_VIDEO_ON BIT(11)
+ #define m_Y_SYNC_ON BIT(7)
+ #define m_YPP_MODE BIT(3)
+ #define m_MONO_EN BIT(2)
+ #define m_PIC_MODE BIT(1)
+
+ #define v_DAC_SENSE_EN(x) (((x) & 1) << 27)
+ #define v_Y_IRE_7_5(x) (((x) & 1) << 19)
+ #define v_Y_AGC_PULSE_ON(x) (((x) & 1) << 15)
+ #define v_Y_VIDEO_ON(x) (((x) & 1) << 11)
+ #define v_Y_SYNC_ON(x) (((x) & 1) << 7)
+ #define v_YPP_MODE(x) (((x) & 1) << 3)
+ #define v_MONO_EN(x) (((x) & 1) << 2)
+ #define v_PIC_MODE(x) (((x) & 1) << 1)
+
+#define TV_SYNC_ADJUST (0x50)
+#define TV_STATUS (0x54)
+#define TV_RESET (0x68)
+ #define m_RESET BIT(1)
+ #define v_RESET(x) (((x) & 1) << 1)
+#define TV_SATURATION (0x78)
+#define TV_BW_CTRL (0x8C)
+ #define m_CHROMA_BW (3 << 4)
+ #define m_COLOR_DIFF_BW (0xf)
+
+ enum {
+ BP_FILTER_PASS = 0,
+ BP_FILTER_NTSC,
+ BP_FILTER_PAL,
+ };
+ enum {
+ COLOR_DIFF_FILTER_OFF = 0,
+ COLOR_DIFF_FILTER_BW_0_6,
+ COLOR_DIFF_FILTER_BW_1_3,
+ COLOR_DIFF_FILTER_BW_2_0
+ };
+
+ #define v_CHROMA_BW(x) ((3 & (x)) << 4)
+ #define v_COLOR_DIFF_BW(x) (0xF & (x))
+
+#define TV_BRIGHTNESS_CONTRAST (0x90)
+
+#define VDAC_VDAC0 (0x00)
+ #define m_RST_ANA BIT(7)
+ #define m_RST_DIG BIT(6)
+
+ #define v_RST_ANA(x) (((x) & 1) << 7)
+ #define v_RST_DIG(x) (((x) & 1) << 6)
+#define VDAC_VDAC1 (0x280)
+ #define m_CUR_REG (0xf << 4)
+ #define m_DR_PWR_DOWN BIT(1)
+ #define m_BG_PWR_DOWN BIT(0)
+
+ #define v_CUR_REG(x) (((x) & 0xf) << 4)
+ #define v_DR_PWR_DOWN(x) (((x) & 1) << 1)
+ #define v_BG_PWR_DOWN(x) (((x) & 1) << 0)
+#define VDAC_VDAC2 (0x284)
+ #define m_CUR_CTR (0X3f)
+
+ #define v_CUR_CTR(x) (((x) & 0x3f))
+#define VDAC_VDAC3 (0x288)
+ #define m_CAB_EN BIT(5)
+ #define m_CAB_REF BIT(4)
+ #define m_CAB_FLAG BIT(0)
+
+ #define v_CAB_EN(x) (((x) & 1) << 5)
+ #define v_CAB_REF(x) (((x) & 1) << 4)
+ #define v_CAB_FLAG(x) (((x) & 1) << 0)
+
+// RK3528 CVBS GRF
+#define RK3528_VO_GRF_VDAC_DIS 0x60000
+ #define m_VDAC_DIS_NEGE_ST BIT(2)
+ #define m_VDAC_DIS_POSE_ST BIT(1)
+ #define m_STAT_VDAC_DISDET BIT(0)
+
+ #define v_VDAC_DIS_NEGE_ST(x) (((x) & 1) << 2)
+ #define v_VDAC_DIS_POSE_ST(x) (((x) & 1) << 1)
+ #define v_STAT_VDAC_DISDET(x) (((x) & 1) << 0)
+
+#define RK3528_VO_GRF_CVBS_CON 0x60010
+ #define m_VDAC_DIS_INT_EN BIT(8)
+ #define m_VDAC_DIS_NEGE_MASK BIT(7)
+ #define m_VDAC_DIS_POSE_MASK BIT(6)
+ #define m_TVE_DCLK_POL BIT(5)
+ #define m_TVE_DCLK_EN BIT(4)
+ #define m_DCLK_UPSAMPLE_2X4X BIT(3)
+ #define m_DCLK_UPSAMPLE_EN BIT(2)
+ #define m_TVE_MODE BIT(1)
+ #define m_TVE_EN BIT(0)
+
+ #define v_VDAC_DIS_INT_EN(x) (((x) & 1) << 8)
+ #define v_VDAC_DIS_NEGE_MASK(x) (((x) & 1) << 7)
+ #define v_VDAC_DIS_POSE_MASK(x) (((x) & 1) << 6)
+ #define v_TVE_DCLK_POL(x) (((x) & 1) << 5)
+ #define v_TVE_DCLK_EN(x) (((x) & 1) << 4)
+ #define v_DCLK_UPSAMPLE_2X4X(x) (((x) & 1) << 3)
+ #define v_DCLK_UPSAMPLE_EN(x) (((x) & 1) << 2)
+ #define v_TVE_MODE(x) (((x) & 1) << 1)
+ #define v_TVE_EN(x) (((x) & 1) << 0)
+
+// RK3528 CVBS TVE
+#define BT656_DECODER_CTRL (0x3D00)
+#define BT656_DECODER_CROP (0x3D04)
+#define BT656_DECODER_SIZE (0x3D08)
+#define BT656_DECODER_HTOTAL_HS_END (0x3D0C)
+#define BT656_DECODER_VACT_ST_HACT_ST (0x3D10)
+#define BT656_DECODER_VTOTAL_VS_END (0x3D14)
+#define BT656_DECODER_VS_ST_END_F1 (0x3D18)
+#define BT656_DECODER_DBG_REG (0x3D1C)
+#define TVE_MODE_CTRL (0x3E00)
+#define TVE_HOR_TIMING1 (0x3E04)
+#define TVE_HOR_TIMING2 (0x3E08)
+#define TVE_HOR_TIMING3 (0x3E0C)
+#define TVE_SUB_CAR_FRQ (0x3E10)
+#define TVE_LUMA_FILTER1 (0x3E14)
+#define TVE_LUMA_FILTER2 (0x3E18)
+#define TVE_LUMA_FILTER3 (0x3E1C)
+#define TVE_LUMA_FILTER4 (0x3E20)
+#define TVE_LUMA_FILTER5 (0x3E24)
+#define TVE_LUMA_FILTER6 (0x3E28)
+#define TVE_LUMA_FILTER7 (0x3E2C)
+#define TVE_LUMA_FILTER8 (0x3E30)
+#define TVE_IMAGE_POSITION (0x3E34)
+#define TVE_ROUTING (0x3E38)
+#define TVE_SYNC_ADJUST (0x3E50)
+#define TVE_STATUS (0x3E54)
+#define TVE_CTRL (0x3E68)
+#define TVE_INTR_STATUS (0x3E6C)
+#define TVE_INTR_EN (0x3E70)
+#define TVE_INTR_CLR (0x3E74)
+#define TVE_COLOR_BUSRT_SAT (0x3E78)
+#define TVE_CHROMA_BANDWIDTH (0x3E8C)
+#define TVE_BRIGHTNESS_CONTRAST (0x3E90)
+#define TVE_ID (0x3E98)
+#define TVE_REVISION (0x3E9C)
+#define TVE_CLAMP (0x3EA0)
+
+// RK3528 CVBS VDAC
+#define VDAC_CLK_RST (0x0000)
+ #define m_ANALOG_RST BIT(7)
+ #define m_DIGITAL_RST BIT(6)
+ #define m_INPUT_CLK_INV BIT(0)
+
+ #define v_ANALOG_RST(x) (((x) & 1) << 7)
+ #define v_DIGITAL_RST(x) (((x) & 1) << 6)
+ #define v_INPUT_CLK_INV(x) (((x) & 1) << 0)
+#define VDAC_SINE_CTRL (0x0004)
+#define VDAC_SQUARE_CTRL (0x0008)
+#define VDAC_LEVEL_CTRL0 (0x0018)
+#define VDAC_LEVEL_CTRL1 (0x001C)
+#define VDAC_PWM_REF_CTRL (0x0280)
+ #define m_REF_VOLTAGE (0xf << 4)
+ #define m_REF_RESISTOR BIT(3)
+ #define m_SMP_CLK_INV BIT(2)
+ #define m_DAC_PWN BIT(1)
+ #define m_BIAS_PWN BIT(0)
+
+ #define v_REF_VOLTAGE(x) (((x) & 0xf) << 4)
+ #define v_SMP_CLK_INV(x) (((x) & 1) << 2)
+ #define v_REF_RESISTOR(x) (((x) & 1) << 3)
+ #define v_DAC_PWN(x) (((x) & 1) << 1)
+ #define v_BIAS_PWN(x) (((x) & 1) << 0)
+#define VDAC_CURRENT_CTRL (0x0284)
+ #define m_OUT_CURRENT (0xff << 0)
+
+ #define v_OUT_CURRENT(x) (((x) & 0xff) << 0)
+#define VDAC_CABLE_CTRL (0x0288)
+#define VDAC_VOLTAGE_CTRL (0x028C)
+#define VDAC_BIAS_CLK_CTRL0 (0x0290)
+#define VDAC_BIAS_CLK_CTRL1 (0x0294)
+#define VDAC_AUTO_CLK_CTRL0 (0x0298)
+#define VDAC_AUTO_CLK_CTRL1 (0x029C)
+
+enum {
+ TVOUT_CVBS_NTSC = 0,
+ TVOUT_CVBS_PAL,
+};
+
+enum {
+ INPUT_FORMAT_RGB = 0,
+ INPUT_FORMAT_YUV
+};
+
+enum {
+ SOC_RK3036 = 0,
+ SOC_RK312X,
+ SOC_RK322X,
+ SOC_RK3328,
+ SOC_RK3528
+};
+
+
+enum {
+ DCLK_UPSAMPLEx1 = 0,
+ DCLK_UPSAMPLEx2,
+ DCLK_UPSAMPLEx4
+};
+
+#define RK30_TVE_REGBASE 0x10118000 + 0x200
+#define MAX_TVE_COUNT 2
+
+#ifdef TVEDEBUG
+#define TVEDBG(format, ...) \
+ printf("TVE: " format, ## __VA_ARGS__)
+#else
+#define TVEDBG(format, ...)
+#endif
+
+#endif /* __ROCKCHIP_TVE_H__ */
diff --git a/u-boot/drivers/video/drm/rockchip_vop.c b/u-boot/drivers/video/drm/rockchip_vop.c
index e0ce7cf..fb90de8 100644
--- a/u-boot/drivers/video/drm/rockchip_vop.c
+++ b/u-boot/drivers/video/drm/rockchip_vop.c
@@ -97,6 +97,19 @@
return false;
}
+static bool is_rb_swap(uint32_t bus_format, uint32_t output_mode)
+{
+ /*
+ * The default component order of serial rgb3x8 formats
+ * is BGR. So it is needed to enable RB swap.
+ */
+ if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 ||
+ bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8)
+ return true;
+ else
+ return false;
+}
+
static int rockchip_vop_init_gamma(struct vop *vop, struct display_state *state)
{
struct crtc_state *crtc_state = &state->crtc_state;
@@ -298,7 +311,7 @@
VOP_CTRL_SET(vop, win_channel[2], 0x56);
VOP_CTRL_SET(vop, dsp_blank, 0);
- dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
/* For improving signal quality, dclk need to be inverted by default on rv1106. */
if ((VOP_MAJOR(vop->version) == 2 && VOP_MINOR(vop->version) == 12))
dclk_inv = !dclk_inv;
@@ -403,8 +416,9 @@
VOP_CTRL_SET(vop, hdmi_dclk_out_en,
conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420 ? 1 : 0);
- if (is_uv_swap(conn_state->bus_format, conn_state->output_mode))
- VOP_CTRL_SET(vop, dsp_data_swap, DSP_RB_SWAP);
+ if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) ||
+ is_rb_swap(conn_state->bus_format, conn_state->output_mode))
+ VOP_CTRL_SET(vop, dsp_rb_swap, 1);
else
VOP_CTRL_SET(vop, dsp_data_swap, 0);
@@ -888,6 +902,16 @@
return 0;
}
+static int rockchip_vop_mode_fixup(struct display_state *state)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
+
+ return 0;
+}
+
const struct rockchip_crtc_funcs rockchip_vop_funcs = {
.preinit = rockchip_vop_preinit,
.init = rockchip_vop_init,
@@ -899,4 +923,5 @@
.send_mcu_cmd = rockchip_vop_send_mcu_cmd,
.mode_valid = rockchip_vop_mode_valid,
.plane_check = rockchip_vop_plane_check,
+ .mode_fixup = rockchip_vop_mode_fixup,
};
diff --git a/u-boot/drivers/video/drm/rockchip_vop.h b/u-boot/drivers/video/drm/rockchip_vop.h
index c75550d..aa2209d 100644
--- a/u-boot/drivers/video/drm/rockchip_vop.h
+++ b/u-boot/drivers/video/drm/rockchip_vop.h
@@ -298,6 +298,11 @@
struct vop_reg dsp_out_yuv;
struct vop_reg dsp_data_swap;
+ struct vop_reg dsp_bg_swap;
+ struct vop_reg dsp_rb_swap;
+ struct vop_reg dsp_rg_swap;
+ struct vop_reg dsp_delta_swap;
+ struct vop_reg dsp_dummy_swap;
struct vop_reg dsp_ccir656_avg;
struct vop_reg dsp_black;
struct vop_reg dsp_blank;
diff --git a/u-boot/drivers/video/drm/rockchip_vop2.c b/u-boot/drivers/video/drm/rockchip_vop2.c
index 4015101..040b54d 100644
--- a/u-boot/drivers/video/drm/rockchip_vop2.c
+++ b/u-boot/drivers/video/drm/rockchip_vop2.c
@@ -17,20 +17,24 @@
#include <linux/list.h>
#include <linux/log2.h>
#include <linux/media-bus-format.h>
-#include <clk.h>
#include <asm/arch/clock.h>
+#include <asm/gpio.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <dm/device.h>
#include <dm/read.h>
+#include <dm/ofnode.h>
#include <fixp-arith.h>
#include <syscon.h>
#include <linux/iopoll.h>
#include <dm/uclass-internal.h>
+#include <stdlib.h>
#include "rockchip_display.h"
#include "rockchip_crtc.h"
#include "rockchip_connector.h"
+#include "rockchip_phy.h"
+#include "rockchip_post_csc.h"
/* System registers definition */
#define RK3568_REG_CFG_DONE 0x000
@@ -40,9 +44,12 @@
#define EN_MASK 1
#define RK3568_AUTO_GATING_CTRL 0x008
+#define AUTO_GATING_EN_SHIFT 31
+#define PORT_DCLK_AUTO_GATING_EN_SHIFT 14
#define RK3568_SYS_AXI_LUT_CTRL 0x024
#define LUT_DMA_EN_SHIFT 0
+#define DSP_VS_T_SEL_SHIFT 16
#define RK3568_DSP_IF_EN 0x028
#define RGB_EN_SHIFT 0
@@ -81,6 +88,9 @@
#define LVDS_DUAL_EN_SHIFT 0
#define LVDS_DUAL_LEFT_RIGHT_EN_SHIFT 1
#define LVDS_DUAL_SWAP_EN_SHIFT 2
+#define BT656_UV_SWAP 4
+#define BT656_YC_SWAP 5
+#define BT656_DCLK_POL 6
#define RK3588_HDMI_DUAL_EN_SHIFT 8
#define RK3588_EDP_DUAL_EN_SHIFT 8
#define RK3588_DP_DUAL_EN_SHIFT 9
@@ -93,15 +103,22 @@
#define IF_CTRL_REG_DONE_IMD_SHIFT 28
#define IF_CRTL_MIPI_DCLK_POL_SHIT 19
#define IF_CRTL_EDP_DCLK_POL_SHIT 15
+#define IF_CTRL_EDP_PIN_POL_MASK 0x7
+#define IF_CTRL_EDP_PIN_POL_SHIFT 12
#define IF_CRTL_HDMI_DCLK_POL_SHIT 7
#define IF_CRTL_HDMI_PIN_POL_MASK 0x7
#define IF_CRTL_HDMI_PIN_POL_SHIT 4
+#define IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT 3
+#define IF_CTRL_RGB_LVDS_PIN_POL_MASK 0x7
+#define IF_CTRL_RGB_LVDS_PIN_POL_SHIFT 0
+
+#define RK3562_MIPI_DCLK_POL_SHIFT 15
+#define RK3562_MIPI_PIN_POL_SHIFT 12
+#define RK3562_IF_PIN_POL_MASK 0x7
#define RK3588_DP0_PIN_POL_SHIFT 8
#define RK3588_DP1_PIN_POL_SHIFT 12
#define RK3588_IF_PIN_POL_MASK 0x7
-
-#define IF_CRTL_RGB_LVDS_DCLK_POL_SHIT 3
#define HDMI_EDP0_DCLK_DIV_SHIFT 16
#define HDMI_EDP0_PIXCLK_DIV_SHIFT 18
@@ -118,6 +135,8 @@
#define GAMMA_AHB_WRITE_SEL_MASK 0x3
#define GAMMA_AHB_WRITE_SEL_SHIFT 12
#define PORT_MERGE_EN_SHIFT 16
+#define ESMART_LB_MODE_SEL_MASK 0x3
+#define ESMART_LB_MODE_SEL_SHIFT 26
#define RK3568_SYS_PD_CTRL 0x034
#define RK3568_VP0_LINE_FLAG 0x70
@@ -145,6 +164,11 @@
#define RK3588_DSC_8K_PD_EN_SHIFT 5
#define RK3588_DSC_4K_PD_EN_SHIFT 6
#define RK3588_ESMART_PD_EN_SHIFT 7
+
+#define RK3588_SYS_VAR_FREQ_CTRL 0x038
+#define RK3588_VP0_LINE_FLAG_OR_EN_SHIFT 20
+#define RK3588_VP0_DSP_HOLD_OR_EN_SHIFT 24
+#define RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT 28
#define RK3568_SYS_STATUS0 0x60
#define RK3588_CLUSTER0_PD_STATUS_SHIFT 8
@@ -212,10 +236,27 @@
#define RK3588_DSC_8K_STATUS 0x220
/* Overlay registers definition */
+#define RK3528_OVL_SYS 0x500
+#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504
+#define RK3528_OVL_SYS_GATING_EN_IMD 0x508
+#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510
+#define RK3528_OVL_SYS_ESMART0_CTRL 0x520
+#define ESMART_DLY_NUM_MASK 0xff
+#define ESMART_DLY_NUM_SHIFT 0
+#define RK3528_OVL_SYS_ESMART1_CTRL 0x524
+#define RK3528_OVL_SYS_ESMART2_CTRL 0x528
+#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C
+#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530
+#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534
+#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538
+#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c
+
+#define RK3528_OVL_PORT0_CTRL 0x600
#define RK3568_OVL_CTRL 0x600
#define OVL_MODE_SEL_MASK 0x1
#define OVL_MODE_SEL_SHIFT 0
#define OVL_PORT_MUX_REG_DONE_IMD_SHIFT 28
+#define RK3528_OVL_PORT0_LAYER_SEL 0x604
#define RK3568_OVL_LAYER_SEL 0x604
#define LAYER_SEL_MASK 0xf
@@ -229,10 +270,27 @@
#define RK3568_CLUSTER0_MIX_DST_COLOR_CTRL 0x614
#define RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x618
#define RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL 0x61C
+#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620
+#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624
+#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628
+#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C
+#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630
+#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634
+#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638
+#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C
+#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640
+#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644
+#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648
+#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C
#define RK3568_MIX0_SRC_COLOR_CTRL 0x650
#define RK3568_MIX0_DST_COLOR_CTRL 0x654
#define RK3568_MIX0_SRC_ALPHA_CTRL 0x658
#define RK3568_MIX0_DST_ALPHA_CTRL 0x65C
+#define RK3528_HDR_SRC_COLOR_CTRL 0x660
+#define RK3528_HDR_DST_COLOR_CTRL 0x664
+#define RK3528_HDR_SRC_ALPHA_CTRL 0x668
+#define RK3528_HDR_DST_ALPHA_CTRL 0x66C
+#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670
#define RK3568_HDR0_SRC_COLOR_CTRL 0x6C0
#define RK3568_HDR0_DST_COLOR_CTRL 0x6C4
#define RK3568_HDR0_SRC_ALPHA_CTRL 0x6C8
@@ -244,6 +302,22 @@
#define RK3568_VP2_BG_MIX_CTRL 0x6E8
#define RK3568_CLUSTER_DLY_NUM 0x6F0
#define RK3568_SMART_DLY_NUM 0x6F8
+
+#define RK3528_OVL_PORT1_CTRL 0x700
+#define RK3528_OVL_PORT1_LAYER_SEL 0x704
+#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720
+#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724
+#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728
+#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C
+#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730
+#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734
+#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738
+#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C
+#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740
+#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744
+#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748
+#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C
+#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770
/* Video Port registers definition */
#define RK3568_VP0_DSP_CTRL 0xC00
@@ -263,6 +337,7 @@
#define POST_DSP_OUT_R2Y_SHIFT 15
#define PRE_DITHER_DOWN_EN_SHIFT 16
#define DITHER_DOWN_EN_SHIFT 17
+#define DITHER_DOWN_MODE_SHIFT 20
#define GAMMA_UPDATE_EN_SHIFT 22
#define DSP_LUT_EN_SHIFT 28
@@ -279,6 +354,9 @@
#define RK3568_VP0_COLOR_BAR_CTRL 0xC08
+
+#define RK3568_VP0_DCLK_SEL 0xC0C
+
#define RK3568_VP0_3D_LUT_CTRL 0xC10
#define VP0_3D_LUT_EN_SHIFT 0
#define VP0_3D_LUT_UPDATE_SHIFT 2
@@ -333,6 +411,50 @@
#define BCSH_EN_SHIFT 31
#define BCSH_EN_MASK 1
+#define RK3528_VP0_ACM_CTRL 0xCD0
+#define POST_CSC_COE00_MASK 0xFFFF
+#define POST_CSC_COE00_SHIFT 16
+#define POST_R2Y_MODE_MASK 0x7
+#define POST_R2Y_MODE_SHIFT 8
+#define POST_CSC_MODE_MASK 0x7
+#define POST_CSC_MODE_SHIFT 3
+#define POST_R2Y_EN_MASK 0x1
+#define POST_R2Y_EN_SHIFT 2
+#define POST_CSC_EN_MASK 0x1
+#define POST_CSC_EN_SHIFT 1
+#define POST_ACM_BYPASS_EN_MASK 0x1
+#define POST_ACM_BYPASS_EN_SHIFT 0
+#define RK3528_VP0_CSC_COE01_02 0xCD4
+#define RK3528_VP0_CSC_COE10_11 0xCD8
+#define RK3528_VP0_CSC_COE12_20 0xCDC
+#define RK3528_VP0_CSC_COE21_22 0xCE0
+#define RK3528_VP0_CSC_OFFSET0 0xCE4
+#define RK3528_VP0_CSC_OFFSET1 0xCE8
+#define RK3528_VP0_CSC_OFFSET2 0xCEC
+
+#define RK3562_VP0_MCU_CTRL 0xCF8
+#define MCU_TYPE_SHIFT 31
+#define MCU_BYPASS_SHIFT 30
+#define MCU_RS_SHIFT 29
+#define MCU_FRAME_ST_SHIFT 28
+#define MCU_HOLD_MODE_SHIFT 27
+#define MCU_CLK_SEL_SHIFT 26
+#define MCU_CLK_SEL_MASK 0x1
+#define MCU_RW_PEND_SHIFT 20
+#define MCU_RW_PEND_MASK 0x3F
+#define MCU_RW_PST_SHIFT 16
+#define MCU_RW_PST_MASK 0xF
+#define MCU_CS_PEND_SHIFT 10
+#define MCU_CS_PEND_MASK 0x3F
+#define MCU_CS_PST_SHIFT 6
+#define MCU_CS_PST_MASK 0xF
+#define MCU_PIX_TOTAL_SHIFT 0
+#define MCU_PIX_TOTAL_MASK 0x3F
+
+#define RK3562_VP0_MCU_RW_BYPASS_PORT 0xCFC
+#define MCU_WRITE_DATA_BYPASS_SHIFT 0
+#define MCU_WRITE_DATA_BYPASS_MASK 0xFFFFFFFF
+
#define RK3568_VP1_DSP_CTRL 0xD00
#define RK3568_VP1_MIPI_CTRL 0xD04
#define RK3568_VP1_COLOR_BAR_CTRL 0xD08
@@ -374,9 +496,20 @@
#define CLUSTER_YUV2RGB_EN_SHIFT 8
#define CLUSTER_RGB2YUV_EN_SHIFT 9
#define CLUSTER_CSC_MODE_SHIFT 10
-#define CLUSTER_YRGB_XSCL_MODE_SHIFT 12
-#define CLUSTER_YRGB_YSCL_MODE_SHIFT 14
+#define CLUSTER_DITHER_UP_EN_SHIFT 18
#define RK3568_CLUSTER0_WIN0_CTRL1 0x1004
+#define RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT 12
+#define RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
+#define RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT 14
+#define AVG2_MASK 0x1
+#define CLUSTER_AVG2_SHIFT 18
+#define AVG4_MASK 0x1
+#define CLUSTER_AVG4_SHIFT 19
+#define RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT 22
+#define CLUSTER_XGT_EN_SHIFT 24
+#define XGT_MODE_MASK 0x3
+#define CLUSTER_XGT_MODE_SHIFT 25
+#define CLUSTER_XAVG_EN_SHIFT 27
#define CLUSTER_YRGB_GT2_SHIFT 28
#define CLUSTER_YRGB_GT4_SHIFT 29
#define RK3568_CLUSTER0_WIN0_CTRL2 0x1008
@@ -399,6 +532,7 @@
#define RK3568_CLUSTER0_WIN0_AFBCD_PIC_OFFSET 0x1064
#define RK3568_CLUSTER0_WIN0_AFBCD_DSP_OFFSET 0x1068
#define RK3568_CLUSTER0_WIN0_AFBCD_CTRL 0x106C
+#define CLUSTER_AFBCD_HALF_BLOCK_SHIFT 7
#define RK3568_CLUSTER0_WIN1_CTRL0 0x1080
#define RK3568_CLUSTER0_WIN1_CTRL1 0x1084
@@ -463,6 +597,8 @@
#define RGB2YUV_EN_SHIFT 1
#define CSC_MODE_SHIFT 2
#define CSC_MODE_MASK 0x3
+#define ESMART_LB_SELECT_SHIFT 12
+#define ESMART_LB_SELECT_MASK 0x3
#define RK3568_ESMART0_CTRL1 0x1804
#define ESMART_AXI_YRGB_ID_MASK 0x1f
@@ -476,10 +612,14 @@
#define ESMART_AXI_ID_SHIFT 1
#define RK3568_ESMART0_REGION0_CTRL 0x1810
-#define REGION0_RB_SWAP_SHIFT 14
#define WIN_EN_SHIFT 0
#define WIN_FORMAT_MASK 0x1f
#define WIN_FORMAT_SHIFT 1
+#define REGION0_DITHER_UP_EN_SHIFT 12
+#define REGION0_RB_SWAP_SHIFT 14
+#define ESMART_XAVG_EN_SHIFT 20
+#define ESMART_XGT_EN_SHIFT 21
+#define ESMART_XGT_MODE_SHIFT 22
#define RK3568_ESMART0_REGION0_YRGB_MST 0x1814
#define RK3568_ESMART0_REGION0_CBR_MST 0x1818
@@ -680,6 +820,13 @@
#define RK3568_SMART1_REGION3_SCL_FACTOR_CBR 0x1EC8
#define RK3568_SMART1_REGION3_SCL_OFFSET 0x1ECC
+/* HDR register definition */
+#define RK3568_HDR_LUT_CTRL 0x2000
+
+#define RK3588_VP3_DSP_CTRL 0xF00
+#define RK3588_CLUSTER2_WIN0_CTRL0 0x1400
+#define RK3588_CLUSTER3_WIN0_CTRL0 0x1600
+
/* DSC 8K/4K register definition */
#define RK3588_DSC_8K_PPS0_3 0x4000
#define RK3588_DSC_8K_CTRL0 0x40A0
@@ -690,10 +837,14 @@
#define DSC_MER_SHIFT 5
#define DSC_EPB_SHIFT 6
#define DSC_EPL_SHIFT 7
+#define DSC_NSLC_MASK 0x7
#define DSC_NSLC_SHIFT 16
#define DSC_SBO_SHIFT 28
#define DSC_IFEP_SHIFT 29
#define DSC_PPS_UPD_SHIFT 31
+#define DSC_CTRL0_DEF_CON ((1 << DSC_EN_SHIFT) | (1 << DSC_RBIT_SHIFT) | (0 << DSC_RBYT_SHIFT) | \
+ (1 << DSC_FLAL_SHIFT) | (1 << DSC_MER_SHIFT) | (0 << DSC_EPB_SHIFT) | \
+ (1 << DSC_EPL_SHIFT) | (1 << DSC_SBO_SHIFT))
#define RK3588_DSC_8K_CTRL1 0x40A4
#define RK3588_DSC_8K_STS0 0x40A8
@@ -705,8 +856,24 @@
#define RK3588_DSC_4K_STS0 0x41A8
#define RK3588_DSC_4K_ERS 0x41C4
+/* RK3528 HDR register definition */
+#define RK3528_HDR_LUT_CTRL 0x2000
+
+/* RK3528 ACM register definition */
+#define RK3528_ACM_CTRL 0x6400
+#define RK3528_ACM_DELTA_RANGE 0x6404
+#define RK3528_ACM_FETCH_START 0x6408
+#define RK3528_ACM_FETCH_DONE 0x6420
+#define RK3528_ACM_YHS_DEL_HY_SEG0 0x6500
+#define RK3528_ACM_YHS_DEL_HY_SEG152 0x6760
+#define RK3528_ACM_YHS_DEL_HS_SEG0 0x6764
+#define RK3528_ACM_YHS_DEL_HS_SEG220 0x6ad4
+#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x6ad8
+#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x6bd8
+
#define RK3568_MAX_REG 0x1ED0
+#define RK3562_GRF_IOC_VO_IO_CON 0x10500
#define RK3568_GRF_VO_CON1 0x0364
#define GRF_BT656_CLK_INV_SHIFT 1
#define GRF_BT1120_CLK_INV_SHIFT 2
@@ -771,11 +938,52 @@
#define VOP2_PLANE_NO_SCALING BIT(16)
-enum vop2_csc_format {
+#define VOP_FEATURE_OUTPUT_10BIT BIT(0)
+#define VOP_FEATURE_AFBDC BIT(1)
+#define VOP_FEATURE_ALPHA_SCALE BIT(2)
+#define VOP_FEATURE_HDR10 BIT(3)
+#define VOP_FEATURE_NEXT_HDR BIT(4)
+/* a feature to splice two windows and two vps to support resolution > 4096 */
+#define VOP_FEATURE_SPLICE BIT(5)
+#define VOP_FEATURE_OVERSCAN BIT(6)
+#define VOP_FEATURE_VIVID_HDR BIT(7)
+#define VOP_FEATURE_POST_ACM BIT(8)
+#define VOP_FEATURE_POST_CSC BIT(9)
+
+#define WIN_FEATURE_HDR2SDR BIT(0)
+#define WIN_FEATURE_SDR2HDR BIT(1)
+#define WIN_FEATURE_PRE_OVERLAY BIT(2)
+#define WIN_FEATURE_AFBDC BIT(3)
+#define WIN_FEATURE_CLUSTER_MAIN BIT(4)
+#define WIN_FEATURE_CLUSTER_SUB BIT(5)
+/* a mirror win can only get fb address
+ * from source win:
+ * Cluster1---->Cluster0
+ * Esmart1 ---->Esmart0
+ * Smart1 ---->Smart0
+ * This is a feather on rk3566
+ */
+#define WIN_FEATURE_MIRROR BIT(6)
+#define WIN_FEATURE_MULTI_AREA BIT(7)
+#define WIN_FEATURE_Y2R_13BIT_DEPTH BIT(8)
+
+#define V4L2_COLORSPACE_BT709F 0xfe
+#define V4L2_COLORSPACE_BT2020F 0xff
+
+enum vop_csc_format {
CSC_BT601L,
CSC_BT709L,
CSC_BT601F,
CSC_BT2020,
+ CSC_BT709L_13BIT,
+ CSC_BT709F_13BIT,
+ CSC_BT2020L_13BIT,
+ CSC_BT2020F_13BIT,
+};
+
+enum vop_csc_bit_depth {
+ CSC_10BIT_DEPTH,
+ CSC_13BIT_DEPTH,
};
enum vop2_pol {
@@ -861,6 +1069,19 @@
VOP_DSC_IF_MIPI_VIDEO_MODE = 3,
};
+enum vop3_pre_scale_down_mode {
+ VOP3_PRE_SCALE_UNSPPORT,
+ VOP3_PRE_SCALE_DOWN_GT,
+ VOP3_PRE_SCALE_DOWN_AVG,
+};
+
+enum vop3_esmart_lb_mode {
+ VOP3_ESMART_8K_MODE,
+ VOP3_ESMART_4K_4K_MODE,
+ VOP3_ESMART_4K_2K_2K_MODE,
+ VOP3_ESMART_2K_2K_2K_2K_MODE,
+};
+
struct vop2_layer {
u8 id;
/**
@@ -886,12 +1107,19 @@
u8 phys_id;
enum vop2_layer_type type;
u8 win_sel_port_offset;
- u8 layer_sel_win_id;
+ u8 layer_sel_win_id[VOP2_VP_MAX];
u8 axi_id;
u8 axi_uv_id;
u8 axi_yrgb_id;
u8 splice_win_id;
u8 pd_id;
+ u8 hsu_filter_mode;
+ u8 hsd_filter_mode;
+ u8 vsu_filter_mode;
+ u8 vsd_filter_mode;
+ u8 hsd_pre_filter_mode;
+ u8 vsd_pre_filter_mode;
+ u8 scale_engine_num;
u32 reg_offset;
u32 max_upscale_factor;
u32 max_downscale_factor;
@@ -901,6 +1129,9 @@
struct vop2_vp_data {
u32 feature;
u8 pre_scan_max_dly;
+ u8 layer_mix_dly;
+ u8 hdr_mix_dly;
+ u8 win_dly;
u8 splice_vp_id;
struct vop_rect max_output;
u32 max_dclk;
@@ -936,8 +1167,18 @@
char dsc_error_info[50];
};
+struct vop2_dump_regs {
+ u32 offset;
+ const char *name;
+ u32 state_base;
+ u32 state_mask;
+ u32 state_shift;
+ bool enable_state;
+};
+
struct vop2_data {
u32 version;
+ u32 esmart_lb_mode;
struct vop2_vp_data *vp_data;
struct vop2_win_data *win_data;
struct vop2_vp_plane_mask *plane_mask;
@@ -946,6 +1187,8 @@
struct vop2_dsc_data *dsc;
struct dsc_error_info *dsc_error_ecw;
struct dsc_error_info *dsc_error_buffer_flow;
+ struct vop2_dump_regs *dump_regs;
+ u8 *vp_primary_plane_order;
u8 nr_vps;
u8 nr_layers;
u8 nr_mixers;
@@ -955,6 +1198,7 @@
u8 nr_dsc_ecw;
u8 nr_dsc_buffer_flow;
u32 reg_len;
+ u32 dump_regs_size;
};
struct vop2 {
@@ -966,12 +1210,22 @@
void *sys_pmu;
u32 reg_len;
u32 version;
+ u32 esmart_lb_mode;
bool global_init;
const struct vop2_data *data;
struct vop2_vp_plane_mask vp_plane_mask[VOP2_VP_MAX];
};
static struct vop2 *rockchip_vop2;
+
+static inline bool is_vop3(struct vop2 *vop2)
+{
+ if (vop2->version == VOP_VERSION_RK3568 || vop2->version == VOP_VERSION_RK3588)
+ return false;
+ else
+ return true;
+}
+
/*
* bli_sd_factor = (src - 1) / (dst - 1) << 12;
* avg_sd_factor:
@@ -979,8 +1233,8 @@
* bic_su_factor:
* = (src - 1) / (dst - 1) << 16;
*
- * gt2 enable: dst get one line from two line of the src
- * gt4 enable: dst get one line from four line of the src.
+ * ygt2 enable: dst get one line from two line of the src
+ * ygt4 enable: dst get one line from four line of the src.
*
*/
#define VOP2_BILI_SCL_DN(src, dst) (((src - 1) << 12) / (dst - 1))
@@ -989,6 +1243,8 @@
#define VOP2_BILI_SCL_FAC_CHECK(src, dst, fac) \
(fac * (dst - 1) >> 12 < (src - 1))
#define VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac) \
+ (fac * (dst - 1) >> 16 < (src - 1))
+#define VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac) \
(fac * (dst - 1) >> 16 < (src - 1))
static uint16_t vop2_scale_factor(enum scale_mode mode,
@@ -1030,6 +1286,51 @@
return fac;
}
+static bool vop3_scale_up_fac_check(uint32_t src, uint32_t dst, uint32_t fac, bool is_hor)
+{
+ if (is_hor)
+ return VOP3_COMMON_HOR_SCL_FAC_CHECK(src, dst, fac);
+ return VOP2_COMMON_SCL_FAC_CHECK(src, dst, fac);
+}
+
+static uint16_t vop3_scale_factor(enum scale_mode mode,
+ uint32_t src, uint32_t dst, bool is_hor)
+{
+ uint32_t fac = 0;
+ int i = 0;
+
+ if (mode == SCALE_NONE)
+ return 0;
+
+ /*
+ * A workaround to avoid zero div.
+ */
+ if ((dst == 1) || (src == 1)) {
+ dst = dst + 1;
+ src = src + 1;
+ }
+
+ if (mode == SCALE_DOWN) {
+ fac = VOP2_BILI_SCL_DN(src, dst);
+ for (i = 0; i < 100; i++) {
+ if (VOP2_BILI_SCL_FAC_CHECK(src, dst, fac))
+ break;
+ fac -= 1;
+ printf("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
+ }
+ } else {
+ fac = VOP2_COMMON_SCL(src, dst);
+ for (i = 0; i < 100; i++) {
+ if (vop3_scale_up_fac_check(src, dst, fac, is_hor))
+ break;
+ fac -= 1;
+ printf("up fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
+ }
+ }
+
+ return fac;
+}
+
static inline enum scale_mode scl_get_scl_mode(int src, int dst)
{
if (src < dst)
@@ -1040,19 +1341,6 @@
return SCALE_NONE;
}
-static u8 rk3588_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
- ROCKCHIP_VOP2_ESMART0,
- ROCKCHIP_VOP2_ESMART1,
- ROCKCHIP_VOP2_ESMART2,
- ROCKCHIP_VOP2_ESMART3,
-};
-
-static u8 rk3568_vop2_vp_primary_plane_order[VOP2_VP_MAX] = {
- ROCKCHIP_VOP2_SMART0,
- ROCKCHIP_VOP2_SMART1,
- ROCKCHIP_VOP2_ESMART1,
-};
-
static inline int interpolate(int x1, int y1, int x2, int y2, int x)
{
return y1 + (y2 - y1) * (x - x1) / (x2 - x1);
@@ -1061,23 +1349,13 @@
static int vop2_get_primary_plane(struct vop2 *vop2, u32 plane_mask)
{
int i = 0;
- u8 *vop2_vp_primary_plane_order;
- u8 default_primary_plane;
- if (vop2->version == VOP_VERSION_RK3588) {
- vop2_vp_primary_plane_order = rk3588_vop2_vp_primary_plane_order;
- default_primary_plane = ROCKCHIP_VOP2_ESMART0;
- } else {
- vop2_vp_primary_plane_order = rk3568_vop2_vp_primary_plane_order;
- default_primary_plane = ROCKCHIP_VOP2_SMART0;
+ for (i = 0; i < vop2->data->nr_layers; i++) {
+ if (plane_mask & BIT(vop2->data->vp_primary_plane_order[i]))
+ return vop2->data->vp_primary_plane_order[i];
}
- for (i = 0; i < vop2->data->nr_vps; i++) {
- if (plane_mask & BIT(vop2_vp_primary_plane_order[i]))
- return vop2_vp_primary_plane_order[i];
- }
-
- return default_primary_plane;
+ return vop2->data->vp_primary_plane_order[0];
}
static inline u16 scl_cal_scale(int src, int dst, int shift)
@@ -1210,6 +1488,7 @@
switch (bus_format) {
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_YUV10_1X30:
+ case MEDIA_BUS_FMT_YUYV10_1X20:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
case MEDIA_BUS_FMT_YUYV8_2X8:
@@ -1226,7 +1505,7 @@
}
}
-static int vop2_convert_csc_mode(int csc_mode)
+static int vop2_convert_csc_mode(int csc_mode, int bit_depth)
{
switch (csc_mode) {
case V4L2_COLORSPACE_SMPTE170M:
@@ -1236,11 +1515,31 @@
case V4L2_COLORSPACE_REC709:
case V4L2_COLORSPACE_SMPTE240M:
case V4L2_COLORSPACE_DEFAULT:
- return CSC_BT709L;
+ if (bit_depth == CSC_13BIT_DEPTH)
+ return CSC_BT709L_13BIT;
+ else
+ return CSC_BT709L;
case V4L2_COLORSPACE_JPEG:
return CSC_BT601F;
case V4L2_COLORSPACE_BT2020:
- return CSC_BT2020;
+ if (bit_depth == CSC_13BIT_DEPTH)
+ return CSC_BT2020L_13BIT;
+ else
+ return CSC_BT2020;
+ case V4L2_COLORSPACE_BT709F:
+ if (bit_depth == CSC_10BIT_DEPTH) {
+ printf("WARN: Unsupported bt709f at 10bit csc depth, use bt601f instead\n");
+ return CSC_BT601F;
+ } else {
+ return CSC_BT709F_13BIT;
+ }
+ case V4L2_COLORSPACE_BT2020F:
+ if (bit_depth == CSC_10BIT_DEPTH) {
+ printf("WARN: Unsupported bt2020f at 10bit csc depth, use bt601f instead\n");
+ return CSC_BT601F;
+ } else {
+ return CSC_BT2020F_13BIT;
+ }
default:
return CSC_BT709L;
}
@@ -1265,6 +1564,19 @@
bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
(output_mode == ROCKCHIP_OUT_MODE_AAAA ||
output_mode == ROCKCHIP_OUT_MODE_P888)))
+ return true;
+ else
+ return false;
+}
+
+static bool is_rb_swap(u32 bus_format, u32 output_mode)
+{
+ /*
+ * The default component order of serial rgb3x8 formats
+ * is BGR. So it is needed to enable RB swap.
+ */
+ if (bus_format == MEDIA_BUS_FMT_SRGB888_3X8 ||
+ bus_format == MEDIA_BUS_FMT_SRGB888_DUMMY_4X8)
return true;
else
return false;
@@ -1533,7 +1845,7 @@
cstate->post_y2r_en = 1;
}
- cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space);
+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
if (cstate->feature & VOP_FEATURE_OUTPUT_10BIT)
brightness = interpolate(0, -128, 100, 127,
@@ -1578,7 +1890,7 @@
u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
bg_ovl_dly = cstate->crtc->vps[crtc_id].bg_ovl_dly;
- bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
+ bg_dly = vop2->data->vp_data[crtc_id].pre_scan_max_dly;
bg_dly -= bg_ovl_dly;
if (cstate->splice_mode)
@@ -1590,6 +1902,33 @@
hsync_len = 8;
pre_scan_dly = (pre_scan_dly << 16) | hsync_len;
vop2_mask_write(vop2, RK3568_VP0_BG_MIX_CTRL + crtc_id * 4,
+ BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
+ vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
+}
+
+static void vop3_setup_pipe_dly(struct display_state *state, struct vop2 *vop2, int crtc_id)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2_win_data *win_data;
+ u32 bg_dly, pre_scan_dly;
+ u16 hdisplay = mode->crtc_hdisplay;
+ u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
+ u8 primary_plane_id = vop2->vp_plane_mask[cstate->crtc_id].primary_plane_id;
+ u8 win_id;
+
+ win_data = vop2_find_win_by_phys_id(vop2, primary_plane_id);
+ win_id = atoi(&win_data->name[strlen(win_data->name) - 1]);
+ vop2_mask_write(vop2, RK3528_OVL_SYS_ESMART0_CTRL + win_id * 4,
+ ESMART_DLY_NUM_MASK, ESMART_DLY_NUM_SHIFT, 0, false);
+
+ bg_dly = vop2->data->vp_data[crtc_id].win_dly +
+ vop2->data->vp_data[crtc_id].layer_mix_dly +
+ vop2->data->vp_data[crtc_id].hdr_mix_dly;
+ pre_scan_dly = bg_dly + (hdisplay >> 1) - 1;
+ pre_scan_dly = (pre_scan_dly << 16) | hsync_len;
+ vop2_mask_write(vop2, RK3528_OVL_PORT0_BG_MIX_CTRL + crtc_id * 0x100,
BG_MIX_CTRL_MASK, BG_MIX_CTRL_SHIFT, bg_dly, false);
vop2_writel(vop2, RK3568_VP0_PRE_SCAN_HTIMING + (crtc_id * 0x100), pre_scan_dly);
}
@@ -1644,9 +1983,176 @@
vop2_writel(vop2, RK3568_VP0_POST_DSP_VACT_INFO_F1 + vp_offset, val);
}
- vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
- if (cstate->splice_mode)
- vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
+ if (is_vop3(vop2)) {
+ vop3_setup_pipe_dly(state, vop2, cstate->crtc_id);
+ } else {
+ vop2_setup_dly_for_vp(state, vop2, cstate->crtc_id);
+ if (cstate->splice_mode)
+ vop2_setup_dly_for_vp(state, vop2, cstate->splice_crtc_id);
+ }
+}
+
+static void vop3_post_acm_config(struct display_state *state, struct vop2 *vop2)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct crtc_state *cstate = &state->crtc_state;
+ struct acm_data *acm = &conn_state->disp_info->acm_data;
+ struct drm_display_mode *mode = &conn_state->mode;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+ s16 *lut_y;
+ s16 *lut_h;
+ s16 *lut_s;
+ u32 value;
+ int i;
+
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_ACM_BYPASS_EN_MASK, POST_ACM_BYPASS_EN_SHIFT, 0, false);
+ if (!acm->acm_enable) {
+ writel(0, vop2->regs + RK3528_ACM_CTRL);
+ return;
+ }
+
+ printf("post acm enable\n");
+
+ writel(1, vop2->regs + RK3528_ACM_FETCH_START);
+
+ value = (acm->acm_enable & 0x1) + ((mode->hdisplay & 0xfff) << 8) +
+ ((mode->vdisplay & 0xfff) << 20);
+ writel(value, vop2->regs + RK3528_ACM_CTRL);
+
+ value = (acm->y_gain & 0x3ff) + ((acm->h_gain << 10) & 0xffc00) +
+ ((acm->s_gain << 20) & 0x3ff00000);
+ writel(value, vop2->regs + RK3528_ACM_DELTA_RANGE);
+
+ lut_y = &acm->gain_lut_hy[0];
+ lut_h = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH];
+ lut_s = &acm->gain_lut_hy[ACM_GAIN_LUT_HY_LENGTH * 2];
+ for (i = 0; i < ACM_GAIN_LUT_HY_LENGTH; i++) {
+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
+ ((lut_s[i] << 16) & 0xff0000);
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HY_SEG0 + (i << 2));
+ }
+
+ lut_y = &acm->gain_lut_hs[0];
+ lut_h = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH];
+ lut_s = &acm->gain_lut_hs[ACM_GAIN_LUT_HS_LENGTH * 2];
+ for (i = 0; i < ACM_GAIN_LUT_HS_LENGTH; i++) {
+ value = (lut_y[i] & 0xff) + ((lut_h[i] << 8) & 0xff00) +
+ ((lut_s[i] << 16) & 0xff0000);
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HS_SEG0 + (i << 2));
+ }
+
+ lut_y = &acm->delta_lut_h[0];
+ lut_h = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH];
+ lut_s = &acm->delta_lut_h[ACM_DELTA_LUT_H_LENGTH * 2];
+ for (i = 0; i < ACM_DELTA_LUT_H_LENGTH; i++) {
+ value = (lut_y[i] & 0x3ff) + ((lut_h[i] << 12) & 0xff000) +
+ ((lut_s[i] << 20) & 0x3ff00000);
+ writel(value, vop2->regs + RK3528_ACM_YHS_DEL_HGAIN_SEG0 + (i << 2));
+ }
+
+ writel(1, vop2->regs + RK3528_ACM_FETCH_DONE);
+}
+
+static void vop3_post_csc_config(struct display_state *state, struct vop2 *vop2)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct crtc_state *cstate = &state->crtc_state;
+ struct acm_data *acm = &conn_state->disp_info->acm_data;
+ struct csc_info *csc = &conn_state->disp_info->csc_info;
+ struct post_csc_coef csc_coef;
+ bool is_input_yuv = false;
+ bool is_output_yuv = false;
+ bool post_r2y_en = false;
+ bool post_csc_en = false;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+ u32 value;
+ int range_type;
+
+ printf("post csc enable\n");
+
+ if (acm->acm_enable) {
+ if (!cstate->yuv_overlay)
+ post_r2y_en = true;
+
+ /* do y2r in csc module */
+ if (!is_yuv_output(conn_state->bus_format))
+ post_csc_en = true;
+ } else {
+ if (!cstate->yuv_overlay && is_yuv_output(conn_state->bus_format))
+ post_r2y_en = true;
+
+ /* do y2r in csc module */
+ if (cstate->yuv_overlay && !is_yuv_output(conn_state->bus_format))
+ post_csc_en = true;
+ }
+
+ if (csc->csc_enable)
+ post_csc_en = true;
+
+ if (cstate->yuv_overlay || post_r2y_en)
+ is_input_yuv = true;
+
+ if (is_yuv_output(conn_state->bus_format))
+ is_output_yuv = true;
+
+ cstate->post_csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_13BIT_DEPTH);
+
+ if (post_csc_en) {
+ rockchip_calc_post_csc(csc, &csc_coef, cstate->post_csc_mode, is_input_yuv,
+ is_output_yuv);
+
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_CSC_COE00_MASK, POST_CSC_COE00_SHIFT,
+ csc_coef.csc_coef00, false);
+ value = csc_coef.csc_coef01 & 0xffff;
+ value |= (csc_coef.csc_coef02 << 16) & 0xffff0000;
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE01_02);
+ value = csc_coef.csc_coef10 & 0xffff;
+ value |= (csc_coef.csc_coef11 << 16) & 0xffff0000;
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE10_11);
+ value = csc_coef.csc_coef12 & 0xffff;
+ value |= (csc_coef.csc_coef20 << 16) & 0xffff0000;
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE12_20);
+ value = csc_coef.csc_coef21 & 0xffff;
+ value |= (csc_coef.csc_coef22 << 16) & 0xffff0000;
+ writel(value, vop2->regs + RK3528_VP0_CSC_COE21_22);
+ writel(csc_coef.csc_dc0, vop2->regs + RK3528_VP0_CSC_OFFSET0);
+ writel(csc_coef.csc_dc1, vop2->regs + RK3528_VP0_CSC_OFFSET1);
+ writel(csc_coef.csc_dc2, vop2->regs + RK3528_VP0_CSC_OFFSET2);
+
+ range_type = csc_coef.range_type ? 0 : 1;
+ range_type <<= is_input_yuv ? 0 : 1;
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_CSC_MODE_MASK, POST_CSC_MODE_SHIFT, range_type, false);
+ }
+
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_R2Y_EN_MASK, POST_R2Y_EN_SHIFT, post_r2y_en ? 1 : 0, false);
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_CSC_EN_MASK, POST_CSC_EN_SHIFT, post_csc_en ? 1 : 0, false);
+ vop2_mask_write(vop2, RK3528_VP0_ACM_CTRL + vp_offset,
+ POST_R2Y_MODE_MASK, POST_R2Y_MODE_SHIFT, cstate->post_csc_mode, false);
+}
+
+static void vop3_post_config(struct display_state *state, struct vop2 *vop2)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct base2_disp_info *disp_info = conn_state->disp_info;
+ const char *enable_flag;
+ if (!disp_info) {
+ printf("disp_info is empty\n");
+ return;
+ }
+
+ enable_flag = (const char *)&disp_info->cacm_header;
+ if (strncasecmp(enable_flag, "CACM", 4)) {
+ printf("acm and csc is not support\n");
+ return;
+ }
+
+ vop3_post_acm_config(state, vop2);
+ vop3_post_csc_config(state, vop2);
}
/*
@@ -1731,112 +2237,55 @@
vop2->regsbak[i] = base[i];
}
-static void vop2_global_initial(struct vop2 *vop2, struct display_state *state)
+static void vop3_overlay_init(struct vop2 *vop2, struct display_state *state)
+{
+ struct vop2_win_data *win_data;
+ int layer_phy_id = 0;
+ int i, j;
+ u32 ovl_port_offset = 0;
+ u32 layer_nr = 0;
+ u8 shift = 0;
+
+ /* layer sel win id */
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ shift = 0;
+ ovl_port_offset = 0x100 * i;
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
+ for (j = 0; j < layer_nr; j++) {
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
+ vop2_mask_write(vop2, RK3528_OVL_PORT0_LAYER_SEL + ovl_port_offset, LAYER_SEL_MASK,
+ shift, win_data->layer_sel_win_id[i], false);
+ shift += 4;
+ }
+ }
+
+ /* win sel port */
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
+ for (j = 0; j < layer_nr; j++) {
+ if (!vop2->vp_plane_mask[i].attached_layers[j])
+ continue;
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
+ win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
+ shift = win_data->win_sel_port_offset * 2;
+ vop2_mask_write(vop2, RK3528_OVL_SYS_PORT_SEL_IMD, LAYER_SEL_PORT_MASK,
+ shift, i, false);
+ }
+ }
+}
+
+static void vop2_overlay_init(struct vop2 *vop2, struct display_state *state)
{
struct crtc_state *cstate = &state->crtc_state;
- int i, j, port_mux = 0, total_used_layer = 0;
- u8 shift = 0;
- int layer_phy_id = 0;
- u32 layer_nr = 0;
struct vop2_win_data *win_data;
- struct vop2_vp_plane_mask *plane_mask;
+ int layer_phy_id = 0;
+ int total_used_layer = 0;
+ int port_mux = 0;
+ int i, j;
+ u32 layer_nr = 0;
+ u8 shift = 0;
- if (vop2->global_init)
- return;
-
- /* OTP must enable at the first time, otherwise mirror layer register is error */
- if (soc_is_rk3566())
- vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
- OTP_WIN_EN_SHIFT, 1, false);
-
- if (cstate->crtc->assign_plane) {/* dts assign plane */
- u32 plane_mask;
- int primary_plane_id;
-
- for (i = 0; i < vop2->data->nr_vps; i++) {
- plane_mask = cstate->crtc->vps[i].plane_mask;
- vop2->vp_plane_mask[i].plane_mask = plane_mask;
- layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
- vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
- primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
- if (primary_plane_id < 0)
- primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
- vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
- vop2->vp_plane_mask[i].plane_mask = plane_mask;
-
- /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
- for (j = 0; j < layer_nr; j++) {
- vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
- plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
- }
- }
- } else {/* need soft assign plane mask */
- /* find the first unplug devices and set it as main display */
- int main_vp_index = -1;
- int active_vp_num = 0;
-
- for (i = 0; i < vop2->data->nr_vps; i++) {
- if (cstate->crtc->vps[i].enable)
- active_vp_num++;
- }
- printf("VOP have %d active VP\n", active_vp_num);
-
- if (soc_is_rk3566() && active_vp_num > 2)
- printf("ERROR: rk3566 only support 2 display output!!\n");
- plane_mask = vop2->data->plane_mask;
- plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
-
- for (i = 0; i < vop2->data->nr_vps; i++) {
- if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
- vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
- main_vp_index = i;
- break;
- }
- }
-
- /* if no find unplug devices, use vp0 as main display */
- if (main_vp_index < 0) {
- main_vp_index = 0;
- vop2->vp_plane_mask[0] = plane_mask[0];
- }
-
- j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
-
- /* init other display except main display */
- for (i = 0; i < vop2->data->nr_vps; i++) {
- if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */
- continue;
- vop2->vp_plane_mask[i] = plane_mask[j++];
- }
-
- /* store plane mask for vop2_fixup_dts */
- for (i = 0; i < vop2->data->nr_vps; i++) {
- layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
- for (j = 0; j < layer_nr; j++) {
- layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
- vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id);
- }
- }
- }
-
- if (vop2->version == VOP_VERSION_RK3588)
- rk3588_vop2_regsbak(vop2);
- else
- memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
-
- vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
- OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
- IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
-
- for (i = 0; i < vop2->data->nr_vps; i++) {
- printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
- for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
- printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
- printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
- }
-
- shift = 0;
/* layer sel win id */
for (i = 0; i < vop2->data->nr_vps; i++) {
layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
@@ -1844,7 +2293,7 @@
layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
win_data = vop2_find_win_by_phys_id(vop2, layer_phy_id);
vop2_mask_write(vop2, RK3568_OVL_LAYER_SEL, LAYER_SEL_MASK,
- shift, win_data->layer_sel_win_id, false);
+ shift, win_data->layer_sel_win_id[i], false);
shift += 4;
}
}
@@ -1882,6 +2331,190 @@
vop2_mask_write(vop2, RK3568_OVL_PORT_SEL, PORT_MUX_MASK,
PORT_MUX_SHIFT + shift, port_mux, false);
}
+}
+
+static bool vop3_ignore_plane(struct vop2 *vop2, struct vop2_win_data *win)
+{
+ if (!is_vop3(vop2))
+ return false;
+
+ if (vop2->esmart_lb_mode == VOP3_ESMART_8K_MODE &&
+ win->phys_id != ROCKCHIP_VOP2_ESMART0)
+ return true;
+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_4K_MODE &&
+ (win->phys_id == ROCKCHIP_VOP2_ESMART1 || win->phys_id == ROCKCHIP_VOP2_ESMART3))
+ return true;
+ else if (vop2->esmart_lb_mode == VOP3_ESMART_4K_2K_2K_MODE &&
+ win->phys_id == ROCKCHIP_VOP2_ESMART1)
+ return true;
+ else
+ return false;
+}
+
+static void vop3_init_esmart_scale_engine(struct vop2 *vop2)
+{
+ struct vop2_win_data *win_data;
+ int i;
+ u8 scale_engine_num = 0;
+
+ /* store plane mask for vop2_fixup_dts */
+ for (i = 0; i < vop2->data->nr_layers; i++) {
+ win_data = &vop2->data->win_data[i];
+ if (win_data->type == CLUSTER_LAYER || vop3_ignore_plane(vop2, win_data))
+ continue;
+
+ win_data->scale_engine_num = scale_engine_num++;
+ }
+}
+
+static void vop2_global_initial(struct vop2 *vop2, struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2_vp_plane_mask *plane_mask;
+ int layer_phy_id = 0;
+ int i, j;
+ int ret;
+ u32 layer_nr = 0;
+
+ if (vop2->global_init)
+ return;
+
+ /* OTP must enable at the first time, otherwise mirror layer register is error */
+ if (soc_is_rk3566())
+ vop2_mask_write(vop2, RK3568_SYS_OTP_WIN_EN, EN_MASK,
+ OTP_WIN_EN_SHIFT, 1, false);
+
+ if (cstate->crtc->assign_plane) {/* dts assign plane */
+ u32 plane_mask;
+ int primary_plane_id;
+
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ plane_mask = cstate->crtc->vps[i].plane_mask;
+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
+ layer_nr = hweight32(plane_mask); /* use bitmap to store plane mask */
+ vop2->vp_plane_mask[i].attached_layers_nr = layer_nr;
+ primary_plane_id = cstate->crtc->vps[i].primary_plane_id;
+ if (primary_plane_id >= ROCKCHIP_VOP2_LAYER_MAX)
+ primary_plane_id = vop2_get_primary_plane(vop2, plane_mask);
+ vop2->vp_plane_mask[i].primary_plane_id = primary_plane_id;
+ vop2->vp_plane_mask[i].plane_mask = plane_mask;
+
+ /* plane mask[bitmap] convert into layer phy id[enum vop2_layer_phy_id]*/
+ for (j = 0; j < layer_nr; j++) {
+ vop2->vp_plane_mask[i].attached_layers[j] = ffs(plane_mask) - 1;
+ plane_mask &= ~BIT(vop2->vp_plane_mask[i].attached_layers[j]);
+ }
+ }
+ } else {/* need soft assign plane mask */
+ /* find the first unplug devices and set it as main display */
+ int main_vp_index = -1;
+ int active_vp_num = 0;
+
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ if (cstate->crtc->vps[i].enable)
+ active_vp_num++;
+ }
+ printf("VOP have %d active VP\n", active_vp_num);
+
+ if (soc_is_rk3566() && active_vp_num > 2)
+ printf("ERROR: rk3566 only support 2 display output!!\n");
+ plane_mask = vop2->data->plane_mask;
+ plane_mask += (active_vp_num - 1) * VOP2_VP_MAX;
+ /*
+ * For rk3528, one display policy for hdmi store in plane_mask[0], and the other
+ * for cvbs store in plane_mask[2].
+ */
+ if (vop2->version == VOP_VERSION_RK3528 && active_vp_num == 1 &&
+ cstate->crtc->vps[1].output_type == DRM_MODE_CONNECTOR_TV)
+ plane_mask += 2 * VOP2_VP_MAX;
+
+ if (vop2->version == VOP_VERSION_RK3528) {
+ /*
+ * For rk3528, the plane mask of vp is limited, only esmart2 can be selected
+ * by both vp0 and vp1.
+ */
+ j = 0;
+ } else {
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ if (!is_hot_plug_devices(cstate->crtc->vps[i].output_type)) {
+ vop2->vp_plane_mask[i] = plane_mask[0]; /* the first store main display plane mask*/
+ main_vp_index = i;
+ break;
+ }
+ }
+
+ /* if no find unplug devices, use vp0 as main display */
+ if (main_vp_index < 0) {
+ main_vp_index = 0;
+ vop2->vp_plane_mask[0] = plane_mask[0];
+ }
+
+ j = 1; /* plane_mask[0] store main display, so we from plane_mask[1] */
+ }
+
+ /* init other display except main display */
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ if (i == main_vp_index || !cstate->crtc->vps[i].enable) /* main display or no connect devices */
+ continue;
+ vop2->vp_plane_mask[i] = plane_mask[j++];
+ }
+
+ /* store plane mask for vop2_fixup_dts */
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ layer_nr = vop2->vp_plane_mask[i].attached_layers_nr;
+ for (j = 0; j < layer_nr; j++) {
+ layer_phy_id = vop2->vp_plane_mask[i].attached_layers[j];
+ vop2->vp_plane_mask[i].plane_mask |= BIT(layer_phy_id);
+ }
+ }
+ }
+
+ if (vop2->version == VOP_VERSION_RK3588)
+ rk3588_vop2_regsbak(vop2);
+ else
+ memcpy(vop2->regsbak, vop2->regs, vop2->reg_len);
+
+ vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK,
+ OVL_PORT_MUX_REG_DONE_IMD_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
+ IF_CTRL_REG_DONE_IMD_SHIFT, 1, false);
+
+ for (i = 0; i < vop2->data->nr_vps; i++) {
+ printf("vp%d have layer nr:%d[", i, vop2->vp_plane_mask[i].attached_layers_nr);
+ for (j = 0; j < vop2->vp_plane_mask[i].attached_layers_nr; j++)
+ printf("%d ", vop2->vp_plane_mask[i].attached_layers[j]);
+ printf("], primary plane: %d\n", vop2->vp_plane_mask[i].primary_plane_id);
+ }
+
+ if (is_vop3(vop2))
+ vop3_overlay_init(vop2, state);
+ else
+ vop2_overlay_init(vop2, state);
+
+ if (is_vop3(vop2)) {
+ /*
+ * you can rewrite at dts vop node:
+ *
+ * VOP3_ESMART_8K_MODE = 0,
+ * VOP3_ESMART_4K_4K_MODE = 1,
+ * VOP3_ESMART_4K_2K_2K_MODE = 2,
+ * VOP3_ESMART_2K_2K_2K_2K_MODE = 3,
+ *
+ * &vop {
+ * esmart_lb_mode = /bits/ 8 <2>;
+ * };
+ */
+ ret = ofnode_read_u32(cstate->node, "esmart_lb_mode", &vop2->esmart_lb_mode);
+ if (ret < 0)
+ vop2->esmart_lb_mode = vop2->data->esmart_lb_mode;
+ vop2_mask_write(vop2, RK3568_SYS_LUT_PORT_SEL, ESMART_LB_MODE_SEL_MASK,
+ ESMART_LB_MODE_SEL_SHIFT, vop2->esmart_lb_mode, false);
+
+ vop3_init_esmart_scale_engine(vop2);
+
+ vop2_mask_write(vop2, RK3568_SYS_AXI_LUT_CTRL, EN_MASK,
+ DSP_VS_T_SEL_SHIFT, 0, false);
+ }
if (vop2->version == VOP_VERSION_RK3568)
vop2_writel(vop2, RK3568_AUTO_GATING_CTRL, 0);
@@ -1891,14 +2524,6 @@
static int vop2_initial(struct vop2 *vop2, struct display_state *state)
{
- struct crtc_state *cstate = &state->crtc_state;
- int ret;
-
- /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */
- ret = clk_set_defaults(cstate->dev);
- if (ret)
- debug("%s clk_set_defaults failed %d\n", __func__, ret);
-
rockchip_vop2_gamma_lut_init(vop2, state);
rockchip_vop2_cubic_lut_init(vop2, state);
@@ -1918,12 +2543,17 @@
rockchip_vop2 = calloc(1, sizeof(struct vop2));
if (!rockchip_vop2)
return -ENOMEM;
- rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
+ memset(rockchip_vop2, 0, sizeof(struct vop2));
rockchip_vop2->regsbak = malloc(RK3568_MAX_REG);
rockchip_vop2->reg_len = RK3568_MAX_REG;
+#ifdef CONFIG_SPL_BUILD
+ rockchip_vop2->regs = (void *)RK3528_VOP_BASE;
+#else
+ rockchip_vop2->regs = dev_read_addr_ptr(cstate->dev);
rockchip_vop2->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
if (rockchip_vop2->grf <= 0)
printf("%s: Get syscon grf failed (ret=%p)\n", __func__, rockchip_vop2->grf);
+#endif
rockchip_vop2->version = vop2_data->version;
rockchip_vop2->data = vop2_data;
if (rockchip_vop2->version == VOP_VERSION_RK3588) {
@@ -2021,11 +2651,12 @@
}
if (v_pixclk > VOP2_MAX_DCLK_RATE)
- dclk_rate = vop2_calc_dclk(dclk_core_rate, vop2->data->vp_data->max_dclk);
+ dclk_rate = vop2_calc_dclk(dclk_core_rate,
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
if (!dclk_rate) {
printf("DP if_pixclk_rate out of range(max_dclk: %d KHZ, dclk_core: %lld KHZ)\n",
- vop2->data->vp_data->max_dclk, if_pixclk_rate);
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, if_pixclk_rate);
return -EINVAL;
}
*if_pixclk_div = dclk_rate / if_pixclk_rate;
@@ -2045,10 +2676,11 @@
dclk_out_rate = v_pixclk >> 2;
dclk_out_rate = dclk_out_rate / K;
- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
if (!dclk_rate) {
printf("DP dclk_core out of range(max_dclk: %d KHZ, dclk_core: %ld KHZ)\n",
- vop2->data->vp_data->max_dclk, dclk_core_rate);
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_core_rate);
return -EINVAL;
}
*dclk_out_div = dclk_rate / dclk_out_rate;
@@ -2064,21 +2696,22 @@
/* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */
dclk_out_rate = dclk_core_rate / K;
/* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */
- dclk_rate = vop2_calc_dclk(dclk_out_rate, vop2->data->vp_data->max_dclk);
+ dclk_rate = vop2_calc_dclk(dclk_out_rate,
+ vop2->data->vp_data[cstate->crtc_id].max_dclk);
if (!dclk_rate) {
printf("MIPI dclk out of range(max_dclk: %d KHZ, dclk_rate: %ld KHZ)\n",
- vop2->data->vp_data->max_dclk, dclk_rate);
+ vop2->data->vp_data[cstate->crtc_id].max_dclk, dclk_rate);
return -EINVAL;
}
if (cstate->dsc_enable)
- dclk_rate = dclk_rate >> 1;
+ dclk_rate /= cstate->dsc_slice_num;
*dclk_out_div = dclk_rate / dclk_out_rate;
*dclk_core_div = dclk_rate / dclk_core_rate;
*if_pixclk_div = 1; /*mipi pixclk == dclk_out*/
if (cstate->dsc_enable)
- *if_pixclk_div = dclk_out_rate / if_pixclk_rate;
+ *if_pixclk_div = dclk_out_rate * 1000LL / if_pixclk_rate;
} else if (output_type == DRM_MODE_CONNECTOR_DPI) {
dclk_rate = v_pixclk;
@@ -2098,7 +2731,7 @@
struct connector_state *conn_state = &state->conn_state;
struct drm_display_mode *mode = &conn_state->mode;
struct crtc_state *cstate = &state->crtc_state;
- u64 v_pixclk = mode->clock; /* video timing pixclk */
+ u64 v_pixclk = mode->crtc_clock * 1000LL; /* video timing pixclk */
u8 k = 1;
if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE)
@@ -2201,8 +2834,7 @@
if (conn_state->hold_mode) {
vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
- EN_MASK, EDPI_TE_EN, 1, false);
-
+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
}
@@ -2227,14 +2859,8 @@
if_pixclk_div, false);
if (conn_state->hold_mode) {
- /* UNDO: RK3588 VP1->DSC1->DSI1 only can support soft TE mode */
- if (vop2->version == VOP_VERSION_RK3588 && val == 3)
- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
- EN_MASK, EDPI_TE_EN, 0, false);
- else
- vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
- EN_MASK, EDPI_TE_EN, 1, false);
-
+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
+ EN_MASK, EDPI_TE_EN, !cstate->soft_te, false);
vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
EN_MASK, EDPI_WMS_HOLD_EN, 1, false);
}
@@ -2371,7 +2997,7 @@
bool dclk_inv;
u32 val;
- dclk_inv = (mode->flags & DRM_MODE_FLAG_PPIXDATA) ? 0 : 1;
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
@@ -2380,6 +3006,8 @@
1, false);
vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
RGB_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
vop2_grf_writel(vop2, vop2->grf, RK3568_GRF_VO_CON1, EN_MASK,
GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
}
@@ -2409,8 +3037,10 @@
1, false);
vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
LVDS0_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
}
if (conn_state->output_if & VOP_OUTPUT_IF_LVDS1) {
@@ -2418,8 +3048,10 @@
1, false);
vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
LVDS1_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_RGB_LVDS_PIN_POL_MASK,
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
- IF_CRTL_RGB_LVDS_DCLK_POL_SHIT, dclk_inv, false);
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
}
if (conn_state->output_flags &
@@ -2472,6 +3104,8 @@
EDP0_MUX_SHIFT, cstate->crtc_id, false);
vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
IF_CRTL_EDP_DCLK_POL_SHIT, dclk_inv, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, IF_CTRL_EDP_PIN_POL_MASK,
+ IF_CTRL_EDP_PIN_POL_SHIFT, val, false);
}
if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
@@ -2489,6 +3123,88 @@
return mode->clock;
}
+static unsigned long rk3528_vop2_if_cfg(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+ struct vop2 *vop2 = cstate->private;
+ u32 val;
+
+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
+ val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
+
+ if (conn_state->output_if & VOP_OUTPUT_IF_BT656) {
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, BT656_EN_SHIFT,
+ 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
+ RGB_MUX_SHIFT, cstate->crtc_id, false);
+ }
+
+ if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0) {
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, HDMI0_EN_SHIFT,
+ 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
+ HDMI0_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
+ IF_CRTL_HDMI_DCLK_POL_SHIT, 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL,
+ IF_CRTL_HDMI_PIN_POL_MASK,
+ IF_CRTL_HDMI_PIN_POL_SHIT, val, false);
+ }
+
+ return mode->crtc_clock;
+}
+
+static unsigned long rk3562_vop2_if_cfg(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+ struct vop2 *vop2 = cstate->private;
+ bool dclk_inv;
+ u32 val;
+
+ dclk_inv = (conn_state->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) ? 1 : 0;
+ val = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : BIT(HSYNC_POSITIVE);
+ val |= (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : BIT(VSYNC_POSITIVE);
+
+ if (conn_state->output_if & VOP_OUTPUT_IF_RGB) {
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, RGB_EN_SHIFT,
+ 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
+ RGB_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_grf_writel(vop2, vop2->grf, RK3562_GRF_IOC_VO_IO_CON, EN_MASK,
+ GRF_RGB_DCLK_INV_SHIFT, dclk_inv);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
+ }
+
+ if (conn_state->output_if & VOP_OUTPUT_IF_LVDS0) {
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, LVDS0_EN_SHIFT,
+ 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
+ LVDS0_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
+ IF_CTRL_RGB_LVDS_DCLK_POL_SHIFT, dclk_inv, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
+ IF_CTRL_RGB_LVDS_PIN_POL_SHIFT, val, false);
+ }
+
+ if (conn_state->output_if & VOP_OUTPUT_IF_MIPI0) {
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, EN_MASK, MIPI0_EN_SHIFT,
+ 1, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_EN, IF_MUX_MASK,
+ MIPI0_MUX_SHIFT, cstate->crtc_id, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, EN_MASK,
+ RK3562_MIPI_DCLK_POL_SHIFT, dclk_inv, false);
+ vop2_mask_write(vop2, RK3568_DSP_IF_POL, RK3562_IF_PIN_POL_MASK,
+ RK3562_MIPI_PIN_POL_SHIFT, val, false);
+ }
+
+ return mode->crtc_clock;
+}
+
static void vop2_post_color_swap(struct display_state *state)
{
struct crtc_state *cstate = &state->crtc_state;
@@ -2498,7 +3214,8 @@
u32 output_type = conn_state->type;
u32 data_swap = 0;
- if (is_uv_swap(conn_state->bus_format, conn_state->output_mode))
+ if (is_uv_swap(conn_state->bus_format, conn_state->output_mode) ||
+ is_rb_swap(conn_state->bus_format, conn_state->output_mode))
data_swap = DSP_RB_SWAP;
if (vop2->version == VOP_VERSION_RK3588 &&
@@ -2603,10 +3320,10 @@
u16 vact_end = vact_st + vdisplay;
u32 ctrl_regs_offset = (dsc_id * 0x30);
u32 decoder_regs_offset = (dsc_id * 0x100);
- u32 backup_regs_offset = 0;
int dsc_txp_clk_div = 0;
int dsc_pxl_clk_div = 0;
int dsc_cds_clk_div = 0;
+ int val = 0;
if (!vop2->data->nr_dscs) {
printf("Unsupported DSC\n");
@@ -2678,21 +3395,42 @@
* dly_num = delay_line_num * T(one-line) / T (dsc_cds)
* T (one-line) = 1/v_pixclk_mhz * htotal = htotal/v_pixclk_mhz
* T (dsc_cds) = 1 / dsc_cds_rate_mhz
+ *
+ * HDMI:
* delay_line_num: according the pps initial_xmit_delay to adjust vop dsc delay
* delay_line_num = 4 - BPP / 8
* = (64 - target_bpp / 8) / 16
- *
* dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
+ *
+ * MIPI DSI[4320 and 9216 is buffer size for DSC]:
+ * DSC0:delay_line_num = 4320 * 8 / slince_num / chunk_size;
+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
+ * DSC1:delay_line_num = 9216 * 2 / slince_num / chunk_size;
+ * delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
+ * dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num
*/
do_div(dsc_cds_rate, 1000000); /* hz to Mhz */
dsc_cds_rate_mhz = dsc_cds_rate;
- dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
+ dsc_hsync = hsync_len / 2;
+ if (dsc_interface_mode == VOP_DSC_IF_HDMI) {
+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * (64 - target_bpp / 8) / 16;
+ } else {
+ int dsc_buf_size = dsc_id == 0 ? 4320 * 8 : 9216 * 2;
+ int delay_line_num = dsc_buf_size / cstate->dsc_slice_num /
+ be16_to_cpu(cstate->pps.chunk_size);
+
+ delay_line_num = delay_line_num > 5 ? 5 : delay_line_num;
+ dly_num = htotal * dsc_cds_rate_mhz / v_pixclk_mhz * delay_line_num;
+
+ /* The dsc mipi video mode dsc_hsync minimum size is 8 pixels */
+ if (dsc_hsync < 8)
+ dsc_hsync = 8;
+ }
vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_MODE_MASK,
DSC_INIT_DLY_MODE_SHIFT, 0, false);
vop2_mask_write(vop2, RK3588_DSC_8K_INIT_DLY + ctrl_regs_offset, DSC_INIT_DLY_NUM_MASK,
DSC_INIT_DLY_NUM_SHIFT, dly_num, false);
- dsc_hsync = hsync_len / 2;
/*
* htotal / dclk_core = dsc_htotal /cds_clk
*
@@ -2724,34 +3462,15 @@
vop2_mask_write(vop2, RK3588_DSC_8K_RST + ctrl_regs_offset, RST_DEASSERT_MASK,
RST_DEASSERT_SHIFT, 1, false);
udelay(10);
- /* read current dsc core register and backup to regsbak */
- backup_regs_offset = RK3588_DSC_8K_CTRL0;
- vop2->regsbak[backup_regs_offset >> 2] = vop2_readl(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_EN_SHIFT, 1, false);
+ val |= DSC_CTRL0_DEF_CON | (ilog2(cstate->dsc_slice_num) << DSC_NSLC_SHIFT) |
+ ((dsc_sink_cap->version_minor == 2 ? 1 : 0) << DSC_IFEP_SHIFT);
+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
+
vop2_load_pps(state, vop2, dsc_id);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_RBIT_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_RBYT_SHIFT, 0, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_FLAL_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_MER_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_EPB_SHIFT, 0, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_EPL_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_NSLC_SHIFT, ilog2(cstate->dsc_slice_num), false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_SBO_SHIFT, 1, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_IFEP_SHIFT, dsc_sink_cap->version_minor == 2 ? 1 : 0, false);
- vop2_mask_write(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, EN_MASK,
- DSC_PPS_UPD_SHIFT, 1, false);
+ val |= (1 << DSC_PPS_UPD_SHIFT);
+ vop2_writel(vop2, RK3588_DSC_8K_CTRL0 + decoder_regs_offset, val);
printf("DSC%d: txp:%lld div:%d, pxl:%lld div:%d, dsc:%lld div:%d\n",
dsc_id,
@@ -2800,6 +3519,133 @@
return false;
}
+static void vop3_mcu_mode_setup(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_TYPE_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_HOLD_MODE_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
+ MCU_PIX_TOTAL_SHIFT, cstate->mcu_timing.mcu_pix_total, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
+ MCU_CS_PST_SHIFT, cstate->mcu_timing.mcu_cs_pst, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
+ MCU_CS_PEND_SHIFT, cstate->mcu_timing.mcu_cs_pend, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
+ MCU_RW_PST_SHIFT, cstate->mcu_timing.mcu_rw_pst, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
+ MCU_RW_PEND_SHIFT, cstate->mcu_timing.mcu_rw_pend, false);
+}
+
+static void vop3_mcu_bypass_mode_setup(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_TYPE_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_HOLD_MODE_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_PIX_TOTAL_MASK,
+ MCU_PIX_TOTAL_SHIFT, 53, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PST_MASK,
+ MCU_CS_PST_SHIFT, 6, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_CS_PEND_MASK,
+ MCU_CS_PEND_SHIFT, 48, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PST_MASK,
+ MCU_RW_PST_SHIFT, 12, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, MCU_RW_PEND_MASK,
+ MCU_RW_PEND_SHIFT, 30, false);
+}
+
+static int rockchip_vop2_send_mcu_cmd(struct display_state *state, u32 type, u32 value)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+ struct vop2 *vop2 = cstate->private;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+ u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
+
+ /*
+ * 1.disable port dclk auto gating.
+ * 2.set mcu bypass mode timing to adapt to the mode of sending cmds.
+ * 3.make setting of output mode take effect.
+ * 4.set dclk rate to 150M, in order to sync with hclk in sending cmds.
+ */
+ if (type == MCU_SETBYPASS && value) {
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
+ AUTO_GATING_EN_SHIFT, 0, false);
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 0, false);
+ vop3_mcu_bypass_mode_setup(state);
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ STANDBY_EN_SHIFT, 0, false);
+ vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
+ vop2_clk_set_rate(&cstate->dclk, 150000000);
+ }
+
+ switch (type) {
+ case MCU_WRCMD:
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_RS_SHIFT, 0, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
+ value, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_RS_SHIFT, 1, false);
+ break;
+ case MCU_WRDATA:
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_RS_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3562_VP0_MCU_RW_BYPASS_PORT + vp_offset,
+ MCU_WRITE_DATA_BYPASS_MASK, MCU_WRITE_DATA_BYPASS_SHIFT,
+ value, false);
+ break;
+ case MCU_SETBYPASS:
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_BYPASS_SHIFT, value ? 1 : 0, false);
+ break;
+ default:
+ break;
+ }
+
+ /*
+ * 1.restore port dclk auto gating.
+ * 2.restore mcu data mode timing.
+ * 3.restore dclk rate to crtc_clock.
+ */
+ if (type == MCU_SETBYPASS && !value) {
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
+ AUTO_GATING_EN_SHIFT, 1, false);
+ vop2_mask_write(vop2, RK3568_AUTO_GATING_CTRL, EN_MASK,
+ PORT_DCLK_AUTO_GATING_EN_SHIFT, 1, false);
+ vop3_mcu_mode_setup(state);
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ STANDBY_EN_SHIFT, 1, false);
+ vop2_clk_set_rate(&cstate->dclk, mode->crtc_clock * 1000);
+ }
+
+ return 0;
+}
+
+static int vop2_get_vrefresh(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+
+ if (cstate->mcu_timing.mcu_pix_total)
+ return mode->vrefresh / cstate->mcu_timing.mcu_pix_total;
+ else
+ return mode->vrefresh;
+}
+
static int rockchip_vop2_init(struct display_state *state)
{
struct crtc_state *cstate = &state->crtc_state;
@@ -2822,22 +3668,24 @@
u32 line_flag_offset = (cstate->crtc_id * 4);
u32 val, act_end;
u8 dither_down_en = 0;
+ u8 dither_down_mode = 0;
u8 pre_dither_down_en = 0;
u8 dclk_div_factor = 0;
char output_type_name[30] = {0};
+#ifndef CONFIG_SPL_BUILD
char dclk_name[9];
- struct clk dclk;
+#endif
struct clk hdmi0_phy_pll;
struct clk hdmi1_phy_pll;
struct clk hdmi_phy_pll;
struct udevice *disp_dev;
- unsigned long dclk_rate;
+ unsigned long dclk_rate = 0;
int ret;
printf("VOP update mode to: %dx%d%s%d, type:%s for VP%d\n",
mode->crtc_hdisplay, mode->vdisplay,
mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
- mode->vrefresh,
+ vop2_get_vrefresh(state),
get_output_if_name(conn_state->output_if, output_type_name),
cstate->crtc_id);
@@ -2854,11 +3702,20 @@
PORT_MERGE_EN_SHIFT, 1, false);
}
+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
+ RK3588_VP0_LINE_FLAG_OR_EN_SHIFT + cstate->crtc_id, 1, false);
+ vop2_mask_write(vop2, RK3588_SYS_VAR_FREQ_CTRL, EN_MASK,
+ RK3588_VP0_ALMOST_FULL_OR_EN_SHIFT + cstate->crtc_id, 1, false);
+
vop2_initial(vop2, state);
if (vop2->version == VOP_VERSION_RK3588)
dclk_rate = rk3588_vop2_if_cfg(state);
- else
+ else if (vop2->version == VOP_VERSION_RK3568)
dclk_rate = rk3568_vop2_if_cfg(state);
+ else if (vop2->version == VOP_VERSION_RK3528)
+ dclk_rate = rk3528_vop2_if_cfg(state);
+ else if (vop2->version == VOP_VERSION_RK3562)
+ dclk_rate = rk3562_vop2_if_cfg(state);
if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
!(cstate->feature & VOP_FEATURE_OUTPUT_10BIT))
@@ -2872,12 +3729,16 @@
switch (conn_state->bus_format) {
case MEDIA_BUS_FMT_RGB565_1X16:
dither_down_en = 1;
+ dither_down_mode = RGB888_TO_RGB565;
+ pre_dither_down_en = 1;
break;
case MEDIA_BUS_FMT_RGB666_1X18:
case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
case MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA:
dither_down_en = 1;
+ dither_down_mode = RGB888_TO_RGB666;
+ pre_dither_down_en = 1;
break;
case MEDIA_BUS_FMT_YUV8_1X24:
case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
@@ -2886,23 +3747,28 @@
break;
case MEDIA_BUS_FMT_YUV10_1X30:
case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
- case MEDIA_BUS_FMT_RGB888_1X24:
- case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
- case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
- default:
dither_down_en = 0;
pre_dither_down_en = 0;
break;
+ case MEDIA_BUS_FMT_YUYV10_1X20:
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
+ case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
+ case MEDIA_BUS_FMT_RGB101010_1X30:
+ default:
+ dither_down_en = 0;
+ pre_dither_down_en = 1;
+ break;
}
- if (conn_state->output_mode == ROCKCHIP_OUT_MODE_AAAA)
- pre_dither_down_en = 0;
- else
- pre_dither_down_en = 1;
vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
DITHER_DOWN_EN_SHIFT, dither_down_en, false);
vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
PRE_DITHER_DOWN_EN_SHIFT, pre_dither_down_en, false);
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ DITHER_DOWN_MODE_SHIFT, dither_down_mode, false);
yuv_overlay = is_yuv_output(conn_state->bus_format) ? 1 : 0;
vop2_mask_write(vop2, RK3568_OVL_CTRL, EN_MASK, cstate->crtc_id,
@@ -2946,15 +3812,13 @@
vop2_writel(vop2, RK3568_VP0_DSP_VTOTAL_VS_END + vp_offset,
(vtotal << 16) | vsync_len);
- if (vop2->version == VOP_VERSION_RK3568) {
- if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
- conn_state->output_if & VOP_OUTPUT_IF_BT656)
- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
- CORE_DCLK_DIV_EN_SHIFT, 1, false);
- else
- vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
- CORE_DCLK_DIV_EN_SHIFT, 0, false);
- }
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK ||
+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ CORE_DCLK_DIV_EN_SHIFT, 1, false);
+ else
+ vop2_mask_write(vop2, RK3568_VP0_DSP_CTRL + vp_offset, EN_MASK,
+ CORE_DCLK_DIV_EN_SHIFT, 0, false);
if (conn_state->output_mode == ROCKCHIP_OUT_MODE_YUV420)
vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
@@ -2987,22 +3851,26 @@
vop2_tv_config_update(state, vop2);
vop2_post_config(state, vop2);
+ if (cstate->feature & (VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC))
+ vop3_post_config(state, vop2);
if (cstate->dsc_enable) {
if (conn_state->output_flags & ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE) {
- vop2_dsc_enable(state, vop2, 0, dclk_rate);
- vop2_dsc_enable(state, vop2, 1, dclk_rate);
+ vop2_dsc_enable(state, vop2, 0, dclk_rate * 1000LL);
+ vop2_dsc_enable(state, vop2, 1, dclk_rate * 1000LL);
} else {
- vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate);
+ vop2_dsc_enable(state, vop2, cstate->dsc_id, dclk_rate * 1000LL);
}
}
+#ifndef CONFIG_SPL_BUILD
snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", cstate->crtc_id);
- ret = clk_get_by_name(cstate->dev, dclk_name, &dclk);
+ ret = clk_get_by_name(cstate->dev, dclk_name, &cstate->dclk);
if (ret) {
printf("%s: Failed to get dclk ret=%d\n", __func__, ret);
return ret;
}
+#endif
ret = uclass_get_device_by_name(UCLASS_VIDEO, "display-subsystem", &disp_dev);
if (!ret) {
@@ -3018,11 +3886,27 @@
debug("%s: Faile to find display-subsystem node\n", __func__);
}
+ if (vop2->version == VOP_VERSION_RK3528) {
+ struct ofnode_phandle_args args;
+
+ ret = dev_read_phandle_with_args(cstate->dev, "assigned-clock-parents",
+ "#clock-cells", 0, 0, &args);
+ if (!ret) {
+ ret = uclass_find_device_by_ofnode(UCLASS_CLK, args.node, &hdmi0_phy_pll.dev);
+ if (ret) {
+ debug("warn: can't get clk device\n");
+ return ret;
+ }
+ } else {
+ debug("assigned-clock-parents's node not define\n");
+ }
+ }
+
if (mode->crtc_clock < VOP2_MAX_DCLK_RATE) {
if (conn_state->output_if & VOP_OUTPUT_IF_HDMI0)
- vop2_clk_set_parent(&dclk, &hdmi0_phy_pll);
+ vop2_clk_set_parent(&cstate->dclk, &hdmi0_phy_pll);
else if (conn_state->output_if & VOP_OUTPUT_IF_HDMI1)
- vop2_clk_set_parent(&dclk, &hdmi1_phy_pll);
+ vop2_clk_set_parent(&cstate->dclk, &hdmi1_phy_pll);
/*
* uboot clk driver won't set dclk parent's rate when use
@@ -3035,16 +3919,28 @@
} else if ((conn_state->output_if & VOP_OUTPUT_IF_HDMI1) && hdmi1_phy_pll.dev) {
ret = vop2_clk_set_rate(&hdmi1_phy_pll, dclk_rate * 1000);
} else {
- if (is_extend_pll(state, &hdmi_phy_pll.dev))
+ if (is_extend_pll(state, &hdmi_phy_pll.dev)) {
ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
- else
- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
+ } else {
+#ifndef CONFIG_SPL_BUILD
+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
+#else
+ if (vop2->version == VOP_VERSION_RK3528) {
+ void *cru_base = (void *)RK3528_CRU_BASE;
+
+ /* dclk src switch to hdmiphy pll */
+ writel((BIT(0) << 16) | BIT(0), cru_base + 0x450);
+ rockchip_phy_set_pll(conn_state->connector->phy, dclk_rate * 1000);
+ ret = dclk_rate * 1000;
+ }
+#endif
+ }
}
} else {
if (is_extend_pll(state, &hdmi_phy_pll.dev))
ret = vop2_clk_set_rate(&hdmi_phy_pll, dclk_rate * 1000);
else
- ret = vop2_clk_set_rate(&dclk, dclk_rate * 1000);
+ ret = vop2_clk_set_rate(&cstate->dclk, dclk_rate * 1000);
}
if (IS_ERR_VALUE(ret)) {
@@ -3053,7 +3949,11 @@
return ret;
} else {
dclk_div_factor = mode->clock / dclk_rate;
- mode->crtc_clock = ret * dclk_div_factor / 1000;
+ if (vop2->version == VOP_VERSION_RK3528 &&
+ conn_state->output_if & VOP_OUTPUT_IF_BT656)
+ mode->crtc_clock = ret / 4 / 1000;
+ else
+ mode->crtc_clock = ret * dclk_div_factor / 1000;
printf("VP%d set crtc_clock to %dKHz\n", cstate->crtc_id, mode->crtc_clock);
}
@@ -3061,6 +3961,9 @@
RK3568_DSP_LINE_FLAG_NUM0_SHIFT, act_end, false);
vop2_mask_write(vop2, RK3568_SYS_CTRL_LINE_FLAG0 + line_flag_offset, LINE_FLAG_NUM_MASK,
RK3568_DSP_LINE_FLAG_NUM1_SHIFT, act_end, false);
+
+ if (cstate->mcu_timing.mcu_pix_total)
+ vop3_mcu_mode_setup(state);
return 0;
}
@@ -3071,71 +3974,129 @@
{
uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
uint16_t hscl_filter_mode, vscl_filter_mode;
- uint8_t gt2 = 0, gt4 = 0;
+ uint8_t xgt2 = 0, xgt4 = 0;
+ uint8_t ygt2 = 0, ygt4 = 0;
uint32_t xfac = 0, yfac = 0;
- uint16_t hsu_filter_mode = VOP2_SCALE_UP_BIC;
- uint16_t hsd_filter_mode = VOP2_SCALE_DOWN_BIL;
- uint16_t vsu_filter_mode = VOP2_SCALE_UP_BIL;
- uint16_t vsd_filter_mode = VOP2_SCALE_DOWN_BIL;
u32 win_offset = win->reg_offset;
+ bool xgt_en = false;
+ bool xavg_en = false;
- if (src_h >= (4 * dst_h))
- gt4 = 1;
- else if (src_h >= (2 * dst_h))
- gt2 = 1;
+ if (is_vop3(vop2)) {
+ if (src_w >= (4 * dst_w)) {
+ xgt4 = 1;
+ src_w >>= 2;
+ } else if (src_w >= (2 * dst_w)) {
+ xgt2 = 1;
+ src_w >>= 1;
+ }
+ }
- if (gt4)
+ if (src_h >= (4 * dst_h)) {
+ ygt4 = 1;
src_h >>= 2;
- else if (gt2)
+ } else if (src_h >= (2 * dst_h)) {
+ ygt2 = 1;
src_h >>= 1;
+ }
yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
if (yrgb_hor_scl_mode == SCALE_UP)
- hscl_filter_mode = hsu_filter_mode;
+ hscl_filter_mode = win->hsu_filter_mode;
else
- hscl_filter_mode = hsd_filter_mode;
+ hscl_filter_mode = win->hsd_filter_mode;
if (yrgb_ver_scl_mode == SCALE_UP)
- vscl_filter_mode = vsu_filter_mode;
+ vscl_filter_mode = win->vsu_filter_mode;
else
- vscl_filter_mode = vsd_filter_mode;
+ vscl_filter_mode = win->vsd_filter_mode;
/*
* RK3568 VOP Esmart/Smart dsp_w should be even pixel
* at scale down mode
*/
- if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
+ if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1) && !is_vop3(vop2)) {
printf("win dst_w[%d] should align as 2 pixel\n", dst_w);
dst_w += 1;
}
- xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
- yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
+ if (is_vop3(vop2)) {
+ xfac = vop3_scale_factor(yrgb_hor_scl_mode, src_w, dst_w, true);
+ yfac = vop3_scale_factor(yrgb_ver_scl_mode, src_h, dst_h, false);
+
+ if (win->hsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_AVG)
+ xavg_en = xgt2 || xgt4;
+ else
+ xgt_en = xgt2 || xgt4;
+ } else {
+ xfac = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode, src_w, dst_w);
+ yfac = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode, src_h, dst_h);
+ }
if (win->type == CLUSTER_LAYER) {
vop2_writel(vop2, RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB + win_offset,
yfac << 16 | xfac);
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
- YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, gt2, false);
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
- YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, gt4, false);
+ if (is_vop3(vop2)) {
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ EN_MASK, CLUSTER_XGT_EN_SHIFT, xgt_en, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ EN_MASK, CLUSTER_XAVG_EN_SHIFT, xavg_en, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ XGT_MODE_MASK, CLUSTER_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
- YRGB_XSCL_MODE_MASK, CLUSTER_YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
- vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
- YRGB_YSCL_MODE_MASK, CLUSTER_YRGB_YSCL_MODE_SHIFT, yrgb_ver_scl_mode, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_XSCL_MODE_MASK, RK3528_CLUSTER_YRGB_XSCL_MODE_SHIFT,
+ yrgb_hor_scl_mode, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_YSCL_MODE_MASK, RK3528_CLUSTER_YRGB_YSCL_MODE_SHIFT,
+ yrgb_ver_scl_mode, false);
+ } else {
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_XSCL_MODE_MASK, RK3568_CLUSTER_YRGB_XSCL_MODE_SHIFT,
+ yrgb_hor_scl_mode, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_YSCL_MODE_MASK, RK3568_CLUSTER_YRGB_YSCL_MODE_SHIFT,
+ yrgb_ver_scl_mode, false);
+ }
+ if (!is_vop3(vop2) || win->vsd_pre_filter_mode == VOP3_PRE_SCALE_DOWN_GT) {
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, ygt2, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, ygt4, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ AVG2_MASK, CLUSTER_AVG2_SHIFT, 0, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ AVG4_MASK, CLUSTER_AVG4_SHIFT, 0, false);
+ } else {
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_GT2_MASK, CLUSTER_YRGB_GT2_SHIFT, 0, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ YRGB_GT4_MASK, CLUSTER_YRGB_GT4_SHIFT, 0, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ AVG2_MASK, CLUSTER_AVG2_SHIFT, ygt2, false);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL1 + win_offset,
+ AVG4_MASK, CLUSTER_AVG4_SHIFT, ygt4, false);
+ }
} else {
vop2_writel(vop2, RK3568_ESMART0_REGION0_SCL_FACTOR_YRGB + win_offset,
yfac << 16 | xfac);
+ if (is_vop3(vop2)) {
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
+ EN_MASK, ESMART_XGT_EN_SHIFT, xgt_en, false);
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
+ EN_MASK, ESMART_XAVG_EN_SHIFT, xavg_en, false);
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
+ XGT_MODE_MASK, ESMART_XGT_MODE_SHIFT, xgt2 ? 0 : 1, false);
+ }
+
vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
- YRGB_GT2_MASK, YRGB_GT2_SHIFT, gt2, false);
+ YRGB_GT2_MASK, YRGB_GT2_SHIFT, ygt2, false);
vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset,
- YRGB_GT4_MASK, YRGB_GT4_SHIFT, gt4, false);
+ YRGB_GT4_MASK, YRGB_GT4_SHIFT, ygt4, false);
vop2_mask_write(vop2, RK3568_ESMART0_REGION0_SCL_CTRL + win_offset,
YRGB_XSCL_MODE_MASK, YRGB_XSCL_MODE_SHIFT, yrgb_hor_scl_mode, false);
@@ -3172,6 +4133,16 @@
}
}
+static bool vop2_win_dither_up(uint32_t format)
+{
+ switch (format) {
+ case ROCKCHIP_FMT_RGB565:
+ return true;
+ default:
+ return false;
+ }
+}
+
static void vop2_set_cluster_win(struct display_state *state, struct vop2_win_data *win)
{
struct crtc_state *cstate = &state->crtc_state;
@@ -3193,6 +4164,7 @@
u32 splice_yrgb_offset = 0;
u32 win_offset = win->reg_offset;
u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
+ bool dither_up;
if (win->splice_mode_right) {
src_w = cstate->right_src_rect.w;
@@ -3223,11 +4195,17 @@
vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
- if (vop2->version == VOP_VERSION_RK3588)
+ if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 ||
+ vop2->version == VOP_VERSION_RK3562)
vop2_axi_config(vop2, win);
if (y_mirror)
printf("WARN: y mirror is unsupported by cluster window\n");
+
+ /* rk3588 should set half_blocK_en to 1 in line and tile mode */
+ if (vop2->version == VOP_VERSION_RK3588)
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_AFBCD_CTRL + win_offset,
+ EN_MASK, CLUSTER_AFBCD_HALF_BLOCK_SHIFT, 1, false);
vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset,
WIN_FORMAT_MASK, WIN_FORMAT_SHIFT, cstate->format,
@@ -3242,12 +4220,17 @@
vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK, WIN_EN_SHIFT, 1, false);
- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
CLUSTER_RGB2YUV_EN_SHIFT,
is_yuv_output(conn_state->bus_format), false);
vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, CSC_MODE_MASK,
CLUSTER_CSC_MODE_SHIFT, csc_mode, false);
+
+ dither_up = vop2_win_dither_up(cstate->format);
+ vop2_mask_write(vop2, RK3568_CLUSTER0_WIN0_CTRL0 + win_offset, EN_MASK,
+ CLUSTER_DITHER_UP_EN_SHIFT, dither_up, false);
+
vop2_mask_write(vop2, RK3568_CLUSTER0_CTRL + win_offset, EN_MASK, CLUSTER_EN_SHIFT, 1, false);
vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
@@ -3274,6 +4257,7 @@
u32 splice_yrgb_offset = 0;
u32 win_offset = win->reg_offset;
u32 cfg_done = CFG_DONE_EN | BIT(cstate->crtc_id) | (BIT(cstate->crtc_id) << 16);
+ bool dither_up;
if (win->splice_mode_right) {
src_w = cstate->right_src_rect.w;
@@ -3311,9 +4295,14 @@
else
y_mirror = 0;
+ if (is_vop3(vop2))
+ vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, ESMART_LB_SELECT_MASK,
+ ESMART_LB_SELECT_SHIFT, win->scale_engine_num, false);
+
vop2_setup_scale(vop2, win, src_w, src_h, crtc_w, crtc_h);
- if (vop2->version == VOP_VERSION_RK3588)
+ if (vop2->version == VOP_VERSION_RK3588 || vop2->version == VOP_VERSION_RK3528 ||
+ vop2->version == VOP_VERSION_RK3562)
vop2_axi_config(vop2, win);
if (y_mirror)
@@ -3337,12 +4326,16 @@
vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
WIN_EN_SHIFT, 1, false);
- csc_mode = vop2_convert_csc_mode(conn_state->color_space);
+ csc_mode = vop2_convert_csc_mode(conn_state->color_space, CSC_10BIT_DEPTH);
vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, EN_MASK,
RGB2YUV_EN_SHIFT,
is_yuv_output(conn_state->bus_format), false);
vop2_mask_write(vop2, RK3568_ESMART0_CTRL0 + win_offset, CSC_MODE_MASK,
CSC_MODE_SHIFT, csc_mode, false);
+
+ dither_up = vop2_win_dither_up(cstate->format);
+ vop2_mask_write(vop2, RK3568_ESMART0_REGION0_CTRL + win_offset, EN_MASK,
+ REGION0_DITHER_UP_EN_SHIFT, dither_up, false);
vop2_writel(vop2, RK3568_REG_CFG_DONE, cfg_done);
}
@@ -3412,6 +4405,10 @@
printf("invalid win id %d\n", primary_plane_id);
return -ENODEV;
}
+
+ /* ignore some plane register according vop3 esmart lb mode */
+ if (vop3_ignore_plane(vop2, win_data))
+ return -EACCES;
if (vop2->version == VOP_VERSION_RK3588) {
if (vop2_power_domain_on(vop2, win_data->pd_id))
@@ -3494,6 +4491,10 @@
if (cstate->dsc_enable)
vop2_dsc_cfg_done(state);
+ if (cstate->mcu_timing.mcu_pix_total)
+ vop2_mask_write(vop2, RK3562_VP0_MCU_CTRL + vp_offset, EN_MASK,
+ MCU_HOLD_MODE_SHIFT, 0, false);
+
return 0;
}
@@ -3570,7 +4571,7 @@
int vp_id = 0;
int cursor_plane_id = -1;
- if (vop_fix_dts)
+ if (vop_fix_dts || vop2->version == VOP_VERSION_RK3528)
return 0;
ofnode_for_each_subnode(vp_node, np_to_ofnode(port_parent_node)) {
@@ -3638,6 +4639,53 @@
return 0;
}
+static int rockchip_vop2_mode_fixup(struct display_state *state)
+{
+ struct connector_state *conn_state = &state->conn_state;
+ struct drm_display_mode *mode = &conn_state->mode;
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V | CRTC_STEREO_DOUBLE);
+
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK || conn_state->output_if & VOP_OUTPUT_IF_BT656)
+ mode->crtc_clock *= 2;
+
+ /*
+ * For RK3528, the path of CVBS output is like:
+ * VOP BT656 ENCODER -> CVBS BT656 DECODER -> CVBS ENCODER -> CVBS VDAC
+ * The vop2 dclk should be four times crtc_clock for CVBS sampling
+ * clock needs.
+ */
+ if (vop2->version == VOP_VERSION_RK3528 && conn_state->output_if & VOP_OUTPUT_IF_BT656)
+ mode->crtc_clock *= 4;
+
+ if (cstate->mcu_timing.mcu_pix_total) {
+ if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888)
+ /*
+ * For serial output_mode rgb3x8, one pixel need 3 cycles.
+ * So dclk should be three times mode clock.
+ */
+ mode->crtc_clock *= 3;
+ else if (conn_state->output_mode == ROCKCHIP_OUT_MODE_S888_DUMMY)
+ /*
+ * For serial output_mode argb4x8, one pixel need 4 cycles.
+ * So dclk should be four times mode clock.
+ */
+ mode->crtc_clock *= 4;
+ }
+
+ if (conn_state->secondary) {
+ mode->crtc_clock *= 2;
+ mode->crtc_hdisplay *= 2;
+ mode->crtc_hsync_start *= 2;
+ mode->crtc_hsync_end *= 2;
+ mode->crtc_htotal *= 2;
+ }
+
+ return 0;
+}
+
#define FRAC_16_16(mult, div) (((mult) << 16) / (div))
static int rockchip_vop2_plane_check(struct display_state *state)
@@ -3665,10 +4713,526 @@
if (hscale < 0 || vscale < 0) {
printf("ERROR: VP%d %s: scale factor is out of range\n", cstate->crtc_id, win_data->name);
return -ERANGE;
+ }
+
+ return 0;
+}
+
+static int rockchip_vop2_apply_soft_te(struct display_state *state)
+{
+ __maybe_unused struct connector_state *conn_state = &state->conn_state;
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+ u32 vp_offset = (cstate->crtc_id * 0x100);
+ int val = 0;
+ int ret = 0;
+
+ ret = readl_poll_timeout(vop2->regs + RK3568_VP0_MIPI_CTRL + vp_offset, val,
+ (val >> EDPI_WMS_FS) & 0x1, 50 * 1000);
+ if (!ret) {
+#ifndef CONFIG_SPL_BUILD
+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
+ !val, 50 * 1000);
+ if (!ret) {
+ ret = readx_poll_timeout(dm_gpio_get_value, conn_state->te_gpio, val,
+ val, 50 * 1000);
+ if (!ret) {
+ vop2_mask_write(vop2, RK3568_VP0_MIPI_CTRL + vp_offset,
+ EN_MASK, EDPI_WMS_FS, 1, false);
+ } else {
+ printf("ERROR: vp%d wait for active TE signal timeout\n",
+ cstate->crtc_id);
+ return ret;
+ }
+ } else {
+ printf("ERROR: vp%d TE signal maybe always high\n", cstate->crtc_id);
+ return ret;
+ }
+#endif
+ } else {
+ printf("ERROR: vp%d wait vop2 frame start timeout in hold mode\n", cstate->crtc_id);
+ return ret;
}
return 0;
}
+
+static int rockchip_vop2_regs_dump(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+ const struct vop2_data *vop2_data = vop2->data;
+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
+ u32 n, i, j;
+ u32 base;
+
+ if (!cstate->crtc->active)
+ return -EINVAL;
+
+ n = vop2_data->dump_regs_size;
+ for (i = 0; i < n; i++) {
+ base = regs[i].offset;
+ printf("\n%s:\n", regs[i].name);
+ for (j = 0; j < 68;) {
+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
+ vop2_readl(vop2, base + (4 * j)),
+ vop2_readl(vop2, base + (4 * (j + 1))),
+ vop2_readl(vop2, base + (4 * (j + 2))),
+ vop2_readl(vop2, base + (4 * (j + 3))));
+ j += 4;
+ }
+ }
+
+ return 0;
+}
+
+static int rockchip_vop2_active_regs_dump(struct display_state *state)
+{
+ struct crtc_state *cstate = &state->crtc_state;
+ struct vop2 *vop2 = cstate->private;
+ const struct vop2_data *vop2_data = vop2->data;
+ const struct vop2_dump_regs *regs = vop2_data->dump_regs;
+ u32 n, i, j;
+ u32 base;
+ bool enable_state;
+
+ if (!cstate->crtc->active)
+ return -EINVAL;
+
+ n = vop2_data->dump_regs_size;
+ for (i = 0; i < n; i++) {
+ if (regs[i].state_mask) {
+ enable_state = (vop2_readl(vop2, regs[i].state_base) >> regs[i].state_shift) &
+ regs[i].state_mask;
+ if (enable_state != regs[i].enable_state)
+ continue;
+ }
+
+ base = regs[i].offset;
+ printf("\n%s:\n", regs[i].name);
+ for (j = 0; j < 68;) {
+ printf("%08lx: %08x %08x %08x %08x\n", (uintptr_t)vop2->regs + base + j * 4,
+ vop2_readl(vop2, base + (4 * j)),
+ vop2_readl(vop2, base + (4 * (j + 1))),
+ vop2_readl(vop2, base + (4 * (j + 2))),
+ vop2_readl(vop2, base + (4 * (j + 3))));
+ j += 4;
+ }
+ }
+
+ return 0;
+}
+
+static struct vop2_dump_regs rk3528_dump_regs[] = {
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
+ { RK3528_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
+ { RK3528_ACM_CTRL, "ACM", RK3528_ACM_CTRL, 0x1, 0, 1},
+};
+
+static u8 rk3528_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
+ ROCKCHIP_VOP2_ESMART0,
+ ROCKCHIP_VOP2_ESMART1,
+ ROCKCHIP_VOP2_ESMART2,
+ ROCKCHIP_VOP2_ESMART3,
+};
+
+static struct vop2_plane_table rk3528_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
+ {ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
+};
+
+static struct vop2_vp_plane_mask rk3528_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
+ { /* one display policy for hdmi */
+ {/* main display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
+ .attached_layers_nr = 4,
+ .attached_layers = {
+ ROCKCHIP_VOP2_CLUSTER0,
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1, ROCKCHIP_VOP2_ESMART2
+ },
+ },
+ {/* second display */},
+ {/* third display */},
+ {/* fourth display */},
+ },
+
+ { /* two display policy */
+ {/* main display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
+ .attached_layers_nr = 3,
+ .attached_layers = {
+ ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
+ },
+ },
+
+ {/* second display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
+ .attached_layers_nr = 2,
+ .attached_layers = {
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
+ },
+ },
+ {/* third display */},
+ {/* fourth display */},
+ },
+
+ { /* one display policy for cvbs */
+ {/* main display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
+ .attached_layers_nr = 2,
+ .attached_layers = {
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
+ },
+ },
+ {/* second display */},
+ {/* third display */},
+ {/* fourth display */},
+ },
+
+ {/* reserved */},
+};
+
+static struct vop2_win_data rk3528_win_data[5] = {
+ {
+ .name = "Esmart0",
+ .phys_id = ROCKCHIP_VOP2_ESMART0,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 8,
+ .layer_sel_win_id = { 1, 0xff, 0xff, 0xff },
+ .reg_offset = 0,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x06,
+ .axi_uv_id = 0x07,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart1",
+ .phys_id = ROCKCHIP_VOP2_ESMART1,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 10,
+ .layer_sel_win_id = { 2, 0xff, 0xff, 0xff },
+ .reg_offset = 0x200,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x08,
+ .axi_uv_id = 0x09,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart2",
+ .phys_id = ROCKCHIP_VOP2_ESMART2,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 12,
+ .layer_sel_win_id = { 3, 0, 0xff, 0xff },
+ .reg_offset = 0x400,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x0a,
+ .axi_uv_id = 0x0b,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart3",
+ .phys_id = ROCKCHIP_VOP2_ESMART3,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 14,
+ .layer_sel_win_id = { 0xff, 1, 0xff, 0xff },
+ .reg_offset = 0x600,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x0c,
+ .axi_uv_id = 0x0d,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT, /* gt only */
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Cluster0",
+ .phys_id = ROCKCHIP_VOP2_CLUSTER0,
+ .type = CLUSTER_LAYER,
+ .win_sel_port_offset = 0,
+ .layer_sel_win_id = { 0, 0xff, 0xff, 0xff },
+ .reg_offset = 0,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x02,
+ .axi_uv_id = 0x03,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG, /* gt or avg */
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+};
+
+static struct vop2_vp_data rk3528_vp_data[2] = {
+ {
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_POST_ACM |
+ VOP_FEATURE_POST_CSC,
+ .max_output = {4096, 4096},
+ .layer_mix_dly = 6,
+ .hdr_mix_dly = 2,
+ .win_dly = 8,
+ },
+ {
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
+ .max_output = {1920, 1080},
+ .layer_mix_dly = 2,
+ .hdr_mix_dly = 0,
+ .win_dly = 8,
+ },
+};
+
+const struct vop2_data rk3528_vop = {
+ .version = VOP_VERSION_RK3528,
+ .nr_vps = 2,
+ .vp_data = rk3528_vp_data,
+ .win_data = rk3528_win_data,
+ .plane_mask = rk3528_vp_plane_mask[0],
+ .plane_table = rk3528_plane_table,
+ .vp_primary_plane_order = rk3528_vp_primary_plane_order,
+ .nr_layers = 5,
+ .nr_mixers = 3,
+ .nr_gammas = 2,
+ .esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
+ .dump_regs = rk3528_dump_regs,
+ .dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
+};
+
+static struct vop2_dump_regs rk3562_dump_regs[] = {
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
+ { RK3528_OVL_SYS, "OVL_SYS", 0, 0, 0, 0 },
+ { RK3528_OVL_PORT0_CTRL, "OVL_VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
+ { RK3528_OVL_PORT1_CTRL, "OVL_VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_CTRL0, 0x1, 0, 1 },
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_CTRL0, 0x1, 0, 1 },
+};
+
+static u8 rk3562_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
+ ROCKCHIP_VOP2_ESMART0,
+ ROCKCHIP_VOP2_ESMART1,
+ ROCKCHIP_VOP2_ESMART2,
+ ROCKCHIP_VOP2_ESMART3,
+};
+
+static struct vop2_plane_table rk3562_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
+ {ROCKCHIP_VOP2_ESMART0, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART1, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART2, ESMART_LAYER},
+ {ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
+};
+
+static struct vop2_vp_plane_mask rk3562_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
+ { /* one display policy for hdmi */
+ {/* main display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
+ .attached_layers_nr = 4,
+ .attached_layers = {
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1,
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
+ },
+ },
+ {/* second display */},
+ {/* third display */},
+ {/* fourth display */},
+ },
+
+ { /* two display policy */
+ {/* main display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
+ .attached_layers_nr = 2,
+ .attached_layers = {
+ ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART1
+ },
+ },
+
+ {/* second display */
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
+ .attached_layers_nr = 2,
+ .attached_layers = {
+ ROCKCHIP_VOP2_ESMART2, ROCKCHIP_VOP2_ESMART3
+ },
+ },
+ {/* third display */},
+ {/* fourth display */},
+ },
+
+ {/* reserved */},
+};
+
+static struct vop2_win_data rk3562_win_data[4] = {
+ {
+ .name = "Esmart0",
+ .phys_id = ROCKCHIP_VOP2_ESMART0,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 8,
+ .layer_sel_win_id = { 0, 0, 0xff, 0xff },
+ .reg_offset = 0,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x02,
+ .axi_uv_id = 0x03,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart1",
+ .phys_id = ROCKCHIP_VOP2_ESMART1,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 10,
+ .layer_sel_win_id = { 1, 1, 0xff, 0xff },
+ .reg_offset = 0x200,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x04,
+ .axi_uv_id = 0x05,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart2",
+ .phys_id = ROCKCHIP_VOP2_ESMART2,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 12,
+ .layer_sel_win_id = { 2, 2, 0xff, 0xff },
+ .reg_offset = 0x400,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x06,
+ .axi_uv_id = 0x07,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+
+ {
+ .name = "Esmart3",
+ .phys_id = ROCKCHIP_VOP2_ESMART3,
+ .type = ESMART_LAYER,
+ .win_sel_port_offset = 14,
+ .layer_sel_win_id = { 3, 3, 0xff, 0xff },
+ .reg_offset = 0x600,
+ .axi_id = 0,
+ .axi_yrgb_id = 0x08,
+ .axi_uv_id = 0x0d,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .max_upscale_factor = 8,
+ .max_downscale_factor = 8,
+ },
+};
+
+static struct vop2_vp_data rk3562_vp_data[2] = {
+ {
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
+ .max_output = {2048, 4096},
+ .win_dly = 8,
+ .layer_mix_dly = 8,
+ },
+ {
+ .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
+ .max_output = {2048, 1080},
+ .win_dly = 8,
+ .layer_mix_dly = 8,
+ },
+};
+
+const struct vop2_data rk3562_vop = {
+ .version = VOP_VERSION_RK3562,
+ .nr_vps = 2,
+ .vp_data = rk3562_vp_data,
+ .win_data = rk3562_win_data,
+ .plane_mask = rk3562_vp_plane_mask[0],
+ .plane_table = rk3562_plane_table,
+ .vp_primary_plane_order = rk3562_vp_primary_plane_order,
+ .nr_layers = 4,
+ .nr_mixers = 3,
+ .nr_gammas = 2,
+ .esmart_lb_mode = VOP3_ESMART_2K_2K_2K_2K_MODE,
+ .dump_regs = rk3562_dump_regs,
+ .dump_regs_size = ARRAY_SIZE(rk3562_dump_regs),
+};
+
+static struct vop2_dump_regs rk3568_dump_regs[] = {
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART0_CTRL0, "Smart0", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART1_CTRL0, "Smart1", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
+};
+
+static u8 rk3568_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
+ ROCKCHIP_VOP2_SMART0,
+ ROCKCHIP_VOP2_SMART1,
+ ROCKCHIP_VOP2_ESMART0,
+ ROCKCHIP_VOP2_ESMART1,
+};
+
static struct vop2_plane_table rk356x_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
{ROCKCHIP_VOP2_CLUSTER0, CLUSTER_LAYER},
{ROCKCHIP_VOP2_CLUSTER1, CLUSTER_LAYER},
@@ -3748,8 +5312,12 @@
.phys_id = ROCKCHIP_VOP2_CLUSTER0,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 0,
- .layer_sel_win_id = 0,
+ .layer_sel_win_id = { 0, 0, 0, 0xff },
.reg_offset = 0,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -3759,8 +5327,12 @@
.phys_id = ROCKCHIP_VOP2_CLUSTER1,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 1,
- .layer_sel_win_id = 1,
+ .layer_sel_win_id = { 1, 1, 1, 0xff },
.reg_offset = 0x200,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -3770,8 +5342,12 @@
.phys_id = ROCKCHIP_VOP2_ESMART0,
.type = ESMART_LAYER,
.win_sel_port_offset = 4,
- .layer_sel_win_id = 2,
+ .layer_sel_win_id = { 2, 2, 2, 0xff },
.reg_offset = 0,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -3781,8 +5357,12 @@
.phys_id = ROCKCHIP_VOP2_ESMART1,
.type = ESMART_LAYER,
.win_sel_port_offset = 5,
- .layer_sel_win_id = 6,
+ .layer_sel_win_id = { 6, 6, 6, 0xff },
.reg_offset = 0x200,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -3792,8 +5372,12 @@
.phys_id = ROCKCHIP_VOP2_SMART0,
.type = SMART_LAYER,
.win_sel_port_offset = 6,
- .layer_sel_win_id = 3,
+ .layer_sel_win_id = { 3, 3, 3, 0xff },
.reg_offset = 0x400,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -3803,8 +5387,12 @@
.phys_id = ROCKCHIP_VOP2_SMART1,
.type = SMART_LAYER,
.win_sel_port_offset = 7,
- .layer_sel_win_id = 7,
+ .layer_sel_win_id = { 7, 7, 7, 0xff },
.reg_offset = 0x600,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -3835,9 +5423,23 @@
.win_data = rk3568_win_data,
.plane_mask = rk356x_vp_plane_mask[0],
.plane_table = rk356x_plane_table,
+ .vp_primary_plane_order = rk3568_vp_primary_plane_order,
.nr_layers = 6,
.nr_mixers = 5,
.nr_gammas = 1,
+ .dump_regs = rk3568_dump_regs,
+ .dump_regs_size = ARRAY_SIZE(rk3568_dump_regs),
+};
+
+static u8 rk3588_vp_primary_plane_order[ROCKCHIP_VOP2_LAYER_MAX] = {
+ ROCKCHIP_VOP2_ESMART0,
+ ROCKCHIP_VOP2_ESMART1,
+ ROCKCHIP_VOP2_ESMART2,
+ ROCKCHIP_VOP2_ESMART3,
+ ROCKCHIP_VOP2_CLUSTER0,
+ ROCKCHIP_VOP2_CLUSTER1,
+ ROCKCHIP_VOP2_CLUSTER2,
+ ROCKCHIP_VOP2_CLUSTER3,
};
static struct vop2_plane_table rk3588_plane_table[ROCKCHIP_VOP2_LAYER_MAX] = {
@@ -3851,10 +5453,28 @@
{ROCKCHIP_VOP2_ESMART3, ESMART_LAYER},
};
+static struct vop2_dump_regs rk3588_dump_regs[] = {
+ { RK3568_REG_CFG_DONE, "SYS", 0, 0, 0, 0 },
+ { RK3568_OVL_CTRL, "OVL", 0, 0, 0, 0 },
+ { RK3568_VP0_DSP_CTRL, "VP0", RK3568_VP0_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP1_DSP_CTRL, "VP1", RK3568_VP1_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_VP2_DSP_CTRL, "VP2", RK3568_VP2_DSP_CTRL, 0x1, 31, 0 },
+ { RK3588_VP3_DSP_CTRL, "VP3", RK3588_VP3_DSP_CTRL, 0x1, 31, 0 },
+ { RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3568_CLUSTER1_WIN0_CTRL0, "Cluster1", RK3568_CLUSTER1_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3588_CLUSTER2_WIN0_CTRL0, "Cluster2", RK3588_CLUSTER2_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3588_CLUSTER3_WIN0_CTRL0, "Cluster3", RK3588_CLUSTER3_WIN0_CTRL0, 0x1, 0, 1 },
+ { RK3568_ESMART0_CTRL0, "Esmart0", RK3568_ESMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_ESMART1_CTRL0, "Esmart1", RK3568_ESMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART0_CTRL0, "Esmart2", RK3568_SMART0_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_SMART1_CTRL0, "Esmart3", RK3568_SMART1_REGION0_CTRL, 0x1, 0, 1 },
+ { RK3568_HDR_LUT_CTRL, "HDR", 0, 0, 0, 0 },
+};
+
static struct vop2_vp_plane_mask rk3588_vp_plane_mask[VOP2_VP_MAX][VOP2_VP_MAX] = {
{ /* one display policy */
{/* main display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
.attached_layers_nr = 8,
.attached_layers = {
ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0, ROCKCHIP_VOP2_ESMART2,
@@ -3869,7 +5489,7 @@
{ /* two display policy */
{/* main display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
.attached_layers_nr = 4,
.attached_layers = {
ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0,
@@ -3878,7 +5498,7 @@
},
{/* second display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
.attached_layers_nr = 4,
.attached_layers = {
ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2,
@@ -3891,7 +5511,7 @@
{ /* three display policy */
{/* main display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
.attached_layers_nr = 3,
.attached_layers = {
ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART0
@@ -3899,7 +5519,7 @@
},
{/* second display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
.attached_layers_nr = 3,
.attached_layers = {
ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART1
@@ -3917,25 +5537,25 @@
{ /* four display policy */
{/* main display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER0,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART0,
.attached_layers_nr = 2,
.attached_layers = { ROCKCHIP_VOP2_CLUSTER0, ROCKCHIP_VOP2_ESMART0 },
},
{/* second display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER1,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART1,
.attached_layers_nr = 2,
.attached_layers = { ROCKCHIP_VOP2_CLUSTER1, ROCKCHIP_VOP2_ESMART1 },
},
{/* third display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER2,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART2,
.attached_layers_nr = 2,
.attached_layers = { ROCKCHIP_VOP2_CLUSTER2, ROCKCHIP_VOP2_ESMART2 },
},
{/* fourth display */
- .primary_plane_id = ROCKCHIP_VOP2_CLUSTER3,
+ .primary_plane_id = ROCKCHIP_VOP2_ESMART3,
.attached_layers_nr = 2,
.attached_layers = { ROCKCHIP_VOP2_CLUSTER3, ROCKCHIP_VOP2_ESMART3 },
},
@@ -3950,12 +5570,16 @@
.splice_win_id = ROCKCHIP_VOP2_CLUSTER1,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 0,
- .layer_sel_win_id = 0,
+ .layer_sel_win_id = { 0, 0, 0, 0 },
.reg_offset = 0,
.axi_id = 0,
.axi_yrgb_id = 2,
.axi_uv_id = 3,
.pd_id = VOP2_PD_CLUSTER0,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -3965,12 +5589,16 @@
.phys_id = ROCKCHIP_VOP2_CLUSTER1,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 1,
- .layer_sel_win_id = 1,
+ .layer_sel_win_id = { 1, 1, 1, 1 },
.reg_offset = 0x200,
.axi_id = 0,
.axi_yrgb_id = 6,
.axi_uv_id = 7,
.pd_id = VOP2_PD_CLUSTER1,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -3981,12 +5609,16 @@
.splice_win_id = ROCKCHIP_VOP2_CLUSTER3,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 2,
- .layer_sel_win_id = 4,
+ .layer_sel_win_id = { 4, 4, 4, 4 },
.reg_offset = 0x400,
.axi_id = 1,
.axi_yrgb_id = 2,
.axi_uv_id = 3,
.pd_id = VOP2_PD_CLUSTER2,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -3996,12 +5628,16 @@
.phys_id = ROCKCHIP_VOP2_CLUSTER3,
.type = CLUSTER_LAYER,
.win_sel_port_offset = 3,
- .layer_sel_win_id = 5,
+ .layer_sel_win_id = { 5, 5, 5, 5 },
.reg_offset = 0x600,
.axi_id = 1,
.axi_yrgb_id = 6,
.axi_uv_id = 7,
.pd_id = VOP2_PD_CLUSTER3,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 4,
.max_downscale_factor = 4,
},
@@ -4012,11 +5648,15 @@
.splice_win_id = ROCKCHIP_VOP2_ESMART1,
.type = ESMART_LAYER,
.win_sel_port_offset = 4,
- .layer_sel_win_id = 2,
+ .layer_sel_win_id = { 2, 2, 2, 2 },
.reg_offset = 0,
.axi_id = 0,
.axi_yrgb_id = 0x0a,
.axi_uv_id = 0x0b,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -4026,12 +5666,16 @@
.phys_id = ROCKCHIP_VOP2_ESMART1,
.type = ESMART_LAYER,
.win_sel_port_offset = 5,
- .layer_sel_win_id = 3,
+ .layer_sel_win_id = { 3, 3, 3, 3 },
.reg_offset = 0x200,
.axi_id = 0,
.axi_yrgb_id = 0x0c,
.axi_uv_id = 0x0d,
.pd_id = VOP2_PD_ESMART,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -4042,12 +5686,16 @@
.splice_win_id = ROCKCHIP_VOP2_ESMART3,
.type = ESMART_LAYER,
.win_sel_port_offset = 6,
- .layer_sel_win_id = 6,
+ .layer_sel_win_id = { 6, 6, 6, 6 },
.reg_offset = 0x400,
.axi_id = 1,
.axi_yrgb_id = 0x0a,
.axi_uv_id = 0x0b,
.pd_id = VOP2_PD_ESMART,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -4057,12 +5705,16 @@
.phys_id = ROCKCHIP_VOP2_ESMART3,
.type = ESMART_LAYER,
.win_sel_port_offset = 7,
- .layer_sel_win_id = 7,
+ .layer_sel_win_id = { 7, 7, 7, 7 },
.reg_offset = 0x600,
.axi_id = 1,
.axi_yrgb_id = 0x0c,
.axi_uv_id = 0x0d,
.pd_id = VOP2_PD_ESMART,
+ .hsu_filter_mode = VOP2_SCALE_UP_BIC,
+ .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
+ .vsu_filter_mode = VOP2_SCALE_UP_BIL,
+ .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
.max_upscale_factor = 8,
.max_downscale_factor = 8,
},
@@ -4218,6 +5870,7 @@
.dsc = rk3588_dsc_data,
.dsc_error_ecw = dsc_ecw,
.dsc_error_buffer_flow = dsc_buffer_flow,
+ .vp_primary_plane_order = rk3588_vp_primary_plane_order,
.nr_layers = 8,
.nr_mixers = 7,
.nr_gammas = 4,
@@ -4225,6 +5878,8 @@
.nr_dscs = 2,
.nr_dsc_ecw = ARRAY_SIZE(dsc_ecw),
.nr_dsc_buffer_flow = ARRAY_SIZE(dsc_buffer_flow),
+ .dump_regs = rk3588_dump_regs,
+ .dump_regs_size = ARRAY_SIZE(rk3588_dump_regs),
};
const struct rockchip_crtc_funcs rockchip_vop2_funcs = {
@@ -4235,7 +5890,12 @@
.enable = rockchip_vop2_enable,
.disable = rockchip_vop2_disable,
.fixup_dts = rockchip_vop2_fixup_dts,
+ .send_mcu_cmd = rockchip_vop2_send_mcu_cmd,
.check = rockchip_vop2_check,
.mode_valid = rockchip_vop2_mode_valid,
+ .mode_fixup = rockchip_vop2_mode_fixup,
.plane_check = rockchip_vop2_plane_check,
+ .regs_dump = rockchip_vop2_regs_dump,
+ .active_regs_dump = rockchip_vop2_active_regs_dump,
+ .apply_soft_te = rockchip_vop2_apply_soft_te,
};
diff --git a/u-boot/drivers/video/drm/rockchip_vop_reg.c b/u-boot/drivers/video/drm/rockchip_vop_reg.c
index 710ba20..4bfb85f 100644
--- a/u-boot/drivers/video/drm/rockchip_vop_reg.c
+++ b/u-boot/drivers/video/drm/rockchip_vop_reg.c
@@ -140,6 +140,11 @@
.dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
.dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
+ .dsp_bg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 12),
+ .dsp_rb_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 13),
+ .dsp_rg_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 14),
+ .dsp_delta_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 15),
+ .dsp_dummy_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1, 16),
.dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
.dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
.dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
@@ -383,6 +388,11 @@
.dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
.dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
+ .dsp_bg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 12),
+ .dsp_rb_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 13),
+ .dsp_rg_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 14),
+ .dsp_delta_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 15),
+ .dsp_dummy_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1, 16),
.dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
.dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
.dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
@@ -544,6 +554,9 @@
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
@@ -642,6 +655,9 @@
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
@@ -754,6 +770,9 @@
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
.dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
@@ -826,6 +845,9 @@
.dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 8),
.dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
.dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
+ .dsp_bg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 9),
+ .dsp_rb_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 11),
+ .dsp_rg_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 12),
.dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
.dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
.dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
diff --git a/u-boot/drivers/video/drm/rohm-bu18rl82.c b/u-boot/drivers/video/drm/rohm-bu18rl82.c
index 020d369..db35848 100644
--- a/u-boot/drivers/video/drm/rohm-bu18rl82.c
+++ b/u-boot/drivers/video/drm/rohm-bu18rl82.c
@@ -47,6 +47,7 @@
(BU18RL82_SWRST_REG | BU18RL82_SWRST_EXCREG | BU18RL82_SWRST_ALL));
if (ret < 0)
printf("failed to reset bu18rl82(%s) ret=%d\n", bus->name, ret);
+ mdelay(5);
}
static int bu18rl82_serdes_init_sequence_write(struct bu18rl82_priv *priv)
diff --git a/u-boot/drivers/video/drm/rohm-bu18tl82.c b/u-boot/drivers/video/drm/rohm-bu18tl82.c
index bda247e..04b44e5 100644
--- a/u-boot/drivers/video/drm/rohm-bu18tl82.c
+++ b/u-boot/drivers/video/drm/rohm-bu18tl82.c
@@ -7,6 +7,7 @@
#include <dm.h>
#include <errno.h>
#include <i2c.h>
+#include <drm/drm_mipi_dsi.h>
#include <video_bridge.h>
#include <asm/unaligned.h>
#include <linux/media-bus-format.h>
@@ -31,6 +32,7 @@
struct udevice *power_supply;
struct gpio_desc enable_gpio;
struct serdes_init_seq *serdes_init_seq;
+ bool sel_mipi;
};
static void bu18tl82_bridge_reset(struct rockchip_bridge *bridge)
@@ -216,6 +218,20 @@
return ret;
}
+ priv->sel_mipi = dev_read_bool(dev, "sel-mipi");
+ if (priv->sel_mipi) {
+ struct mipi_dsi_device *device = dev_get_platdata(dev);
+
+ device->dev = dev;
+ device->lanes = dev_read_u32_default(dev, "dsi,lanes", 4);
+ device->format = dev_read_u32_default(dev, "dsi,format",
+ MIPI_DSI_FMT_RGB888);
+ device->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
+ MIPI_DSI_MODE_VIDEO_HBP | MIPI_DSI_MODE_LPM |
+ MIPI_DSI_MODE_EOT_PACKET;
+ device->channel = dev_read_u32_default(dev, "reg", 0);
+ }
+
bridge = calloc(1, sizeof(*bridge));
if (!bridge)
return -ENOMEM;
@@ -250,4 +266,5 @@
.of_match = bu18tl82_of_match,
.probe = bu18tl82_probe,
.priv_auto_alloc_size = sizeof(struct bu18tl82_priv),
+ .platdata_auto_alloc_size = sizeof(struct mipi_dsi_device),
};
diff --git a/u-boot/drivers/watchdog/rockchip_wdt.c b/u-boot/drivers/watchdog/rockchip_wdt.c
index f2962d9..0c2398f 100644
--- a/u-boot/drivers/watchdog/rockchip_wdt.c
+++ b/u-boot/drivers/watchdog/rockchip_wdt.c
@@ -86,7 +86,8 @@
printf("Rockchip watchdog timeout: %lld sec\n", timeout / 1000);
- reset_deassert(&priv->rst);
+ if (priv->rst.dev)
+ reset_deassert(&priv->rst);
rockchip_wdt_reset(dev);
rockchip_wdt_settimeout(timeout, priv);
@@ -100,8 +101,10 @@
{
struct rockchip_wdt_priv *priv = dev_get_priv(dev);
- reset_assert(&priv->rst);
- reset_deassert(&priv->rst);
+ if (priv->rst.dev) {
+ reset_assert(&priv->rst);
+ reset_deassert(&priv->rst);
+ }
printf("Rockchip watchdog stop\n");
@@ -133,7 +136,7 @@
ret = reset_get_by_name(dev, "reset", &priv->rst);
if (ret) {
pr_err("reset_get_by_name(reset) failed: %d\n", ret);
- return ret;
+ priv->rst.dev = NULL;
}
ret = clk_get_by_index(dev, 0, &priv->clk);
diff --git a/u-boot/env/envf.c b/u-boot/env/envf.c
index b469bd2..fc55afd 100644
--- a/u-boot/env/envf.c
+++ b/u-boot/env/envf.c
@@ -44,16 +44,6 @@
#endif
#ifdef CONFIG_DM_MMC
-static int pmbr_part_valid(struct partition *part)
-{
- if (part->sys_ind == EFI_PMBR_OSTYPE_EFI_GPT &&
- get_unaligned_le32(&part->start_sect) == 1UL) {
- return 1;
- }
-
- return 0;
-}
-
static int is_pmbr_valid(legacy_mbr * mbr)
{
int i = 0;
@@ -62,10 +52,10 @@
return 0;
for (i = 0; i < 4; i++) {
- if (pmbr_part_valid(&mbr->partition_record[i])) {
+ if (mbr->partition_record[i].sys_ind == 0xc)
return 1;
- }
}
+
return 0;
}
@@ -76,10 +66,10 @@
/* Read legacy MBR from block 0 and validate it */
if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
|| (is_pmbr_valid(legacymbr) != 1)) {
- return -1;
+ return 0;
}
- return 0;
+ return 1;
}
#endif
@@ -262,35 +252,6 @@
return envf_num;
}
-#ifdef CONFIG_ENV_PARTITION
-static int envf_add_partition_bootargs(void)
-{
- char *part_list;
- char *bootargs;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(part_type); i++) {
- part_list = env_get(part_type[i]);
- if (part_list)
- break;
- }
- if (!part_list)
- return -EINVAL;
-
- bootargs = calloc(1, strlen(part_list) + strlen(part_type[i]) + 2);
- if (!bootargs)
- return -ENOMEM;
-
- strcat(bootargs, part_type[i]);
- strcat(bootargs, "=");
- strcat(bootargs, part_list);
- env_update("bootargs", bootargs);
- free(bootargs);
-
- return 0;
-}
-#endif
-
static int envf_load(void)
{
struct blk_desc *desc;
@@ -313,10 +274,6 @@
return -EINTR;
}
}
-
-#ifdef CONFIG_ENV_PARTITION
- envf_add_partition_bootargs();
-#endif
return 0;
}
diff --git a/u-boot/examples/standalone/Makefile b/u-boot/examples/standalone/Makefile
index c9d6206..cd870f6 100644
--- a/u-boot/examples/standalone/Makefile
+++ b/u-boot/examples/standalone/Makefile
@@ -10,6 +10,7 @@
extra-$(CONFIG_SMC911X) += smc911x_eeprom
extra-$(CONFIG_SPI_FLASH_ATMEL) += atmel_df_pow2
extra-$(CONFIG_PPC) += sched
+extra-$(CONFIG_ROCKCHIP_SPI) += rkspi
#
# Some versions of make do not handle trailing white spaces properly;
diff --git a/u-boot/examples/standalone/README_rkspi.md b/u-boot/examples/standalone/README_rkspi.md
new file mode 100644
index 0000000..7cb986b
--- /dev/null
+++ b/u-boot/examples/standalone/README_rkspi.md
@@ -0,0 +1,126 @@
+# RK SPI Standalone Bin
+
+This is the readme for the Das U-Boot standalone program rkspi
+
+
+How To Use
+------------------------
+### Compile
+
+1.Define the standalone load address in includes/configs/rkxxxxx_common.h
+
+```shell
+#define CONFIG_STANDALONE_LOAD_ADDR 0x40000000
+```
+
+2.Enable rkspi in defconfig
+
+```
+CONFIG_ROCKCHIP_SPI=y
+```
+
+### Setting SPI hardware
+
+1.Setting the iomux and spiclk through:
+
+- u-boot shell command
+- define it in rkspi.c spi_hw_init
+
+Note:
+
+- spiclk is the clock for spi controller, output to IO after internal frequency division of the controller.
+
+### Load And Executable
+
+1. load the bin by serial or tftp, take tftp as example:
+
+```shell
+setenv ipaddr 172.16.12.157
+setenv serverip 172.16.12.167
+tftp 0x40000000 rkspi.bin # 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR
+```
+
+2. execute it
+
+```shell
+go 0x40000000 # 0x40000000 is define by CONFIG_STANDALONE_LOAD_ADDR
+```
+
+## Abort Codes
+
+### Introduction
+
+```c
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode);
+```
+
+- bus: spi bus
+- base_addr: spi register base address
+- rsd: read sample clock shift with spiclk which is controller working rate
+- clock_div: internal frequency division of the controller
+- mode: spi mode, support:
+
+```c
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0 | 0) /* (original MicroWire) */
+#define SPI_MODE_1 (0 | SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL | 0)
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
+```
+
+
+
+```c
+int rockchip_spi_claim_bus(u8 bus);
+```
+
+- bus: spi bus
+
+
+
+```c
+void rockchip_spi_release_bus(u8 bus);
+```
+
+- bus: spi bus
+
+
+
+```c
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags);
+```
+
+- bus: spi bus
+- cs: spi cs
+- bitlen: the transfer length in bits
+- dout: write buffer (if exits)
+- din: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
+- flags: operation chip select, support:
+
+```c
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+```
+
+
+
+```c
+int rockchip_spi_write_then_read(u8 bus, u8 cs,
+ const u8 *opcode, size_t n_opcode,
+ const u8 *txbuf, u8 *rxbuf, size_t n_buf);
+```
+
+- bus: spi bus
+- cs: spi cs
+- opcode: command code
+- n_opcode: the numbers of command code in bytes
+- txbuf: write buffer (if exits)
+- rxbuf: read buffer (if exits), if the dout and din both defined, spi work in duplex mode
+- n_buf: the transfer length in bytes
+
+### Demo
+
+Is right in the main function of rkspi.
+
diff --git a/u-boot/examples/standalone/rkspi.c b/u-boot/examples/standalone/rkspi.c
new file mode 100644
index 0000000..e2e2bef
--- /dev/null
+++ b/u-boot/examples/standalone/rkspi.c
@@ -0,0 +1,454 @@
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <exports.h>
+
+#include "rkspi.h"
+
+/* Change to 1 to output registers at the start of each transaction */
+#define DEBUG_RK_SPI 0
+
+struct rockchip_spi_priv {
+ struct rockchip_spi *regs;
+ unsigned int mode;
+ u8 bits_per_word; /* max 16 bits per word */
+ u8 n_bytes;
+ unsigned int clock_div;
+ uint cr0;
+ u32 rsd; /* Rx sample delay cycles */
+};
+
+#define RK_SPI_BUS_MAX 5
+static struct rockchip_spi_priv spi_bus[RK_SPI_BUS_MAX];
+
+static inline struct rockchip_spi_priv *get_spi_bus(u8 bus)
+{
+ return &spi_bus[bus];
+}
+
+#define SPI_FIFO_DEPTH 32
+#define SPI_CR0_RSD_MAX 0x3
+
+static inline void writel(u32 val, void *addr)
+{
+ *(volatile u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+ return *(volatile u32 *)addr;
+}
+
+static void rkspi_dump_regs(struct rockchip_spi *regs)
+{
+ debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0));
+ debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1));
+ debug("ssienr: \t\t0x%08x\n", readl(®s->enr));
+ debug("ser: \t\t0x%08x\n", readl(®s->ser));
+ debug("baudr: \t\t0x%08x\n", readl(®s->baudr));
+ debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr));
+ debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr));
+ debug("txflr: \t\t0x%08x\n", readl(®s->txflr));
+ debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr));
+ debug("sr: \t\t0x%08x\n", readl(®s->sr));
+ debug("imr: \t\t0x%08x\n", readl(®s->imr));
+ debug("isr: \t\t0x%08x\n", readl(®s->isr));
+ debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr));
+ debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr));
+ debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr));
+}
+
+static void rkspi_enable_chip(struct rockchip_spi *regs, bool enable)
+{
+ writel(enable ? 1 : 0, ®s->enr);
+}
+
+static void rkspi_set_baudr(struct rockchip_spi_priv *priv, uint clk_div)
+{
+ writel(clk_div, &priv->regs->baudr);
+}
+
+static int rkspi_wait_till_not_busy(struct rockchip_spi *regs)
+{
+ unsigned long start;
+
+ start = get_timer(0);
+ while (readl(®s->sr) & SR_BUSY) {
+ if (get_timer(start) > ROCKCHIP_SPI_TIMEOUT_MS) {
+ debug("RK SPI: Status keeps busy for 1000us after a read/write!\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ return 0;
+}
+
+static void spi_cs_activate(u8 bus, u8 cs)
+{
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
+ struct rockchip_spi *regs = priv->regs;
+
+ debug("activate cs%u\n", cs);
+ writel(1 << cs, ®s->ser);
+}
+
+static void spi_cs_deactivate(u8 bus, u8 cs)
+{
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
+ struct rockchip_spi *regs = priv->regs;
+
+ debug("deactivate cs%u\n", cs);
+ writel(0, ®s->ser);
+}
+
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode)
+{
+ struct rockchip_spi_priv *priv;
+
+ if (bus >= RK_SPI_BUS_MAX) {
+ printf("%s bus %d is out of max num(%d)\n", __func__, bus, RK_SPI_BUS_MAX);
+ return -1;
+ }
+
+ debug("%s: probe\n", __func__);
+
+ priv = &spi_bus[bus];
+
+ priv->regs = (struct rockchip_spi *)base_addr;
+ priv->rsd = rsd;
+ priv->mode = mode;
+ if (clock_div % 2 || clock_div < 2) {
+ printf("%s div should be even num, and at least 2\n", __func__);
+
+ return -1;
+ }
+ priv->clock_div = clock_div;
+ priv->bits_per_word = 8;
+
+ return 0;
+}
+
+int rockchip_spi_claim_bus(u8 bus)
+{
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
+ struct rockchip_spi *regs = priv->regs;
+ u8 spi_dfs, spi_tf;
+ uint ctrlr0;
+
+ /* Disable the SPI hardware */
+ rkspi_enable_chip(regs, 0);
+
+ switch (priv->bits_per_word) {
+ case 8:
+ priv->n_bytes = 1;
+ spi_dfs = DFS_8BIT;
+ spi_tf = HALF_WORD_OFF;
+ break;
+ case 16:
+ priv->n_bytes = 2;
+ spi_dfs = DFS_16BIT;
+ spi_tf = HALF_WORD_ON;
+ break;
+ default:
+ debug("%s: unsupported bits: %dbits\n", __func__,
+ priv->bits_per_word);
+ return -EPROTONOSUPPORT;
+ }
+
+ rkspi_set_baudr(priv, priv->clock_div);
+
+ /* Operation Mode */
+ ctrlr0 = OMOD_MASTER << OMOD_SHIFT;
+
+ /* Data Frame Size */
+ ctrlr0 |= spi_dfs << DFS_SHIFT;
+
+ /* set SPI mode 0..3 */
+ if (priv->mode & SPI_CPOL)
+ ctrlr0 |= SCOL_HIGH << SCOL_SHIFT;
+ if (priv->mode & SPI_CPHA)
+ ctrlr0 |= SCPH_TOGSTA << SCPH_SHIFT;
+
+ /* Chip Select Mode */
+ ctrlr0 |= CSM_KEEP << CSM_SHIFT;
+
+ /* SSN to Sclk_out delay */
+ ctrlr0 |= SSN_DELAY_ONE << SSN_DELAY_SHIFT;
+
+ /* Serial Endian Mode */
+ ctrlr0 |= SEM_LITTLE << SEM_SHIFT;
+
+ /* First Bit Mode */
+ ctrlr0 |= FBM_MSB << FBM_SHIFT;
+
+ /* Byte and Halfword Transform */
+ ctrlr0 |= spi_tf << HALF_WORD_TX_SHIFT;
+
+ /* Rxd Sample Delay */
+ ctrlr0 |= priv->rsd << RXDSD_SHIFT;
+
+ /* Frame Format */
+ ctrlr0 |= FRF_SPI << FRF_SHIFT;
+
+ /* Save static configuration */
+ priv->cr0 = ctrlr0;
+
+ writel(ctrlr0, ®s->ctrlr0);
+
+ return 0;
+}
+
+int rockchip_spi_config(struct rockchip_spi_priv *priv, const void *dout)
+{
+ struct rockchip_spi *regs = priv->regs;
+ uint ctrlr0 = priv->cr0;
+ u32 tmod;
+
+ if (dout)
+ tmod = TMOD_TR;
+ else
+ tmod = TMOD_RO;
+
+ ctrlr0 |= (tmod & TMOD_MASK) << TMOD_SHIFT;
+ writel(ctrlr0, ®s->ctrlr0);
+
+ return 0;
+}
+
+void rockchip_spi_release_bus(u8 bus)
+{
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
+
+ rkspi_enable_chip(priv->regs, false);
+}
+
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags)
+{
+ struct rockchip_spi_priv *priv = get_spi_bus(bus);
+ struct rockchip_spi *regs = priv->regs;
+ int len = bitlen >> 3;
+ const u8 *out = dout;
+ u8 *in = din;
+ int toread, towrite;
+ int ret;
+
+ rockchip_spi_config(priv, dout);
+
+ debug("%s: dout=%p, din=%p, len=%x, flags=%lx\n", __func__, dout, din,
+ len, flags);
+ if (DEBUG_RK_SPI)
+ rkspi_dump_regs(regs);
+
+ /* Assert CS before transfer */
+ if (flags & SPI_XFER_BEGIN)
+ spi_cs_activate(bus, cs);
+
+ while (len > 0) {
+ int todo = min(len, 0xffff);
+
+ rkspi_enable_chip(regs, false);
+ writel(todo - 1, ®s->ctrlr1);
+ rkspi_enable_chip(regs, true);
+
+ toread = todo;
+ towrite = todo;
+ while (toread || towrite) {
+ u32 status = readl(®s->sr);
+
+ if (towrite && !(status & SR_TF_FULL)) {
+ if (out)
+ writel(out ? *out++ : 0, regs->txdr);
+ towrite--;
+ }
+ if (toread && !(status & SR_RF_EMPT)) {
+ u32 byte = readl(regs->rxdr);
+
+ if (in)
+ *in++ = byte;
+ toread--;
+ }
+ }
+ ret = rkspi_wait_till_not_busy(regs);
+ if (ret)
+ break;
+ len -= todo;
+ }
+
+ /* Deassert CS after transfer */
+ if (flags & SPI_XFER_END)
+ spi_cs_deactivate(bus, cs);
+
+ rkspi_enable_chip(regs, false);
+
+ return ret;
+}
+
+int rockchip_spi_write_then_read(u8 bus, u8 cs, const u8 *opcode,
+ size_t n_opcode, const u8 *txbuf, u8 *rxbuf,
+ size_t n_buf)
+{
+ unsigned long flags = SPI_XFER_BEGIN;
+ int ret;
+
+ if (n_buf == 0)
+ flags |= SPI_XFER_END;
+
+ ret = rockchip_spi_xfer(bus, cs, n_opcode * 8, opcode, NULL, flags);
+ if (ret) {
+ debug("spi: failed to send command (%zu bytes): %d\n",
+ n_opcode, ret);
+ } else if (n_buf != 0) {
+ ret = rockchip_spi_xfer(bus, cs, n_buf * 8, txbuf, rxbuf, SPI_XFER_END);
+ if (ret)
+ debug("spi: failed to transfer %zu bytes of data: %d\n",
+ n_buf, ret);
+ }
+
+ return ret;
+}
+
+void dbg_print_hex(char *s, void *buf, u32 width, u32 len)
+{
+ u32 i, j;
+ unsigned char *p8 = (unsigned char *)buf;
+ unsigned short *p16 = (unsigned short *)buf;
+ u32 *p32 = (u32 *)buf;
+
+ j = 0;
+
+ for (i = 0; i < len; i++) {
+ if (j == 0)
+ printf("%s %p + 0x%x:", s, buf, i * width);
+
+ if (width == 4)
+ printf("0x%08x,", p32[i]);
+ else if (width == 2)
+ printf("0x%04x,", p16[i]);
+ else
+ printf("0x%02x,", p8[i]);
+
+ if (++j >= (16 / width)) {
+ j = 0;
+ printf("\n");
+ }
+ }
+
+ printf("\n");
+}
+
+static void spi_hw_init(void)
+{
+ /* Setting the clock and iomux */
+ /* todo */
+}
+
+int main(int argc, char * const argv[])
+{
+ int i;
+
+ /* Print the ABI version */
+ app_startup(argv);
+ printf("Example expects ABI version %d\n", XF_VERSION);
+ printf("Actual U-Boot ABI version %d\n", (int)get_version());
+
+ printf("rk_spi standalone version\n");
+
+ printf("argc = %d\n", argc);
+
+ for (i = 0; i <= argc; ++i) {
+ printf("argv[%d] = \"%s\"\n",
+ i,
+ argv[i] ? argv[i] : "<NULL>");
+ }
+
+ /*
+ * spi test demo
+ */
+#if 1
+ u8 bus, cs;
+ unsigned char *pread, *pwrite;
+ u32 test_size = 0x100;
+ int ret;
+
+ pread = malloc(test_size);
+ if (!pread)
+ printf("%s pread malloc fail\n", __func__);
+ pwrite = malloc(test_size);
+ if (!pwrite) {
+ printf("%s pwrite malloc fail\n", __func__);
+ free(pwrite);
+
+ return -1;
+ }
+
+ for (i = 0; i < test_size; i++)
+ pwrite[i] = i;
+
+ bus = 4;
+ cs = 0;
+
+ spi_hw_init();
+
+ rockchip_spi_probe(bus, 0xfecb0000, 0, 20, SPI_MODE_3);
+ rockchip_spi_claim_bus(bus);
+
+ /*
+ * SPI write
+ */
+ ret = rockchip_spi_xfer(bus, cs, test_size * 8, pwrite, NULL, SPI_XFER_ONCE);
+ if (ret) {
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
+
+ return ret;
+ }
+
+ /*
+ * SPI read
+ */
+ rockchip_spi_xfer(bus, cs, test_size * 8, NULL, pread, SPI_XFER_ONCE);
+ if (ret) {
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
+
+ return ret;
+ }
+ dbg_print_hex("spi_read:", pread, 4, test_size / 4);
+
+ /*
+ * SPI duplex
+ */
+ rockchip_spi_xfer(bus, cs, test_size * 8, pwrite, pread, SPI_XFER_ONCE);
+ if (ret) {
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
+
+ return ret;
+ }
+ dbg_print_hex("spi_duplex:", pread, 4, test_size / 4);
+
+ /*
+ * SPI write then read
+ */
+ rockchip_spi_write_then_read(bus, cs, pwrite, 1, NULL, pread, test_size);
+ if (ret) {
+ printf("rockchip_spi_xfer fail ret=%d\n", ret);
+
+ return ret;
+ }
+ dbg_print_hex("spi_write_then_read:", pread, 4, test_size / 4);
+
+ rockchip_spi_release_bus(bus);
+#endif
+
+ printf("Hit any key to exit ... ");
+ while (!tstc())
+ ;
+ /* consume input */
+ (void)getc();
+
+ printf("\n\n");
+
+ return 0;
+}
diff --git a/u-boot/examples/standalone/rkspi.h b/u-boot/examples/standalone/rkspi.h
new file mode 100644
index 0000000..a836cfc
--- /dev/null
+++ b/u-boot/examples/standalone/rkspi.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _DRIVER_SPI_H_
+#define _DRIVER_SPI_H_
+
+struct rockchip_spi {
+ u32 ctrlr0;
+ u32 ctrlr1;
+ u32 enr;
+ u32 ser;
+ u32 baudr;
+ u32 txftlr;
+ u32 rxftlr;
+ u32 txflr;
+ u32 rxflr;
+ u32 sr;
+ u32 ipr;
+ u32 imr;
+ u32 isr;
+ u32 risr;
+ u32 icr;
+ u32 dmacr;
+ u32 dmatdlr;
+ u32 dmardlr; /* 0x44 */
+ u32 reserved[0xef];
+ u32 txdr[0x100]; /* 0x400 */
+ u32 rxdr[0x100]; /* 0x800 */
+};
+
+/* CTRLR0 */
+enum {
+ DFS_SHIFT = 0, /* Data Frame Size */
+ DFS_MASK = 3,
+ DFS_4BIT = 0,
+ DFS_8BIT,
+ DFS_16BIT,
+ DFS_RESV,
+
+ CFS_SHIFT = 2, /* Control Frame Size */
+ CFS_MASK = 0xf,
+
+ SCPH_SHIFT = 6, /* Serial Clock Phase */
+ SCPH_MASK = 1,
+ SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */
+ SCPH_TOGSTA, /* SCLK toggles at start of first data bit */
+
+ SCOL_SHIFT = 7, /* Serial Clock Polarity */
+ SCOL_MASK = 1,
+ SCOL_LOW = 0, /* Inactive state of serial clock is low */
+ SCOL_HIGH, /* Inactive state of serial clock is high */
+
+ CSM_SHIFT = 8, /* Chip Select Mode */
+ CSM_MASK = 0x3,
+ CSM_KEEP = 0, /* ss_n stays low after each frame */
+ CSM_HALF, /* ss_n high for half sclk_out cycles */
+ CSM_ONE, /* ss_n high for one sclk_out cycle */
+ CSM_RESV,
+
+ SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */
+ SSN_DELAY_MASK = 1,
+ SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */
+ SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */
+
+ SEM_SHIFT = 11, /* Serial Endian Mode */
+ SEM_MASK = 1,
+ SEM_LITTLE = 0, /* little endian */
+ SEM_BIG, /* big endian */
+
+ FBM_SHIFT = 12, /* First Bit Mode */
+ FBM_MASK = 1,
+ FBM_MSB = 0, /* first bit is MSB */
+ FBM_LSB, /* first bit in LSB */
+
+ HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */
+ HALF_WORD_MASK = 1,
+ HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */
+ HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */
+
+ RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */
+ RXDSD_MASK = 3,
+
+ FRF_SHIFT = 16, /* Frame Format */
+ FRF_MASK = 3,
+ FRF_SPI = 0, /* Motorola SPI */
+ FRF_SSP, /* Texas Instruments SSP*/
+ FRF_MICROWIRE, /* National Semiconductors Microwire */
+ FRF_RESV,
+
+ TMOD_SHIFT = 18, /* Transfer Mode */
+ TMOD_MASK = 3,
+ TMOD_TR = 0, /* xmit & recv */
+ TMOD_TO, /* xmit only */
+ TMOD_RO, /* recv only */
+ TMOD_RESV,
+
+ OMOD_SHIFT = 20, /* Operation Mode */
+ OMOD_MASK = 1,
+ OMOD_MASTER = 0, /* Master Mode */
+ OMOD_SLAVE, /* Slave Mode */
+};
+
+/* SR */
+enum {
+ SR_MASK = 0x7f,
+ SR_BUSY = 1 << 0,
+ SR_TF_FULL = 1 << 1,
+ SR_TF_EMPT = 1 << 2,
+ SR_RF_EMPT = 1 << 3,
+ SR_RF_FULL = 1 << 4,
+};
+
+#define ROCKCHIP_SPI_TIMEOUT_MS 1000
+
+#define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */
+#define SPI_XFER_END BIT(1) /* Deassert CS after transfer */
+#define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END)
+
+/* SPI mode flags */
+#define SPI_CPHA BIT(0) /* clock phase */
+#define SPI_CPOL BIT(1) /* clock polarity */
+#define SPI_MODE_0 (0 | 0) /* (original MicroWire) */
+#define SPI_MODE_1 (0 | SPI_CPHA)
+#define SPI_MODE_2 (SPI_CPOL | 0)
+#define SPI_MODE_3 (SPI_CPOL | SPI_CPHA)
+
+int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode);
+int rockchip_spi_claim_bus(u8 bus);
+void rockchip_spi_release_bus(u8 bus);
+int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags);
+int rockchip_spi_write_then_read(u8 bus, u8 cs,
+ const u8 *opcode, size_t n_opcode,
+ const u8 *txbuf, u8 *rxbuf, size_t n_buf);
+
+#endif
diff --git a/u-boot/fs/ubifs/debug.h b/u-boot/fs/ubifs/debug.h
index 0d8ed57..87a13f2 100644
--- a/u-boot/fs/ubifs/debug.h
+++ b/u-boot/fs/ubifs/debug.h
@@ -166,40 +166,22 @@
dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \
} while (0)
#else
-#define ubifs_assert(expr) do { \
- if (unlikely(!(expr))) { \
- pr_debug("UBIFS assert failed in %s at %u\n", \
- __func__, __LINE__); \
- dump_stack(); \
- } \
-} while (0)
-#define ubifs_assert_cmt_locked(c) do { \
- if (unlikely(down_write_trylock(&(c)->commit_sem))) { \
- up_write(&(c)->commit_sem); \
- pr_debug("commit lock is not locked!\n"); \
- ubifs_assert(0); \
- } \
-} while (0)
+#include <log.h>
+#define ubifs_assert(expr) assert(expr)
+#define ubifs_assert_cmt_locked(c) do { } while (0)
#define ubifs_dbg_msg(type, fmt, ...) \
pr_debug("UBIFS DBG " type ": " fmt "\n", \
##__VA_ARGS__)
#define DBG_KEY_BUF_LEN 48
-#if defined CONFIG_MTD_DEBUG
#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \
char __tmp_key_buf[DBG_KEY_BUF_LEN]; \
pr_debug("UBIFS DBG " type ": " fmt "%s\n", \
##__VA_ARGS__, \
dbg_snprintf_key(c, key, __tmp_key_buf, DBG_KEY_BUF_LEN)); \
} while (0)
-#else
-#define ubifs_dbg_msg_key(type, key, fmt, ...) do { \
- pr_debug("UBIFS DBG\n"); \
-} while (0)
-
-#endif
#endif
diff --git a/u-boot/fs/ubifs/io.c b/u-boot/fs/ubifs/io.c
index 51a95bb..cad7587 100644
--- a/u-boot/fs/ubifs/io.c
+++ b/u-boot/fs/ubifs/io.c
@@ -111,7 +111,7 @@
int ubifs_leb_write(struct ubifs_info *c, int lnum, const void *buf, int offs,
int len)
{
- int err;
+ int err = 0;
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->ro_error)
@@ -133,7 +133,7 @@
int ubifs_leb_change(struct ubifs_info *c, int lnum, const void *buf, int len)
{
- int err;
+ int err = 0;
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->ro_error)
@@ -155,7 +155,7 @@
int ubifs_leb_unmap(struct ubifs_info *c, int lnum)
{
- int err;
+ int err = 0;
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->ro_error)
@@ -176,7 +176,7 @@
int ubifs_leb_map(struct ubifs_info *c, int lnum)
{
- int err;
+ int err = 0;
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->ro_error)
diff --git a/u-boot/fs/ubifs/super.c b/u-boot/fs/ubifs/super.c
index effa8d9..b7f39cc 100644
--- a/u-boot/fs/ubifs/super.c
+++ b/u-boot/fs/ubifs/super.c
@@ -1749,6 +1749,8 @@
kfree(c->bottom_up_buf);
ubifs_debugging_exit(c);
#ifdef __UBOOT__
+ ubi_close_volume(c->ubi);
+ mutex_unlock(&c->umount_mutex);
/* Finally free U-Boot's global copy of superblock */
if (ubifs_sb != NULL) {
free(ubifs_sb->s_fs_info);
@@ -2050,9 +2052,9 @@
ubifs_umount(c);
#ifndef __UBOOT__
bdi_destroy(&c->bdi);
-#endif
ubi_close_volume(c->ubi);
mutex_unlock(&c->umount_mutex);
+#endif
}
#endif
@@ -2319,6 +2321,9 @@
out_umount:
ubifs_umount(c);
+#ifdef __UBOOT__
+ goto out;
+#endif
out_unlock:
mutex_unlock(&c->umount_mutex);
#ifndef __UBOOT__
@@ -2356,7 +2361,9 @@
return ERR_PTR(err);
}
+#ifndef __UBOOT__
INIT_HLIST_NODE(&s->s_instances);
+#endif
INIT_LIST_HEAD(&s->s_inodes);
s->s_time_gran = 1000000000;
s->s_flags = flags;
@@ -2425,14 +2432,12 @@
#ifndef __UBOOT__
strlcpy(s->s_id, type->name, sizeof(s->s_id));
list_add_tail(&s->s_list, &super_blocks);
-#else
- strncpy(s->s_id, type->name, sizeof(s->s_id));
-#endif
hlist_add_head(&s->s_instances, &type->fs_supers);
-#ifndef __UBOOT__
spin_unlock(&sb_lock);
get_filesystem(type);
register_shrinker(&s->s_shrink);
+#else
+ strncpy(s->s_id, type->name, sizeof(s->s_id));
#endif
return s;
}
@@ -2457,7 +2462,7 @@
*/
ubi = open_ubi(name, UBI_READONLY);
if (IS_ERR(ubi)) {
- pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d",
+ pr_err("UBIFS error (pid: %d): cannot open \"%s\", error %d\n",
current->pid, name, (int)PTR_ERR(ubi));
return ERR_CAST(ubi);
}
@@ -2599,7 +2604,7 @@
* UBIFS_BLOCK_SIZE. It is assumed that both are powers of 2.
*/
if (PAGE_CACHE_SIZE < UBIFS_BLOCK_SIZE) {
- pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes",
+ pr_err("UBIFS error (pid %d): VFS page cache size is %u bytes, but UBIFS requires at least 4096 bytes\n",
current->pid, (unsigned int)PAGE_CACHE_SIZE);
return -EINVAL;
}
@@ -2628,7 +2633,7 @@
err = register_filesystem(&ubifs_fs_type);
if (err) {
- pr_err("UBIFS error (pid %d): cannot register file system, error %d",
+ pr_err("UBIFS error (pid %d): cannot register file system, error %d\n",
current->pid, err);
goto out_dbg;
}
diff --git a/u-boot/fs/ubifs/tnc.c b/u-boot/fs/ubifs/tnc.c
index f6316a3..77811ca 100644
--- a/u-boot/fs/ubifs/tnc.c
+++ b/u-boot/fs/ubifs/tnc.c
@@ -46,6 +46,11 @@
NOT_ON_MEDIA = 3,
};
+static int try_read_node(const struct ubifs_info *c, void *buf, int type,
+ int len, int lnum, int offs);
+static int fallible_read_node(struct ubifs_info *c, const union ubifs_key *key,
+ struct ubifs_zbranch *zbr, void *node);
+
/**
* insert_old_idx - record an index node obsoleted since the last commit start.
* @c: UBIFS file-system description object
@@ -398,7 +403,19 @@
return 0;
}
- err = ubifs_tnc_read_node(c, zbr, node);
+ if (c->replaying) {
+ err = fallible_read_node(c, &zbr->key, zbr, node);
+ /*
+ * When the node was not found, return -ENOENT, 0 otherwise.
+ * Negative return codes stay as-is.
+ */
+ if (err == 0)
+ err = -ENOENT;
+ else if (err == 1)
+ err = 0;
+ } else {
+ err = ubifs_tnc_read_node(c, zbr, node);
+ }
if (err)
return err;
@@ -2766,7 +2783,11 @@
if (nm->name) {
if (err) {
/* Handle collisions */
- err = resolve_collision(c, key, &znode, &n, nm);
+ if (c->replaying)
+ err = fallible_resolve_collision(c, key, &znode, &n,
+ nm, 0);
+ else
+ err = resolve_collision(c, key, &znode, &n, nm);
dbg_tnc("rc returned %d, znode %p, n %d",
err, znode, n);
if (unlikely(err < 0))
diff --git a/u-boot/fs/ubifs/ubifs.c b/u-boot/fs/ubifs/ubifs.c
index 739df5d..a9ca923 100644
--- a/u-boot/fs/ubifs/ubifs.c
+++ b/u-boot/fs/ubifs/ubifs.c
@@ -126,6 +126,7 @@
{
struct ubifs_compressor *compr = ubifs_compressors[tfm->compressor];
int err;
+ size_t tmp_len = *dlen;
if (compr->compr_type == UBIFS_COMPR_NONE) {
memcpy(dst, src, slen);
@@ -133,11 +134,12 @@
return 0;
}
- err = compr->decompress(src, slen, dst, (size_t *)dlen);
+ err = compr->decompress(src, slen, dst, &tmp_len);
if (err)
ubifs_err(c, "cannot decompress %d bytes, compressor %s, "
"error %d", slen, compr->name, err);
+ *dlen = tmp_len;
return err;
return 0;
@@ -466,14 +468,10 @@
dbg_gen("cannot find next direntry, error %d", err);
out_free:
- if (file->private_data)
- kfree(file->private_data);
- if (file)
- free(file);
- if (dentry)
- free(dentry);
- if (dir)
- free(dir);
+ kfree(file->private_data);
+ free(file);
+ free(dentry);
+ free(dir);
return ret;
}
@@ -801,6 +799,8 @@
if (last_block_size)
dlen = last_block_size;
+ else if (ret)
+ dlen = UBIFS_BLOCK_SIZE;
else
dlen = le32_to_cpu(dn->size);
diff --git a/u-boot/fs/ubifs/ubifs.h b/u-boot/fs/ubifs/ubifs.h
index 1d89465..7fc6e41 100644
--- a/u-boot/fs/ubifs/ubifs.h
+++ b/u-boot/fs/ubifs/ubifs.h
@@ -317,8 +317,8 @@
struct backing_dev_info *s_bdi;
#endif
struct mtd_info *s_mtd;
- struct hlist_node s_instances;
#ifndef __UBOOT__
+ struct hlist_node s_instances;
struct quota_info s_dquot; /* Diskquota specific options */
#endif
@@ -611,16 +611,20 @@
/* misc.h */
#define mutex_lock_nested(...)
#define mutex_unlock_nested(...)
-#define mutex_is_locked(...) 0
+#define mutex_is_locked(...) 1
#endif
/* Version of this UBIFS implementation */
#define UBIFS_VERSION 1
/* Normal UBIFS messages */
+#ifdef CONFIG_UBIFS_SILENCE_MSG
+#define ubifs_msg(c, fmt, ...)
+#else
#define ubifs_msg(c, fmt, ...) \
pr_notice("UBIFS (ubi%d:%d): " fmt "\n", \
(c)->vi.ubi_num, (c)->vi.vol_id, ##__VA_ARGS__)
+#endif
/* UBIFS error messages */
#ifndef __UBOOT__
#define ubifs_err(c, fmt, ...) \
diff --git a/u-boot/include/android_ab.h b/u-boot/include/android_ab.h
index aa621ca..15be4b8 100644
--- a/u-boot/include/android_ab.h
+++ b/u-boot/include/android_ab.h
@@ -47,7 +47,7 @@
int read_misc_virtual_ab_message(struct misc_virtual_ab_message *message);
int write_misc_virtual_ab_message(struct misc_virtual_ab_message *message);
-void ab_update_root_uuid(void);
+void ab_update_root_partition(void);
int ab_get_slot_suffix(char *slot_suffix);
int ab_is_support_dynamic_partition(struct blk_desc *dev_desc);
int ab_decrease_tries(void);
diff --git a/u-boot/include/android_avb/avb_ops_user.h b/u-boot/include/android_avb/avb_ops_user.h
index 36a98da..28e807b 100755
--- a/u-boot/include/android_avb/avb_ops_user.h
+++ b/u-boot/include/android_avb/avb_ops_user.h
@@ -63,6 +63,22 @@
/* Frees an AvbOps instance previously allocated with avb_ops_device_new(). */
void avb_ops_user_free(AvbOps* ops);
+struct preloaded_partition {
+ uint8_t *addr;
+ size_t size; // 0 means the partition hasn't yet been preloaded
+};
+
+struct AvbOpsData {
+ struct AvbOps *ops;
+ const char *iface;
+ const char *devnum;
+ const char *slot_suffix;
+ struct preloaded_partition boot;
+ struct preloaded_partition vendor_boot;
+ struct preloaded_partition init_boot;
+ struct preloaded_partition resource;
+};
+
#ifdef __cplusplus
}
#endif
diff --git a/u-boot/include/android_image.h b/u-boot/include/android_image.h
index 8af0998..8ebd10d 100644
--- a/u-boot/include/android_image.h
+++ b/u-boot/include/android_image.h
@@ -13,8 +13,10 @@
#define ANDROID_PARTITION_BOOT "boot"
#define ANDROID_PARTITION_VENDOR_BOOT "vendor_boot"
+#define ANDROID_PARTITION_INIT_BOOT "init_boot"
#define ANDROID_PARTITION_MISC "misc"
#define ANDROID_PARTITION_OEM "oem"
+#define ANDROID_PARTITION_RESOURCE "resource"
#define ANDROID_PARTITION_RECOVERY "recovery"
#define ANDROID_PARTITION_SYSTEM "system"
#define ANDROID_PARTITION_VBMETA "vbmeta"
@@ -117,7 +119,6 @@
* we have to partly merge fields from boot_img_hdr_v34 and vendor_boot_img_hdr_v34
* into this structure to compatible with boot_img_hdr_v012.
*/
- u32 boot_ramdisk_size; /* size in bytes */
u32 vendor_ramdisk_size; /* size in bytes */
u32 vendor_page_size;
u32 vendor_header_version;
@@ -135,6 +136,9 @@
u32 vendor_ramdisk_table_entry_size;
u32 vendor_bootconfig_size; /* size in bytes for bootconfig image */
+ void *init_boot_buf;
+ void *vendor_boot_buf;
+
/*
* Don't define 'char total_cmdline[TOTAL_BOOT_ARGS_SIZE]' to avoid
* this structrue is over size than page_size.
diff --git a/u-boot/include/asm-generic/atomic-long.h b/u-boot/include/asm-generic/atomic-long.h
index d0469ef..32f288b 100644
--- a/u-boot/include/asm-generic/atomic-long.h
+++ b/u-boot/include/asm-generic/atomic-long.h
@@ -66,6 +66,7 @@
atomic64_sub(i, v);
}
+#ifndef __UBOOT__
static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
{
atomic64_t *v = (atomic64_t *)l;
@@ -135,6 +136,7 @@
(atomic64_cmpxchg((atomic64_t *)(l), (old), (new)))
#define atomic_long_xchg(v, new) \
(atomic64_xchg((atomic64_t *)(v), (new)))
+#endif /* __UBOOT__ */
#else /* BITS_PER_LONG == 64 */
diff --git a/u-boot/include/asm-generic/u-boot.h b/u-boot/include/asm-generic/u-boot.h
index 17493cb..43775c5 100644
--- a/u-boot/include/asm-generic/u-boot.h
+++ b/u-boot/include/asm-generic/u-boot.h
@@ -87,8 +87,6 @@
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
- /* same as android image header 'os_version' */
- unsigned int bi_andr_version;
#ifdef CONFIG_NR_DRAM_BANKS
struct { /* RAM configuration */
u64 start;
diff --git a/u-boot/include/boot_rkimg.h b/u-boot/include/boot_rkimg.h
index cb57818..eb8b1ef 100644
--- a/u-boot/include/boot_rkimg.h
+++ b/u-boot/include/boot_rkimg.h
@@ -19,6 +19,7 @@
BOOT_MODE_PANIC,
BOOT_MODE_WATCHDOG,
BOOT_MODE_DFU,
+ BOOT_MODE_QUIESCENT,
BOOT_MODE_UNDEFINE,
};
diff --git a/u-boot/include/charset.h b/u-boot/include/charset.h
index 39279f7..0d06b03 100644
--- a/u-boot/include/charset.h
+++ b/u-boot/include/charset.h
@@ -9,6 +9,9 @@
#ifndef __CHARSET_H_
#define __CHARSET_H_
+#include <linux/kernel.h>
+#include <linux/types.h>
+
#define MAX_UTF8_PER_UTF16 4
/**
diff --git a/u-boot/include/configs/evb_rk3528.h b/u-boot/include/configs/evb_rk3528.h
new file mode 100644
index 0000000..f315482
--- /dev/null
+++ b/u-boot/include/configs/evb_rk3528.h
@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIGS_RK3528_EVB_H
+#define __CONFIGS_RK3528_EVB_H
+
+#include <configs/rk3528_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+
+#undef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND
+#endif
+
+#endif /* __CONFIGS_RK3528_EVB_H */
diff --git a/u-boot/include/configs/evb_rk3562.h b/u-boot/include/configs/evb_rk3562.h
new file mode 100644
index 0000000..8f555ac
--- /dev/null
+++ b/u-boot/include/configs/evb_rk3562.h
@@ -0,0 +1,26 @@
+/*
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __CONFIGS_RK3562_EVB_H
+#define __CONFIGS_RK3562_EVB_H
+
+#include <configs/rk3562_common.h>
+
+#ifndef CONFIG_SPL_BUILD
+
+#undef ROCKCHIP_DEVICE_SETTINGS
+#define ROCKCHIP_DEVICE_SETTINGS \
+ "stdin=serial,usbkbd\0" \
+ "stdout=serial,vidconsole\0" \
+ "stderr=serial,vidconsole\0"
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND RKIMG_BOOTCOMMAND
+#endif
+
+#endif /* __CONFIGS_RK3562_EVB_H */
diff --git a/u-boot/include/configs/rk3288_common.h b/u-boot/include/configs/rk3288_common.h
index 1ffa23e..be29922 100644
--- a/u-boot/include/configs/rk3288_common.h
+++ b/u-boot/include/configs/rk3288_common.h
@@ -59,7 +59,7 @@
#define ENV_MEM_LAYOUT_SETTINGS \
"scriptaddr=0x00000000\0" \
"pxefile_addr_r=0x00100000\0" \
- "fdt_addr_r=0x08300000\0" \
+ "fdt_addr_r=0x08100000\0" \
"kernel_addr_r=0x02008000\0" \
"ramdisk_addr_r=0x0a200000\0"
diff --git a/u-boot/include/configs/rk3528_common.h b/u-boot/include/configs/rk3528_common.h
new file mode 100644
index 0000000..ad81095
--- /dev/null
+++ b/u-boot/include/configs/rk3528_common.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2020 Rockchip Electronics Co., Ltd
+ *
+ */
+
+#ifndef __CONFIG_RK3528_COMMON_H
+#define __CONFIG_RK3528_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x00000000
+#define CONFIG_SPL_MAX_SIZE 0x00040000
+#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
+#define CONFIG_SPL_STACK 0x03fe0000
+
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_SUPPORT_USBPLUG
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00200000
+#endif
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
+#define CONFIG_SYS_LOAD_ADDR 0x00c00800
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+#define COUNTER_FREQUENCY 24000000
+
+#define GICD_BASE 0xfed01000
+#define GICC_BASE 0xfed02000
+
+#ifdef CONFIG_SPL_DM_VIDEO
+#undef CONFIG_SPL_MAX_SIZE
+#undef CONFIG_SPL_BSS_MAX_SIZE
+#define CONFIG_SPL_MAX_SIZE 0x00140000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
+#endif
+
+#ifdef CONFIG_ARM_SMP
+#define SMP_CPU1 0x1
+#define SMP_CPU1_STACK 0x04fe0000
+#define SMP_CPU2 0x2
+#define SMP_CPU2_STACK 0x05fe0000
+#endif
+
+/* secure otp */
+#define OTP_UBOOT_ROLLBACK_OFFSET 0x350
+#define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */
+#define OTP_ALL_ONES_NUM_BITS 32
+#define OTP_SECURE_BOOT_ENABLE_ADDR 0x20
+#define OTP_SECURE_BOOT_ENABLE_SIZE 1
+#define OTP_RSA_HASH_ADDR 0x180
+#define OTP_RSA_HASH_SIZE 32
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfc000000
+#define CONFIG_PREBOOT
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000
+
+#ifndef CONFIG_SPL_BUILD
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_ROCKUSB_G_DNL_PID 0x350c
+
+#ifdef CONFIG_ARM64
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "fdt_addr_r=0x08300000\0" \
+ "kernel_addr_r=0x00280000\0" \
+ "kernel_addr_c=0x04080000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+#else
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00000000\0" \
+ "pxefile_addr_r=0x00100000\0" \
+ "fdt_addr_r=0x08300000\0" \
+ "kernel_addr_c=0x02008000\0" \
+ "kernel_addr_r=0x00208000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+#endif
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "partitions=" PARTS_RKIMG \
+ ROCKCHIP_DEVICE_SETTINGS \
+ RKIMG_DET_BOOTDEV \
+ BOOTENV
+#endif
+
+/* rockchip ohci host driver */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+
+#define CONFIG_LIB_HW_RAND
+
+#endif
diff --git a/u-boot/include/configs/rk3562_common.h b/u-boot/include/configs/rk3562_common.h
new file mode 100644
index 0000000..b076f90
--- /dev/null
+++ b/u-boot/include/configs/rk3562_common.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Rockchip Electronics Co., Ltd
+ *
+ */
+
+#ifndef __CONFIG_RK3562_COMMON_H
+#define __CONFIG_RK3562_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE 0x00000000
+#define CONFIG_SPL_MAX_SIZE 0x00040000
+#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
+#define CONFIG_SPL_STACK 0x03fe0000
+
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+#define CONFIG_SYS_CBSIZE 1024
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#ifdef CONFIG_SUPPORT_USBPLUG
+#define CONFIG_SYS_TEXT_BASE 0x00000000
+#else
+#define CONFIG_SYS_TEXT_BASE 0x00200000
+#endif
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x00c00000
+#define CONFIG_SYS_LOAD_ADDR 0x00c00800
+#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
+#define COUNTER_FREQUENCY 24000000
+
+#define GICD_BASE 0xfe901000
+#define GICC_BASE 0xfe902000
+
+/* secure otp */
+#define OTP_UBOOT_ROLLBACK_OFFSET 0x350
+#define OTP_UBOOT_ROLLBACK_WORDS 2 /* 64 bits, 2 words */
+#define OTP_ALL_ONES_NUM_BITS 32
+#define OTP_SECURE_BOOT_ENABLE_ADDR 0x20
+#define OTP_SECURE_BOOT_ENABLE_SIZE 1
+#define OTP_RSA_HASH_ADDR 0x180
+#define OTP_RSA_HASH_SIZE 32
+
+/* MMC/SD IP block */
+#define CONFIG_BOUNCE_BUFFER
+
+#define CONFIG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfc000000
+#define CONFIG_PREBOOT
+#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
+
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x2000000
+
+#ifndef CONFIG_SPL_BUILD
+/* usb mass storage */
+#define CONFIG_USB_FUNCTION_MASS_STORAGE
+#define CONFIG_ROCKUSB_G_DNL_PID 0x350d
+
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00c00000\0" \
+ "pxefile_addr_r=0x00e00000\0" \
+ "fdt_addr_r=0x08300000\0" \
+ "kernel_addr_r=0x00400000\0" \
+ "kernel_addr_c=0x04080000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ ENV_MEM_LAYOUT_SETTINGS \
+ "partitions=" PARTS_RKIMG \
+ ROCKCHIP_DEVICE_SETTINGS \
+ RKIMG_DET_BOOTDEV \
+ BOOTENV
+#endif
+
+/* rockchip ohci host driver */
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
+#define CONFIG_LIB_HW_RAND
+
+#endif
diff --git a/u-boot/include/configs/rk3588_common.h b/u-boot/include/configs/rk3588_common.h
index 5bb057a..1399468 100644
--- a/u-boot/include/configs/rk3588_common.h
+++ b/u-boot/include/configs/rk3588_common.h
@@ -15,14 +15,18 @@
#define CONFIG_SPL_BSS_START_ADDR 0x03fe0000
#define CONFIG_SPL_BSS_MAX_SIZE 0x00010000
#define CONFIG_SPL_STACK 0x03fe0000
+#ifdef CONFIG_SPL_LOAD_FIT_ADDRESS
+#undef CONFIG_SPL_LOAD_FIT_ADDRESS
+#endif
+#define CONFIG_SPL_LOAD_FIT_ADDRESS 0x10000000
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_TEXT_BASE 0x00200000
-#define CONFIG_SYS_INIT_SP_ADDR 0x00400000
-#define CONFIG_SYS_LOAD_ADDR 0x00400800
+#define CONFIG_SYS_INIT_SP_ADDR 0x00600000
+#define CONFIG_SYS_LOAD_ADDR 0x00600800
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
#define COUNTER_FREQUENCY 24000000
diff --git a/u-boot/include/configs/rockchip-common.h b/u-boot/include/configs/rockchip-common.h
index 870da94..002dcd6 100644
--- a/u-boot/include/configs/rockchip-common.h
+++ b/u-boot/include/configs/rockchip-common.h
@@ -158,7 +158,7 @@
"setenv devtype spinand; setenv devnum 0;" \
"elif rksfc dev 1; then " \
"setenv devtype spinor; setenv devnum 1;" \
- "else" \
+ "else;" \
"setenv devtype ramdisk; setenv devnum 0;" \
"fi; \0"
diff --git a/u-boot/include/configs/rv1106_common.h b/u-boot/include/configs/rv1106_common.h
index 4974d55..1a03803 100644
--- a/u-boot/include/configs/rv1106_common.h
+++ b/u-boot/include/configs/rv1106_common.h
@@ -12,7 +12,6 @@
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_MALLOC_LEN (16 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_NS16550_MEM32
#define CONFIG_SYS_TEXT_BASE 0x00200000
diff --git a/u-boot/include/configs/rv1126_common.h b/u-boot/include/configs/rv1126_common.h
index ac173a9..8f7e94e 100644
--- a/u-boot/include/configs/rv1126_common.h
+++ b/u-boot/include/configs/rv1126_common.h
@@ -12,7 +12,6 @@
#define COUNTER_FREQUENCY 24000000
#define CONFIG_SYS_MALLOC_LEN (32 << 20)
#define CONFIG_SYS_CBSIZE 1024
-#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SYS_NS16550_MEM32
#ifdef CONFIG_SUPPORT_USBPLUG
@@ -106,6 +105,7 @@
#endif
#endif
+#define CONFIG_LIB_HW_RAND
#define CONFIG_PREBOOT
#endif
diff --git a/u-boot/include/configs/woodburn_common.h b/u-boot/include/configs/woodburn_common.h
index 9794f2d..1c66615 100644
--- a/u-boot/include/configs/woodburn_common.h
+++ b/u-boot/include/configs/woodburn_common.h
@@ -168,10 +168,6 @@
#define CONFIG_MXC_NAND_HWECC
#define CONFIG_SYS_NAND_LARGEPAGE
-#if 0
-#define CONFIG_MTD_DEBUG
-#define CONFIG_MTD_DEBUG_VERBOSE 7
-#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION
/*
diff --git a/u-boot/include/dm/fdtaddr.h b/u-boot/include/dm/fdtaddr.h
index c46f0e9..9265677 100644
--- a/u-boot/include/dm/fdtaddr.h
+++ b/u-boot/include/dm/fdtaddr.h
@@ -35,6 +35,18 @@
void *devfdt_get_addr_ptr(struct udevice *dev);
/**
+ * devfdt_remap_addr_index() - Return indexed pointer to the memory-mapped
+ * I/O address of the reg property of a device
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * @dev: Pointer to a device
+ *
+ * Return: Pointer to addr, or NULL if there is no such property
+ */
+void *devfdt_remap_addr_index(struct udevice *dev, int index);
+
+/**
* devfdt_map_physmem() - Read device address from reg property of the
* device node and map the address into CPU address
* space.
diff --git a/u-boot/include/dm/read.h b/u-boot/include/dm/read.h
index 5f3738f..7c1d2f6 100644
--- a/u-boot/include/dm/read.h
+++ b/u-boot/include/dm/read.h
@@ -271,6 +271,18 @@
int dev_read_addr_cells(struct udevice *dev);
/**
+ * dev_remap_addr_index() - Get the indexed reg property of a device
+ * as a memory-mapped I/O pointer
+ *
+ * @dev: Device to read from
+ * @index: the 'reg' property can hold a list of <addr, size> pairs
+ * and @index is used to select which one is required
+ *
+ * Return: pointer or NULL if not found
+ */
+void *dev_remap_addr_index(struct udevice *dev, int index);
+
+/**
* dev_read_size_cells() - Get the number of size cells for a device's node
*
* This walks back up the tree to find the closest #size-cells property
@@ -588,6 +600,11 @@
return fdt_address_cells(gd->fdt_blob, dev_of_offset(dev));
}
+static inline void *dev_remap_addr_index(struct udevice *dev, int index)
+{
+ return devfdt_remap_addr_index(dev, index);
+}
+
static inline int dev_read_size_cells(struct udevice *dev)
{
/* NOTE: this call should walk up the parent stack */
diff --git a/u-boot/include/dm/uclass-id.h b/u-boot/include/dm/uclass-id.h
index b4c0c64..c2e12d4 100644
--- a/u-boot/include/dm/uclass-id.h
+++ b/u-boot/include/dm/uclass-id.h
@@ -89,6 +89,7 @@
UCLASS_THERMAL, /* Thermal sensor */
UCLASS_TIMER, /* Timer device */
UCLASS_TPM, /* Trusted Platform Module TIS interface */
+ UCLASS_UFS, /* Universal Flash Storage */
UCLASS_USB, /* USB bus */
UCLASS_USB_DEV_GENERIC, /* USB generic device */
UCLASS_USB_HUB, /* USB hub */
diff --git a/u-boot/include/drm_modes.h b/u-boot/include/drm_modes.h
index eda5c94..a79dfdf 100644
--- a/u-boot/include/drm_modes.h
+++ b/u-boot/include/drm_modes.h
@@ -38,7 +38,6 @@
#define DRM_MODE_FLAG_PIXMUX (1 << 11)
#define DRM_MODE_FLAG_DBLCLK (1 << 12)
#define DRM_MODE_FLAG_CLKDIV2 (1 << 13)
-#define DRM_MODE_FLAG_PPIXDATA BIT(31)
/*
* When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
* (define not exposed to user space).
@@ -212,6 +211,95 @@
bool invalid;
};
+/**
+ * enum drm_mode_status - hardware support status of a mode
+ * @MODE_OK: Mode OK
+ * @MODE_HSYNC: hsync out of range
+ * @MODE_VSYNC: vsync out of range
+ * @MODE_H_ILLEGAL: mode has illegal horizontal timings
+ * @MODE_V_ILLEGAL: mode has illegal vertical timings
+ * @MODE_BAD_WIDTH: requires an unsupported linepitch
+ * @MODE_NOMODE: no mode with a matching name
+ * @MODE_NO_INTERLACE: interlaced mode not supported
+ * @MODE_NO_DBLESCAN: doublescan mode not supported
+ * @MODE_NO_VSCAN: multiscan mode not supported
+ * @MODE_MEM: insufficient video memory
+ * @MODE_VIRTUAL_X: mode width too large for specified virtual size
+ * @MODE_VIRTUAL_Y: mode height too large for specified virtual size
+ * @MODE_MEM_VIRT: insufficient video memory given virtual size
+ * @MODE_NOCLOCK: no fixed clock available
+ * @MODE_CLOCK_HIGH: clock required is too high
+ * @MODE_CLOCK_LOW: clock required is too low
+ * @MODE_CLOCK_RANGE: clock/mode isn't in a ClockRange
+ * @MODE_BAD_HVALUE: horizontal timing was out of range
+ * @MODE_BAD_VVALUE: vertical timing was out of range
+ * @MODE_BAD_VSCAN: VScan value out of range
+ * @MODE_HSYNC_NARROW: horizontal sync too narrow
+ * @MODE_HSYNC_WIDE: horizontal sync too wide
+ * @MODE_HBLANK_NARROW: horizontal blanking too narrow
+ * @MODE_HBLANK_WIDE: horizontal blanking too wide
+ * @MODE_VSYNC_NARROW: vertical sync too narrow
+ * @MODE_VSYNC_WIDE: vertical sync too wide
+ * @MODE_VBLANK_NARROW: vertical blanking too narrow
+ * @MODE_VBLANK_WIDE: vertical blanking too wide
+ * @MODE_PANEL: exceeds panel dimensions
+ * @MODE_INTERLACE_WIDTH: width too large for interlaced mode
+ * @MODE_ONE_WIDTH: only one width is supported
+ * @MODE_ONE_HEIGHT: only one height is supported
+ * @MODE_ONE_SIZE: only one resolution is supported
+ * @MODE_NO_REDUCED: monitor doesn't accept reduced blanking
+ * @MODE_NO_STEREO: stereo modes not supported
+ * @MODE_NO_420: ycbcr 420 modes not supported
+ * @MODE_STALE: mode has become stale
+ * @MODE_BAD: unspecified reason
+ * @MODE_ERROR: error condition
+ *
+ * This enum is used to filter out modes not supported by the driver/hardware
+ * combination.
+ */
+enum drm_mode_status {
+ MODE_OK = 0,
+ MODE_HSYNC,
+ MODE_VSYNC,
+ MODE_H_ILLEGAL,
+ MODE_V_ILLEGAL,
+ MODE_BAD_WIDTH,
+ MODE_NOMODE,
+ MODE_NO_INTERLACE,
+ MODE_NO_DBLESCAN,
+ MODE_NO_VSCAN,
+ MODE_MEM,
+ MODE_VIRTUAL_X,
+ MODE_VIRTUAL_Y,
+ MODE_MEM_VIRT,
+ MODE_NOCLOCK,
+ MODE_CLOCK_HIGH,
+ MODE_CLOCK_LOW,
+ MODE_CLOCK_RANGE,
+ MODE_BAD_HVALUE,
+ MODE_BAD_VVALUE,
+ MODE_BAD_VSCAN,
+ MODE_HSYNC_NARROW,
+ MODE_HSYNC_WIDE,
+ MODE_HBLANK_NARROW,
+ MODE_HBLANK_WIDE,
+ MODE_VSYNC_NARROW,
+ MODE_VSYNC_WIDE,
+ MODE_VBLANK_NARROW,
+ MODE_VBLANK_WIDE,
+ MODE_PANEL,
+ MODE_INTERLACE_WIDTH,
+ MODE_ONE_WIDTH,
+ MODE_ONE_HEIGHT,
+ MODE_ONE_SIZE,
+ MODE_NO_REDUCED,
+ MODE_NO_STEREO,
+ MODE_NO_420,
+ MODE_STALE = -3,
+ MODE_BAD = -2,
+ MODE_ERROR = -1
+};
+
/*
* Subsystem independent description of a videomode.
* Can be generated from struct display_timing.
@@ -233,12 +321,16 @@
};
struct drm_display_mode *drm_mode_create(void);
+void drm_mode_copy(struct drm_display_mode *dst,
+ const struct drm_display_mode *src);
void drm_mode_destroy(struct drm_display_mode *mode);
bool drm_mode_match(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2,
unsigned int match_flags);
bool drm_mode_equal(const struct drm_display_mode *mode1,
const struct drm_display_mode *mode2);
+void drm_display_mode_from_videomode(const struct videomode *vm,
+ struct drm_display_mode *dmode);
void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
struct videomode *vm);
diff --git a/u-boot/include/dt-bindings/clock/rk3528-cru.h b/u-boot/include/dt-bindings/clock/rk3528-cru.h
new file mode 100644
index 0000000..807f19c
--- /dev/null
+++ b/u-boot/include/dt-bindings/clock/rk3528-cru.h
@@ -0,0 +1,754 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Joseph Chen <chenjh@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3528_H
+
+/* cru-clocks indices */
+
+/* core clocks */
+#define PLL_APLL 1
+#define PLL_CPLL 2
+#define PLL_GPLL 3
+#define PLL_PPLL 4
+#define PLL_DPLL 5
+#define ARMCLK 6
+
+#define XIN_OSC0_HALF 8
+#define CLK_MATRIX_50M_SRC 9
+#define CLK_MATRIX_100M_SRC 10
+#define CLK_MATRIX_150M_SRC 11
+#define CLK_MATRIX_200M_SRC 12
+#define CLK_MATRIX_250M_SRC 13
+#define CLK_MATRIX_300M_SRC 14
+#define CLK_MATRIX_339M_SRC 15
+#define CLK_MATRIX_400M_SRC 16
+#define CLK_MATRIX_500M_SRC 17
+#define CLK_MATRIX_600M_SRC 18
+#define CLK_UART0_SRC 19
+#define CLK_UART0_FRAC 20
+#define SCLK_UART0 21
+#define CLK_UART1_SRC 22
+#define CLK_UART1_FRAC 23
+#define SCLK_UART1 24
+#define CLK_UART2_SRC 25
+#define CLK_UART2_FRAC 26
+#define SCLK_UART2 27
+#define CLK_UART3_SRC 28
+#define CLK_UART3_FRAC 29
+#define SCLK_UART3 30
+#define CLK_UART4_SRC 31
+#define CLK_UART4_FRAC 32
+#define SCLK_UART4 33
+#define CLK_UART5_SRC 34
+#define CLK_UART5_FRAC 35
+#define SCLK_UART5 36
+#define CLK_UART6_SRC 37
+#define CLK_UART6_FRAC 38
+#define SCLK_UART6 39
+#define CLK_UART7_SRC 40
+#define CLK_UART7_FRAC 41
+#define SCLK_UART7 42
+#define CLK_I2S0_2CH_SRC 43
+#define CLK_I2S0_2CH_FRAC 44
+#define MCLK_I2S0_2CH_SAI_SRC 45
+#define CLK_I2S3_8CH_SRC 46
+#define CLK_I2S3_8CH_FRAC 47
+#define MCLK_I2S3_8CH_SAI_SRC 48
+#define CLK_I2S1_8CH_SRC 49
+#define CLK_I2S1_8CH_FRAC 50
+#define MCLK_I2S1_8CH_SAI_SRC 51
+#define CLK_I2S2_2CH_SRC 52
+#define CLK_I2S2_2CH_FRAC 53
+#define MCLK_I2S2_2CH_SAI_SRC 54
+#define CLK_SPDIF_SRC 55
+#define CLK_SPDIF_FRAC 56
+#define MCLK_SPDIF_SRC 57
+#define DCLK_VOP_SRC0 58
+#define DCLK_VOP_SRC1 59
+#define CLK_HSM 60
+#define CLK_CORE_SRC_ACS 63
+#define CLK_CORE_SRC_PVTMUX 65
+#define CLK_CORE_SRC 66
+#define CLK_CORE 67
+#define ACLK_M_CORE_BIU 68
+#define CLK_CORE_PVTPLL_SRC 69
+#define PCLK_DBG 70
+#define SWCLKTCK 71
+#define CLK_SCANHS_CORE 72
+#define CLK_SCANHS_ACLKM_CORE 73
+#define CLK_SCANHS_PCLK_DBG 74
+#define CLK_SCANHS_PCLK_CPU_BIU 76
+#define PCLK_CPU_ROOT 77
+#define PCLK_CORE_GRF 78
+#define PCLK_DAPLITE_BIU 79
+#define PCLK_CPU_BIU 80
+#define CLK_REF_PVTPLL_CORE 81
+#define ACLK_BUS_VOPGL_ROOT 85
+#define ACLK_BUS_VOPGL_BIU 86
+#define ACLK_BUS_H_ROOT 87
+#define ACLK_BUS_H_BIU 88
+#define ACLK_BUS_ROOT 89
+#define HCLK_BUS_ROOT 90
+#define PCLK_BUS_ROOT 91
+#define ACLK_BUS_M_ROOT 92
+#define ACLK_SYSMEM_BIU 93
+#define CLK_TIMER_ROOT 95
+#define ACLK_BUS_BIU 96
+#define HCLK_BUS_BIU 97
+#define PCLK_BUS_BIU 98
+#define PCLK_DFT2APB 99
+#define PCLK_BUS_GRF 100
+#define ACLK_BUS_M_BIU 101
+#define ACLK_GIC 102
+#define ACLK_SPINLOCK 103
+#define ACLK_DMAC 104
+#define PCLK_TIMER 105
+#define CLK_TIMER0 106
+#define CLK_TIMER1 107
+#define CLK_TIMER2 108
+#define CLK_TIMER3 109
+#define CLK_TIMER4 110
+#define CLK_TIMER5 111
+#define PCLK_JDBCK_DAP 112
+#define CLK_JDBCK_DAP 113
+#define PCLK_WDT_NS 114
+#define TCLK_WDT_NS 115
+#define HCLK_TRNG_NS 116
+#define PCLK_UART0 117
+#define CLK_CORE_CRYPTO 119
+#define CLK_PKA_CRYPTO 120
+#define ACLK_CRYPTO 121
+#define HCLK_CRYPTO 122
+#define PCLK_DMA2DDR 123
+#define ACLK_DMA2DDR 124
+#define PCLK_PWM0 126
+#define CLK_PWM0 127
+#define CLK_CAPTURE_PWM0 128
+#define PCLK_PWM1 129
+#define CLK_PWM1 130
+#define CLK_CAPTURE_PWM1 131
+#define PCLK_SCR 134
+#define ACLK_DCF 135
+#define PCLK_INTMUX 138
+#define CLK_PPLL_I 141
+#define CLK_PPLL_MUX 142
+#define CLK_PPLL_100M_MATRIX 143
+#define CLK_PPLL_50M_MATRIX 144
+#define CLK_REF_PCIE_INNER_PHY 145
+#define CLK_REF_PCIE_100M_PHY 146
+#define ACLK_VPU_L_ROOT 147
+#define CLK_GMAC1_VPU_25M 148
+#define CLK_PPLL_125M_MATRIX 149
+#define ACLK_VPU_ROOT 150
+#define HCLK_VPU_ROOT 151
+#define PCLK_VPU_ROOT 152
+#define ACLK_VPU_BIU 153
+#define HCLK_VPU_BIU 154
+#define PCLK_VPU_BIU 155
+#define ACLK_VPU 156
+#define HCLK_VPU 157
+#define PCLK_CRU_PCIE 158
+#define PCLK_VPU_GRF 159
+#define HCLK_SFC 160
+#define SCLK_SFC 161
+#define CCLK_SRC_EMMC 163
+#define HCLK_EMMC 164
+#define ACLK_EMMC 165
+#define BCLK_EMMC 166
+#define TCLK_EMMC 167
+#define PCLK_GPIO1 168
+#define DBCLK_GPIO1 169
+#define ACLK_VPU_L_BIU 172
+#define PCLK_VPU_IOC 173
+#define HCLK_SAI_I2S0 174
+#define MCLK_SAI_I2S0 175
+#define HCLK_SAI_I2S2 176
+#define MCLK_SAI_I2S2 177
+#define PCLK_ACODEC 178
+#define MCLK_ACODEC_TX 179
+#define PCLK_GPIO3 186
+#define DBCLK_GPIO3 187
+#define PCLK_SPI1 189
+#define CLK_SPI1 190
+#define SCLK_IN_SPI1 191
+#define PCLK_UART2 192
+#define PCLK_UART5 194
+#define PCLK_UART6 196
+#define PCLK_UART7 198
+#define PCLK_I2C3 200
+#define CLK_I2C3 201
+#define PCLK_I2C5 202
+#define CLK_I2C5 203
+#define PCLK_I2C6 204
+#define CLK_I2C6 205
+#define ACLK_MAC_VPU 206
+#define PCLK_MAC_VPU 207
+#define CLK_GMAC1_RMII_VPU 209
+#define CLK_GMAC1_SRC_VPU 210
+#define PCLK_PCIE 215
+#define CLK_PCIE_AUX 216
+#define ACLK_PCIE 217
+#define HCLK_PCIE_SLV 218
+#define HCLK_PCIE_DBI 219
+#define PCLK_PCIE_PHY 220
+#define PCLK_PIPE_GRF 221
+#define CLK_PIPE_USB3OTG_COMBO 230
+#define CLK_UTMI_USB3OTG 232
+#define CLK_PCIE_PIPE_PHY 235
+#define CCLK_SRC_SDIO0 240
+#define HCLK_SDIO0 241
+#define CCLK_SRC_SDIO1 244
+#define HCLK_SDIO1 245
+#define CLK_TS_0 246
+#define CLK_TS_1 247
+#define PCLK_CAN2 250
+#define CLK_CAN2 251
+#define PCLK_CAN3 252
+#define CLK_CAN3 253
+#define PCLK_SARADC 256
+#define CLK_SARADC 257
+#define PCLK_TSADC 258
+#define CLK_TSADC 259
+#define CLK_TSADC_TSEN 260
+#define ACLK_USB3OTG 261
+#define CLK_REF_USB3OTG 262
+#define CLK_SUSPEND_USB3OTG 263
+#define ACLK_GPU_ROOT 269
+#define PCLK_GPU_ROOT 270
+#define ACLK_GPU_BIU 271
+#define PCLK_GPU_BIU 272
+#define ACLK_GPU 273
+#define CLK_GPU_PVTPLL_SRC 274
+#define ACLK_GPU_MALI 275
+#define HCLK_RKVENC_ROOT 281
+#define ACLK_RKVENC_ROOT 282
+#define PCLK_RKVENC_ROOT 283
+#define HCLK_RKVENC_BIU 284
+#define ACLK_RKVENC_BIU 285
+#define PCLK_RKVENC_BIU 286
+#define HCLK_RKVENC 287
+#define ACLK_RKVENC 288
+#define CLK_CORE_RKVENC 289
+#define HCLK_SAI_I2S1 290
+#define MCLK_SAI_I2S1 291
+#define PCLK_I2C1 292
+#define CLK_I2C1 293
+#define PCLK_I2C0 294
+#define CLK_I2C0 295
+#define CLK_UART_JTAG 296
+#define PCLK_SPI0 297
+#define CLK_SPI0 298
+#define SCLK_IN_SPI0 299
+#define PCLK_GPIO4 300
+#define DBCLK_GPIO4 301
+#define PCLK_RKVENC_IOC 302
+#define HCLK_SPDIF 308
+#define MCLK_SPDIF 309
+#define HCLK_PDM 310
+#define MCLK_PDM 311
+#define PCLK_UART1 315
+#define PCLK_UART3 317
+#define PCLK_RKVENC_GRF 319
+#define PCLK_CAN0 320
+#define CLK_CAN0 321
+#define PCLK_CAN1 322
+#define CLK_CAN1 323
+#define ACLK_VO_ROOT 324
+#define HCLK_VO_ROOT 325
+#define PCLK_VO_ROOT 326
+#define ACLK_VO_BIU 327
+#define HCLK_VO_BIU 328
+#define PCLK_VO_BIU 329
+#define HCLK_RGA2E 330
+#define ACLK_RGA2E 331
+#define CLK_CORE_RGA2E 332
+#define HCLK_VDPP 333
+#define ACLK_VDPP 334
+#define CLK_CORE_VDPP 335
+#define PCLK_VO_GRF 336
+#define PCLK_CRU 337
+#define ACLK_VOP_ROOT 338
+#define ACLK_VOP_BIU 339
+#define HCLK_VOP 340
+#define DCLK_VOP0 341
+#define DCLK_VOP1 342
+#define ACLK_VOP 343
+#define PCLK_HDMI 344
+#define CLK_SFR_HDMI 345
+#define CLK_CEC_HDMI 346
+#define CLK_SPDIF_HDMI 347
+#define CLK_HDMIPHY_TMDSSRC 348
+#define CLK_HDMIPHY_PREP 349
+#define PCLK_HDMIPHY 352
+#define HCLK_HDCP_KEY 354
+#define ACLK_HDCP 355
+#define HCLK_HDCP 356
+#define PCLK_HDCP 357
+#define HCLK_CVBS 358
+#define DCLK_CVBS 359
+#define DCLK_4X_CVBS 360
+#define ACLK_JPEG_DECODER 361
+#define HCLK_JPEG_DECODER 362
+#define ACLK_VO_L_ROOT 375
+#define ACLK_VO_L_BIU 376
+#define ACLK_MAC_VO 377
+#define PCLK_MAC_VO 378
+#define CLK_GMAC0_SRC 379
+#define CLK_GMAC0_RMII_50M 380
+#define CLK_GMAC0_TX 381
+#define CLK_GMAC0_RX 382
+#define ACLK_JPEG_ROOT 385
+#define ACLK_JPEG_BIU 386
+#define HCLK_SAI_I2S3 387
+#define MCLK_SAI_I2S3 388
+#define CLK_MACPHY 398
+#define PCLK_VCDCPHY 399
+#define PCLK_GPIO2 404
+#define DBCLK_GPIO2 405
+#define PCLK_VO_IOC 406
+#define CCLK_SRC_SDMMC0 407
+#define HCLK_SDMMC0 408
+#define PCLK_OTPC_NS 411
+#define CLK_SBPI_OTPC_NS 412
+#define CLK_USER_OTPC_NS 413
+#define CLK_HDMIHDP0 415
+#define HCLK_USBHOST 416
+#define HCLK_USBHOST_ARB 417
+#define CLK_USBHOST_OHCI 418
+#define CLK_USBHOST_UTMI 419
+#define PCLK_UART4 420
+#define PCLK_I2C4 422
+#define CLK_I2C4 423
+#define PCLK_I2C7 424
+#define CLK_I2C7 425
+#define PCLK_USBPHY 426
+#define CLK_REF_USBPHY 427
+#define HCLK_RKVDEC_ROOT 433
+#define ACLK_RKVDEC_ROOT_NDFT 434
+#define PCLK_DDRPHY_CRU 435
+#define HCLK_RKVDEC_BIU 436
+#define ACLK_RKVDEC_BIU 437
+#define ACLK_RKVDEC 439
+#define HCLK_RKVDEC 440
+#define CLK_HEVC_CA_RKVDEC 441
+#define ACLK_RKVDEC_PVTMUX_ROOT 442
+#define CLK_RKVDEC_PVTPLL_SRC 443
+#define PCLK_DDR_ROOT 449
+#define PCLK_DDR_BIU 450
+#define PCLK_DDRC 451
+#define PCLK_DDRMON 452
+#define CLK_TIMER_DDRMON 453
+#define PCLK_MSCH_BIU 454
+#define PCLK_DDR_GRF 455
+#define PCLK_DDR_HWLP 456
+#define PCLK_DDRPHY 457
+#define CLK_MSCH_BIU 463
+#define ACLK_DDR_UPCTL 464
+#define CLK_DDR_UPCTL 465
+#define CLK_DDRMON 466
+#define ACLK_DDR_SCRAMBLE 467
+#define ACLK_SPLIT 468
+#define CLK_DDRC_SRC 470
+#define CLK_DDR_PHY 471
+#define PCLK_OTPC_S 472
+#define CLK_SBPI_OTPC_S 473
+#define CLK_USER_OTPC_S 474
+#define PCLK_KEYREADER 475
+#define PCLK_BUS_SGRF 476
+#define PCLK_STIMER 477
+#define CLK_STIMER0 478
+#define CLK_STIMER1 479
+#define PCLK_WDT_S 480
+#define TCLK_WDT_S 481
+#define HCLK_TRNG_S 482
+#define PCLK_KLAD 483
+#define HCLK_CRYPTO_S 484
+#define HCLK_KLAD 485
+#define HCLK_BOOTROM 486
+#define PCLK_DCF 487
+#define ACLK_SYSMEM 488
+#define HCLK_TSP 489
+#define ACLK_TSP 490
+#define CLK_CORE_TSP 491
+#define CLK_OTPC_ARB 492
+#define PCLK_OTP_MASK 493
+#define CLK_PMC_OTP 494
+#define PCLK_PMU_ROOT 495
+#define HCLK_PMU_ROOT 496
+#define PCLK_I2C2 497
+#define CLK_I2C2 498
+#define HCLK_PMU_BIU 500
+#define PCLK_PMU_BIU 501
+#define FCLK_MCU 502
+#define RTC_CLK_MCU 504
+#define PCLK_OSCCHK 505
+#define CLK_PMU_MCU_JTAG 506
+#define PCLK_PMU 508
+#define PCLK_GPIO0 509
+#define DBCLK_GPIO0 510
+#define XIN_OSC0_DIV 511
+#define CLK_DEEPSLOW 512
+#define CLK_DDR_FAIL_SAFE 513
+#define PCLK_PMU_HP_TIMER 514
+#define CLK_PMU_HP_TIMER 515
+#define CLK_PMU_32K_HP_TIMER 516
+#define PCLK_PMU_IOC 517
+#define PCLK_PMU_CRU 518
+#define PCLK_PMU_GRF 519
+#define PCLK_PMU_WDT 520
+#define TCLK_PMU_WDT 521
+#define PCLK_PMU_MAILBOX 522
+#define PCLK_SCRKEYGEN 524
+#define CLK_SCRKEYGEN 525
+#define CLK_PVTM_OSCCHK 526
+#define CLK_REFOUT 530
+#define CLK_PVTM_PMU 532
+#define PCLK_PVTM_PMU 533
+#define PCLK_PMU_SGRF 534
+#define HCLK_PMU_SRAM 535
+#define CLK_UART0 536
+#define CLK_UART1 537
+#define CLK_UART2 538
+#define CLK_UART3 539
+#define CLK_UART4 540
+#define CLK_UART5 541
+#define CLK_UART6 542
+#define CLK_UART7 543
+#define MCLK_I2S0_2CH_SAI_SRC_PRE 544
+#define MCLK_I2S1_8CH_SAI_SRC_PRE 545
+#define MCLK_I2S2_2CH_SAI_SRC_PRE 546
+#define MCLK_I2S3_8CH_SAI_SRC_PRE 547
+#define MCLK_SDPDIF_SRC_PRE 548
+#define CLK_NR_CLKS (MCLK_SDPDIF_SRC_PRE + 1)
+
+/* grf-clocks indices */
+#define SCLK_SDMMC_DRV 1
+#define SCLK_SDMMC_SAMPLE 2
+#define SCLK_SDIO0_DRV 3
+#define SCLK_SDIO0_SAMPLE 4
+#define SCLK_SDIO1_DRV 5
+#define SCLK_SDIO1_SAMPLE 6
+#define CLK_NR_GRF_CLKS (SCLK_SDIO1_SAMPLE + 1)
+
+/* scmi-clocks indices */
+#define SCMI_PCLK_KEYREADER 0
+#define SCMI_HCLK_KLAD 1
+#define SCMI_PCLK_KLAD 2
+#define SCMI_HCLK_TRNG_S 3
+#define SCMI_HCLK_CRYPTO_S 4
+#define SCMI_PCLK_WDT_S 5
+#define SCMI_TCLK_WDT_S 6
+#define SCMI_PCLK_STIMER 7
+#define SCMI_CLK_STIMER0 8
+#define SCMI_CLK_STIMER1 9
+#define SCMI_PCLK_OTP_MASK 10
+#define SCMI_PCLK_OTPC_S 11
+#define SCMI_CLK_SBPI_OTPC_S 12
+#define SCMI_CLK_USER_OTPC_S 13
+#define SCMI_CLK_PMC_OTP 14
+#define SCMI_CLK_OTPC_ARB 15
+#define SCMI_CLK_CORE_TSP 16
+#define SCMI_ACLK_TSP 17
+#define SCMI_HCLK_TSP 18
+#define SCMI_PCLK_DCF 19
+#define SCMI_CLK_DDR 20
+#define SCMI_CLK_CPU 21
+#define SCMI_CLK_GPU 22
+#define SCMI_CORE_CRYPTO 23
+#define SCMI_ACLK_CRYPTO 24
+#define SCMI_PKA_CRYPTO 25
+#define SCMI_HCLK_CRYPTO 26
+#define SCMI_CORE_CRYPTO_S 27
+#define SCMI_ACLK_CRYPTO_S 28
+#define SCMI_PKA_CRYPTO_S 29
+#define SCMI_CORE_KLAD 30
+#define SCMI_ACLK_KLAD 31
+#define SCMI_HCLK_TRNG 32
+
+// CRU_SOFTRST_CON03(Offset:0xA0C)
+#define SRST_NCOREPORESET0 0x00000030
+#define SRST_NCOREPORESET1 0x00000031
+#define SRST_NCOREPORESET2 0x00000032
+#define SRST_NCOREPORESET3 0x00000033
+#define SRST_NCORESET0 0x00000034
+#define SRST_NCORESET1 0x00000035
+#define SRST_NCORESET2 0x00000036
+#define SRST_NCORESET3 0x00000037
+#define SRST_NL2RESET 0x00000038
+#define SRST_ARESETN_M_CORE_BIU 0x00000039
+#define SRST_RESETN_CORE_CRYPTO 0x0000003A
+
+// CRU_SOFTRST_CON05(Offset:0xA14)
+#define SRST_PRESETN_DBG 0x0000005D
+#define SRST_POTRESETN_DBG 0x0000005E
+#define SRST_NTRESETN_DBG 0x0000005F
+
+// CRU_SOFTRST_CON06(Offset:0xA18)
+#define SRST_PRESETN_CORE_GRF 0x00000062
+#define SRST_PRESETN_DAPLITE_BIU 0x00000063
+#define SRST_PRESETN_CPU_BIU 0x00000064
+#define SRST_RESETN_REF_PVTPLL_CORE 0x00000067
+
+// CRU_SOFTRST_CON08(Offset:0xA20)
+#define SRST_ARESETN_BUS_VOPGL_BIU 0x00000081
+#define SRST_ARESETN_BUS_H_BIU 0x00000083
+#define SRST_ARESETN_SYSMEM_BIU 0x00000088
+#define SRST_ARESETN_BUS_BIU 0x0000008A
+#define SRST_HRESETN_BUS_BIU 0x0000008B
+#define SRST_PRESETN_BUS_BIU 0x0000008C
+#define SRST_PRESETN_DFT2APB 0x0000008D
+#define SRST_PRESETN_BUS_GRF 0x0000008F
+
+// CRU_SOFTRST_CON09(Offset:0xA24)
+#define SRST_ARESETN_BUS_M_BIU 0x00000090
+#define SRST_ARESETN_GIC 0x00000091
+#define SRST_ARESETN_SPINLOCK 0x00000092
+#define SRST_ARESETN_DMAC 0x00000094
+#define SRST_PRESETN_TIMER 0x00000095
+#define SRST_RESETN_TIMER0 0x00000096
+#define SRST_RESETN_TIMER1 0x00000097
+#define SRST_RESETN_TIMER2 0x00000098
+#define SRST_RESETN_TIMER3 0x00000099
+#define SRST_RESETN_TIMER4 0x0000009A
+#define SRST_RESETN_TIMER5 0x0000009B
+#define SRST_PRESETN_JDBCK_DAP 0x0000009C
+#define SRST_RESETN_JDBCK_DAP 0x0000009D
+#define SRST_PRESETN_WDT_NS 0x0000009F
+
+// CRU_SOFTRST_CON10(Offset:0xA28)
+#define SRST_TRESETN_WDT_NS 0x000000A0
+#define SRST_HRESETN_TRNG_NS 0x000000A3
+#define SRST_PRESETN_UART0 0x000000A7
+#define SRST_SRESETN_UART0 0x000000A8
+#define SRST_RESETN_PKA_CRYPTO 0x000000AA
+#define SRST_ARESETN_CRYPTO 0x000000AB
+#define SRST_HRESETN_CRYPTO 0x000000AC
+#define SRST_PRESETN_DMA2DDR 0x000000AD
+#define SRST_ARESETN_DMA2DDR 0x000000AE
+
+// CRU_SOFTRST_CON11(Offset:0xA2C)
+#define SRST_PRESETN_PWM0 0x000000B4
+#define SRST_RESETN_PWM0 0x000000B5
+#define SRST_PRESETN_PWM1 0x000000B7
+#define SRST_RESETN_PWM1 0x000000B8
+#define SRST_PRESETN_SCR 0x000000BA
+#define SRST_ARESETN_DCF 0x000000BB
+#define SRST_PRESETN_INTMUX 0x000000BC
+
+// CRU_SOFTRST_CON25(Offset:0xA64)
+#define SRST_ARESETN_VPU_BIU 0x00000196
+#define SRST_HRESETN_VPU_BIU 0x00000197
+#define SRST_PRESETN_VPU_BIU 0x00000198
+#define SRST_ARESETN_VPU 0x00000199
+#define SRST_HRESETN_VPU 0x0000019A
+#define SRST_PRESETN_CRU_PCIE 0x0000019B
+#define SRST_PRESETN_VPU_GRF 0x0000019C
+#define SRST_HRESETN_SFC 0x0000019D
+#define SRST_SRESETN_SFC 0x0000019E
+#define SRST_CRESETN_EMMC 0x0000019F
+
+// CRU_SOFTRST_CON26(Offset:0xA68)
+#define SRST_HRESETN_EMMC 0x000001A0
+#define SRST_ARESETN_EMMC 0x000001A1
+#define SRST_BRESETN_EMMC 0x000001A2
+#define SRST_TRESETN_EMMC 0x000001A3
+#define SRST_PRESETN_GPIO1 0x000001A4
+#define SRST_DBRESETN_GPIO1 0x000001A5
+#define SRST_ARESETN_VPU_L_BIU 0x000001A6
+#define SRST_PRESETN_VPU_IOC 0x000001A8
+#define SRST_HRESETN_SAI_I2S0 0x000001A9
+#define SRST_MRESETN_SAI_I2S0 0x000001AA
+#define SRST_HRESETN_SAI_I2S2 0x000001AB
+#define SRST_MRESETN_SAI_I2S2 0x000001AC
+#define SRST_PRESETN_ACODEC 0x000001AD
+
+// CRU_SOFTRST_CON27(Offset:0xA6C)
+#define SRST_PRESETN_GPIO3 0x000001B0
+#define SRST_DBRESETN_GPIO3 0x000001B1
+#define SRST_PRESETN_SPI1 0x000001B4
+#define SRST_RESETN_SPI1 0x000001B5
+#define SRST_PRESETN_UART2 0x000001B7
+#define SRST_SRESETN_UART2 0x000001B8
+#define SRST_PRESETN_UART5 0x000001B9
+#define SRST_SRESETN_UART5 0x000001BA
+#define SRST_PRESETN_UART6 0x000001BB
+#define SRST_SRESETN_UART6 0x000001BC
+#define SRST_PRESETN_UART7 0x000001BD
+#define SRST_SRESETN_UART7 0x000001BE
+#define SRST_PRESETN_I2C3 0x000001BF
+
+// CRU_SOFTRST_CON28(Offset:0xA70)
+#define SRST_RESETN_I2C3 0x000001C0
+#define SRST_PRESETN_I2C5 0x000001C1
+#define SRST_RESETN_I2C5 0x000001C2
+#define SRST_PRESETN_I2C6 0x000001C3
+#define SRST_RESETN_I2C6 0x000001C4
+#define SRST_ARESETN_MAC 0x000001C5
+
+// CRU_SOFTRST_CON30(Offset:0xA78)
+#define SRST_PRESETN_PCIE 0x000001E1
+#define SRST_RESETN_PCIE_PIPE_PHY 0x000001E2
+#define SRST_RESETN_PCIE_POWER_UP 0x000001E3
+#define SRST_PRESETN_PCIE_PHY 0x000001E6
+#define SRST_PRESETN_PIPE_GRF 0x000001E7
+
+// CRU_SOFTRST_CON32(Offset:0xA80)
+#define SRST_HRESETN_SDIO0 0x00000202
+#define SRST_HRESETN_SDIO1 0x00000204
+#define SRST_RESETN_TS_0 0x00000205
+#define SRST_RESETN_TS_1 0x00000206
+#define SRST_PRESETN_CAN2 0x00000207
+#define SRST_RESETN_CAN2 0x00000208
+#define SRST_PRESETN_CAN3 0x00000209
+#define SRST_RESETN_CAN3 0x0000020A
+#define SRST_PRESETN_SARADC 0x0000020B
+#define SRST_RESETN_SARADC 0x0000020C
+#define SRST_RESETN_SARADC_PHY 0x0000020D
+#define SRST_PRESETN_TSADC 0x0000020E
+#define SRST_RESETN_TSADC 0x0000020F
+
+// CRU_SOFTRST_CON33(Offset:0xA84)
+#define SRST_ARESETN_USB3OTG 0x00000211
+
+// CRU_SOFTRST_CON34(Offset:0xA88)
+#define SRST_ARESETN_GPU_BIU 0x00000223
+#define SRST_PRESETN_GPU_BIU 0x00000225
+#define SRST_ARESETN_GPU 0x00000228
+#define SRST_RESETN_REF_PVTPLL_GPU 0x00000229
+
+// CRU_SOFTRST_CON36(Offset:0xA90)
+#define SRST_HRESETN_RKVENC_BIU 0x00000243
+#define SRST_ARESETN_RKVENC_BIU 0x00000244
+#define SRST_PRESETN_RKVENC_BIU 0x00000245
+#define SRST_HRESETN_RKVENC 0x00000246
+#define SRST_ARESETN_RKVENC 0x00000247
+#define SRST_RESETN_CORE_RKVENC 0x00000248
+#define SRST_HRESETN_SAI_I2S1 0x00000249
+#define SRST_MRESETN_SAI_I2S1 0x0000024A
+#define SRST_PRESETN_I2C1 0x0000024B
+#define SRST_RESETN_I2C1 0x0000024C
+#define SRST_PRESETN_I2C0 0x0000024D
+#define SRST_RESETN_I2C0 0x0000024E
+
+// CRU_SOFTRST_CON37(Offset:0xA94)
+#define SRST_PRESETN_SPI0 0x00000252
+#define SRST_RESETN_SPI0 0x00000253
+#define SRST_PRESETN_GPIO4 0x00000258
+#define SRST_DBRESETN_GPIO4 0x00000259
+#define SRST_PRESETN_RKVENC_IOC 0x0000025A
+#define SRST_HRESETN_SPDIF 0x0000025E
+#define SRST_MRESETN_SPDIF 0x0000025F
+
+// CRU_SOFTRST_CON38(Offset:0xA98)
+#define SRST_HRESETN_PDM 0x00000260
+#define SRST_MRESETN_PDM 0x00000261
+#define SRST_PRESETN_UART1 0x00000262
+#define SRST_SRESETN_UART1 0x00000263
+#define SRST_PRESETN_UART3 0x00000264
+#define SRST_SRESETN_UART3 0x00000265
+#define SRST_PRESETN_RKVENC_GRF 0x00000266
+#define SRST_PRESETN_CAN0 0x00000267
+#define SRST_RESETN_CAN0 0x00000268
+#define SRST_PRESETN_CAN1 0x00000269
+#define SRST_RESETN_CAN1 0x0000026A
+
+// CRU_SOFTRST_CON39(Offset:0xA9C)
+#define SRST_ARESETN_VO_BIU 0x00000273
+#define SRST_HRESETN_VO_BIU 0x00000274
+#define SRST_PRESETN_VO_BIU 0x00000275
+#define SRST_HRESETN_RGA2E 0x00000277
+#define SRST_ARESETN_RGA2E 0x00000278
+#define SRST_RESETN_CORE_RGA2E 0x00000279
+#define SRST_HRESETN_VDPP 0x0000027A
+#define SRST_ARESETN_VDPP 0x0000027B
+#define SRST_RESETN_CORE_VDPP 0x0000027C
+#define SRST_PRESETN_VO_GRF 0x0000027D
+#define SRST_PRESETN_CRU 0x0000027F
+
+// CRU_SOFTRST_CON40(Offset:0xAA0)
+#define SRST_ARESETN_VOP_BIU 0x00000281
+#define SRST_HRESETN_VOP 0x00000282
+#define SRST_DRESETN_VOP0 0x00000283
+#define SRST_DRESETN_VOP1 0x00000284
+#define SRST_ARESETN_VOP 0x00000285
+#define SRST_PRESETN_HDMI 0x00000286
+#define SRST_HDMI_RESETN 0x00000287
+#define SRST_PRESETN_HDMIPHY 0x0000028E
+#define SRST_HRESETN_HDCP_KEY 0x0000028F
+
+// CRU_SOFTRST_CON41(Offset:0xAA4)
+#define SRST_ARESETN_HDCP 0x00000290
+#define SRST_HRESETN_HDCP 0x00000291
+#define SRST_PRESETN_HDCP 0x00000292
+#define SRST_HRESETN_CVBS 0x00000293
+#define SRST_DRESETN_CVBS_VOP 0x00000294
+#define SRST_DRESETN_4X_CVBS_VOP 0x00000295
+#define SRST_ARESETN_JPEG_DECODER 0x00000296
+#define SRST_HRESETN_JPEG_DECODER 0x00000297
+#define SRST_ARESETN_VO_L_BIU 0x00000299
+#define SRST_ARESETN_MAC_VO 0x0000029A
+
+// CRU_SOFTRST_CON42(Offset:0xAA8)
+#define SRST_ARESETN_JPEG_BIU 0x000002A0
+#define SRST_HRESETN_SAI_I2S3 0x000002A1
+#define SRST_MRESETN_SAI_I2S3 0x000002A2
+#define SRST_RESETN_MACPHY 0x000002A3
+#define SRST_PRESETN_VCDCPHY 0x000002A4
+#define SRST_PRESETN_GPIO2 0x000002A5
+#define SRST_DBRESETN_GPIO2 0x000002A6
+#define SRST_PRESETN_VO_IOC 0x000002A7
+#define SRST_HRESETN_SDMMC0 0x000002A9
+#define SRST_PRESETN_OTPC_NS 0x000002AB
+#define SRST_RESETN_SBPI_OTPC_NS 0x000002AC
+#define SRST_RESETN_USER_OTPC_NS 0x000002AD
+
+// CRU_SOFTRST_CON43(Offset:0xAAC)
+#define SRST_RESETN_HDMIHDP0 0x000002B2
+#define SRST_HRESETN_USBHOST 0x000002B3
+#define SRST_HRESETN_USBHOST_ARB 0x000002B4
+#define SRST_RESETN_HOST_UTMI 0x000002B6
+#define SRST_PRESETN_UART4 0x000002B7
+#define SRST_SRESETN_UART4 0x000002B8
+#define SRST_PRESETN_I2C4 0x000002B9
+#define SRST_RESETN_I2C4 0x000002BA
+#define SRST_PRESETN_I2C7 0x000002BB
+#define SRST_RESETN_I2C7 0x000002BC
+#define SRST_PRESETN_USBPHY 0x000002BD
+#define SRST_RESETN_USBPHY_POR 0x000002BE
+#define SRST_RESETN_USBPHY_OTG 0x000002BF
+
+// CRU_SOFTRST_CON44(Offset:0xAB0)
+#define SRST_RESETN_USBPHY_HOST 0x000002C0
+#define SRST_PRESETN_DDRPHY_CRU 0x000002C4
+#define SRST_HRESETN_RKVDEC_BIU 0x000002C6
+#define SRST_ARESETN_RKVDEC_BIU 0x000002C7
+#define SRST_ARESETN_RKVDEC 0x000002C8
+#define SRST_HRESETN_RKVDEC 0x000002C9
+#define SRST_RESETN_HEVC_CA_RKVDEC 0x000002CB
+#define SRST_RESETN_REF_PVTPLL_RKVDEC 0x000002CC
+
+// CRU_SOFTRST_CON45(Offset:0xAB4)
+#define SRST_PRESETN_DDR_BIU 0x000002D1
+#define SRST_PRESETN_DDRC 0x000002D2
+#define SRST_PRESETN_DDRMON 0x000002D3
+#define SRST_RESETN_TIMER_DDRMON 0x000002D4
+#define SRST_PRESETN_MSCH_BIU 0x000002D5
+#define SRST_PRESETN_DDR_GRF 0x000002D6
+#define SRST_PRESETN_DDR_HWLP 0x000002D8
+#define SRST_PRESETN_DDRPHY 0x000002D9
+#define SRST_RESETN_MSCH_BIU 0x000002DA
+#define SRST_ARESETN_DDR_UPCTL 0x000002DB
+#define SRST_RESETN_DDR_UPCTL 0x000002DC
+#define SRST_RESETN_DDRMON 0x000002DD
+#define SRST_ARESETN_DDR_SCRAMBLE 0x000002DE
+#define SRST_ARESETN_SPLIT 0x000002DF
+
+// CRU_SOFTRST_CON46(Offset:0xAB8)
+#define SRST_RESETN_DDR_PHY 0x000002E0
+
+#endif
+
diff --git a/u-boot/include/dt-bindings/clock/rk3562-cru.h b/u-boot/include/dt-bindings/clock/rk3562-cru.h
new file mode 100644
index 0000000..3bdbed5
--- /dev/null
+++ b/u-boot/include/dt-bindings/clock/rk3562-cru.h
@@ -0,0 +1,733 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co. Ltd.
+ * Author: Finley Xiao <finley.xiao@rock-chips.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+#define _DT_BINDINGS_CLK_ROCKCHIP_RK3562_H
+
+/* cru-clocks indices */
+
+/* cru plls */
+#define PLL_APLL 1
+#define PLL_GPLL 2
+#define PLL_VPLL 3
+#define PLL_HPLL 4
+#define PLL_CPLL 5
+#define PLL_DPLL 6
+
+/* cru clocks */
+#define ARMCLK 8
+#define CLK_GPU 9
+#define ACLK_RKNN 10
+#define CLK_DDR 11
+#define CLK_MATRIX_50M_SRC 12
+#define CLK_MATRIX_100M_SRC 13
+#define CLK_MATRIX_125M_SRC 14
+#define CLK_MATRIX_200M_SRC 15
+#define CLK_MATRIX_300M_SRC 16
+#define ACLK_TOP 17
+#define ACLK_TOP_VIO 18
+#define CLK_CAM0_OUT2IO 19
+#define CLK_CAM1_OUT2IO 20
+#define CLK_CAM2_OUT2IO 21
+#define CLK_CAM3_OUT2IO 22
+#define ACLK_BUS 23
+#define HCLK_BUS 24
+#define PCLK_BUS 25
+#define PCLK_I2C1 26
+#define PCLK_I2C2 27
+#define PCLK_I2C3 28
+#define PCLK_I2C4 29
+#define PCLK_I2C5 30
+#define CLK_I2C 31
+#define CLK_I2C1 32
+#define CLK_I2C2 33
+#define CLK_I2C3 34
+#define CLK_I2C4 35
+#define CLK_I2C5 36
+#define DCLK_BUS_GPIO 37
+#define DCLK_BUS_GPIO3 38
+#define DCLK_BUS_GPIO4 39
+#define PCLK_TIMER 40
+#define CLK_TIMER0 41
+#define CLK_TIMER1 42
+#define CLK_TIMER2 43
+#define CLK_TIMER3 44
+#define CLK_TIMER4 45
+#define CLK_TIMER5 46
+#define PCLK_STIMER 47
+#define CLK_STIMER0 48
+#define CLK_STIMER1 49
+#define PCLK_WDTNS 50
+#define CLK_WDTNS 51
+#define PCLK_GRF 52
+#define PCLK_SGRF 53
+#define PCLK_MAILBOX 54
+#define PCLK_INTC 55
+#define ACLK_BUS_GIC400 56
+#define ACLK_BUS_SPINLOCK 57
+#define ACLK_DCF 58
+#define PCLK_DCF 59
+#define FCLK_BUS_CM0_CORE 60
+#define CLK_BUS_CM0_RTC 61
+#define HCLK_ICACHE 62
+#define HCLK_DCACHE 63
+#define PCLK_TSADC 64
+#define CLK_TSADC 65
+#define CLK_TSADC_TSEN 66
+#define PCLK_DFT2APB 67
+#define CLK_SARADC_VCCIO156 68
+#define PCLK_GMAC 69
+#define ACLK_GMAC 70
+#define CLK_GMAC_125M_CRU_I 71
+#define CLK_GMAC_50M_CRU_I 72
+#define CLK_GMAC_50M_O 73
+#define CLK_GMAC_ETH_OUT2IO 74
+#define PCLK_APB2ASB_VCCIO156 75
+#define PCLK_TO_VCCIO156 76
+#define PCLK_DSIPHY 77
+#define PCLK_DSITX 78
+#define PCLK_CPU_EMA_DET 79
+#define PCLK_HASH 80
+#define PCLK_TOPCRU 81
+#define PCLK_ASB2APB_VCCIO156 82
+#define PCLK_IOC_VCCIO156 83
+#define PCLK_GPIO3_VCCIO156 84
+#define PCLK_GPIO4_VCCIO156 85
+#define PCLK_SARADC_VCCIO156 86
+#define PCLK_MAC100 87
+#define ACLK_MAC100 89
+#define CLK_MAC100_50M_MATRIX 90
+#define HCLK_CORE 91
+#define PCLK_DDR 92
+#define CLK_MSCH_BRG_BIU 93
+#define PCLK_DDR_HWLP 94
+#define PCLK_DDR_UPCTL 95
+#define PCLK_DDR_PHY 96
+#define PCLK_DDR_DFICTL 97
+#define PCLK_DDR_DMA2DDR 98
+#define PCLK_DDR_MON 99
+#define TMCLK_DDR_MON 100
+#define PCLK_DDR_GRF 101
+#define PCLK_DDR_CRU 102
+#define PCLK_SUBDDR_CRU 103
+#define CLK_GPU_PRE 104
+#define ACLK_GPU_PRE 105
+#define CLK_GPU_BRG 107
+#define CLK_NPU_PRE 108
+#define HCLK_NPU_PRE 109
+#define HCLK_RKNN 111
+#define ACLK_PERI 112
+#define HCLK_PERI 113
+#define PCLK_PERI 114
+#define PCLK_PERICRU 115
+#define HCLK_SAI0 116
+#define CLK_SAI0_SRC 117
+#define CLK_SAI0_FRAC 118
+#define CLK_SAI0 119
+#define MCLK_SAI0 120
+#define MCLK_SAI0_OUT2IO 121
+#define HCLK_SAI1 122
+#define CLK_SAI1_SRC 123
+#define CLK_SAI1_FRAC 124
+#define CLK_SAI1 125
+#define MCLK_SAI1 126
+#define MCLK_SAI1_OUT2IO 127
+#define HCLK_SAI2 128
+#define CLK_SAI2_SRC 129
+#define CLK_SAI2_FRAC 130
+#define CLK_SAI2 131
+#define MCLK_SAI2 132
+#define MCLK_SAI2_OUT2IO 133
+#define HCLK_DSM 134
+#define CLK_DSM 135
+#define HCLK_PDM 136
+#define MCLK_PDM 137
+#define HCLK_SPDIF 138
+#define CLK_SPDIF_SRC 139
+#define CLK_SPDIF_FRAC 140
+#define CLK_SPDIF 141
+#define MCLK_SPDIF 142
+#define HCLK_SDMMC0 143
+#define CCLK_SDMMC0 144
+#define HCLK_SDMMC1 145
+#define CCLK_SDMMC1 146
+#define SCLK_SDMMC0_DRV 147
+#define SCLK_SDMMC0_SAMPLE 148
+#define SCLK_SDMMC1_DRV 149
+#define SCLK_SDMMC1_SAMPLE 150
+#define HCLK_EMMC 151
+#define ACLK_EMMC 152
+#define CCLK_EMMC 153
+#define BCLK_EMMC 154
+#define TMCLK_EMMC 155
+#define SCLK_SFC 156
+#define HCLK_SFC 157
+#define HCLK_USB2HOST 158
+#define HCLK_USB2HOST_ARB 159
+#define PCLK_SPI1 160
+#define CLK_SPI1 161
+#define SCLK_IN_SPI1 162
+#define PCLK_SPI2 163
+#define CLK_SPI2 164
+#define SCLK_IN_SPI2 165
+#define PCLK_UART1 166
+#define PCLK_UART2 167
+#define PCLK_UART3 168
+#define PCLK_UART4 169
+#define PCLK_UART5 170
+#define PCLK_UART6 171
+#define PCLK_UART7 172
+#define PCLK_UART8 173
+#define PCLK_UART9 174
+#define CLK_UART1_SRC 175
+#define CLK_UART1_FRAC 176
+#define CLK_UART1 177
+#define SCLK_UART1 178
+#define CLK_UART2_SRC 179
+#define CLK_UART2_FRAC 180
+#define CLK_UART2 181
+#define SCLK_UART2 182
+#define CLK_UART3_SRC 183
+#define CLK_UART3_FRAC 184
+#define CLK_UART3 185
+#define SCLK_UART3 186
+#define CLK_UART4_SRC 187
+#define CLK_UART4_FRAC 188
+#define CLK_UART4 189
+#define SCLK_UART4 190
+#define CLK_UART5_SRC 191
+#define CLK_UART5_FRAC 192
+#define CLK_UART5 193
+#define SCLK_UART5 194
+#define CLK_UART6_SRC 195
+#define CLK_UART6_FRAC 196
+#define CLK_UART6 197
+#define SCLK_UART6 198
+#define CLK_UART7_SRC 199
+#define CLK_UART7_FRAC 200
+#define CLK_UART7 201
+#define SCLK_UART7 202
+#define CLK_UART8_SRC 203
+#define CLK_UART8_FRAC 204
+#define CLK_UART8 205
+#define SCLK_UART8 206
+#define CLK_UART9_SRC 207
+#define CLK_UART9_FRAC 208
+#define CLK_UART9 209
+#define SCLK_UART9 210
+#define PCLK_PWM1_PERI 211
+#define CLK_PWM1_PERI 212
+#define CLK_CAPTURE_PWM1_PERI 213
+#define PCLK_PWM2_PERI 214
+#define CLK_PWM2_PERI 215
+#define CLK_CAPTURE_PWM2_PERI 216
+#define PCLK_PWM3_PERI 217
+#define CLK_PWM3_PERI 218
+#define CLK_CAPTURE_PWM3_PERI 219
+#define PCLK_CAN0 220
+#define CLK_CAN0 221
+#define PCLK_CAN1 222
+#define CLK_CAN1 223
+#define ACLK_CRYPTO 224
+#define HCLK_CRYPTO 225
+#define PCLK_CRYPTO 226
+#define CLK_CORE_CRYPTO 227
+#define CLK_PKA_CRYPTO 228
+#define HCLK_KLAD 229
+#define PCLK_KEY_READER 230
+#define HCLK_RK_RNG_NS 231
+#define HCLK_RK_RNG_S 232
+#define HCLK_TRNG_NS 233
+#define HCLK_TRNG_S 234
+#define HCLK_CRYPTO_S 235
+#define PCLK_PERI_WDT 236
+#define TCLK_PERI_WDT 237
+#define ACLK_SYSMEM 238
+#define HCLK_BOOTROM 239
+#define PCLK_PERI_GRF 240
+#define ACLK_DMAC 241
+#define ACLK_RKDMAC 242
+#define PCLK_OTPC_NS 243
+#define CLK_SBPI_OTPC_NS 244
+#define CLK_USER_OTPC_NS 245
+#define PCLK_OTPC_S 246
+#define CLK_SBPI_OTPC_S 247
+#define CLK_USER_OTPC_S 248
+#define CLK_OTPC_ARB 249
+#define PCLK_OTPPHY 250
+#define PCLK_USB2PHY 251
+#define PCLK_PIPEPHY 252
+#define PCLK_SARADC 253
+#define CLK_SARADC 254
+#define PCLK_IOC_VCCIO234 255
+#define PCLK_PERI_GPIO1 256
+#define PCLK_PERI_GPIO2 257
+#define DCLK_PERI_GPIO 258
+#define DCLK_PERI_GPIO1 259
+#define DCLK_PERI_GPIO2 260
+#define ACLK_PHP 261
+#define PCLK_PHP 262
+#define ACLK_PCIE20_MST 263
+#define ACLK_PCIE20_SLV 264
+#define ACLK_PCIE20_DBI 265
+#define PCLK_PCIE20 266
+#define CLK_PCIE20_AUX 267
+#define ACLK_USB3OTG 268
+#define CLK_USB3OTG_SUSPEND 269
+#define CLK_USB3OTG_REF 270
+#define CLK_PIPEPHY_REF_FUNC 271
+#define CLK_200M_PMU 272
+#define CLK_RTC_32K 273
+#define CLK_RTC32K_FRAC 274
+#define BUSCLK_PDPMU0 275
+#define PCLK_PMU0_CRU 276
+#define PCLK_PMU0_PMU 277
+#define CLK_PMU0_PMU 278
+#define PCLK_PMU0_HP_TIMER 279
+#define CLK_PMU0_HP_TIMER 280
+#define CLK_PMU0_32K_HP_TIMER 281
+#define PCLK_PMU0_PVTM 282
+#define CLK_PMU0_PVTM 283
+#define PCLK_IOC_PMUIO 284
+#define PCLK_PMU0_GPIO0 285
+#define DBCLK_PMU0_GPIO0 286
+#define PCLK_PMU0_GRF 287
+#define PCLK_PMU0_SGRF 288
+#define CLK_DDR_FAIL_SAFE 289
+#define PCLK_PMU0_SCRKEYGEN 290
+#define PCLK_PMU1_CRU 291
+#define HCLK_PMU1_MEM 292
+#define PCLK_PMU0_I2C0 293
+#define CLK_PMU0_I2C0 294
+#define PCLK_PMU1_UART0 295
+#define CLK_PMU1_UART0_SRC 296
+#define CLK_PMU1_UART0_FRAC 297
+#define CLK_PMU1_UART0 298
+#define SCLK_PMU1_UART0 299
+#define PCLK_PMU1_SPI0 300
+#define CLK_PMU1_SPI0 301
+#define SCLK_IN_PMU1_SPI0 302
+#define PCLK_PMU1_PWM0 303
+#define CLK_PMU1_PWM0 304
+#define CLK_CAPTURE_PMU1_PWM0 305
+#define CLK_PMU1_WIFI 306
+#define FCLK_PMU1_CM0_CORE 307
+#define CLK_PMU1_CM0_RTC 308
+#define PCLK_PMU1_WDTNS 309
+#define CLK_PMU1_WDTNS 310
+#define PCLK_PMU1_MAILBOX 311
+#define CLK_PIPEPHY_DIV 312
+#define CLK_PIPEPHY_XIN24M 313
+#define CLK_PIPEPHY_REF 314
+#define CLK_24M_SSCSRC 315
+#define CLK_USB2PHY_XIN24M 316
+#define CLK_USB2PHY_REF 317
+#define CLK_MIPIDSIPHY_XIN24M 318
+#define CLK_MIPIDSIPHY_REF 319
+#define ACLK_RGA_PRE 320
+#define HCLK_RGA_PRE 321
+#define ACLK_RGA 322
+#define HCLK_RGA 323
+#define CLK_RGA_CORE 324
+#define ACLK_JDEC 325
+#define HCLK_JDEC 326
+#define ACLK_VDPU_PRE 327
+#define CLK_RKVDEC_HEVC_CA 328
+#define HCLK_VDPU_PRE 329
+#define ACLK_RKVDEC 330
+#define HCLK_RKVDEC 331
+#define CLK_RKVENC_CORE 332
+#define ACLK_VEPU_PRE 333
+#define HCLK_VEPU_PRE 334
+#define ACLK_RKVENC 335
+#define HCLK_RKVENC 336
+#define ACLK_VI 337
+#define HCLK_VI 338
+#define PCLK_VI 339
+#define ACLK_ISP 340
+#define HCLK_ISP 341
+#define CLK_ISP 342
+#define ACLK_VICAP 343
+#define HCLK_VICAP 344
+#define DCLK_VICAP 345
+#define CSIRX0_CLK_DATA 346
+#define CSIRX1_CLK_DATA 347
+#define CSIRX2_CLK_DATA 348
+#define CSIRX3_CLK_DATA 349
+#define PCLK_CSIHOST0 350
+#define PCLK_CSIHOST1 351
+#define PCLK_CSIHOST2 352
+#define PCLK_CSIHOST3 353
+#define PCLK_CSIPHY0 354
+#define PCLK_CSIPHY1 355
+#define ACLK_VO_PRE 356
+#define HCLK_VO_PRE 357
+#define ACLK_VOP 358
+#define HCLK_VOP 359
+#define DCLK_VOP 360
+#define DCLK_VOP1 361
+#define ACLK_CRYPTO_S 362
+#define PCLK_CRYPTO_S 363
+#define CLK_CORE_CRYPTO_S 364
+#define CLK_PKA_CRYPTO_S 365
+
+#define CLK_NR_CLKS (CLK_PKA_CRYPTO_S + 1)
+
+/* soft-reset indices */
+
+/********Name=SOFTRST_CON01,Offset=0x404********/
+#define SRST_A_TOP_BIU 16
+#define SRST_A_TOP_VIO_BIU 17
+#define SRST_REF_PVTPLL_LOGIC 18
+/********Name=SOFTRST_CON03,Offset=0x40C********/
+#define SRST_NCOREPORESET0 48
+#define SRST_NCOREPORESET1 49
+#define SRST_NCOREPORESET2 50
+#define SRST_NCOREPORESET3 51
+#define SRST_NCORESET0 52
+#define SRST_NCORESET1 53
+#define SRST_NCORESET2 54
+#define SRST_NCORESET3 55
+#define SRST_NL2RESET 56
+/********Name=SOFTRST_CON04,Offset=0x410********/
+#define SRST_DAP 73
+#define SRST_P_DBG_DAPLITE 74
+#define SRST_REF_PVTPLL_CORE 77
+/********Name=SOFTRST_CON05,Offset=0x414********/
+#define SRST_A_CORE_BIU 80
+#define SRST_P_CORE_BIU 81
+#define SRST_H_CORE_BIU 82
+/********Name=SOFTRST_CON06,Offset=0x418********/
+#define SRST_A_NPU_BIU 98
+#define SRST_H_NPU_BIU 99
+#define SRST_A_RKNN 100
+#define SRST_H_RKNN 101
+#define SRST_REF_PVTPLL_NPU 102
+/********Name=SOFTRST_CON08,Offset=0x420********/
+#define SRST_A_GPU_BIU 131
+#define SRST_GPU 132
+#define SRST_REF_PVTPLL_GPU 133
+#define SRST_GPU_BRG_BIU 134
+/********Name=SOFTRST_CON09,Offset=0x424********/
+#define SRST_RKVENC_CORE 144
+#define SRST_A_VEPU_BIU 147
+#define SRST_H_VEPU_BIU 148
+#define SRST_A_RKVENC 149
+#define SRST_H_RKVENC 150
+/********Name=SOFTRST_CON10,Offset=0x428********/
+#define SRST_RKVDEC_HEVC_CA 162
+#define SRST_A_VDPU_BIU 165
+#define SRST_H_VDPU_BIU 166
+#define SRST_A_RKVDEC 167
+#define SRST_H_RKVDEC 168
+/********Name=SOFTRST_CON11,Offset=0x42C********/
+#define SRST_A_VI_BIU 179
+#define SRST_H_VI_BIU 180
+#define SRST_P_VI_BIU 181
+#define SRST_ISP 184
+#define SRST_A_VICAP 185
+#define SRST_H_VICAP 186
+#define SRST_D_VICAP 187
+#define SRST_I0_VICAP 188
+#define SRST_I1_VICAP 189
+#define SRST_I2_VICAP 190
+#define SRST_I3_VICAP 191
+/********Name=SOFTRST_CON12,Offset=0x430********/
+#define SRST_P_CSIHOST0 192
+#define SRST_P_CSIHOST1 193
+#define SRST_P_CSIHOST2 194
+#define SRST_P_CSIHOST3 195
+#define SRST_P_CSIPHY0 196
+#define SRST_P_CSIPHY1 197
+/********Name=SOFTRST_CON13,Offset=0x434********/
+#define SRST_A_VO_BIU 211
+#define SRST_H_VO_BIU 212
+#define SRST_A_VOP 214
+#define SRST_H_VOP 215
+#define SRST_D_VOP 216
+#define SRST_D_VOP1 217
+/********Name=SOFTRST_CON14,Offset=0x438********/
+#define SRST_A_RGA_BIU 227
+#define SRST_H_RGA_BIU 228
+#define SRST_A_RGA 230
+#define SRST_H_RGA 231
+#define SRST_RGA_CORE 232
+#define SRST_A_JDEC 233
+#define SRST_H_JDEC 234
+/********Name=SOFTRST_CON15,Offset=0x43C********/
+#define SRST_B_EBK_BIU 242
+#define SRST_P_EBK_BIU 243
+#define SRST_AHB2AXI_EBC 244
+#define SRST_H_EBC 245
+#define SRST_D_EBC 246
+#define SRST_H_EINK 247
+#define SRST_P_EINK 248
+/********Name=SOFTRST_CON16,Offset=0x440********/
+#define SRST_P_PHP_BIU 258
+#define SRST_A_PHP_BIU 259
+#define SRST_P_PCIE20 263
+#define SRST_PCIE20_POWERUP 264
+#define SRST_USB3OTG 266
+/********Name=SOFTRST_CON17,Offset=0x444********/
+#define SRST_PIPEPHY 275
+/********Name=SOFTRST_CON18,Offset=0x448********/
+#define SRST_A_BUS_BIU 291
+#define SRST_H_BUS_BIU 292
+#define SRST_P_BUS_BIU 293
+/********Name=SOFTRST_CON19,Offset=0x44C********/
+#define SRST_P_I2C1 304
+#define SRST_P_I2C2 305
+#define SRST_P_I2C3 306
+#define SRST_P_I2C4 307
+#define SRST_P_I2C5 308
+#define SRST_I2C1 310
+#define SRST_I2C2 311
+#define SRST_I2C3 312
+#define SRST_I2C4 313
+#define SRST_I2C5 314
+/********Name=SOFTRST_CON20,Offset=0x450********/
+#define SRST_BUS_GPIO3 325
+#define SRST_BUS_GPIO4 326
+/********Name=SOFTRST_CON21,Offset=0x454********/
+#define SRST_P_TIMER 336
+#define SRST_TIMER0 337
+#define SRST_TIMER1 338
+#define SRST_TIMER2 339
+#define SRST_TIMER3 340
+#define SRST_TIMER4 341
+#define SRST_TIMER5 342
+#define SRST_P_STIMER 343
+#define SRST_STIMER0 344
+#define SRST_STIMER1 345
+/********Name=SOFTRST_CON22,Offset=0x458********/
+#define SRST_P_WDTNS 352
+#define SRST_WDTNS 353
+#define SRST_P_GRF 354
+#define SRST_P_SGRF 355
+#define SRST_P_MAILBOX 356
+#define SRST_P_INTC 357
+#define SRST_A_BUS_GIC400 358
+#define SRST_A_BUS_GIC400_DEBUG 359
+/********Name=SOFTRST_CON23,Offset=0x45C********/
+#define SRST_A_BUS_SPINLOCK 368
+#define SRST_A_DCF 369
+#define SRST_P_DCF 370
+#define SRST_F_BUS_CM0_CORE 371
+#define SRST_T_BUS_CM0_JTAG 373
+#define SRST_H_ICACHE 376
+#define SRST_H_DCACHE 377
+/********Name=SOFTRST_CON24,Offset=0x460********/
+#define SRST_P_TSADC 384
+#define SRST_TSADC 385
+#define SRST_TSADCPHY 386
+#define SRST_P_DFT2APB 388
+/********Name=SOFTRST_CON25,Offset=0x464********/
+#define SRST_A_GMAC 401
+#define SRST_P_APB2ASB_VCCIO156 405
+#define SRST_P_DSIPHY 408
+#define SRST_P_DSITX 409
+#define SRST_P_CPU_EMA_DET 410
+#define SRST_P_HASH 411
+#define SRST_P_TOPCRU 415
+/********Name=SOFTRST_CON26,Offset=0x468********/
+#define SRST_P_ASB2APB_VCCIO156 416
+#define SRST_P_IOC_VCCIO156 417
+#define SRST_P_GPIO3_VCCIO156 418
+#define SRST_P_GPIO4_VCCIO156 419
+#define SRST_P_SARADC_VCCIO156 420
+#define SRST_SARADC_VCCIO156 421
+#define SRST_SARADC_VCCIO156_PHY 422
+/********Name=SOFTRST_CON27,Offset=0x46c********/
+#define SRST_A_MAC100 433
+
+/* (0x10200 - 0x400) / 4 * 16 = 260096 */
+/********Name=PMU0SOFTRST_CON00,Offset=0x10200********/
+#define SRST_P_PMU0_CRU 260096
+#define SRST_P_PMU0_PMU 260097
+#define SRST_PMU0_PMU 260098
+#define SRST_P_PMU0_HP_TIMER 260099
+#define SRST_PMU0_HP_TIMER 260100
+#define SRST_PMU0_32K_HP_TIMER 260101
+#define SRST_P_PMU0_PVTM 260102
+#define SRST_PMU0_PVTM 260103
+#define SRST_P_IOC_PMUIO 260104
+#define SRST_P_PMU0_GPIO0 260105
+#define SRST_PMU0_GPIO0 260106
+#define SRST_P_PMU0_GRF 260107
+#define SRST_P_PMU0_SGRF 260108
+/********Name=PMU0SOFTRST_CON01,Offset=0x10204********/
+#define SRST_DDR_FAIL_SAFE 260112
+#define SRST_P_PMU0_SCRKEYGEN 260113
+/********Name=PMU0SOFTRST_CON02,Offset=0x10208********/
+#define SRST_P_PMU0_I2C0 260136
+#define SRST_PMU0_I2C0 260137
+
+/* (0x18200 - 0x400) / 4 * 16 = 391168 */
+/********Name=PMU1SOFTRST_CON00,Offset=0x18200********/
+#define SRST_P_PMU1_CRU 391168
+#define SRST_H_PMU1_MEM 391170
+#define SRST_H_PMU1_BIU 391171
+#define SRST_P_PMU1_BIU 391172
+#define SRST_P_PMU1_UART0 391175
+#define SRST_S_PMU1_UART0 391178
+/********Name=PMU1SOFTRST_CON01,Offset=0x18204********/
+#define SRST_P_PMU1_SPI0 391184
+#define SRST_PMU1_SPI0 391185
+#define SRST_P_PMU1_PWM0 391187
+#define SRST_PMU1_PWM0 391188
+/********Name=PMU1SOFTRST_CON02,Offset=0x18208********/
+#define SRST_F_PMU1_CM0_CORE 391200
+#define SRST_T_PMU1_CM0_JTAG 391202
+#define SRST_P_PMU1_WDTNS 391203
+#define SRST_PMU1_WDTNS 391204
+#define SRST_PMU1_MAILBOX 391208
+
+/* (0x20200 - 0x400) / 4 * 16 = 522240 */
+/********Name=DDRSOFTRST_CON00,Offset=0x20200********/
+#define SRST_MSCH_BRG_BIU 522244
+#define SRST_P_MSCH_BIU 522245
+#define SRST_P_DDR_HWLP 522246
+#define SRST_P_DDR_PHY 522248
+#define SRST_P_DDR_DFICTL 522249
+#define SRST_P_DDR_DMA2DDR 522250
+/********Name=DDRSOFTRST_CON01,Offset=0x20204********/
+#define SRST_P_DDR_MON 522256
+#define SRST_TM_DDR_MON 522257
+#define SRST_P_DDR_GRF 522258
+#define SRST_P_DDR_CRU 522259
+#define SRST_P_SUBDDR_CRU 522260
+
+/* (0x28200 - 0x400) / 4 * 16 = 653312 */
+/********Name=SUBDDRSOFTRST_CON00,Offset=0x28200********/
+#define SRST_MSCH_BIU 653313
+#define SRST_DDR_PHY 653316
+#define SRST_DDR_DFICTL 653317
+#define SRST_DDR_SCRAMBLE 653318
+#define SRST_DDR_MON 653319
+#define SRST_A_DDR_SPLIT 653320
+#define SRST_DDR_DMA2DDR 653321
+
+/* (0x30400 - 0x400) / 4 * 16 = 786432 */
+/********Name=PERISOFTRST_CON01,Offset=0x30404********/
+#define SRST_A_PERI_BIU 786451
+#define SRST_H_PERI_BIU 786452
+#define SRST_P_PERI_BIU 786453
+#define SRST_P_PERICRU 786454
+/********Name=PERISOFTRST_CON02,Offset=0x30408********/
+#define SRST_H_SAI0_8CH 786464
+#define SRST_M_SAI0_8CH 786467
+#define SRST_H_SAI1_8CH 786469
+#define SRST_M_SAI1_8CH 786472
+#define SRST_H_SAI2_2CH 786474
+#define SRST_M_SAI2_2CH 786477
+/********Name=PERISOFTRST_CON03,Offset=0x3040C********/
+#define SRST_H_DSM 786481
+#define SRST_DSM 786482
+#define SRST_H_PDM 786484
+#define SRST_M_PDM 786485
+#define SRST_H_SPDIF 786488
+#define SRST_M_SPDIF 786491
+/********Name=PERISOFTRST_CON04,Offset=0x30410********/
+#define SRST_H_SDMMC0 786496
+#define SRST_H_SDMMC1 786498
+#define SRST_H_EMMC 786504
+#define SRST_A_EMMC 786505
+#define SRST_C_EMMC 786506
+#define SRST_B_EMMC 786507
+#define SRST_T_EMMC 786508
+#define SRST_S_SFC 786509
+#define SRST_H_SFC 786510
+/********Name=PERISOFTRST_CON05,Offset=0x30414********/
+#define SRST_H_USB2HOST 786512
+#define SRST_H_USB2HOST_ARB 786513
+#define SRST_USB2HOST_UTMI 786514
+/********Name=PERISOFTRST_CON06,Offset=0x30418********/
+#define SRST_P_SPI1 786528
+#define SRST_SPI1 786529
+#define SRST_P_SPI2 786531
+#define SRST_SPI2 786532
+/********Name=PERISOFTRST_CON07,Offset=0x3041C********/
+#define SRST_P_UART1 786544
+#define SRST_P_UART2 786545
+#define SRST_P_UART3 786546
+#define SRST_P_UART4 786547
+#define SRST_P_UART5 786548
+#define SRST_P_UART6 786549
+#define SRST_P_UART7 786550
+#define SRST_P_UART8 786551
+#define SRST_P_UART9 786552
+#define SRST_S_UART1 786555
+#define SRST_S_UART2 786558
+/********Name=PERISOFTRST_CON08,Offset=0x30420********/
+#define SRST_S_UART3 786561
+#define SRST_S_UART4 786564
+#define SRST_S_UART5 786567
+#define SRST_S_UART6 786570
+#define SRST_S_UART7 786573
+/********Name=PERISOFTRST_CON09,Offset=0x30424********/
+#define SRST_S_UART8 786576
+#define SRST_S_UART9 786579
+/********Name=PERISOFTRST_CON10,Offset=0x30428********/
+#define SRST_P_PWM1_PERI 786592
+#define SRST_PWM1_PERI 786593
+#define SRST_P_PWM2_PERI 786595
+#define SRST_PWM2_PERI 786596
+#define SRST_P_PWM3_PERI 786598
+#define SRST_PWM3_PERI 786599
+/********Name=PERISOFTRST_CON11,Offset=0x3042C********/
+#define SRST_P_CAN0 786608
+#define SRST_CAN0 786609
+#define SRST_P_CAN1 786610
+#define SRST_CAN1 786611
+/********Name=PERISOFTRST_CON12,Offset=0x30430********/
+#define SRST_A_CRYPTO 786624
+#define SRST_H_CRYPTO 786625
+#define SRST_P_CRYPTO 786626
+#define SRST_CORE_CRYPTO 786627
+#define SRST_PKA_CRYPTO 786628
+#define SRST_H_KLAD 786629
+#define SRST_P_KEY_READER 786630
+#define SRST_H_RK_RNG_NS 786631
+#define SRST_H_RK_RNG_S 786632
+#define SRST_H_TRNG_NS 786633
+#define SRST_H_TRNG_S 786634
+#define SRST_H_CRYPTO_S 786635
+/********Name=PERISOFTRST_CON13,Offset=0x30434********/
+#define SRST_P_PERI_WDT 786640
+#define SRST_T_PERI_WDT 786641
+#define SRST_A_SYSMEM 786642
+#define SRST_H_BOOTROM 786643
+#define SRST_P_PERI_GRF 786644
+#define SRST_A_DMAC 786645
+#define SRST_A_RKDMAC 786646
+/********Name=PERISOFTRST_CON14,Offset=0x30438********/
+#define SRST_P_OTPC_NS 786656
+#define SRST_SBPI_OTPC_NS 786657
+#define SRST_USER_OTPC_NS 786658
+#define SRST_P_OTPC_S 786659
+#define SRST_SBPI_OTPC_S 786660
+#define SRST_USER_OTPC_S 786661
+#define SRST_OTPC_ARB 786662
+#define SRST_P_OTPPHY 786663
+#define SRST_OTP_NPOR 786664
+/********Name=PERISOFTRST_CON15,Offset=0x3043C********/
+#define SRST_P_USB2PHY 786672
+#define SRST_USB2PHY_POR 786676
+#define SRST_USB2PHY_OTG 786677
+#define SRST_USB2PHY_HOST 786678
+#define SRST_P_PIPEPHY 786679
+/********Name=PERISOFTRST_CON16,Offset=0x30440********/
+#define SRST_P_SARADC 786692
+#define SRST_SARADC 786693
+#define SRST_SARADC_PHY 786694
+#define SRST_P_IOC_VCCIO234 786700
+/********Name=PERISOFTRST_CON17,Offset=0x30444********/
+#define SRST_P_PERI_GPIO1 786704
+#define SRST_P_PERI_GPIO2 786705
+#define SRST_PERI_GPIO1 786706
+#define SRST_PERI_GPIO2 786707
+
+#endif
diff --git a/u-boot/include/dt-bindings/display/rockchip-tve.h b/u-boot/include/dt-bindings/display/rockchip-tve.h
new file mode 100644
index 0000000..d72d692
--- /dev/null
+++ b/u-boot/include/dt-bindings/display/rockchip-tve.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
+ */
+
+
+#ifndef _DT_BINDINGS_ROCKCHIP_TVE_H
+#define _DT_BINDINGS_ROCKCHIP_TVE_H
+
+/* tve dclk upsample mode */
+#define DCLK_UPSAMPLEx1 0
+#define DCLK_UPSAMPLEx2 1
+#define DCLK_UPSAMPLEx4 2
+
+#endif
diff --git a/u-boot/include/dt-bindings/power/rk3528-power.h b/u-boot/include/dt-bindings/power/rk3528-power.h
new file mode 100644
index 0000000..4f7c978
--- /dev/null
+++ b/u-boot/include/dt-bindings/power/rk3528-power.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+#ifndef __DT_BINDINGS_POWER_RK3528_POWER_H__
+#define __DT_BINDINGS_POWER_RK3528_POWER_H__
+
+/*
+ * RK3528 idle id Summary.
+ */
+#define RK3528_PD_PMU 0
+#define RK3528_PD_BUS 1
+#define RK3528_PD_DDR 2
+#define RK3528_PD_MSCH 3
+#define RK3528_PD_GPU 4
+#define RK3528_PD_RKVDEC 5
+#define RK3528_PD_RKVENC 6
+#define RK3528_PD_VO 7
+#define RK3528_PD_VPU 8
+
+#endif
diff --git a/u-boot/include/dt-bindings/power/rk3562-power.h b/u-boot/include/dt-bindings/power/rk3562-power.h
new file mode 100644
index 0000000..ed57c40
--- /dev/null
+++ b/u-boot/include/dt-bindings/power/rk3562-power.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_BINDINGS_POWER_RK3562_POWER_H__
+#define __DT_BINDINGS_POWER_RK3562_POWER_H__
+
+/* VD_CORE */
+#define RK3562_PD_CPU_0 0
+#define RK3562_PD_CPU_1 1
+#define RK3562_PD_CPU_2 2
+#define RK3562_PD_CPU_3 3
+#define RK3562_PD_CORE_ALIVE 4
+
+/* VD_PMU */
+#define RK3562_PD_PMU 5
+#define RK3562_PD_PMU_ALIVE 6
+
+/* VD_NPU */
+#define RK3562_PD_NPU 7
+
+/* VD_GPU */
+#define RK3562_PD_GPU 8
+
+/* VD_LOGIC */
+#define RK3562_PD_DDR 9
+#define RK3562_PD_VEPU 10
+#define RK3562_PD_VDPU 11
+#define RK3562_PD_VI 12
+#define RK3562_PD_VO 13
+#define RK3562_PD_RGA 14
+#define RK3562_PD_EBK 15
+#define RK3562_PD_PHP 16
+#define RK3562_PD_LOGIC_ALIVE 17
+
+#endif
diff --git a/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h b/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h
index 1436e1d..ec4e5dd 100644
--- a/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h
+++ b/u-boot/include/dt-bindings/soc/rockchip,boot-mode.h
@@ -20,5 +20,7 @@
#define BOOT_CHARGING (REBOOT_FLAG + 11)
/* enter usb mass storage mode */
#define BOOT_UMS (REBOOT_FLAG + 12)
+/* reboot system quiescent */
+#define BOOT_QUIESCENT (REBOOT_FLAG + 14)
#endif
diff --git a/u-boot/include/dt-bindings/suspend/rockchip-rk3528.h b/u-boot/include/dt-bindings/suspend/rockchip-rk3528.h
new file mode 100644
index 0000000..7f81bf8
--- /dev/null
+++ b/u-boot/include/dt-bindings/suspend/rockchip-rk3528.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Header providing constants for Rockchip suspend bindings.
+ *
+ * Copyright (C) 2022, Rockchip Electronics Co., Ltd
+ * Author: XiaoDong.Huang
+ */
+
+#ifndef __DT_BINDINGS_RK3528_PM_H__
+#define __DT_BINDINGS_RK3528_PM_H__
+/******************************bits ops************************************/
+
+#ifndef BIT
+#define BIT(nr) (1 << (nr))
+#endif
+
+#define RKPM_SLP_ARMPD BIT(0)
+#define RKPM_SLP_ARMOFF BIT(1)
+#define RKPM_SLP_ARMOFF_DDRPD BIT(2)
+#define RKPM_SLP_ARMOFF_LOGOFF BIT(3)
+
+/* all plls except ddr's pll*/
+#define RKPM_SLP_PMU_HW_PLLS_PD BIT(8)
+#define RKPM_SLP_PMU_PMUALIVE_32K BIT(9)
+#define RKPM_SLP_PMU_DIS_OSC BIT(10)
+
+#define RKPM_SLP_CLK_GT BIT(16)
+#define RKPM_SLP_PMIC_LP BIT(17)
+
+#define RKPM_SLP_32K_EXT BIT(24)
+#define RKPM_SLP_TIME_OUT_WKUP BIT(25)
+#define RKPM_SLP_PMU_DBG BIT(26)
+
+/* the wake up source */
+#define RKPM_CPU0_WKUP_EN BIT(0)
+#define RKPM_CPU1_WKUP_EN BIT(1)
+#define RKPM_CPU2_WKUP_EN BIT(2)
+#define RKPM_CPU3_WKUP_EN BIT(3)
+#define RKPM_GPIO_WKUP_EN BIT(4)
+#define RKPM_HDMI_HDP_WKUP_EN BIT(5)
+#define RKPM_HDMI_CEC_WKUP_EN BIT(6)
+#define RKPM_PWMIR_WKUP_EN BIT(7)
+#define RKPM_GMAC_WKUP_EN BIT(8)
+#define RKPM_TIMER_WKUP_EN BIT(9)
+#define RKPM_USBDEV_WKUP_EN BIT(10)
+#define RKPM_SYSINT_WKUP_EN BIT(11)
+#define RKPM_TIME_OUT_WKUP_EN BIT(12)
+
+/* the pwm regulator */
+#define RKPM_PWM0_M0_REGULATOR_EN BIT(0)
+#define RKPM_PWM1_M0_REGULATOR_EN BIT(1)
+#define RKPM_PWM2_M0_REGULATOR_EN BIT(2)
+
+#endif
diff --git a/u-boot/include/edid.h b/u-boot/include/edid.h
index 6cfc308..0967912 100644
--- a/u-boot/include/edid.h
+++ b/u-boot/include/edid.h
@@ -882,6 +882,38 @@
u32 fps;
};
+struct csc_info {
+ u16 hue;
+ u16 saturation;
+ u16 contrast;
+ u16 brightness;
+ u16 r_gain;
+ u16 g_gain;
+ u16 b_gain;
+ u16 r_offset;
+ u16 g_offset;
+ u16 b_offset;
+ u16 csc_enable;
+};
+
+
+#define ACM_GAIN_LUT_HY_LENGTH (9*17)
+#define ACM_GAIN_LUT_HY_TOTAL_LENGTH (ACM_GAIN_LUT_HY_LENGTH * 3)
+#define ACM_GAIN_LUT_HS_LENGTH (13*17)
+#define ACM_GAIN_LUT_HS_TOTAL_LENGTH (ACM_GAIN_LUT_HS_LENGTH * 3)
+#define ACM_DELTA_LUT_H_LENGTH 65
+#define ACM_DELTA_LUT_H_TOTAL_LENGTH (ACM_DELTA_LUT_H_LENGTH * 3)
+
+struct acm_data {
+ s16 delta_lut_h[ACM_DELTA_LUT_H_TOTAL_LENGTH];
+ s16 gain_lut_hy[ACM_GAIN_LUT_HY_TOTAL_LENGTH];
+ s16 gain_lut_hs[ACM_GAIN_LUT_HS_TOTAL_LENGTH];
+ u16 y_gain;
+ u16 h_gain;
+ u16 s_gain;
+ u16 acm_enable;
+};
+
struct base2_disp_info {
char disp_head_flag[6];
struct base2_screen_info screen_info[4];
@@ -890,8 +922,15 @@
struct base2_gamma_lut_data gamma_lut_data;
struct base2_cubic_lut_data cubic_lut_data;
struct framebuffer_info framebuffer_info;
- u32 reserved[244];
+ u32 cacm_header;
+ u32 reserved[243];
u32 crc;
+ /* baseparameter version 3.0 add */
+ struct csc_info csc_info;
+ struct acm_data acm_data;
+ u8 resv2[10*1024]; /* */
+ u32 crc2;
+ /* baseparameter version 3.0 add */
};
struct base2_disp_header {
diff --git a/u-boot/include/image.h b/u-boot/include/image.h
index 449bd36..88009cc 100644
--- a/u-boot/include/image.h
+++ b/u-boot/include/image.h
@@ -703,6 +703,7 @@
bootm_headers_t *images,
char **of_flat_tree, ulong *of_size);
void boot_fdt_add_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
+void boot_mem_rsv_regions(struct lmb *lmb, void *fdt_blob);
#ifdef CONFIG_SYSMEM
int boot_fdt_add_sysmem_rsv_regions(void *fdt_blob);
#else
@@ -1347,9 +1348,13 @@
#endif /* CONFIG_FIT */
#if defined(CONFIG_ANDROID_BOOT_IMAGE)
+#include <android_image.h>
+
struct andr_img_hdr;
u32 android_bcb_msg_sector_offset(void);
-u32 android_image_major_version(void);
+int android_image_init_resource(struct blk_desc *desc,
+ disk_partition_t *out_part,
+ ulong *out_blk_offset);
int android_image_check_header(const struct andr_img_hdr *hdr);
int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
ulong *os_data, ulong *os_len);
@@ -1368,6 +1373,10 @@
struct andr_img_hdr *populate_andr_img_hdr(struct blk_desc *dev_desc,
disk_partition_t *part_boot);
+int populate_boot_info(const struct boot_img_hdr_v34 *boot_hdr,
+ const struct vendor_boot_img_hdr_v34 *vendor_boot_hdr,
+ const struct boot_img_hdr_v34 *init_boot_hdr,
+ struct andr_img_hdr *hdr, bool save_hdr);
/** android_image_load - Load an Android Image from storage.
*
@@ -1392,6 +1401,9 @@
int android_image_load_by_partname(struct blk_desc *dev_desc,
const char *boot_partname,
unsigned long *load_address);
+
+int android_image_verify_resource(const char *boot_part, ulong *resc_buf);
+
#endif /* CONFIG_ANDROID_BOOT_IMAGE */
int bootm_parse_comp(const unsigned char *hdr);
diff --git a/u-boot/include/irq-platform.h b/u-boot/include/irq-platform.h
index 222d5c7..53516fc 100644
--- a/u-boot/include/irq-platform.h
+++ b/u-boot/include/irq-platform.h
@@ -241,6 +241,46 @@
#define IRQ_GPIO3 69
#define IRQ_GPIO4 70
+#elif defined(CONFIG_ROCKCHIP_RK3528)
+#define GPIO0_PHYS 0xff610000
+#define GPIO1_PHYS 0xffaf0000
+#define GPIO2_PHYS 0xffb00000
+#define GPIO3_PHYS 0xffb10000
+#define GPIO4_PHYS 0xffb20000
+
+#define GIC_IRQS_NR (5 * 32)
+#define GPIO_IRQS_NR (5 * 32)
+
+#define GPIO_BANK_NUM 5
+#define GPIO_BANK_PINS 32
+
+#define IRQ_TIMER0 63
+#define IRQ_GPIO0 103
+#define IRQ_GPIO1 105
+#define IRQ_GPIO2 107
+#define IRQ_GPIO3 108
+#define IRQ_GPIO4 110
+
+#elif defined(CONFIG_ROCKCHIP_RK3562)
+#define GPIO0_PHYS 0xff260000
+#define GPIO1_PHYS 0xff620000
+#define GPIO2_PHYS 0xff630000
+#define GPIO3_PHYS 0xffac0000
+#define GPIO4_PHYS 0xffad0000
+
+#define GIC_IRQS_NR (5 * 32)
+#define GPIO_IRQS_NR (5 * 32)
+
+#define GPIO_BANK_NUM 5
+#define GPIO_BANK_PINS 32
+
+#define IRQ_TIMER0 77
+#define IRQ_GPIO0 32
+#define IRQ_GPIO1 34
+#define IRQ_GPIO2 36
+#define IRQ_GPIO3 38
+#define IRQ_GPIO4 40
+
#elif defined(CONFIG_ROCKCHIP_RK3568)
#define GPIO0_PHYS 0xfdd60000
#define GPIO1_PHYS 0xfe740000
diff --git a/u-boot/include/key.h b/u-boot/include/key.h
index 7a9f9e4..0ccf7b1 100644
--- a/u-boot/include/key.h
+++ b/u-boot/include/key.h
@@ -33,9 +33,10 @@
/* ADC key */
u8 channel;
- u32 adcval;
- u32 min;
- u32 max;
+ int in_volt;
+ int center;
+ int min;
+ int max;
/* GPIO key */
u32 irq;
diff --git a/u-boot/include/linux/dw_hdmi.h b/u-boot/include/linux/dw_hdmi.h
index 18433ea..3d15ead 100644
--- a/u-boot/include/linux/dw_hdmi.h
+++ b/u-boot/include/linux/dw_hdmi.h
@@ -92,6 +92,7 @@
RK3366_HDMI,
RK3368_HDMI,
RK3399_HDMI,
+ RK3528_HDMI,
RK3568_HDMI,
};
@@ -177,7 +178,7 @@
const struct dw_hdmi_mpll_config *mpll_cfg;
const struct dw_hdmi_mpll_config *mpll_cfg_420;
const struct dw_hdmi_curr_ctrl *cur_ctr;
- const struct dw_hdmi_phy_config *phy_config;
+ struct dw_hdmi_phy_config *phy_config;
int (*configure_phy)(struct dw_hdmi *hdmi,
const struct dw_hdmi_plat_data *pdata,
unsigned long mpixelclock);
diff --git a/u-boot/include/linux/mtd/mtd.h b/u-boot/include/linux/mtd/mtd.h
index b848c0d..c5c9c41 100644
--- a/u-boot/include/linux/mtd/mtd.h
+++ b/u-boot/include/linux/mtd/mtd.h
@@ -551,30 +551,6 @@
}
#endif
-#ifdef __UBOOT__
-/*
- * Debugging macro and defines
- */
-#define MTD_DEBUG_LEVEL0 (0) /* Quiet */
-#define MTD_DEBUG_LEVEL1 (1) /* Audible */
-#define MTD_DEBUG_LEVEL2 (2) /* Loud */
-#define MTD_DEBUG_LEVEL3 (3) /* Noisy */
-
-#ifdef CONFIG_MTD_DEBUG
-#define MTDDEBUG(n, args...) \
- do { \
- if (n <= CONFIG_MTD_DEBUG_VERBOSE) \
- printk(KERN_INFO args); \
- } while(0)
-#else /* CONFIG_MTD_DEBUG */
-#define MTDDEBUG(n, args...) \
- do { \
- if (0) \
- printk(KERN_INFO args); \
- } while(0)
-#endif /* CONFIG_MTD_DEBUG */
-#endif
-
static inline int mtd_is_bitflip(int err) {
return err == -EUCLEAN;
}
diff --git a/u-boot/include/linux/mtd/spinand.h b/u-boot/include/linux/mtd/spinand.h
index 99024f7..cc905f8 100644
--- a/u-boot/include/linux/mtd/spinand.h
+++ b/u-boot/include/linux/mtd/spinand.h
@@ -252,6 +252,7 @@
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
extern const struct spinand_manufacturer dosilicon_spinand_manufacturer;
extern const struct spinand_manufacturer esmt_spinand_manufacturer;
+extern const struct spinand_manufacturer xincun_spinand_manufacturer;
extern const struct spinand_manufacturer xtx_spinand_manufacturer;
extern const struct spinand_manufacturer hyf_spinand_manufacturer;
extern const struct spinand_manufacturer fmsh_spinand_manufacturer;
@@ -262,6 +263,7 @@
extern const struct spinand_manufacturer silicongo_spinand_manufacturer;
extern const struct spinand_manufacturer unim_spinand_manufacturer;
extern const struct spinand_manufacturer skyhigh_spinand_manufacturer;
+extern const struct spinand_manufacturer gsto_spinand_manufacturer;
/**
* struct spinand_op_variants - SPI NAND operation variants
diff --git a/u-boot/include/max96745.h b/u-boot/include/max96745.h
index b69e011..2eb0450 100644
--- a/u-boot/include/max96745.h
+++ b/u-boot/include/max96745.h
@@ -17,6 +17,21 @@
#define RESET_ALL BIT(7)
#define SLEEP BIT(3)
+/* 0011h */
+#define CXTP_B BIT(2)
+#define CXTP_A BIT(0)
+
+/* 0028h, 0032h */
+#define LINK_EN BIT(7)
+#define TX_RATE GENMASK(3, 2)
+
+/* 0029h, 0033h */
+#define RESET_LINK BIT(0)
+#define RESET_ONESHOT BIT(1)
+
+/* 002Ah, 0034h */
+#define LINK_LOCKED BIT(0)
+
/* 0076h, 0086h */
#define DIS_REM_CC BIT(7)
diff --git a/u-boot/include/max96752f.h b/u-boot/include/max96752f.h
deleted file mode 100644
index cda7291..0000000
--- a/u-boot/include/max96752f.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * (C) Copyright 2022 Rockchip Electronics Co., Ltd
- */
-
-#ifndef _MAX96752F_H_
-#define _MAX96752F_H_
-
-#include <linux/bitfield.h>
-
-#define GPIO_A_REG(gpio) (0x0200 + ((gpio) * 3))
-#define GPIO_B_REG(gpio) (0x0201 + ((gpio) * 3))
-#define GPIO_C_REG(gpio) (0x0202 + ((gpio) * 3))
-#define OLDI_REG(x) (0x01cd + (x))
-
-/* 0002h */
-#define AUD_TX_EN BIT(2)
-
-/* 0010h */
-#define RESET_ALL BIT(7)
-#define RESET_LINK BIT(6)
-#define RESET_ONESHOT BIT(5)
-#define AUTO_LINK BIT(4)
-#define SLEEP BIT(3)
-#define LINK_CFG GENMASK(1, 0)
-
-/* 0050h */
-#define STR_SEL GENMASK(1, 0)
-
-/* 0073h */
-#define TX_SRC_ID GENMASK(2, 0)
-
-/* 0140h */
-#define AUD_RX_EN BIT(0)
-
-/* 0200h */
-#define RES_CFG BIT(7)
-#define TX_PRIO BIT(6)
-#define TX_COMP_EN BIT(5)
-#define GPIO_OUT BIT(4)
-#define GPIO_IN BIT(3)
-#define GPIO_RX_EN BIT(2)
-#define GPIO_TX_EN BIT(1)
-#define GPIO_OUT_DIS BIT(0)
-
-/* 0201h */
-#define PULL_UPDN_SEL GENMASK(7, 6)
-#define OUT_TYPE BIT(5)
-#define GPIO_TX_ID GENMASK(4, 0)
-
-/* 0202h */
-#define OVR_RES_CFG BIT(7)
-#define GPIO_RX_ID GENMASK(4, 0)
-
-/* 01CEh */
-#define OLDI_OUTSEL BIT(7)
-#define OLDI_FORMAT BIT(6)
-#define OLDI_4TH_LANE BIT(5)
-#define OLDI_SWAP_AB BIT(4)
-#define OLDI_SPL_EN BIT(3)
-#define OLDI_SPL_MODE GENMASK(2, 1)
-#define OLDI_SPL_POL BIT(0)
-
-void max96752f_init(struct udevice *dev);
-
-#endif
diff --git a/u-boot/include/max96755f.h b/u-boot/include/max96755f.h
index deea4ce..de33ab6 100644
--- a/u-boot/include/max96755f.h
+++ b/u-boot/include/max96755f.h
@@ -181,6 +181,7 @@
struct drm_display_mode mode;
u32 num_lanes;
struct gpio_desc lock_gpio;
+ u32 dsi_lane_map[4];
};
#endif
diff --git a/u-boot/include/mmc.h b/u-boot/include/mmc.h
index 0d23e40..45b77ec 100644
--- a/u-boot/include/mmc.h
+++ b/u-boot/include/mmc.h
@@ -192,6 +192,8 @@
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
@@ -231,6 +233,7 @@
#define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
#define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
#define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_STROBE BIT(7) /* Enhanced strobe mode */
#define EXT_CSD_TIMING_BC 0 /* Backwards compatility */
#define EXT_CSD_TIMING_HS 1 /* High speed */
@@ -470,6 +473,8 @@
* @return 0 if write-enabled, 1 if write-protected, -ve on error
*/
int (*execute_tuning)(struct udevice *dev, u32 opcode);
+ /* set_enhanced_strobe() - set HS400 enhanced strobe */
+ int (*set_enhanced_strobe)(struct udevice *dev);
};
#define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
@@ -487,6 +492,7 @@
int mmc_getcd(struct mmc *mmc);
int mmc_getwp(struct mmc *mmc);
+int mmc_set_enhanced_strobe(struct mmc *mmc);
#else
struct mmc_ops {
bool (*card_busy)(struct mmc *mmc);
@@ -511,6 +517,7 @@
uint f_max;
uint b_max;
unsigned char part_type;
+ u8 fixed_drv_type;
};
struct sd_ssr {
@@ -598,6 +605,7 @@
#if CONFIG_IS_ENABLED(DM_MMC)
struct udevice *dev; /* Device for this MMC controller */
#endif
+ u8 raw_driver_strength;
};
struct mmc_hwpart_conf {
@@ -785,5 +793,7 @@
*/
void mmc_gpio_init_direct(void);
+#define mmc_driver_type_mask(n) (1 << (n))
+
#endif /* _MMC_H_ */
diff --git a/u-boot/include/mp_boot.h b/u-boot/include/mp_boot.h
new file mode 100644
index 0000000..44a16c6
--- /dev/null
+++ b/u-boot/include/mp_boot.h
@@ -0,0 +1,25 @@
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _MP_BOOT_H_
+#define _MP_BOOT_H_
+
+#include <spl.h>
+
+struct task_data {
+ struct spl_load_info info;
+
+ /* to be filled by smp task */
+ void *boot_addr;
+ ulong boot_size;
+};
+
+void mpb_init_1(struct spl_load_info info);
+void mpb_init_x(int evt);
+ulong mpb_post(int evt);
+
+#endif
+
diff --git a/u-boot/include/power/rk8xx_pmic.h b/u-boot/include/power/rk8xx_pmic.h
index aa51e88..84d1104 100644
--- a/u-boot/include/power/rk8xx_pmic.h
+++ b/u-boot/include/power/rk8xx_pmic.h
@@ -206,6 +206,7 @@
#define RK817_ID_LSB 0xee
#define RK8XX_ID_MSK 0xfff0
+#define RK817_PMIC_CHRG_TERM 0xe6
#define RK817_PMIC_SYS_CFG1 0xf1
#define RK817_PMIC_SYS_CFG3 0xf4
#define RK817_GPIO_INT_CFG 0xfe
@@ -287,6 +288,7 @@
uint8_t sleep_pin;
uint8_t rst_fun;
int not_save_power_en;
+ int sys_can_sd;
};
int rk8xx_spl_configure_buck(struct udevice *pmic, int buck, int uvolt);
diff --git a/u-boot/include/rk_timer_irq.h b/u-boot/include/rk_timer_irq.h
index 44fc395..69f9ee3 100644
--- a/u-boot/include/rk_timer_irq.h
+++ b/u-boot/include/rk_timer_irq.h
@@ -66,6 +66,12 @@
#elif defined(CONFIG_ROCKCHIP_RV1126)
#define TIMER_BASE (0xFF660000 + 0x20) /* TIMER 1 */
#define TIMER_IRQ IRQ_TIMER1
+#elif defined(CONFIG_ROCKCHIP_RK3528)
+#define TIMER_BASE (0xFFAB0000 + 0x00) /* TIMER 0 */
+#define TIMER_IRQ IRQ_TIMER0
+#elif defined(CONFIG_ROCKCHIP_RK3562)
+#define TIMER_BASE (0xFFA50000 + 0x00) /* TIMER 0 */
+#define TIMER_IRQ IRQ_TIMER0
#elif defined(CONFIG_ROCKCHIP_RK3568)
/* Only timer0 can wakeup system suspend */
#define TIMER_BASE (0xFE5F0000 + 0x00) /* TIMER 1 */
diff --git a/u-boot/include/rockchip/crypto_v2.h b/u-boot/include/rockchip/crypto_v2.h
index 9469266..41d1e83 100644
--- a/u-boot/include/rockchip/crypto_v2.h
+++ b/u-boot/include/rockchip/crypto_v2.h
@@ -564,7 +564,7 @@
#define LLI_DMA_CTRL_DST_DONE _BIT(9)
#define LLI_DMA_CTRL_SRC_DONE _BIT(10)
-#define LLI_USER_CPIHER_START _BIT(0)
+#define LLI_USER_CIPHER_START _BIT(0)
#define LLI_USER_STRING_START _BIT(1)
#define LLI_USER_STRING_LAST _BIT(2)
#define LLI_USER_STRING_AAD _BIT(3)
diff --git a/u-boot/include/scsi.h b/u-boot/include/scsi.h
index 7173912..23a275f 100644
--- a/u-boot/include/scsi.h
+++ b/u-boot/include/scsi.h
@@ -7,6 +7,9 @@
#ifndef _SCSI_H
#define _SCSI_H
+#include <asm/cache.h>
+#include <linux/dma-direction.h>
+
struct scsi_cmd {
unsigned char cmd[16]; /* command */
/* for request sense */
@@ -27,6 +30,7 @@
unsigned long trans_bytes; /* tranfered bytes */
unsigned int priv;
+ enum dma_data_direction dma_dir;
};
/*-----------------------------------------------------------
diff --git a/u-boot/include/sdhci.h b/u-boot/include/sdhci.h
index 354f1e7..ebbca24 100644
--- a/u-boot/include/sdhci.h
+++ b/u-boot/include/sdhci.h
@@ -256,6 +256,18 @@
void (*set_ios_post)(struct sdhci_host *host);
int (*set_clock)(struct sdhci_host *host, unsigned int clock);
void (*set_clock_ext)(struct sdhci_host *host, u32 div);
+
+ /**
+ * set_enhanced_strobe() - Set HS400 Enhanced Strobe config
+ *
+ * This is called after setting the card speed and mode to
+ * HS400 ES, and should set any host-specific configuration
+ * necessary for it.
+ *
+ * @host: SDHCI host structure
+ * Return: 0 if successful, -ve on error
+ */
+ int (*set_enhanced_strobe)(struct sdhci_host *host);
};
struct sdhci_host {
@@ -280,6 +292,7 @@
struct mmc_config cfg;
};
+void sdhci_enable_clk(struct sdhci_host *host, u16 clk);
int sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/u-boot/include/spl_ab.h b/u-boot/include/spl_ab.h
index 6075555..f24d3ff 100644
--- a/u-boot/include/spl_ab.h
+++ b/u-boot/include/spl_ab.h
@@ -6,6 +6,7 @@
#ifndef _SPL_AB_H_
#define _SPL_AB_H_
+#include <spl.h>
#include <android_avb/libavb_ab.h>
#include <android_avb/avb_ab_flow.h>
@@ -45,4 +46,13 @@
*/
int spl_ab_decrease_tries(struct blk_desc *dev_desc);
+/*
+ * spl_ab_decrease_reset
+ *
+ * @dev_desc: block description
+ *
+ * return: 0 success, others fail.
+ */
+int spl_ab_decrease_reset(struct blk_desc *dev_desc);
+
#endif
diff --git a/u-boot/include/spl_display.h b/u-boot/include/spl_display.h
new file mode 100644
index 0000000..3cb7fe2
--- /dev/null
+++ b/u-boot/include/spl_display.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2023 Rockchip Electronics Co., Ltd
+ *
+ */
+
+#ifndef _SPL_DISPLAY_H_
+#define _SPL_DISPLAY_H_
+
+#include <common.h>
+#include <drm_modes.h>
+#include <mp_boot.h>
+
+/* SPL display */
+#define RK3528_VOP_BASE 0xff840000
+#define RK3528_HDMI_BASE 0xff8d0000
+#define RK3528_HDMIPHY_BASE 0xffe00000
+#define RK3528_CRU_BASE 0xff4a0000
+#define RK3528_GPIO0_IOC_BASE 0xff540000
+#define RK3528_GPIO_BASE 0xff610000
+
+struct spl_display_info {
+ struct drm_display_mode mode;
+ u32 bus_format;
+ u32 enabled;
+};
+#endif
+
diff --git a/u-boot/include/u-boot/sha1.h b/u-boot/include/u-boot/sha1.h
index 2634a29..3bb6e62 100644
--- a/u-boot/include/u-boot/sha1.h
+++ b/u-boot/include/u-boot/sha1.h
@@ -31,7 +31,7 @@
typedef struct
{
unsigned long total[2]; /*!< number of bytes processed */
- unsigned long state[5]; /*!< intermediate digest state */
+ uint32_t state[5]; /*!< intermediate digest state */
unsigned char buffer[64]; /*!< data block being processed */
}
sha1_context;
diff --git a/u-boot/lib/avb/libavb/avb_sha512.c b/u-boot/lib/avb/libavb/avb_sha512.c
index d3e437b..2cdd6ca 100644
--- a/u-boot/lib/avb/libavb/avb_sha512.c
+++ b/u-boot/lib/avb/libavb/avb_sha512.c
@@ -38,33 +38,6 @@
#include <android_avb/avb_sha.h>
#include <android_avb/avb_util.h>
-/* Crypto-v1 is not support sha512 */
-#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
-void avb_sha512_init(AvbSHA512Ctx* ctx) {
- ctx->crypto_ctx.algo = CRYPTO_SHA512;
- ctx->crypto_ctx.length = ctx->tot_len;
- memset(ctx->buf, 0, sizeof(ctx->buf));
-
- ctx->crypto_dev = crypto_get_device(ctx->crypto_ctx.algo);
- if (!ctx->crypto_dev)
- avb_error("Can't get sha512 crypto device\n");
- else
- crypto_sha_init(ctx->crypto_dev, &ctx->crypto_ctx);
-}
-
-void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
- if (ctx->crypto_dev)
- crypto_sha_update(ctx->crypto_dev, (u32 *)data, len);
-}
-
-uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
- if (ctx->crypto_dev)
- crypto_sha_final(ctx->crypto_dev, &ctx->crypto_ctx, ctx->buf);
-
- return ctx->buf;
-}
-
-#else
#define SHFR(x, n) (x >> n)
#define ROTR(x, n) ((x >> n) | (x << ((sizeof(x) << 3) - n)))
#define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
@@ -160,6 +133,19 @@
/* SHA-512 implementation */
void avb_sha512_init(AvbSHA512Ctx* ctx) {
+/* Crypto-v1 is not support sha512 */
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
+ ctx->crypto_ctx.algo = CRYPTO_SHA512;
+ ctx->crypto_ctx.length = ctx->tot_len;
+ memset(ctx->buf, 0, sizeof(ctx->buf));
+
+ ctx->crypto_dev = crypto_get_device(ctx->crypto_ctx.algo);
+ /* If there is no available crypto device, calculate in software instead. */
+ if (ctx->crypto_dev) {
+ crypto_sha_init(ctx->crypto_dev, &ctx->crypto_ctx);
+ return;
+ }
+#endif
#ifdef UNROLL_LOOPS_SHA512
ctx->h[0] = sha512_h0[0];
ctx->h[1] = sha512_h0[1];
@@ -347,6 +333,15 @@
}
void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
+/* Crypto-v1 is not support sha512 */
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
+ /* If there is no available crypto device, calculate in software instead. */
+ if (ctx->crypto_dev) {
+ crypto_sha_update(ctx->crypto_dev, (u32 *)data, len);
+ return;
+ }
+#endif
+
size_t block_nb;
size_t new_len, rem_len, tmp_len;
const uint8_t* shifted_data;
@@ -378,6 +373,15 @@
}
uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
+/* Crypto-v1 is not support sha512 */
+#ifdef CONFIG_ROCKCHIP_CRYPTO_V2
+ /* If there is no available crypto device, calculate in software instead. */
+ if (ctx->crypto_dev) {
+ crypto_sha_final(ctx->crypto_dev, &ctx->crypto_ctx, ctx->buf);
+ return ctx->buf;
+ }
+#endif
+
size_t block_nb;
size_t pm_len;
uint64_t len_b;
@@ -414,4 +418,3 @@
return ctx->buf;
}
-#endif
diff --git a/u-boot/lib/avb/libavb/avb_slot_verify.c b/u-boot/lib/avb/libavb/avb_slot_verify.c
index af556e5..be3ff38 100644
--- a/u-boot/lib/avb/libavb/avb_slot_verify.c
+++ b/u-boot/lib/avb/libavb/avb_slot_verify.c
@@ -22,7 +22,7 @@
* SOFTWARE.
*/
#include <common.h>
-#include <sysmem.h>
+#include <android_image.h>
#include <android_avb/avb_slot_verify.h>
#include <android_avb/avb_chain_partition_descriptor.h>
#include <android_avb/avb_cmdline.h>
@@ -30,6 +30,7 @@
#include <android_avb/avb_hash_descriptor.h>
#include <android_avb/avb_hashtree_descriptor.h>
#include <android_avb/avb_kernel_cmdline_descriptor.h>
+#include <android_avb/avb_ops_user.h>
#include <android_avb/avb_sha.h>
#include <android_avb/avb_util.h>
#include <android_avb/avb_vbmeta_image.h>
@@ -118,7 +119,7 @@
/* Allocate and copy the partition. */
if (!*out_image_preloaded) {
- *out_image_buf = sysmem_alloc(MEM_AVB_ANDROID, image_size);
+ *out_image_buf = avb_malloc(image_size);
if (*out_image_buf == NULL) {
return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
}
@@ -296,7 +297,7 @@
bool image_preloaded = false;
uint8_t* digest;
size_t digest_len;
- const char* found;
+ const char* found = NULL;
uint64_t image_size;
size_t expected_digest_len = 0;
uint8_t expected_digest_buf[AVB_SHA512_DIGEST_SIZE];
@@ -388,7 +389,7 @@
allow_verification_error);
if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
goto out;
- } else if (image_preloaded) {
+ } else if (allow_verification_error) {
goto out;
}
@@ -482,7 +483,7 @@
fail:
if (image_buf != NULL && !image_preloaded) {
- sysmem_free((phys_addr_t)image_buf);
+ avb_free(image_buf);
}
return ret;
}
@@ -556,7 +557,7 @@
out:
/* Free the current buffer if any. */
if (image_buf != NULL && !image_preloaded) {
- sysmem_free((phys_addr_t)image_buf);
+ avb_free(image_buf);
}
/* Buffers that are already saved in slot_data will be handled by the caller
* even on failure. */
@@ -1662,7 +1663,7 @@
avb_free(loaded_partition->partition_name);
}
if (loaded_partition->data != NULL && !loaded_partition->preloaded) {
- sysmem_free((phys_addr_t)loaded_partition->data);
+ avb_free(loaded_partition->data);
}
}
avb_free(data->loaded_partitions);
diff --git a/u-boot/lib/avb/libavb_user/Kconfig b/u-boot/lib/avb/libavb_user/Kconfig
index 3892094..249263e 100755
--- a/u-boot/lib/avb/libavb_user/Kconfig
+++ b/u-boot/lib/avb/libavb_user/Kconfig
@@ -16,7 +16,6 @@
- only allow "boot_android" as bootcmd;
- enter rockusb or fastboot when boot failed;
- not allow ctrl+c to enter hush;
- only the CONFIG_BOOTDELAY can interrupt the bootflow.
config SPL_AVB_LIBAVB_USER
bool "Android AVB read/write hardware for spl"
diff --git a/u-boot/lib/avb/libavb_user/avb_ops_user.c b/u-boot/lib/avb/libavb_user/avb_ops_user.c
index f7b2ac7..18c0c1f 100644
--- a/u-boot/lib/avb/libavb_user/avb_ops_user.c
+++ b/u-boot/lib/avb/libavb_user/avb_ops_user.c
@@ -81,10 +81,9 @@
return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
}
- if (part_get_info_by_name(dev_desc, partition, &part_info) < 0) {
- printf("Could not find \"%s\" partition\n", partition);
+ if (part_get_info_by_name(dev_desc, partition, &part_info) < 0)
return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
- }
+
*out_size_in_bytes = (part_info.size) * 512;
return AVB_IO_RESULT_OK;
}
@@ -281,6 +280,7 @@
{
if (out_is_unlocked) {
#ifdef CONFIG_OPTEE_CLIENT
+ uint8_t vboot_flag = 0;
int ret;
ret = trusty_read_lock_state((uint8_t *)out_is_unlocked);
@@ -291,7 +291,16 @@
case TEE_ERROR_GENERIC:
case TEE_ERROR_NO_DATA:
case TEE_ERROR_ITEM_NOT_FOUND:
- *out_is_unlocked = 1;
+ if (trusty_read_vbootkey_enable_flag(&vboot_flag)) {
+ printf("Can't read vboot flag\n");
+ return AVB_IO_RESULT_ERROR_IO;
+ }
+
+ if (vboot_flag)
+ *out_is_unlocked = 0;
+ else
+ *out_is_unlocked = 1;
+
if (trusty_write_lock_state(*out_is_unlocked)) {
printf("%s: init lock state error\n", __FILE__);
ret = AVB_IO_RESULT_ERROR_IO;
@@ -429,30 +438,111 @@
size_t* out_num_bytes_preloaded,
int allow_verification_error)
{
+ struct preloaded_partition *preload_info = NULL;
+ struct AvbOpsData *data = ops->user_data;
struct blk_desc *dev_desc;
+ disk_partition_t part_info;
ulong load_addr;
- int ret;
+ AvbIOResult ret;
+ int full_preload = 0;
- /* no need go further */
- if (!allow_verification_error)
- return AVB_IO_RESULT_OK;
-
- printf("get image from preloaded partition...\n");
dev_desc = rockchip_get_bootdev();
if (!dev_desc)
- return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+ return AVB_IO_RESULT_ERROR_IO;
- load_addr = env_get_ulong("kernel_addr_r", 16, 0);
- if (!load_addr)
- return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
+ if (part_get_info_by_name(dev_desc, partition, &part_info) < 0) {
+ printf("Could not find \"%s\" partition\n", partition);
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+ }
- ret = android_image_load_by_partname(dev_desc, partition, &load_addr);
- if (!ret) {
- *out_pointer = (u8 *)load_addr;
- *out_num_bytes_preloaded = num_bytes; /* return what it expects */
+ if (!allow_verification_error) {
+ if (!strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8))
+ preload_info = &data->boot;
+ else if (!strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11))
+ preload_info = &data->vendor_boot;
+ else if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9))
+ preload_info = &data->init_boot;
+ else if (!strncmp(partition, ANDROID_PARTITION_RESOURCE, 8))
+ preload_info = &data->resource;
+
+ if (!preload_info) {
+ printf("Error: unknown full load partition '%s'\n", partition);
+ return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
+ }
+
+ printf("preloaded(s): %sfull image from '%s' at 0x%08lx - 0x%08lx\n",
+ preload_info->size ? "pre-" : "", partition,
+ (ulong)preload_info->addr,
+ (ulong)preload_info->addr + num_bytes);
+
+ /* If the partition hasn't yet been preloaded, do it now.*/
+ if (preload_info->size == 0) {
+ ret = ops->read_from_partition(ops, partition,
+ 0, num_bytes,
+ preload_info->addr,
+ &preload_info->size);
+ if (ret != AVB_IO_RESULT_OK)
+ return ret;
+ }
+ *out_pointer = preload_info->addr;
+ *out_num_bytes_preloaded = preload_info->size;
ret = AVB_IO_RESULT_OK;
} else {
- ret = AVB_IO_RESULT_ERROR_IO;
+ if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9) ||
+ !strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11) ||
+ !strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8) ||
+ !strncmp(partition, ANDROID_PARTITION_RESOURCE, 8)) {
+ /* If already full preloaded, just use it */
+ if (!strncmp(partition, ANDROID_PARTITION_BOOT, 4) ||
+ !strncmp(partition, ANDROID_PARTITION_RECOVERY, 8)) {
+ preload_info = &data->boot;
+ if (preload_info->size) {
+ *out_pointer = preload_info->addr;
+ *out_num_bytes_preloaded = num_bytes;
+ full_preload = 1;
+ }
+ }
+ printf("preloaded: %s image from '%s\n",
+ full_preload ? "pre-full" : "distribute", partition);
+ } else {
+ printf("Error: unknown preloaded partition '%s'\n", partition);
+ return AVB_IO_RESULT_ERROR_OOM;
+ }
+
+ /*
+ * Already preloaded during boot/recovery loading,
+ * here we just return a dummy buffer.
+ */
+ if (!strncmp(partition, ANDROID_PARTITION_INIT_BOOT, 9) ||
+ !strncmp(partition, ANDROID_PARTITION_VENDOR_BOOT, 11) ||
+ !strncmp(partition, ANDROID_PARTITION_RESOURCE, 8)) {
+ *out_pointer = (u8 *)avb_malloc(ARCH_DMA_MINALIGN);
+ *out_num_bytes_preloaded = num_bytes; /* return what it expects */
+ return AVB_IO_RESULT_OK;
+ }
+
+ /* If already full preloaded, there is nothing to do and just return */
+ if (full_preload)
+ return AVB_IO_RESULT_OK;
+
+ /*
+ * only boot/recovery partition can reach here
+ * and init/vendor_boot are loaded at this round.
+ */
+ load_addr = env_get_ulong("kernel_addr_r", 16, 0);
+ if (!load_addr)
+ return AVB_IO_RESULT_ERROR_NO_SUCH_VALUE;
+
+ ret = android_image_load_by_partname(dev_desc, partition, &load_addr);
+ if (!ret) {
+ *out_pointer = (u8 *)load_addr;
+ *out_num_bytes_preloaded = num_bytes; /* return what it expects */
+ ret = AVB_IO_RESULT_OK;
+ } else {
+ ret = AVB_IO_RESULT_ERROR_IO;
+ }
}
return ret;
@@ -489,7 +579,8 @@
AvbOps *avb_ops_user_new(void)
{
- AvbOps *ops;
+ AvbOps *ops = NULL;
+ struct AvbOpsData *ops_data = NULL;
ops = calloc(1, sizeof(AvbOps));
if (!ops) {
@@ -510,8 +601,20 @@
free(ops);
goto out;
}
+
+ ops_data = calloc(1, sizeof(struct AvbOpsData));
+ if (!ops_data) {
+ printf("Error allocating memory for AvbOpsData.\n");
+ free(ops->atx_ops);
+ free(ops->ab_ops);
+ free(ops);
+ goto out;
+ }
+
ops->ab_ops->ops = ops;
ops->atx_ops->ops = ops;
+ ops_data->ops = ops;
+ ops->user_data = ops_data;
ops->read_from_partition = read_from_partition;
ops->write_to_partition = write_to_partition;
@@ -533,12 +636,14 @@
ops->atx_ops->set_key_version = avb_set_key_version;
ops->atx_ops->get_random = rk_get_random;
-out:
return ops;
+out:
+ return NULL;
}
void avb_ops_user_free(AvbOps *ops)
{
+ free(ops->user_data);
free(ops->ab_ops);
free(ops->atx_ops);
free(ops);
diff --git a/u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c b/u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c
index a536fd9..78e0d9a 100644
--- a/u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c
+++ b/u-boot/lib/avb/rk_avb_user/rk_avb_ops_user.c
@@ -158,6 +158,7 @@
int rk_avb_read_lock_state(uint8_t *lock_state)
{
#ifdef CONFIG_OPTEE_CLIENT
+ uint8_t vboot_flag = 0;
int ret;
ret = trusty_read_lock_state(lock_state);
@@ -167,7 +168,16 @@
case TEE_ERROR_GENERIC:
case TEE_ERROR_NO_DATA:
case TEE_ERROR_ITEM_NOT_FOUND:
- *lock_state = 1;
+ if (trusty_read_vbootkey_enable_flag(&vboot_flag)) {
+ printf("Can't read vboot flag\n");
+ return -1;
+ }
+
+ if (vboot_flag)
+ *lock_state = 0;
+ else
+ *lock_state = 1;
+
if (rk_avb_write_lock_state(*lock_state)) {
printf("avb_write_lock_state error!");
ret = -1;
diff --git a/u-boot/lib/optee_clientApi/OpteeClientInterface.c b/u-boot/lib/optee_clientApi/OpteeClientInterface.c
index c16a460..9f2022b 100644
--- a/u-boot/lib/optee_clientApi/OpteeClientInterface.c
+++ b/u-boot/lib/optee_clientApi/OpteeClientInterface.c
@@ -73,6 +73,20 @@
flush_cache(aligned_input, aligned_len);
}
+static void crypto_invalidate_cacheline(uint32_t addr, uint32_t size)
+{
+ ulong alignment = CONFIG_SYS_CACHELINE_SIZE;
+ ulong aligned_input, aligned_len;
+
+ if (!addr || !size)
+ return;
+
+ /* Must invalidate dcache after crypto DMA write data region */
+ aligned_input = round_down(addr, alignment);
+ aligned_len = round_up(size + (addr - aligned_input), alignment);
+ invalidate_dcache_range(aligned_input, aligned_input + aligned_len);
+}
+
static uint32_t trusty_base_write_security_data(char *filename,
uint32_t filename_size,
uint8_t *data,
@@ -1014,6 +1028,8 @@
&TeecOperation,
&ErrorOrigin);
+ crypto_invalidate_cacheline(dst_phys_addr, len);
+
exit:
TEEC_ReleaseSharedMemory(&SharedMem_config);
TEEC_CloseSession(&TeecSession);
diff --git a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c
index ca60698..414f5f4 100644
--- a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c
+++ b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v1.c
@@ -528,7 +528,7 @@
{
unsigned char *cp, *vp;
struct rkss_file_verification *verify;
- int ret, i;
+ int ret, i, write_table_flag = 0;
for (i = 0; i < RKSS_PARTITION_TABLE_COUNT; i++) {
cp = table_data + (i * RKSS_DATA_SECTION_LEN);
@@ -541,12 +541,15 @@
memset(cp, 0, RKSS_DATA_SECTION_LEN);
verify->checkstr = RKSS_CHECK_STR;
verify->version = RKSS_VERSION_V1;
+ write_table_flag = 1;
}
}
- ret = rkss_write_multi_sections(table_data, 0, RKSS_PARTITION_TABLE_COUNT);
- if (ret < 0) {
- printf("TEEC: rkss_write_multi_sections failed!!! ret: %d.\n", ret);
- return TEEC_ERROR_GENERIC;
+ if (write_table_flag == 1) {
+ ret = rkss_write_multi_sections(table_data, 0, RKSS_PARTITION_TABLE_COUNT);
+ if (ret < 0) {
+ printf("TEEC: rkss_write_multi_sections failed!!! ret: %d.\n", ret);
+ return TEEC_ERROR_GENERIC;
+ }
}
debug("TEEC: verify ptable success.\n");
return TEEC_SUCCESS;
diff --git a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c
index ff34e4e..d204a31 100644
--- a/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c
+++ b/u-boot/lib/optee_clientApi/OpteeClientRkNewFs_v2.c
@@ -1384,7 +1384,6 @@
case OPTEE_MRF_CLOSE:
debug(">>>>>>> [%d] OPTEE_MRF_CLOSE!\n", rkss_step++);
ret = ree_fs_new_close(num_params, params);
- rkss_storage_write();
break;
case OPTEE_MRF_READ:
debug(">>>>>>> [%d] OPTEE_MRF_READ!\n", rkss_step++);
@@ -1401,12 +1400,10 @@
case OPTEE_MRF_REMOVE:
debug(">>>>>>> [%d] OPTEE_MRF_REMOVE!\n", rkss_step++);
ret = ree_fs_new_remove(num_params, params);
- rkss_storage_write();
break;
case OPTEE_MRF_RENAME:
debug(">>>>>>> [%d] OPTEE_MRF_RENAME!\n", rkss_step++);
ret = ree_fs_new_rename(num_params, params);
- rkss_storage_write();
break;
case OPTEE_MRF_OPENDIR:
debug(">>>>>>> [%d] OPTEE_MRF_OPENDIR!\n", rkss_step++);
@@ -1424,5 +1421,6 @@
ret = TEEC_ERROR_BAD_PARAMETERS;
break;
}
+ rkss_storage_write();
return ret;
}
diff --git a/u-boot/lib/rsa/rsa-sign.c b/u-boot/lib/rsa/rsa-sign.c
index fed64d5..71a940c 100644
--- a/u-boot/lib/rsa/rsa-sign.c
+++ b/u-boot/lib/rsa/rsa-sign.c
@@ -610,7 +610,7 @@
BIGNUM **modulusp, BIGNUM **exponent_BN, BIGNUM **r_squaredp,
BIGNUM **c_factorp, BIGNUM **np_factorp)
{
- BIGNUM *big1, *big2, *big32, *big2_32, *big4100, *big2180;
+ BIGNUM *big1, *big2, *big32, *big2_32, *big4100, *big2180, *big4228;
BIGNUM *n, *e, *r, *r_squared, *tmp, *c_factor, *np_factor;
const BIGNUM *key_n, *key_e;
BN_CTX *bn_ctx = BN_CTX_new();
@@ -622,6 +622,7 @@
big32 = BN_new();
big4100 = BN_new();
big2180 = BN_new();
+ big4228 = BN_new();
r = BN_new();
r_squared = BN_new();
@@ -631,7 +632,7 @@
big2_32 = BN_new();
n = BN_new();
e = BN_new();
- if (!big1 || !big2 || !big32 || !big4100 || !big2180 || !r ||
+ if (!big1 || !big2 || !big32 || !big4100 || !big2180 || !big4228 || !r ||
!r_squared || !tmp || !big2_32 || !n || !e ||
!c_factor || !np_factor) {
fprintf(stderr, "Out of memory (bignum)\n");
@@ -645,7 +646,8 @@
if (!BN_copy(n, key_n) || !BN_copy(e, key_e) ||
!BN_set_word(big1, 1L) ||
!BN_set_word(big2, 2L) || !BN_set_word(big32, 32L) ||
- !BN_set_word(big4100, 4100L) || !BN_set_word(big2180, 2180L))
+ !BN_set_word(big4100, 4100L) || !BN_set_word(big2180, 2180L) ||
+ !BN_set_word(big4228, 4228L))
ret = -1;
/* big2_32 = 2^32 */
@@ -675,9 +677,15 @@
ret = -1;
/* Calculate np_factor = 2^2180 div n */
- if (!BN_exp(tmp, big2, big2180, bn_ctx) ||
- !BN_div(np_factor, NULL, tmp, n, bn_ctx))
- ret = -1;
+ if (BN_num_bits(n) == 2048) {
+ if (!BN_exp(tmp, big2, big2180, bn_ctx) ||
+ !BN_div(np_factor, NULL, tmp, n, bn_ctx))
+ ret = -1;
+ } else {/* Calculate 4096 np_factor = 2^4228 div n */
+ if (!BN_exp(tmp, big2, big4228, bn_ctx) ||
+ !BN_div(np_factor, NULL, tmp, n, bn_ctx))
+ ret = -1;
+ }
*modulusp = n;
*exponent_BN = e;
@@ -690,6 +698,7 @@
BN_free(big32);
BN_free(big4100);
BN_free(big2180);
+ BN_free(big4228);
BN_free(r);
BN_free(tmp);
BN_free(big2_32);
diff --git a/u-boot/lib/rsa/rsa-verify.c b/u-boot/lib/rsa/rsa-verify.c
index 18b9ff9..fe15293 100644
--- a/u-boot/lib/rsa/rsa-verify.c
+++ b/u-boot/lib/rsa/rsa-verify.c
@@ -86,11 +86,17 @@
uint8_t buf[sig_len];
rsa_key rsa_key;
int i, ret;
+#ifdef CONFIG_FIT_ENABLE_RSA4096_SUPPORT
+ if (key_len != RSA4096_BYTES)
+ return -EINVAL;
+ rsa_key.algo = CRYPTO_RSA4096;
+#else
if (key_len != RSA2048_BYTES)
return -EINVAL;
rsa_key.algo = CRYPTO_RSA2048;
+#endif
rsa_key.n = malloc(key_len);
rsa_key.e = malloc(key_len);
rsa_key.c = malloc(key_len);
@@ -599,7 +605,7 @@
struct udevice *dev;
struct key_prop prop;
char name[100] = {0};
- u16 secure_boot_enable = 0;
+ u16 secure_flags = 0;
const void *blob = info->fdt_blob;
uint8_t digest[FIT_MAX_HASH_LEN];
uint8_t digest_read[FIT_MAX_HASH_LEN];
@@ -610,11 +616,11 @@
return -ENODEV;
ret = misc_otp_read(dev, OTP_SECURE_BOOT_ENABLE_ADDR,
- &secure_boot_enable, OTP_SECURE_BOOT_ENABLE_SIZE);
+ &secure_flags, OTP_SECURE_BOOT_ENABLE_SIZE);
if (ret)
return ret;
- if (secure_boot_enable)
+ if (secure_flags == 0xff)
return 0;
sig_node = fdt_subnode_offset(blob, 0, FIT_SIG_NODENAME);
@@ -701,9 +707,9 @@
goto error;
}
- secure_boot_enable = 0xff;
+ secure_flags = 0xff;
ret = misc_otp_write(dev, OTP_SECURE_BOOT_ENABLE_ADDR,
- &secure_boot_enable, OTP_SECURE_BOOT_ENABLE_SIZE);
+ &secure_flags, OTP_SECURE_BOOT_ENABLE_SIZE);
if (ret)
goto error;
diff --git a/u-boot/lib/sha1.c b/u-boot/lib/sha1.c
index f54bb5b..399607a 100644
--- a/u-boot/lib/sha1.c
+++ b/u-boot/lib/sha1.c
@@ -26,6 +26,15 @@
#include <watchdog.h>
#include <u-boot/sha1.h>
+#include <linux/compiler.h>
+
+#ifdef USE_HOSTCC
+#undef __weak
+#define __weak
+#undef __maybe_unused
+#define __maybe_unused
+#endif
+
const uint8_t sha1_der_prefix[SHA1_DER_LEN] = {
0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
@@ -66,7 +75,7 @@
ctx->state[4] = 0xC3D2E1F0;
}
-static void sha1_process(sha1_context *ctx, const unsigned char data[64])
+static void __maybe_unused sha1_process_one(sha1_context *ctx, const unsigned char data[64])
{
unsigned long temp, W[16], A, B, C, D, E;
@@ -220,6 +229,18 @@
ctx->state[4] += E;
}
+__weak void sha1_process(sha1_context *ctx, const unsigned char *data,
+ unsigned int blocks)
+{
+ if (!blocks)
+ return;
+
+ while (blocks--) {
+ sha1_process_one(ctx, data);
+ data += 64;
+ }
+}
+
/*
* SHA-1 process buffer
*/
@@ -243,17 +264,15 @@
if (left && ilen >= fill) {
memcpy ((void *) (ctx->buffer + left), (void *) input, fill);
- sha1_process (ctx, ctx->buffer);
+ sha1_process(ctx, ctx->buffer, 1);
input += fill;
ilen -= fill;
left = 0;
}
- while (ilen >= 64) {
- sha1_process (ctx, input);
- input += 64;
- ilen -= 64;
- }
+ sha1_process(ctx, input, ilen / 64);
+ input += ilen / 64 * 64;
+ ilen = ilen % 64;
if (ilen > 0) {
memcpy ((void *) (ctx->buffer + left), (void *) input, ilen);
diff --git a/u-boot/lib/sha256.c b/u-boot/lib/sha256.c
index 251825c..ef20b40 100644
--- a/u-boot/lib/sha256.c
+++ b/u-boot/lib/sha256.c
@@ -15,6 +15,13 @@
#include <watchdog.h>
#include <u-boot/sha256.h>
+#include <linux/compiler.h>
+
+#ifdef USE_HOSTCC
+#undef __weak
+#define __weak
+#endif
+
const uint8_t sha256_der_prefix[SHA256_DER_LEN] = {
0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
@@ -56,7 +63,7 @@
ctx->state[7] = 0x5BE0CD19;
}
-static void sha256_process(sha256_context *ctx, const uint8_t data[64])
+static void sha256_process_one(sha256_context *ctx, const uint8_t data[64])
{
uint32_t temp1, temp2;
uint32_t W[64];
@@ -187,6 +194,18 @@
ctx->state[7] += H;
}
+__weak void sha256_process(sha256_context *ctx, const unsigned char *data,
+ unsigned int blocks)
+{
+ if (!blocks)
+ return;
+
+ while (blocks--) {
+ sha256_process_one(ctx, data);
+ data += 64;
+ }
+}
+
void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length)
{
uint32_t left, fill;
@@ -205,17 +224,15 @@
if (left && length >= fill) {
memcpy((void *) (ctx->buffer + left), (void *) input, fill);
- sha256_process(ctx, ctx->buffer);
+ sha256_process(ctx, ctx->buffer, 1);
length -= fill;
input += fill;
left = 0;
}
- while (length >= 64) {
- sha256_process(ctx, input);
- length -= 64;
- input += 64;
- }
+ sha256_process(ctx, input, length / 64);
+ input += length / 64 * 64;
+ length = length % 64;
if (length)
memcpy((void *) (ctx->buffer + left), (void *) input, length);
diff --git a/u-boot/make.sh b/u-boot/make.sh
index 233bc9a..de6d978 100755
--- a/u-boot/make.sh
+++ b/u-boot/make.sh
@@ -13,7 +13,7 @@
########################################### User can modify #############################################
RKBIN_TOOLS=../rkbin/tools
CROSS_COMPILE_ARM32=../prebuilts/gcc/linux-x86/arm/gcc-linaro-6.3.1-2017.05-x86_64_arm-linux-gnueabihf/bin/arm-linux-gnueabihf-
-CROSS_COMPILE_ARM64=../prebuilts/gcc/linux-x86/aarch64/gcc-linaro-6.3.1-2017.05-x86_64_aarch64-linux-gnu/bin/aarch64-linux-gnu-
+CROSS_COMPILE_ARM64=../prebuilts/gcc/linux-x86/aarch64/gcc-arm-10.3-2021.07-x86_64-aarch64-none-linux-gnu/bin/aarch64-none-linux-gnu-
########################################### User not touch #############################################
# Declare global INI file searching index name for every chip, update in select_chip_info()
RKCHIP=
@@ -48,6 +48,7 @@
SCRIPT_UBOOT="${SRCTREE}/scripts/uboot.sh"
SCRIPT_LOADER="${SRCTREE}/scripts/loader.sh"
SCRIPT_DECOMP="${SRCTREE}/scripts/decomp.sh"
+SCRIPT_CHECKCONFIG="${SRCTREE}/scripts/check-rkconfig.sh"
CC_FILE=".cc"
REP_DIR="./rep"
#########################################################################################################
@@ -268,7 +269,7 @@
CROSS_COMPILE_ARM64=`cat ${CC_FILE}`
else
if grep -q '^CONFIG_ARM64=y' .config ; then
- CROSS_COMPILE_ARM64=$(cd `dirname ${CROSS_COMPILE_ARM64}`; pwd)"/aarch64-linux-gnu-"
+ CROSS_COMPILE_ARM64=$(cd `dirname ${CROSS_COMPILE_ARM64}`; pwd)"/aarch64-none-linux-gnu-"
else
CROSS_COMPILE_ARM32=$(cd `dirname ${CROSS_COMPILE_ARM32}`; pwd)"/arm-linux-gnueabihf-"
fi
@@ -768,6 +769,9 @@
function finish()
{
+ # check special config
+ ${SCRIPT_CHECKCONFIG}
+
echo
if [ "${ARG_BOARD}" == "" ]; then
echo "Platform ${RKCHIP_LABEL} is build OK, with exist .config"
diff --git a/u-boot/scripts/README.rockchip b/u-boot/scripts/README.rockchip
index 907e376..8c8ea31 100644
--- a/u-boot/scripts/README.rockchip
+++ b/u-boot/scripts/README.rockchip
@@ -33,7 +33,7 @@
./scripts/stacktrace.sh dump.txt tpl
# avbtool.py
- ./avbtool.py info_image --image vbmeta.img
+ ./scripts/avbtool.py info_image --image vbmeta.img
[tools]
# resource_tool
diff --git a/u-boot/scripts/android2fit.sh b/u-boot/scripts/android2fit.sh
index cb7d2c9..b2ef05c 100755
--- a/u-boot/scripts/android2fit.sh
+++ b/u-boot/scripts/android2fit.sh
@@ -61,9 +61,9 @@
rm images/ -rf && mkdir -p images/
cp ${OUT}/kernel images/
- cp ${OUT}/resource images/
+ cp ${OUT}/resource images/second
cp ${OUT}/ramdisk images/
- cp ${OUT}/rk-kernel.dtb images/
+ cp ${OUT}/rk-kernel.dtb images/dtb
rm ${OUT}/ -rf
./make.sh fit
diff --git a/u-boot/scripts/check-rkconfig.sh b/u-boot/scripts/check-rkconfig.sh
new file mode 100755
index 0000000..fcf2f55
--- /dev/null
+++ b/u-boot/scripts/check-rkconfig.sh
@@ -0,0 +1,23 @@
+#!/bin/bash
+#
+# Copyright (c) 2023 Rockchip Electronics Co., Ltd
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+
+set -e
+
+if [ -f dts/kern.dtb ]; then
+ if ! grep -Eq 'CONFIG_EMBED_KERNEL_DTB=y' .config ; then
+ echo "ERROR: dts/kern.dtb was found, but CONFIG_EMBED_KERNEL_DTB is disabled."
+ exit 1
+ fi
+fi
+
+if grep -Eq 'CONFIG_EMBED_KERNEL_DTB=y' .config ; then
+ KDTB=`sed -n "/CONFIG_EMBED_KERNEL_DTB_PATH=/s/CONFIG_EMBED_KERNEL_DTB_PATH=//p" .config | tr -d '\r' | tr -d '"'`
+ if [ ! -f ${KDTB} ]; then
+ echo "ERROR: '${KDTB}' was not found assigned by CONFIG_EMBED_KERNEL_DTB_PATH."
+ exit 1
+ fi
+fi
diff --git a/u-boot/scripts/fit-core.sh b/u-boot/scripts/fit-core.sh
index ecfd40d..1136ecb 100644
--- a/u-boot/scripts/fit-core.sh
+++ b/u-boot/scripts/fit-core.sh
@@ -18,9 +18,11 @@
SIG_BOOT="${FIT_DIR}/boot.data2sign"
SIG_RECOVERY="${FIT_DIR}/recovery.data2sign"
# offs
-OFFS_DATA="0x1000"
-# file
-CHIP_FILE="arch/arm/lib/.asm-offsets.s.cmd"
+if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
+ OFFS_DATA="0x1200"
+else
+ OFFS_DATA="0x1000"
+fi
# placeholder address
FDT_ADDR_PLACEHOLDER="0xffffff00"
KERNEL_ADDR_PLACEHOLDER="0xffffff01"
@@ -94,6 +96,19 @@
exit 1
fi
done
+}
+
+function check_rsa_algo()
+{
+ if grep -q '^CONFIG_FIT_ENABLE_RSA4096_SUPPORT=y' .config ; then
+ rsa_algo="rsa4096"
+ else
+ rsa_algo="rsa2048"
+ fi
+ if ! grep -qr ${rsa_algo} $1 ; then
+ echo "ERROR: Wrong rsa_algo in its file. It should be ${rsa_algo}."
+ exit 1
+ fi
}
function check_rsa_keys()
@@ -378,6 +393,8 @@
else
check_rsa_keys
+ check_rsa_algo ${ITS_BOOT}
+
if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then
echo "ERROR: CONFIG_FIT_SIGNATURE is disabled"
exit 1
@@ -396,10 +413,9 @@
fi
# fixup
- COMMON_FILE=`sed -n "/_common.h/p" ${CHIP_FILE} | awk '{ print $1 }'`
- FDT_ADDR_R=`awk /fdt_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
- KERNEL_ADDR_R=`awk /kernel_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
- RMADISK_ADDR_R=`awk /ramdisk_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
+ FDT_ADDR_R=`strings env/built-in.o | grep 'fdt_addr_r=' | awk -F "=" '{ print $2 }'`
+ KERNEL_ADDR_R=`strings env/built-in.o | grep 'kernel_addr_r=' | awk -F "=" '{ print $2 }'`
+ RMADISK_ADDR_R=`strings env/built-in.o | grep 'ramdisk_addr_r=' | awk -F "=" '{ print $2 }'`
sed -i "s/${FDT_ADDR_PLACEHOLDER}/${FDT_ADDR_R}/g" ${ITS_BOOT}
sed -i "s/${KERNEL_ADDR_PLACEHOLDER}/${KERNEL_ADDR_R}/g" ${ITS_BOOT}
sed -i "s/${RAMDISK_ADDR_PLACEHOLDER}/${RMADISK_ADDR_R}/g" ${ITS_BOOT}
@@ -464,6 +480,8 @@
else
check_rsa_keys
+ check_rsa_algo ${ITS_RECOVERY}
+
if ! grep -q '^CONFIG_FIT_SIGNATURE=y' .config ; then
echo "ERROR: CONFIG_FIT_SIGNATURE is disabled"
exit 1
@@ -482,10 +500,9 @@
fi
# fixup
- COMMON_FILE=`sed -n "/_common.h/p" ${CHIP_FILE} | awk '{ print $1 }'`
- FDT_ADDR_R=`awk /fdt_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
- KERNEL_ADDR_R=`awk /kernel_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
- RMADISK_ADDR_R=`awk /ramdisk_addr_r/ ${COMMON_FILE} | awk -F '=' '{ print $2 }' | awk -F '\\' '{ print $1 }'`
+ FDT_ADDR_R=`strings env/built-in.o | grep 'fdt_addr_r=' | awk -F "=" '{ print $2 }'`
+ KERNEL_ADDR_R=`strings env/built-in.o | grep 'kernel_addr_r=' | awk -F "=" '{ print $2 }'`
+ RMADISK_ADDR_R=`strings env/built-in.o | grep 'ramdisk_addr_r=' | awk -F "=" '{ print $2 }'`
sed -i "s/${FDT_ADDR_PLACEHOLDER}/${FDT_ADDR_R}/g" ${ITS_RECOVERY}
sed -i "s/${KERNEL_ADDR_PLACEHOLDER}/${KERNEL_ADDR_R}/g" ${ITS_RECOVERY}
sed -i "s/${RAMDISK_ADDR_PLACEHOLDER}/${RMADISK_ADDR_R}/g" ${ITS_RECOVERY}
diff --git a/u-boot/scripts/setlocalversion b/u-boot/scripts/setlocalversion
index a3014ca..6b433f0 100755
--- a/u-boot/scripts/setlocalversion
+++ b/u-boot/scripts/setlocalversion
@@ -60,8 +60,6 @@
# "v2.6.30-rc5-302-g72357d5"), we pretty print it.
if atag="`git describe 2>/dev/null`"; then
echo "$atag" | awk -F- '{printf("-%s", $(NF))}'
- date=`git log -1 --author='@rock-chips' --date=format:%y%m%d | sed -n '/Date:/p' | awk '{ print "-"$2 }'`
- printf '%s' $date
# If we don't have a tag at all we print -g{commitish}.
else
@@ -74,11 +72,16 @@
printf -- '-svn%s' "`git svn find-rev $head`"
fi
+ # Check submit date of the last rockchip commit
+ date=`git log -1 --author='@rock-chips' --date=format:%y%m%d | sed -n '/Date:/p' | awk '{ print "-"$2 }'`
+ printf '%s' $date
+
# Check for uncommitted changes
if git diff-index --name-only HEAD | grep -qv "^scripts/package"; then
printf '%s' -dirty
fi
+ # Print build user
printf ' \#%s' $USER
# All done with git
diff --git a/u-boot/tools/Makefile b/u-boot/tools/Makefile
index 2bc097f..354b449 100644
--- a/u-boot/tools/Makefile
+++ b/u-boot/tools/Makefile
@@ -59,15 +59,9 @@
# Rockchip pack tools
ifdef CONFIG_ARCH_ROCKCHIP
-hostprogs-y += boot_merger
-hostprogs-y += trust_merger
-hostprogs-y += loaderimage
hostprogs-y += resource_tool
hostprogs-y += bmp2gray16
-boot_merger-objs := rockchip/boot_merger.o rockchip/sha2.o lib/sha256.o
-trust_merger-objs := rockchip/trust_merger.o rockchip/sha2.o lib/sha256.o
-loaderimage-objs := rockchip/loaderimage.o rockchip/sha.o lib/sha256.o rockchip/crc32_rk.o
resource_tool-objs := rockchip/resource_tool.o
bmp2gray16-objs := rockchip/bmp2gray16.o
endif
diff --git a/u-boot/tools/rkcommon.c b/u-boot/tools/rkcommon.c
index 7650fa5..dc62d9c 100644
--- a/u-boot/tools/rkcommon.c
+++ b/u-boot/tools/rkcommon.c
@@ -138,6 +138,8 @@
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
{ "rk1808", "RK18", 0x200000 - 0x2000, false, RK_HEADER_V1 },
+ { "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3562", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
diff --git a/u-boot/usb_update.txt b/u-boot/usb_update.txt
new file mode 100644
index 0000000..fee7683
--- /dev/null
+++ b/u-boot/usb_update.txt
@@ -0,0 +1,4 @@
+# script file start
+echo "this is usb update script!"
+
+% script file end
\ No newline at end of file
--
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