From 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 13 May 2024 10:30:14 +0000
Subject: [PATCH] modify sin led gpio
---
kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt | 151 ++++++--------------------------------------------
1 files changed, 18 insertions(+), 133 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt
index 101743d..88e06e5 100644
--- a/kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt
+++ b/kernel/Documentation/devicetree/bindings/reset/uniphier-reset.txt
@@ -1,149 +1,34 @@
-UniPhier reset controller
+UniPhier glue reset controller
-System reset
-------------
+Peripheral core reset in glue layer
+-----------------------------------
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-reset" - for LD4 SoC
- "socionext,uniphier-pro4-reset" - for Pro4 SoC
- "socionext,uniphier-sld8-reset" - for sLD8 SoC
- "socionext,uniphier-pro5-reset" - for Pro5 SoC
- "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC
- "socionext,uniphier-ld11-reset" - for LD11 SoC
- "socionext,uniphier-ld20-reset" - for LD20 SoC
- "socionext,uniphier-pxs3-reset" - for PXs3 SoC
-- #reset-cells: should be 1.
-
-Example:
-
- sysctrl@61840000 {
- compatible = "socionext,uniphier-ld11-sysctrl",
- "simple-mfd", "syscon";
- reg = <0x61840000 0x4000>;
-
- reset {
- compatible = "socionext,uniphier-ld11-reset";
- #reset-cells = <1>;
- };
-
- other nodes ...
- };
-
-
-Media I/O (MIO) reset, SD reset
--------------------------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-mio-reset" - for LD4 SoC
- "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC
- "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC
- "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC
- "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC
- "socionext,uniphier-ld11-mio-reset" - for LD11 SoC (MIO)
- "socionext,uniphier-ld11-sd-reset" - for LD11 SoC (SD)
- "socionext,uniphier-ld20-sd-reset" - for LD20 SoC
- "socionext,uniphier-pxs3-sd-reset" - for PXs3 SoC
-- #reset-cells: should be 1.
-
-Example:
-
- mioctrl@59810000 {
- compatible = "socionext,uniphier-ld11-mioctrl",
- "simple-mfd", "syscon";
- reg = <0x59810000 0x800>;
-
- reset {
- compatible = "socionext,uniphier-ld11-mio-reset";
- #reset-cells = <1>;
- };
-
- other nodes ...
- };
-
-
-Peripheral reset
-----------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld4-peri-reset" - for LD4 SoC
- "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC
- "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC
- "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC
- "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC
- "socionext,uniphier-ld11-peri-reset" - for LD11 SoC
- "socionext,uniphier-ld20-peri-reset" - for LD20 SoC
- "socionext,uniphier-pxs3-peri-reset" - for PXs3 SoC
-- #reset-cells: should be 1.
-
-Example:
-
- perictrl@59820000 {
- compatible = "socionext,uniphier-ld11-perictrl",
- "simple-mfd", "syscon";
- reg = <0x59820000 0x200>;
-
- reset {
- compatible = "socionext,uniphier-ld11-peri-reset";
- #reset-cells = <1>;
- };
-
- other nodes ...
- };
-
-
-Analog signal amplifier reset
------------------------------
-
-Required properties:
-- compatible: should be one of the following:
- "socionext,uniphier-ld11-adamv-reset" - for LD11 SoC
- "socionext,uniphier-ld20-adamv-reset" - for LD20 SoC
-- #reset-cells: should be 1.
-
-Example:
-
- adamv@57920000 {
- compatible = "socionext,uniphier-ld11-adamv",
- "simple-mfd", "syscon";
- reg = <0x57920000 0x1000>;
-
- adamv_rst: reset {
- compatible = "socionext,uniphier-ld11-adamv-reset";
- #reset-cells = <1>;
- };
-
- other nodes ...
- };
-
-
-USB3 core reset
----------------
-
-USB3 core reset belongs to USB3 glue layer. Before using the core reset,
-it is necessary to control the clocks and resets to enable this layer.
-These clocks and resets should be described in each property.
+Some peripheral core reset belongs to its own glue layer. Before using
+this core reset, it is necessary to control the clocks and resets to enable
+this layer. These clocks and resets should be described in each property.
Required properties:
- compatible: Should be
- "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC
- "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC
- "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC
- "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC
+ "socionext,uniphier-pro4-usb3-reset" - for Pro4 SoC USB3
+ "socionext,uniphier-pro5-usb3-reset" - for Pro5 SoC USB3
+ "socionext,uniphier-pxs2-usb3-reset" - for PXs2 SoC USB3
+ "socionext,uniphier-ld20-usb3-reset" - for LD20 SoC USB3
+ "socionext,uniphier-pxs3-usb3-reset" - for PXs3 SoC USB3
+ "socionext,uniphier-pro4-ahci-reset" - for Pro4 SoC AHCI
+ "socionext,uniphier-pxs2-ahci-reset" - for PXs2 SoC AHCI
+ "socionext,uniphier-pxs3-ahci-reset" - for PXs3 SoC AHCI
- #reset-cells: Should be 1.
- reg: Specifies offset and length of the register set for the device.
-- clocks: A list of phandles to the clock gate for USB3 glue layer.
+- clocks: A list of phandles to the clock gate for the glue layer.
According to the clock-names, appropriate clocks are required.
- clock-names: Should contain
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro4 and Pro5 SoCs
"link" - for others
-- resets: A list of phandles to the reset control for USB3 glue layer.
+- resets: A list of phandles to the reset control for the glue layer.
According to the reset-names, appropriate resets are required.
- reset-names: Should contain
- "gio", "link" - for Pro4 SoC
+ "gio", "link" - for Pro4 and Pro5 SoCs
"link" - for others
Example:
--
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