From 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 13 May 2024 10:30:14 +0000
Subject: [PATCH] modify sin led gpio
---
kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt | 76 +++++++++++++++++++++++++++-----------
1 files changed, 54 insertions(+), 22 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt b/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
index 7c44d17..aaf8c44 100644
--- a/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
+++ b/kernel/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
@@ -1,19 +1,30 @@
-Rockchip SoCs LVDS interface
+Rockchip RK3288 LVDS interface
================================
Required properties:
- compatible: matching the soc type, one of
- - "rockchip,px30-lvds",
- - "rockchip,rk3126-lvds",
- - "rockchip,rk3288-lvds",
- - "rockchip,rk3368-lvds";
- - "rockchip,rk3568-lvds";
-- phys : phandle for the PHY device
-- phy-names : should be "phy"
+ - "rockchip,rk3288-lvds";
+ - "rockchip,px30-lvds";
+
+- reg: physical base address of the controller and length
+ of memory mapped region.
+- clocks: must include clock specifiers corresponding to entries in the
+ clock-names property.
+- clock-names: must contain "pclk_lvds"
+
+- avdd1v0-supply: regulator phandle for 1.0V analog power
+- avdd1v8-supply: regulator phandle for 1.8V analog power
+- avdd3v3-supply: regulator phandle for 3.3V analog power
+
+- rockchip,grf: phandle to the general register files syscon
+- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
+
+- phys: LVDS/DSI DPHY (px30 only)
+- phy-names: name of the PHY, must be "dphy" (px30 only)
Optional properties:
-- dual-channel: boolean. if it exists, enable dual channel mode
-- rockchip,data-swap: boolean to enable odd/even data swap in dual channel mode
+- pinctrl-names: must contain a "lcdc" entry.
+- pinctrl-0: pin control group to be used for this controller.
Required nodes:
@@ -27,34 +38,55 @@
Example:
-&grf {
- status = "okay";
+lvds_panel: lvds-panel {
+ compatible = "auo,b101ean01";
+ enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+ data-mapping = "jeida-24";
- lvds: lvds {
+ ports {
+ panel_in_lvds: endpoint {
+ remote-endpoint = <&lvds_out_panel>;
+ };
+ };
+};
+
+For Rockchip RK3288:
+
+ lvds: lvds@ff96c000 {
compatible = "rockchip,rk3288-lvds";
- phys = <&video_phy>;
- phy-names = "phy";
- status = "disabled";
-
+ rockchip,grf = <&grf>;
+ reg = <0xff96c000 0x4000>;
+ clocks = <&cru PCLK_LVDS_PHY>;
+ clock-names = "pclk_lvds";
+ pinctrl-names = "lcdc";
+ pinctrl-0 = <&lcdc_ctl>;
+ avdd1v0-supply = <&vdd10_lcd>;
+ avdd1v8-supply = <&vcc18_lcd>;
+ avdd3v3-supply = <&vcca_33>;
+ rockchip,output = "rgb";
ports {
#address-cells = <1>;
#size-cells = <0>;
- port@0 {
+ lvds_in: port@0 {
reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
lvds_in_vopb: endpoint@0 {
reg = <0>;
remote-endpoint = <&vopb_out_lvds>;
};
-
lvds_in_vopl: endpoint@1 {
reg = <1>;
remote-endpoint = <&vopl_out_lvds>;
};
};
+
+ lvds_out: port@1 {
+ reg = <1>;
+
+ lvds_out_panel: endpoint {
+ remote-endpoint = <&panel_in_lvds>;
+ };
+ };
};
};
-};
--
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