From 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 13 May 2024 10:30:14 +0000
Subject: [PATCH] modify sin led gpio
---
kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt | 70 +++++++++++++++++++----------------
1 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt b/kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
index aa6bf1b..151be3b 100644
--- a/kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+++ b/kernel/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
@@ -4,44 +4,35 @@
Required properties:
- #address-cells: Should be <1>.
- #size-cells: Should be <0>.
-- compatible: must be one of:
- "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk1808-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi".
- "rockchip,rv1126-mipi-dsi", "snps,dw-mipi-dsi".
+- compatible: one of
+ "rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
+ "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
+ "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
- reg: Represent the physical address range of the controller.
- interrupts: Represent the controller's interrupt to the CPU(s).
-- power-domains: a phandle to mipi dsi power domain node.
-- resets: list of phandle + reset specifier pairs, as described in [3].
-- reset-names: string reset name, must be "apb".
-- clocks, clock-names: Phandles to the controller's APB clock(pclk),
- As described in [1].
+- clocks, clock-names: Phandles to the controller's pll reference
+ clock(ref) when using an internal dphy and APB clock(pclk).
+ For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
+ are required. As described in [1].
- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
- ports: contain a port node with endpoint definitions as defined in [2].
For vopb,set the reg = <0> and set the reg = <1> for vopl.
+- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+- video port 1 for either a panel or subsequent encoder
Optional properties:
-- clocks, clock-names:
- phandle to the SNPS-PHY config clock, name should be "phy_cfg".
- phandle to the SNPS-PHY PLL reference clock, name should be "ref".
- phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
-- phys: phandle to Non-SNPS PHY node
-- phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
- attribute, provides phandle to MIPI PHY node
-- rockchip,lane-rate: optional override of the desired bandwidth.
-- rockchip,dual-channel: for dual-channel mode, phandle to the slave channel.
-- rockchip,data-swap: for dual-channel mode, swap two channel data of MIPI.
+- phys: from general PHY binding: the phandle for the PHY device.
+- phy-names: Should be "dphy" if phys references an external phy.
+- power-domains: a phandle to mipi dsi power domain node.
+- resets: list of phandle + reset specifier pairs, as described in [3].
+- reset-names: string reset name, must be "apb".
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
[2] Documentation/devicetree/bindings/media/video-interfaces.txt
[3] Documentation/devicetree/bindings/reset/reset.txt
Example:
- dsi: dsi@ff960000 {
+ mipi_dsi: mipi@ff960000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
@@ -56,20 +47,29 @@
ports {
#address-cells = <1>;
#size-cells = <0>;
- reg = <1>;
- port {
+ mipi_in: port@0 {
+ reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
- dsi_in_vopb: endpoint@0 {
+ mipi_in_vopb: endpoint@0 {
reg = <0>;
- remote-endpoint = <&vopb_out_dsi>;
+ remote-endpoint = <&vopb_out_mipi>;
};
-
- dsi_in_vopl: endpoint@1 {
+ mipi_in_vopl: endpoint@1 {
reg = <1>;
- remote-endpoint = <&vopl_out_dsi>;
+ remote-endpoint = <&vopl_out_mipi>;
+ };
+ };
+
+ mipi_out: port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&panel_in_mipi>;
};
};
};
@@ -82,5 +82,11 @@
pinctrl-names = "default";
pinctrl-0 = <&lcd_en>;
backlight = <&backlight>;
+
+ port {
+ panel_in_mipi: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
};
};
--
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