From 9d77db3c730780c8ef5ccd4b66403ff5675cfe4e Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 13 May 2024 10:30:14 +0000
Subject: [PATCH] modify sin led gpio
---
kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
index d60b997..aed713c 100644
--- a/kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
+++ b/kernel/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
@@ -13,6 +13,7 @@
- external (optional) RGMII_REFCLK
- clock-names: Must be:
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ - #power-domain-cells: Must be 0
Examples
--------
@@ -27,6 +28,7 @@
clocks = <&ext_mclk>, <&ext_rtc_clk>,
<&ext_jtag_clk>, <&ext_rgmii_ref>;
clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #power-domain-cells = <0>;
};
- Other nodes can use the clocks provided by SYSCTRL as in:
@@ -38,6 +40,7 @@
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg-shift = <2>;
reg-io-width = <4>;
- clocks = <&sysctrl R9A06G032_CLK_UART0>;
- clock-names = "baudclk";
+ clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ power-domains = <&sysctrl>;
};
--
Gitblit v1.6.2