From 9999e48639b3cecb08ffb37358bcba3b48161b29 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 08:50:17 +0000
Subject: [PATCH] add ax88772_rst
---
kernel/arch/arm/boot/dts/socfpga.dtsi | 78 ++++++++++++++++++++++++++++----------
1 files changed, 57 insertions(+), 21 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/socfpga.dtsi b/kernel/arch/arm/boot/dts/socfpga.dtsi
index 602511c..0b021ee 100644
--- a/kernel/arch/arm/boot/dts/socfpga.dtsi
+++ b/kernel/arch/arm/boot/dts/socfpga.dtsi
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
/*
- * Copyright (C) 2012 Altera <www.altera.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (C) 2012 Altera <www.altera.com>
*/
#include <dt-bindings/reset/altr,rst-mgr.h>
@@ -22,8 +10,6 @@
#size-cells = <1>;
aliases {
- ethernet0 = &gmac0;
- ethernet1 = &gmac1;
serial0 = &uart0;
serial1 = &uart1;
timer0 = &timer0;
@@ -98,6 +84,8 @@
#dma-requests = <32>;
clocks = <&l4_main_clk>;
clock-names = "apb_pclk";
+ resets = <&rst DMA_RESET>;
+ reset-names = "dma";
};
};
@@ -114,6 +102,7 @@
reg = <0xffc00000 0x1000>;
interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
clocks = <&can0_clk>;
+ resets = <&rst CAN0_RESET>;
status = "disabled";
};
@@ -122,6 +111,7 @@
reg = <0xffc01000 0x1000>;
interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
clocks = <&can1_clk>;
+ resets = <&rst CAN1_RESET>;
status = "disabled";
};
@@ -483,10 +473,17 @@
clk-gate = <0xa0 9>;
};
+ nand_ecc_clk: nand_ecc_clk {
+ #clock-cells = <0>;
+ compatible = "altr,socfpga-gate-clk";
+ clocks = <&nand_x_clk>;
+ clk-gate = <0xa0 9>;
+ };
+
nand_clk: nand_clk {
#clock-cells = <0>;
compatible = "altr,socfpga-gate-clk";
- clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
+ clocks = <&nand_x_clk>;
clk-gate = <0xa0 10>;
fixed-divider = <4>;
};
@@ -534,6 +531,7 @@
reg = <0xff400000 0x100000>;
resets = <&rst LWHPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
+ status = "disabled";
};
fpga_bridge1: fpga_bridge@ff500000 {
@@ -541,6 +539,21 @@
reg = <0xff500000 0x10000>;
resets = <&rst HPS2FPGA_RESET>;
clocks = <&l4_main_clk>;
+ status = "disabled";
+ };
+
+ fpga_bridge2: fpga-bridge@ff600000 {
+ compatible = "altr,socfpga-fpga2hps-bridge";
+ reg = <0xff600000 0x100000>;
+ resets = <&rst FPGA2HPS_RESET>;
+ clocks = <&l4_main_clk>;
+ status = "disabled";
+ };
+
+ fpga_bridge3: fpga-bridge@ffc25080 {
+ compatible = "altr,socfpga-fpga2sdram-bridge";
+ reg = <0xffc25080 0x4>;
+ status = "disabled";
};
fpgamgr0: fpgamgr@ff706000 {
@@ -592,6 +605,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff708000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO0_RESET>;
status = "disabled";
porta: gpio-controller@0 {
@@ -612,6 +626,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff709000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO1_RESET>;
status = "disabled";
portb: gpio-controller@0 {
@@ -632,6 +647,7 @@
compatible = "snps,dw-apb-gpio";
reg = <0xff70a000 0x1000>;
clocks = <&l4_mp_clk>;
+ resets = <&rst GPIO2_RESET>;
status = "disabled";
portc: gpio-controller@0 {
@@ -742,19 +758,21 @@
#size-cells = <0>;
clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>;
clock-names = "biu", "ciu";
+ resets = <&rst SDMMC_RESET>;
status = "disabled";
};
nand0: nand@ff900000 {
#address-cells = <0x1>;
- #size-cells = <0x1>;
+ #size-cells = <0x0>;
compatible = "altr,socfpga-denali-nand";
reg = <0xff900000 0x100000>,
<0xffb80000 0x10000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0x0 0x90 0x4>;
- dma-mask = <0xffffffff>;
- clocks = <&nand_x_clk>;
+ clocks = <&nand_clk>, <&nand_x_clk>, <&nand_ecc_clk>;
+ clock-names = "nand", "nand_x", "ecc";
+ resets = <&rst NAND_RESET>;
status = "disabled";
};
@@ -765,7 +783,7 @@
qspi: spi@ff705000 {
compatible = "cdns,qspi-nor";
- #address-cells = <1>;
+ #address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
<0xffa00000 0x1000>;
@@ -774,6 +792,7 @@
cdns,fifo-width = <4>;
cdns,trigger-address = <0x00000000>;
clocks = <&qspi_clk>;
+ resets = <&rst QSPI_RESET>;
status = "disabled";
};
@@ -792,6 +811,7 @@
sdr: sdr@ffc25000 {
compatible = "altr,sdr-ctl", "syscon";
reg = <0xffc25000 0x1000>;
+ resets = <&rst SDR_RESET>;
};
sdramedac {
@@ -808,6 +828,8 @@
interrupts = <0 154 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
+ resets = <&rst SPIM0_RESET>;
+ reset-names = "spi";
status = "disabled";
};
@@ -819,6 +841,8 @@
interrupts = <0 155 4>;
num-cs = <4>;
clocks = <&spi_m_clk>;
+ resets = <&rst SPIM1_RESET>;
+ reset-names = "spi";
status = "disabled";
};
@@ -841,6 +865,8 @@
reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER0_RESET>;
+ reset-names = "timer";
};
timer1: timer1@ffc09000 {
@@ -849,6 +875,8 @@
reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
+ resets = <&rst SPTIMER1_RESET>;
+ reset-names = "timer";
};
timer2: timer2@ffd00000 {
@@ -857,6 +885,8 @@
reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER0_RESET>;
+ reset-names = "timer";
};
timer3: timer3@ffd01000 {
@@ -865,6 +895,8 @@
reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
+ resets = <&rst OSC1TIMER1_RESET>;
+ reset-names = "timer";
};
uart0: serial0@ffc02000 {
@@ -877,6 +909,7 @@
dmas = <&pdma 28>,
<&pdma 29>;
dma-names = "tx", "rx";
+ resets = <&rst UART0_RESET>;
};
uart1: serial1@ffc03000 {
@@ -889,6 +922,7 @@
dmas = <&pdma 30>,
<&pdma 31>;
dma-names = "tx", "rx";
+ resets = <&rst UART1_RESET>;
};
usbphy0: usbphy {
@@ -928,6 +962,7 @@
reg = <0xffd02000 0x1000>;
interrupts = <0 171 4>;
clocks = <&osc1>;
+ resets = <&rst L4WD0_RESET>;
status = "disabled";
};
@@ -936,6 +971,7 @@
reg = <0xffd03000 0x1000>;
interrupts = <0 172 4>;
clocks = <&osc1>;
+ resets = <&rst L4WD1_RESET>;
status = "disabled";
};
};
--
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