From 958e46acc8e900e8569dd467c1af9b8d2d019394 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 09 Dec 2023 08:38:54 +0000
Subject: [PATCH] disable cpu isolcpus
---
kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h | 78 ++-------------------------------------
1 files changed, 4 insertions(+), 74 deletions(-)
diff --git a/kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h b/kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h
index 0d01d15..441248b 100644
--- a/kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h
+++ b/kernel/drivers/gpu/drm/rockchip/cdn-dp-reg.h
@@ -1,23 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
* Author: Chris Zhong <zyw@rock-chips.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef _CDN_DP_REG_H
#define _CDN_DP_REG_H
#include <linux/bitops.h>
-#include <linux/phy/phy.h>
-#include <linux/phy/phy-rockchip-typec.h>
#define ADDR_IMEM 0x10000
#define ADDR_DMEM 0x20000
@@ -139,7 +129,7 @@
#define HPD_EVENT_MASK 0x211c
#define HPD_EVENT_DET 0x2120
-/* dptx framer addr */
+/* dpyx framer addr */
#define DP_FRAMER_GLOBAL_CONFIG 0x2200
#define DP_SW_RESET 0x2204
#define DP_FRAMER_TU 0x2208
@@ -330,13 +320,6 @@
#define GENERAL_BUS_SETTINGS 0x03
#define GENERAL_TEST_ACCESS 0x04
-/* AUX status*/
-#define AUX_STATUS_ACK 0
-#define AUX_STATUS_NACK 1
-#define AUX_STATUS_DEFER 2
-#define AUX_STATUS_SINK_ERROR 3
-#define AUX_STATUS_BUS_ERROR 4
-
#define DPTX_SET_POWER_MNG 0x00
#define DPTX_SET_HOST_CAPABILITIES 0x01
#define DPTX_GET_EDID 0x02
@@ -430,54 +413,8 @@
#define SPDIF_JITTER_THRSH(x) (((x) & 0xff) << 3)
#define SPDIF_JITTER_AVG_WIN(x) ((x) & 0x7)
-/* SOURCE_PIF_WR_REQ */
-#define HOST_WR BIT(0)
-
-/* SOURCE_PIF_PKT_ALLOC_REG */
-#define ACTIVE_IDLE_TYPE(x) (((x) & 0x1) << 17)
-#define TYPE_VALID BIT(16)
-#define PACKET_TYPE(x) (((x) & 0xff) << 8)
-#define PKT_ALLOC_ADDRESS(x) (((x) & 0xf) << 0)
-
-/* SOURCE_PIF_PKT_ALLOC_WR_EN */
-#define PKT_ALLOC_WR_EN BIT(0)
-
/* Reference cycles when using lane clock as reference */
#define LANE_REF_CYC 0x8000
-
-/* register CM_VID_CTRL */
-#define LANE_VID_REF_CYC(x) (((x) & (BIT(24) - 1)) << 0)
-#define NMVID_MEAS_TOLERANCE(x) (((x) & 0xf) << 24)
-
-/* register DP_TX_PHY_CONFIG_REG */
-#define DP_TX_PHY_TRAINING_ENABLE(x) ((x) & 1)
-#define DP_TX_PHY_TRAINING_TYPE_PRBS7 (0 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_TPS1 (1 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_TPS2 (2 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_TPS3 (3 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_TPS4 (4 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_PLTPAT (5 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_D10_2 (6 << 1)
-#define DP_TX_PHY_TRAINING_TYPE_HBR2CPAT (8 << 1)
-#define DP_TX_PHY_TRAINING_PATTERN(x) ((x) << 1)
-#define DP_TX_PHY_SCRAMBLER_BYPASS(x) (((x) & 1) << 5)
-#define DP_TX_PHY_ENCODER_BYPASS(x) (((x) & 1) << 6)
-#define DP_TX_PHY_SKEW_BYPASS(x) (((x) & 1) << 7)
-#define DP_TX_PHY_DISPARITY_RST(x) (((x) & 1) << 8)
-#define DP_TX_PHY_LANE0_SKEW(x) (((x) & 7) << 9)
-#define DP_TX_PHY_LANE1_SKEW(x) (((x) & 7) << 12)
-#define DP_TX_PHY_LANE2_SKEW(x) (((x) & 7) << 15)
-#define DP_TX_PHY_LANE3_SKEW(x) (((x) & 7) << 18)
-#define DP_TX_PHY_10BIT_ENABLE(x) (((x) & 1) << 21)
-
-/* register DP_FRAMER_GLOBAL_CONFIG */
-#define NUM_LANES(x) ((x) & 3)
-#define SST_MODE (0 << 2)
-#define RG_EN (0 << 4)
-#define GLOBAL_EN BIT(3)
-#define NO_VIDEO BIT(5)
-#define ENC_RST_DIS BIT(6)
-#define WR_VHSYNC_FALL BIT(7)
enum voltage_swing_level {
VOLTAGE_LEVEL_0,
@@ -524,12 +461,8 @@
int cdn_dp_event_config(struct cdn_dp_device *dp);
u32 cdn_dp_get_event(struct cdn_dp_device *dp);
int cdn_dp_get_hpd_status(struct cdn_dp_device *dp);
-int cdn_dp_reg_write(struct cdn_dp_device *dp, u16 addr, u32 val);
-ssize_t cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr,
- u8 *data, u16 len);
-ssize_t cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr,
- u8 *data, u16 len);
-int cdn_dp_get_aux_status(struct cdn_dp_device *dp);
+int cdn_dp_dpcd_write(struct cdn_dp_device *dp, u32 addr, u8 value);
+int cdn_dp_dpcd_read(struct cdn_dp_device *dp, u32 addr, u8 *data, u16 len);
int cdn_dp_get_edid_block(void *dp, u8 *edid,
unsigned int block, size_t length);
int cdn_dp_train_link(struct cdn_dp_device *dp);
@@ -538,7 +471,4 @@
int cdn_dp_audio_stop(struct cdn_dp_device *dp, struct audio_info *audio);
int cdn_dp_audio_mute(struct cdn_dp_device *dp, bool enable);
int cdn_dp_audio_config(struct cdn_dp_device *dp, struct audio_info *audio);
-int cdn_dp_software_train_link(struct cdn_dp_device *dp);
-void cdn_dp_infoframe_set(struct cdn_dp_device *dp, int entry_id, u8 *buf,
- u32 len, int type);
#endif /* _CDN_DP_REG_H */
--
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