From 95099d4622f8cb224d94e314c7a8e0df60b13f87 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 09 Dec 2023 08:38:01 +0000
Subject: [PATCH] enable docker ppp
---
kernel/drivers/rtc/rtc-zynqmp.c | 75 ++++++++++++++++++-------------------
1 files changed, 37 insertions(+), 38 deletions(-)
diff --git a/kernel/drivers/rtc/rtc-zynqmp.c b/kernel/drivers/rtc/rtc-zynqmp.c
index c532bd1..4b1077e 100644
--- a/kernel/drivers/rtc/rtc-zynqmp.c
+++ b/kernel/drivers/rtc/rtc-zynqmp.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
*
* Copyright (C) 2015 Xilinx, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
@@ -49,14 +38,15 @@
#define RTC_CALIB_DEF 0x198233
#define RTC_CALIB_MASK 0x1FFFFF
-#define RTC_SEC_MAX_VAL 0xFFFFFFFF
+#define RTC_ALRM_MASK BIT(1)
+#define RTC_MSEC 1000
struct xlnx_rtc_dev {
struct rtc_device *rtc;
void __iomem *reg_base;
int alarm_irq;
int sec_irq;
- int calibval;
+ unsigned int calibval;
};
static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
@@ -70,9 +60,6 @@
* to get the correct time on read.
*/
new_time = rtc_tm_to_time64(tm) + 1;
-
- if (new_time > RTC_SEC_MAX_VAL)
- return -EINVAL;
/*
* Writing into calibration register will clear the Tick Counter and
@@ -109,7 +96,7 @@
* RTC has updated the CURRENT_TIME with the time written into
* SET_TIME_WRITE register.
*/
- rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
+ read_time = readl(xrtcdev->reg_base + RTC_CUR_TM);
} else {
/*
* Time written in SET_TIME_WRITE has not yet updated into
@@ -119,8 +106,8 @@
* reading.
*/
read_time = readl(xrtcdev->reg_base + RTC_SET_TM_RD) - 1;
- rtc_time64_to_tm(read_time, tm);
}
+ rtc_time64_to_tm(read_time, tm);
return 0;
}
@@ -138,11 +125,28 @@
static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
{
struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
+ unsigned int status;
+ ulong timeout;
- if (enabled)
+ timeout = jiffies + msecs_to_jiffies(RTC_MSEC);
+
+ if (enabled) {
+ while (1) {
+ status = readl(xrtcdev->reg_base + RTC_INT_STS);
+ if (!((status & RTC_ALRM_MASK) == RTC_ALRM_MASK))
+ break;
+
+ if (time_after_eq(jiffies, timeout)) {
+ dev_err(dev, "Time out occur, while clearing alarm status bit\n");
+ return -ETIMEDOUT;
+ }
+ writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
+ }
+
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
- else
+ } else {
writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
+ }
return 0;
}
@@ -153,9 +157,6 @@
unsigned long alarm_time;
alarm_time = rtc_tm_to_time64(&alrm->time);
-
- if (alarm_time > RTC_SEC_MAX_VAL)
- return -EINVAL;
writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
@@ -201,8 +202,8 @@
if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
return IRQ_NONE;
- /* Clear RTC_INT_ALRM interrupt only */
- writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_STS);
+ /* Disable RTC_INT_ALRM interrupt only */
+ writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
if (status & RTC_INT_ALRM)
rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);
@@ -213,7 +214,6 @@
static int xlnx_rtc_probe(struct platform_device *pdev)
{
struct xlnx_rtc_dev *xrtcdev;
- struct resource *res;
int ret;
xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
@@ -222,17 +222,20 @@
platform_set_drvdata(pdev, xrtcdev);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ xrtcdev->rtc = devm_rtc_allocate_device(&pdev->dev);
+ if (IS_ERR(xrtcdev->rtc))
+ return PTR_ERR(xrtcdev->rtc);
- xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
+ xrtcdev->rtc->ops = &xlnx_rtc_ops;
+ xrtcdev->rtc->range_max = U32_MAX;
+
+ xrtcdev->reg_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(xrtcdev->reg_base))
return PTR_ERR(xrtcdev->reg_base);
xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
- if (xrtcdev->alarm_irq < 0) {
- dev_err(&pdev->dev, "no irq resource\n");
+ if (xrtcdev->alarm_irq < 0)
return xrtcdev->alarm_irq;
- }
ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
xlnx_rtc_interrupt, 0,
dev_name(&pdev->dev), xrtcdev);
@@ -242,10 +245,8 @@
}
xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
- if (xrtcdev->sec_irq < 0) {
- dev_err(&pdev->dev, "no irq resource\n");
+ if (xrtcdev->sec_irq < 0)
return xrtcdev->sec_irq;
- }
ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
xlnx_rtc_interrupt, 0,
dev_name(&pdev->dev), xrtcdev);
@@ -263,9 +264,7 @@
device_init_wakeup(&pdev->dev, 1);
- xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
- &xlnx_rtc_ops, THIS_MODULE);
- return PTR_ERR_OR_ZERO(xrtcdev->rtc);
+ return rtc_register_device(xrtcdev->rtc);
}
static int xlnx_rtc_remove(struct platform_device *pdev)
--
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