From 95099d4622f8cb224d94e314c7a8e0df60b13f87 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Sat, 09 Dec 2023 08:38:01 +0000
Subject: [PATCH] enable docker ppp
---
kernel/arch/arm64/include/asm/cpu.h | 57 ++++++++++++++++++++++++++++-----------------------------
1 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/kernel/arch/arm64/include/asm/cpu.h b/kernel/arch/arm64/include/asm/cpu.h
index 8839227..70dd1d6 100644
--- a/kernel/arch/arm64/include/asm/cpu.h
+++ b/kernel/arch/arm64/include/asm/cpu.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2014 ARM Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef __ASM_CPU_H
#define __ASM_CPU_H
@@ -23,6 +12,31 @@
/*
* Records attributes of an individual CPU.
*/
+struct cpuinfo_32bit {
+ u32 reg_id_dfr0;
+ u32 reg_id_dfr1;
+ u32 reg_id_isar0;
+ u32 reg_id_isar1;
+ u32 reg_id_isar2;
+ u32 reg_id_isar3;
+ u32 reg_id_isar4;
+ u32 reg_id_isar5;
+ u32 reg_id_isar6;
+ u32 reg_id_mmfr0;
+ u32 reg_id_mmfr1;
+ u32 reg_id_mmfr2;
+ u32 reg_id_mmfr3;
+ u32 reg_id_mmfr4;
+ u32 reg_id_mmfr5;
+ u32 reg_id_pfr0;
+ u32 reg_id_pfr1;
+ u32 reg_id_pfr2;
+
+ u32 reg_mvfr0;
+ u32 reg_mvfr1;
+ u32 reg_mvfr2;
+};
+
struct cpuinfo_arm64 {
struct cpu cpu;
struct kobject kobj;
@@ -36,6 +50,7 @@
u64 reg_id_aa64dfr1;
u64 reg_id_aa64isar0;
u64 reg_id_aa64isar1;
+ u64 reg_id_aa64isar2;
u64 reg_id_aa64mmfr0;
u64 reg_id_aa64mmfr1;
u64 reg_id_aa64mmfr2;
@@ -43,23 +58,7 @@
u64 reg_id_aa64pfr1;
u64 reg_id_aa64zfr0;
- u32 reg_id_dfr0;
- u32 reg_id_isar0;
- u32 reg_id_isar1;
- u32 reg_id_isar2;
- u32 reg_id_isar3;
- u32 reg_id_isar4;
- u32 reg_id_isar5;
- u32 reg_id_mmfr0;
- u32 reg_id_mmfr1;
- u32 reg_id_mmfr2;
- u32 reg_id_mmfr3;
- u32 reg_id_pfr0;
- u32 reg_id_pfr1;
-
- u32 reg_mvfr0;
- u32 reg_mvfr1;
- u32 reg_mvfr2;
+ struct cpuinfo_32bit aarch32;
/* pseudo-ZCR for recording maximum ZCR_EL1 LEN value: */
u64 reg_zcr;
--
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