From 8d2a02b24d66aa359e83eebc1ed3c0f85367a1cb Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Thu, 16 May 2024 03:11:33 +0000
Subject: [PATCH] AX88772C_eeprom and ax8872c build together
---
kernel/drivers/gpu/arm/bifrost/mali_kbase_ctx_sched.c | 69 +++++++++++++++++++++++++---------
1 files changed, 50 insertions(+), 19 deletions(-)
diff --git a/kernel/drivers/gpu/arm/bifrost/mali_kbase_ctx_sched.c b/kernel/drivers/gpu/arm/bifrost/mali_kbase_ctx_sched.c
index d06380d..dc6feb9 100644
--- a/kernel/drivers/gpu/arm/bifrost/mali_kbase_ctx_sched.c
+++ b/kernel/drivers/gpu/arm/bifrost/mali_kbase_ctx_sched.c
@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
/*
*
- * (C) COPYRIGHT 2017-2021 ARM Limited. All rights reserved.
+ * (C) COPYRIGHT 2017-2023 ARM Limited. All rights reserved.
*
* This program is free software and is provided to you under the terms of the
* GNU General Public License version 2 as published by the Free Software
@@ -23,6 +23,11 @@
#include <mali_kbase_defs.h>
#include "mali_kbase_ctx_sched.h"
#include "tl/mali_kbase_tracepoints.h"
+#if MALI_USE_CSF
+#include "mali_kbase_reset_gpu.h"
+#else
+#include <mali_kbase_hwaccess_jm.h>
+#endif
/* Helper for ktrace */
#if KBASE_KTRACE_ENABLE
@@ -62,6 +67,12 @@
WARN_ON(kbdev->as_to_kctx[i] != NULL);
WARN_ON(!(kbdev->as_free & (1u << i)));
}
+}
+
+void kbase_ctx_sched_init_ctx(struct kbase_context *kctx)
+{
+ kctx->as_nr = KBASEP_AS_NR_INVALID;
+ atomic_set(&kctx->refcount, 0);
}
/* kbasep_ctx_sched_find_as_for_ctx - Find a free address space
@@ -108,7 +119,7 @@
if (atomic_inc_return(&kctx->refcount) == 1) {
int const free_as = kbasep_ctx_sched_find_as_for_ctx(kctx);
- if (free_as != KBASEP_AS_NR_INVALID) {
+ if (free_as >= 0) {
kbdev->as_free &= ~(1u << free_as);
/* Only program the MMU if the context has not been
* assigned the same address space before.
@@ -124,7 +135,6 @@
kbdev, prev_kctx->id);
prev_kctx->as_nr = KBASEP_AS_NR_INVALID;
}
-
kctx->as_nr = free_as;
kbdev->as_to_kctx[free_as] = kctx;
KBASE_TLSTREAM_TL_KBASE_CTX_ASSIGN_AS(
@@ -150,9 +160,23 @@
struct kbase_device *const kbdev = kctx->kbdev;
lockdep_assert_held(&kbdev->hwaccess_lock);
- WARN_ON(atomic_read(&kctx->refcount) == 0);
- WARN_ON(kctx->as_nr == KBASEP_AS_NR_INVALID);
- WARN_ON(kbdev->as_to_kctx[kctx->as_nr] != kctx);
+#if MALI_USE_CSF
+ /* We expect the context to be active when this function is called,
+ * except for the case where a page fault is reported for it during
+ * the GPU reset sequence, in which case we can expect the refcount
+ * to be 0.
+ */
+ WARN_ON(!atomic_read(&kctx->refcount) && !kbase_reset_gpu_is_active(kbdev));
+#else
+ /* We expect the context to be active (and thus refcount should be non-zero)
+ * when this function is called
+ */
+ WARN_ON(!atomic_read(&kctx->refcount));
+#endif
+ if (likely((kctx->as_nr >= 0) && (kctx->as_nr < BASE_MAX_NR_AS)))
+ WARN_ON(kbdev->as_to_kctx[kctx->as_nr] != kctx);
+ else
+ WARN(true, "Invalid as_nr(%d)", kctx->as_nr);
atomic_inc(&kctx->refcount);
}
@@ -166,13 +190,17 @@
new_ref_count = atomic_dec_return(&kctx->refcount);
if (new_ref_count == 0) {
- kbdev->as_free |= (1u << kctx->as_nr);
- if (kbase_ctx_flag(kctx, KCTX_AS_DISABLED_ON_FAULT)) {
- KBASE_TLSTREAM_TL_KBASE_CTX_UNASSIGN_AS(
- kbdev, kctx->id);
- kbdev->as_to_kctx[kctx->as_nr] = NULL;
- kctx->as_nr = KBASEP_AS_NR_INVALID;
- kbase_ctx_flag_clear(kctx, KCTX_AS_DISABLED_ON_FAULT);
+ if (likely((kctx->as_nr >= 0) && (kctx->as_nr < BASE_MAX_NR_AS))) {
+ kbdev->as_free |= (1u << kctx->as_nr);
+ if (kbase_ctx_flag(kctx, KCTX_AS_DISABLED_ON_FAULT)) {
+ KBASE_TLSTREAM_TL_KBASE_CTX_UNASSIGN_AS(kbdev, kctx->id);
+ kbdev->as_to_kctx[kctx->as_nr] = NULL;
+ kctx->as_nr = KBASEP_AS_NR_INVALID;
+ kbase_ctx_flag_clear(kctx, KCTX_AS_DISABLED_ON_FAULT);
+#if !MALI_USE_CSF
+ kbase_backend_slot_kctx_purge_locked(kbdev, kctx);
+#endif
+ }
}
}
@@ -182,13 +210,14 @@
void kbase_ctx_sched_remove_ctx(struct kbase_context *kctx)
{
struct kbase_device *const kbdev = kctx->kbdev;
+ unsigned long flags;
- lockdep_assert_held(&kbdev->mmu_hw_mutex);
- lockdep_assert_held(&kbdev->hwaccess_lock);
+ mutex_lock(&kbdev->mmu_hw_mutex);
+ spin_lock_irqsave(&kbdev->hwaccess_lock, flags);
WARN_ON(atomic_read(&kctx->refcount) != 0);
- if (kctx->as_nr != KBASEP_AS_NR_INVALID) {
+ if ((kctx->as_nr >= 0) && (kctx->as_nr < BASE_MAX_NR_AS)) {
if (kbdev->pm.backend.gpu_powered)
kbase_mmu_disable(kctx);
@@ -196,6 +225,9 @@
kbdev->as_to_kctx[kctx->as_nr] = NULL;
kctx->as_nr = KBASEP_AS_NR_INVALID;
}
+
+ spin_unlock_irqrestore(&kbdev->hwaccess_lock, flags);
+ mutex_unlock(&kbdev->mmu_hw_mutex);
}
void kbase_ctx_sched_restore_all_as(struct kbase_device *kbdev)
@@ -210,6 +242,7 @@
for (i = 0; i != kbdev->nr_hw_address_spaces; ++i) {
struct kbase_context *kctx;
+ kbdev->as[i].is_unresponsive = false;
#if MALI_USE_CSF
if ((i == MCU_AS_NR) && kbdev->csf.firmware_inited) {
kbase_mmu_update(kbdev, &kbdev->csf.mcu_mmu,
@@ -308,16 +341,14 @@
bool kbase_ctx_sched_inc_refcount_nolock(struct kbase_context *kctx)
{
bool result = false;
- int as_nr;
if (WARN_ON(kctx == NULL))
return result;
lockdep_assert_held(&kctx->kbdev->hwaccess_lock);
- as_nr = kctx->as_nr;
if (atomic_read(&kctx->refcount) > 0) {
- KBASE_DEBUG_ASSERT(as_nr >= 0);
+ KBASE_DEBUG_ASSERT(kctx->as_nr >= 0);
kbase_ctx_sched_retain_ctx_refcount(kctx);
KBASE_KTRACE_ADD(kctx->kbdev, SCHED_RETAIN_CTX_NOLOCK, kctx,
--
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