From 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 22 Oct 2024 10:36:11 +0000
Subject: [PATCH] 修改4g拨号为QMI,需要在系统里后台执行quectel-CM
---
kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h | 80 ++++++++++++++++++++++++++++++++++++++-
1 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h b/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
index 7190174..f62ccf2 100644
--- a/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
+++ b/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h
@@ -36,6 +36,7 @@
#define MAX_AUDIOS 7
#define MAX_PIPES 6
+#define MAX_DWB_PIPES 1
struct gamma_curve {
uint32_t offset;
@@ -52,6 +53,12 @@
uint32_t custom_float_y;
uint32_t custom_float_offset;
uint32_t custom_float_slope;
+};
+
+struct curve_points3 {
+ struct curve_points red;
+ struct curve_points green;
+ struct curve_points blue;
};
struct pwl_result_data {
@@ -72,9 +79,46 @@
uint32_t delta_blue_reg;
};
+struct dc_rgb {
+ uint32_t red;
+ uint32_t green;
+ uint32_t blue;
+};
+
+struct tetrahedral_17x17x17 {
+ struct dc_rgb lut0[1229];
+ struct dc_rgb lut1[1228];
+ struct dc_rgb lut2[1228];
+ struct dc_rgb lut3[1228];
+};
+struct tetrahedral_9x9x9 {
+ struct dc_rgb lut0[183];
+ struct dc_rgb lut1[182];
+ struct dc_rgb lut2[182];
+ struct dc_rgb lut3[182];
+};
+
+struct tetrahedral_params {
+ union {
+ struct tetrahedral_17x17x17 tetrahedral_17;
+ struct tetrahedral_9x9x9 tetrahedral_9;
+ };
+ bool use_tetrahedral_9;
+ bool use_12bits;
+
+};
+
+/* arr_curve_points - regamma regions/segments specification
+ * arr_points - beginning and end point specified separately (only one on DCE)
+ * corner_points - beginning and end point for all 3 colors (DCN)
+ * rgb_resulted - final curve
+ */
struct pwl_params {
struct gamma_curve arr_curve_points[34];
- struct curve_points arr_points[2];
+ union {
+ struct curve_points arr_points[2];
+ struct curve_points3 corner_points[2];
+ };
struct pwl_result_data rgb_resulted[256 + 3];
uint32_t hw_points_num;
};
@@ -106,6 +150,15 @@
IPP_DEGAMMA_MODE_USER_PWL
};
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+enum gamcor_mode {
+ GAMCOR_MODE_BYPASS,
+ GAMCOR_MODE_RESERVED_1,
+ GAMCOR_MODE_USER_PWL,
+ GAMCOR_MODE_RESERVED_3
+};
+#endif
+
enum ipp_output_format {
IPP_OUTPUT_FORMAT_12_BIT_FIX,
IPP_OUTPUT_FORMAT_16_BIT_BYPASS,
@@ -133,12 +186,24 @@
uint16_t regval[12];
};
+enum gamut_remap_select {
+ GAMUT_REMAP_BYPASS = 0,
+ GAMUT_REMAP_COEFF,
+ GAMUT_REMAP_COMA_COEFF,
+ GAMUT_REMAP_COMB_COEFF
+};
enum opp_regamma {
OPP_REGAMMA_BYPASS = 0,
OPP_REGAMMA_SRGB,
OPP_REGAMMA_XVYCC,
OPP_REGAMMA_USER
+};
+
+enum optc_dsc_mode {
+ OPTC_DSC_DISABLED = 0,
+ OPTC_DSC_ENABLED_444 = 1, /* 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4) */
+ OPTC_DSC_ENABLED_NATIVE_SUBSAMPLED = 2 /* Native 4:2:2 or 4:2:0 */
};
struct dc_bias_and_scale {
@@ -162,7 +227,8 @@
TEST_PATTERN_MODE_VERTICALBARS,
TEST_PATTERN_MODE_HORIZONTALBARS,
TEST_PATTERN_MODE_SINGLERAMP_RGB,
- TEST_PATTERN_MODE_DUALRAMP_RGB
+ TEST_PATTERN_MODE_DUALRAMP_RGB,
+ TEST_PATTERN_MODE_XR_BIAS_RGB
};
enum test_pattern_color_format {
@@ -184,7 +250,15 @@
CONTROLLER_DP_TEST_PATTERN_RESERVED_8,
CONTROLLER_DP_TEST_PATTERN_RESERVED_9,
CONTROLLER_DP_TEST_PATTERN_RESERVED_A,
- CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA
+ CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA,
+ CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR
+};
+
+enum controller_dp_color_space {
+ CONTROLLER_DP_COLOR_SPACE_RGB,
+ CONTROLLER_DP_COLOR_SPACE_YCBCR601,
+ CONTROLLER_DP_COLOR_SPACE_YCBCR709,
+ CONTROLLER_DP_COLOR_SPACE_UDEFINED
};
enum dc_lut_mode {
--
Gitblit v1.6.2