From 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 22 Oct 2024 10:36:11 +0000
Subject: [PATCH] 修改4g拨号为QMI,需要在系统里后台执行quectel-CM
---
kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 77 +++++++++++++++++++++++++++++++++++---
1 files changed, 71 insertions(+), 6 deletions(-)
diff --git a/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
index 4f3f9e6..286ccee 100644
--- a/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
+++ b/kernel/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
@@ -28,6 +28,8 @@
#include "mem_input.h"
+#define OPP_ID_INVALID 0xf
+
enum cursor_pitch {
CURSOR_PITCH_64_PIXELS = 0,
@@ -36,10 +38,20 @@
};
enum cursor_lines_per_chunk {
+ CURSOR_LINE_PER_CHUNK_1 = 0, /* new for DCN2 */
CURSOR_LINE_PER_CHUNK_2 = 1,
CURSOR_LINE_PER_CHUNK_4,
CURSOR_LINE_PER_CHUNK_8,
CURSOR_LINE_PER_CHUNK_16
+};
+
+enum hubp_ind_block_size {
+ hubp_ind_block_unconstrained = 0,
+ hubp_ind_block_64b,
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ hubp_ind_block_128b,
+ hubp_ind_block_64b_no_128bcl,
+#endif
};
struct hubp {
@@ -55,6 +67,26 @@
bool power_gated;
};
+struct surface_flip_registers {
+ uint32_t DCSURF_SURFACE_CONTROL;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
+ uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
+ uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_SECONDARY_META_SURFACE_ADDRESS;
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH;
+ uint32_t DCSURF_SECONDARY_SURFACE_ADDRESS;
+ bool tmz_surface;
+ bool immediate;
+ uint8_t vmid;
+ bool grph_stereo;
+};
+
struct hubp_funcs {
void (*hubp_setup)(
struct hubp *hubp,
@@ -63,8 +95,14 @@
struct _vcs_dpi_display_rq_regs_st *rq_regs,
struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest);
+ void (*hubp_setup_interdependent)(
+ struct hubp *hubp,
+ struct _vcs_dpi_display_dlg_regs_st *dlg_regs,
+ struct _vcs_dpi_display_ttu_regs_st *ttu_regs);
+
void (*dcc_control)(struct hubp *hubp, bool enable,
- bool independent_64b_blks);
+ enum hubp_ind_block_size blk_size);
+
void (*mem_program_viewport)(
struct hubp *hubp,
const struct rect *viewport,
@@ -93,15 +131,13 @@
struct hubp *hubp,
enum surface_pixel_format format,
union dc_tiling_info *tiling_info,
- union plane_size *plane_size,
+ struct plane_size *plane_size,
enum dc_rotation_angle rotation,
struct dc_plane_dcc_param *dcc,
- bool horizontal_mirror);
+ bool horizontal_mirror,
+ unsigned int compa_level);
bool (*hubp_is_flip_pending)(struct hubp *hubp);
-
- void (*hubp_update_dchub)(struct hubp *hubp,
- struct dchub_init_data *dh_data);
void (*set_blank)(struct hubp *hubp, bool blank);
void (*set_hubp_blank_en)(struct hubp *hubp, bool blank);
@@ -120,8 +156,37 @@
void (*hubp_clk_cntl)(struct hubp *hubp, bool enable);
void (*hubp_vtg_sel)(struct hubp *hubp, uint32_t otg_inst);
void (*hubp_read_state)(struct hubp *hubp);
+ void (*hubp_clear_underflow)(struct hubp *hubp);
void (*hubp_disable_control)(struct hubp *hubp, bool disable_hubp);
unsigned int (*hubp_get_underflow_status)(struct hubp *hubp);
+ void (*hubp_init)(struct hubp *hubp);
+
+ void (*dmdata_set_attributes)(
+ struct hubp *hubp,
+ const struct dc_dmdata_attributes *attr);
+
+ void (*dmdata_load)(
+ struct hubp *hubp,
+ uint32_t dmdata_sw_size,
+ const uint32_t *dmdata_sw_data);
+ bool (*dmdata_status_done)(struct hubp *hubp);
+ void (*hubp_enable_tripleBuffer)(
+ struct hubp *hubp,
+ bool enable);
+
+ bool (*hubp_is_triplebuffer_enabled)(
+ struct hubp *hubp);
+
+ void (*hubp_set_flip_control_surface_gsl)(
+ struct hubp *hubp,
+ bool enable);
+
+ void (*validate_dml_output)(
+ struct hubp *hubp,
+ struct dc_context *ctx,
+ struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
+ struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
+ struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr);
};
--
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