From 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 22 Oct 2024 10:36:11 +0000
Subject: [PATCH] 修改4g拨号为QMI,需要在系统里后台执行quectel-CM
---
kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h | 41 +++++++++++++++++++++++++++++++++++++++++
1 files changed, 41 insertions(+), 0 deletions(-)
diff --git a/kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
index bf40725..308a543 100644
--- a/kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
+++ b/kernel/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h
@@ -48,6 +48,12 @@
DDC_GPIO_REG_LIST(cd,id),\
.ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP)
+ #define DDC_REG_LIST_DCN2(cd, id) \
+ DDC_GPIO_REG_LIST(cd, id),\
+ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\
+ .phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
+
#define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\
.type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\
.type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\
@@ -82,6 +88,11 @@
DDC_GPIO_I2C_REG_LIST(cd),\
.ddc_setup = 0
+#define DDC_I2C_REG_LIST_DCN2(cd) \
+ DDC_GPIO_I2C_REG_LIST(cd),\
+ .ddc_setup = 0,\
+ .phy_aux_cntl = REG(PHY_AUX_CNTL), \
+ .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5)
#define DDC_MASK_SH_LIST_COMMON(mask_sh) \
SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\
SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\
@@ -95,10 +106,18 @@
SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\
SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh)
+#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \
+ {DDC_MASK_SH_LIST_COMMON(mask_sh),\
+ 0,\
+ 0,\
+ (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\
+ (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)}
struct ddc_registers {
struct gpio_registers gpio;
uint32_t ddc_setup;
+ uint32_t phy_aux_cntl;
+ uint32_t dc_gpio_aux_ctrl_5;
};
struct ddc_sh_mask {
@@ -113,6 +132,9 @@
/* i2cpad_mask */
uint32_t DC_GPIO_SDA_PD_DIS;
uint32_t DC_GPIO_SCL_PD_DIS;
+ //phy_aux_cntl
+ uint32_t AUX_PAD_RXSEL;
+ uint32_t DDC_PAD_I2CMODE;
};
@@ -148,6 +170,25 @@
{\
DDC_I2C_REG_LIST(SCL)\
}
+#define ddc_data_regs_dcn2(id) \
+{\
+ DDC_REG_LIST_DCN2(DATA, id)\
+}
+
+#define ddc_clk_regs_dcn2(id) \
+{\
+ DDC_REG_LIST_DCN2(CLK, id)\
+}
+
+#define ddc_i2c_data_regs_dcn2 \
+{\
+ DDC_I2C_REG_LIST_DCN2(SDA)\
+}
+
+#define ddc_i2c_clk_regs_dcn2 \
+{\
+ DDC_REG_LIST_DCN2(SCL)\
+}
#endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */
--
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