From 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 22 Oct 2024 10:36:11 +0000
Subject: [PATCH] 修改4g拨号为QMI,需要在系统里后台执行quectel-CM
---
kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h | 258 ++++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 254 insertions(+), 4 deletions(-)
diff --git a/kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h b/kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
index 49ead12..04dabed 100644
--- a/kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
+++ b/kernel/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_link_encoder.h
@@ -31,10 +31,10 @@
#define TO_DCN10_LINK_ENC(link_encoder)\
container_of(link_encoder, struct dcn10_link_encoder, base)
-
#define AUX_REG_LIST(id)\
SRI(AUX_CONTROL, DP_AUX, id), \
- SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id)
+ SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
+ SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
#define HPD_REG_LIST(id)\
SRI(DC_HPD_CONTROL, HPD, id)
@@ -62,16 +62,18 @@
SRI(DP_DPHY_FAST_TRAINING, DP, id), \
SRI(DP_SEC_CNTL1, DP, id), \
SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \
- SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id)
#define LE_DCN10_REG_LIST(id)\
+ SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
LE_DCN_COMMON_REG_LIST(id)
struct dcn10_link_enc_aux_registers {
uint32_t AUX_CONTROL;
uint32_t AUX_DPHY_RX_CONTROL0;
+ uint32_t AUX_DPHY_TX_CONTROL;
+ uint32_t AUX_DPHY_RX_CONTROL1;
};
struct dcn10_link_enc_hpd_registers {
@@ -103,6 +105,61 @@
uint32_t DP_DPHY_HBR2_PATTERN_CONTROL;
uint32_t DP_SEC_CNTL1;
uint32_t TMDS_CTL_BITS;
+ /* DCCG */
+ uint32_t CLOCK_ENABLE;
+ /* DIG */
+ uint32_t DIG_LANE_ENABLE;
+ /* UNIPHY */
+ uint32_t CHANNEL_XBAR_CNTL;
+ /* DPCS */
+ uint32_t RDPCSTX_PHY_CNTL3;
+ uint32_t RDPCSTX_PHY_CNTL4;
+ uint32_t RDPCSTX_PHY_CNTL5;
+ uint32_t RDPCSTX_PHY_CNTL6;
+ uint32_t RDPCSTX_PHY_CNTL7;
+ uint32_t RDPCSTX_PHY_CNTL8;
+ uint32_t RDPCSTX_PHY_CNTL9;
+ uint32_t RDPCSTX_PHY_CNTL10;
+ uint32_t RDPCSTX_PHY_CNTL11;
+ uint32_t RDPCSTX_PHY_CNTL12;
+ uint32_t RDPCSTX_PHY_CNTL13;
+ uint32_t RDPCSTX_PHY_CNTL14;
+ uint32_t RDPCSTX_PHY_CNTL15;
+ uint32_t RDPCSTX_CNTL;
+ uint32_t RDPCSTX_CLOCK_CNTL;
+ uint32_t RDPCSTX_PHY_CNTL0;
+ uint32_t RDPCSTX_PHY_CNTL2;
+ uint32_t RDPCSTX_PLL_UPDATE_DATA;
+ uint32_t RDPCS_TX_CR_ADDR;
+ uint32_t RDPCS_TX_CR_DATA;
+ uint32_t DPCSTX_TX_CLOCK_CNTL;
+ uint32_t DPCSTX_TX_CNTL;
+ uint32_t RDPCSTX_INTERRUPT_CONTROL;
+ uint32_t RDPCSTX_PHY_FUSE0;
+ uint32_t RDPCSTX_PHY_FUSE1;
+ uint32_t RDPCSTX_PHY_FUSE2;
+ uint32_t RDPCSTX_PHY_FUSE3;
+ uint32_t RDPCSTX_PHY_RX_LD_VAL;
+ uint32_t DPCSTX_DEBUG_CONFIG;
+ uint32_t RDPCSTX_DEBUG_CONFIG;
+ uint32_t RDPCSTX0_RDPCSTX_SCRATCH;
+ uint32_t RDPCSTX_DMCU_DPALT_DIS_BLOCK_REG;
+ uint32_t DCIO_SOFT_RESET;
+ /* indirect registers */
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE2_DIG_PCS_XF_RX_OVRD_IN_3;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_2;
+ uint32_t RAWLANE3_DIG_PCS_XF_RX_OVRD_IN_3;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ uint32_t TMDS_DCBALANCER_CONTROL;
+ uint32_t PHYA_LINK_CNTL2;
+ uint32_t PHYB_LINK_CNTL2;
+ uint32_t PHYC_LINK_CNTL2;
+#endif
};
#define LE_SF(reg_name, field_name, post_fix)\
@@ -208,12 +265,198 @@
type AUX_LS_READ_EN;\
type AUX_RX_RECEIVE_WINDOW
+
+#define DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type) \
+ type RDPCS_PHY_DP_TX0_DATA_EN;\
+ type RDPCS_PHY_DP_TX1_DATA_EN;\
+ type RDPCS_PHY_DP_TX2_DATA_EN;\
+ type RDPCS_PHY_DP_TX3_DATA_EN;\
+ type RDPCS_PHY_DP_TX0_PSTATE;\
+ type RDPCS_PHY_DP_TX1_PSTATE;\
+ type RDPCS_PHY_DP_TX2_PSTATE;\
+ type RDPCS_PHY_DP_TX3_PSTATE;\
+ type RDPCS_PHY_DP_TX0_MPLL_EN;\
+ type RDPCS_PHY_DP_TX1_MPLL_EN;\
+ type RDPCS_PHY_DP_TX2_MPLL_EN;\
+ type RDPCS_PHY_DP_TX3_MPLL_EN;\
+ type RDPCS_TX_FIFO_LANE0_EN;\
+ type RDPCS_TX_FIFO_LANE1_EN;\
+ type RDPCS_TX_FIFO_LANE2_EN;\
+ type RDPCS_TX_FIFO_LANE3_EN;\
+ type RDPCS_EXT_REFCLK_EN;\
+ type RDPCS_TX_FIFO_EN;\
+ type UNIPHY_LINK_ENABLE;\
+ type UNIPHY_CHANNEL0_XBAR_SOURCE;\
+ type UNIPHY_CHANNEL1_XBAR_SOURCE;\
+ type UNIPHY_CHANNEL2_XBAR_SOURCE;\
+ type UNIPHY_CHANNEL3_XBAR_SOURCE;\
+ type UNIPHY_CHANNEL0_INVERT;\
+ type UNIPHY_CHANNEL1_INVERT;\
+ type UNIPHY_CHANNEL2_INVERT;\
+ type UNIPHY_CHANNEL3_INVERT;\
+ type UNIPHY_LINK_ENABLE_HPD_MASK;\
+ type UNIPHY_LANE_STAGGER_DELAY;\
+ type RDPCS_SRAMCLK_BYPASS;\
+ type RDPCS_SRAMCLK_EN;\
+ type RDPCS_SRAMCLK_CLOCK_ON;\
+ type DPCS_TX_FIFO_EN;\
+ type RDPCS_PHY_DP_TX0_DISABLE;\
+ type RDPCS_PHY_DP_TX1_DISABLE;\
+ type RDPCS_PHY_DP_TX2_DISABLE;\
+ type RDPCS_PHY_DP_TX3_DISABLE;\
+ type RDPCS_PHY_DP_TX0_CLK_RDY;\
+ type RDPCS_PHY_DP_TX1_CLK_RDY;\
+ type RDPCS_PHY_DP_TX2_CLK_RDY;\
+ type RDPCS_PHY_DP_TX3_CLK_RDY;\
+ type RDPCS_PHY_DP_TX0_REQ;\
+ type RDPCS_PHY_DP_TX1_REQ;\
+ type RDPCS_PHY_DP_TX2_REQ;\
+ type RDPCS_PHY_DP_TX3_REQ;\
+ type RDPCS_PHY_DP_TX0_ACK;\
+ type RDPCS_PHY_DP_TX1_ACK;\
+ type RDPCS_PHY_DP_TX2_ACK;\
+ type RDPCS_PHY_DP_TX3_ACK;\
+ type RDPCS_PHY_DP_TX0_RESET;\
+ type RDPCS_PHY_DP_TX1_RESET;\
+ type RDPCS_PHY_DP_TX2_RESET;\
+ type RDPCS_PHY_DP_TX3_RESET;\
+ type RDPCS_PHY_RESET;\
+ type RDPCS_PHY_CR_MUX_SEL;\
+ type RDPCS_PHY_REF_RANGE;\
+ type RDPCS_PHY_DP4_POR;\
+ type RDPCS_SRAM_BYPASS;\
+ type RDPCS_SRAM_EXT_LD_DONE;\
+ type RDPCS_PHY_DP_TX0_TERM_CTRL;\
+ type RDPCS_PHY_DP_TX1_TERM_CTRL;\
+ type RDPCS_PHY_DP_TX2_TERM_CTRL;\
+ type RDPCS_PHY_DP_TX3_TERM_CTRL;\
+ type RDPCS_PHY_DP_REF_CLK_MPLLB_DIV;\
+ type RDPCS_PHY_DP_MPLLB_MULTIPLIER;\
+ type RDPCS_PHY_DP_MPLLB_SSC_EN;\
+ type RDPCS_PHY_DP_MPLLB_DIV5_CLK_EN;\
+ type RDPCS_PHY_DP_MPLLB_TX_CLK_DIV;\
+ type RDPCS_PHY_DP_MPLLB_WORD_DIV2_EN;\
+ type RDPCS_PHY_DP_MPLLB_FRACN_EN;\
+ type RDPCS_PHY_DP_MPLLB_PMIX_EN;\
+ type RDPCS_PHY_DP_MPLLB_FRACN_QUOT;\
+ type RDPCS_PHY_DP_MPLLB_FRACN_DEN;\
+ type RDPCS_PHY_DP_MPLLB_FRACN_REM;\
+ type RDPCS_PHY_DP_MPLLB_SSC_UP_SPREAD;\
+ type RDPCS_PHY_DP_MPLLB_SSC_STEPSIZE;\
+ type RDPCS_PHY_DP_MPLLB_SSC_PEAK;\
+ type RDPCS_PHY_DP_MPLLB_DIV_CLK_EN;\
+ type RDPCS_PHY_DP_MPLLB_DIV_MULTIPLIER;\
+ type RDPCS_PHY_TX_VBOOST_LVL;\
+ type RDPCS_PHY_HDMIMODE_ENABLE;\
+ type RDPCS_PHY_DP_REF_CLK_EN;\
+ type RDPCS_PLL_UPDATE_DATA;\
+ type RDPCS_SRAM_INIT_DONE;\
+ type RDPCS_TX_CR_ADDR;\
+ type RDPCS_TX_CR_DATA;\
+ type RDPCS_PHY_HDMI_MPLLB_HDMI_DIV;\
+ type RDPCS_PHY_DP_MPLLB_STATE;\
+ type RDPCS_PHY_DP_TX0_WIDTH;\
+ type RDPCS_PHY_DP_TX0_RATE;\
+ type RDPCS_PHY_DP_TX1_WIDTH;\
+ type RDPCS_PHY_DP_TX1_RATE;\
+ type RDPCS_PHY_DP_TX2_WIDTH;\
+ type RDPCS_PHY_DP_TX2_RATE;\
+ type RDPCS_PHY_DP_TX3_WIDTH;\
+ type RDPCS_PHY_DP_TX3_RATE;\
+ type DPCS_SYMCLK_CLOCK_ON;\
+ type DPCS_SYMCLK_GATE_DIS;\
+ type DPCS_SYMCLK_EN;\
+ type RDPCS_SYMCLK_DIV2_CLOCK_ON;\
+ type RDPCS_SYMCLK_DIV2_GATE_DIS;\
+ type RDPCS_SYMCLK_DIV2_EN;\
+ type DPCS_TX_DATA_SWAP;\
+ type DPCS_TX_DATA_ORDER_INVERT;\
+ type DPCS_TX_FIFO_RD_START_DELAY;\
+ type RDPCS_TX_FIFO_RD_START_DELAY;\
+ type RDPCS_REG_FIFO_ERROR_MASK;\
+ type RDPCS_TX_FIFO_ERROR_MASK;\
+ type RDPCS_DPALT_DISABLE_TOGGLE_MASK;\
+ type RDPCS_DPALT_4LANE_TOGGLE_MASK;\
+ type RDPCS_PHY_DPALT_DP4;\
+ type RDPCS_PHY_DPALT_DISABLE;\
+ type RDPCS_PHY_DPALT_DISABLE_ACK;\
+ type RDPCS_PHY_DP_MPLLB_V2I;\
+ type RDPCS_PHY_DP_MPLLB_FREQ_VCO;\
+ type RDPCS_PHY_DP_MPLLB_CP_INT_GS;\
+ type RDPCS_PHY_RX_VREF_CTRL;\
+ type RDPCS_PHY_DP_MPLLB_CP_INT;\
+ type RDPCS_PHY_DP_MPLLB_CP_PROP;\
+ type RDPCS_PHY_RX_REF_LD_VAL;\
+ type RDPCS_PHY_RX_VCO_LD_VAL;\
+ type DPCSTX_DEBUG_CONFIG; \
+ type RDPCSTX_DEBUG_CONFIG; \
+ type RDPCS_PHY_DP_TX0_EQ_MAIN;\
+ type RDPCS_PHY_DP_TX0_EQ_PRE;\
+ type RDPCS_PHY_DP_TX0_EQ_POST;\
+ type RDPCS_PHY_DP_TX1_EQ_MAIN;\
+ type RDPCS_PHY_DP_TX1_EQ_PRE;\
+ type RDPCS_PHY_DP_TX1_EQ_POST;\
+ type RDPCS_PHY_DP_TX2_EQ_MAIN;\
+ type RDPCS_PHY_DP_MPLLB_CP_PROP_GS;\
+ type RDPCS_PHY_DP_TX2_EQ_PRE;\
+ type RDPCS_PHY_DP_TX2_EQ_POST;\
+ type RDPCS_PHY_DP_TX3_EQ_MAIN;\
+ type RDPCS_PHY_DCO_RANGE;\
+ type RDPCS_PHY_DCO_FINETUNE;\
+ type RDPCS_PHY_DP_TX3_EQ_PRE;\
+ type RDPCS_PHY_DP_TX3_EQ_POST;\
+ type RDPCS_PHY_SUP_PRE_HP;\
+ type RDPCS_PHY_DP_TX0_VREGDRV_BYP;\
+ type RDPCS_PHY_DP_TX1_VREGDRV_BYP;\
+ type RDPCS_PHY_DP_TX2_VREGDRV_BYP;\
+ type RDPCS_PHY_DP_TX3_VREGDRV_BYP;\
+ type RDPCS_DMCU_DPALT_DIS_BLOCK_REG;\
+ type UNIPHYA_SOFT_RESET;\
+ type UNIPHYB_SOFT_RESET;\
+ type UNIPHYC_SOFT_RESET;\
+ type UNIPHYD_SOFT_RESET;\
+ type UNIPHYE_SOFT_RESET;\
+ type UNIPHYF_SOFT_RESET
+
+#define DCN20_LINK_ENCODER_REG_FIELD_LIST(type) \
+ type DIG_LANE0EN;\
+ type DIG_LANE1EN;\
+ type DIG_LANE2EN;\
+ type DIG_LANE3EN;\
+ type DIG_CLK_EN;\
+ type SYMCLKA_CLOCK_ENABLE;\
+ type DPHY_FEC_EN;\
+ type DPHY_FEC_READY_SHADOW;\
+ type DPHY_FEC_ACTIVE_STATUS;\
+ DCN20_LINK_ENCODER_DPCS_REG_FIELD_LIST(type);\
+ type VCO_LD_VAL_OVRD;\
+ type VCO_LD_VAL_OVRD_EN;\
+ type REF_LD_VAL_OVRD;\
+ type REF_LD_VAL_OVRD_EN;\
+ type AUX_RX_START_WINDOW; \
+ type AUX_RX_HALF_SYM_DETECT_LEN; \
+ type AUX_RX_TRANSITION_FILTER_EN; \
+ type AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT; \
+ type AUX_RX_ALLOW_BELOW_THRESHOLD_START; \
+ type AUX_RX_ALLOW_BELOW_THRESHOLD_STOP; \
+ type AUX_RX_PHASE_DETECT_LEN; \
+ type AUX_RX_DETECTION_THRESHOLD; \
+ type AUX_TX_PRECHARGE_LEN; \
+ type AUX_TX_PRECHARGE_SYMBOLS; \
+ type AUX_MODE_DET_CHECK_DELAY;\
+ type DPCS_DBG_CBUS_DIS;\
+ type AUX_RX_PRECHARGE_SKIP;\
+ type AUX_RX_TIMEOUT_LEN;\
+ type AUX_RX_TIMEOUT_LEN_MUL
+
struct dcn10_link_enc_shift {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
+ DCN20_LINK_ENCODER_REG_FIELD_LIST(uint8_t);
};
struct dcn10_link_enc_mask {
DCN_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
+ DCN20_LINK_ENCODER_REG_FIELD_LIST(uint32_t);
};
struct dcn10_link_encoder {
@@ -271,7 +514,7 @@
struct link_encoder *enc,
enum signal_type signal);
-void configure_encoder(
+void enc1_configure_encoder(
struct dcn10_link_encoder *enc10,
const struct dc_link_settings *link_settings);
@@ -336,6 +579,13 @@
bool dcn10_is_dig_enabled(struct link_encoder *enc);
+unsigned int dcn10_get_dig_frontend(struct link_encoder *enc);
+
void dcn10_aux_initialize(struct dcn10_link_encoder *enc10);
+enum signal_type dcn10_get_dig_mode(
+ struct link_encoder *enc);
+
+void dcn10_link_encoder_get_max_link_cap(struct link_encoder *enc,
+ struct dc_link_settings *link_settings);
#endif /* __DC_LINK_ENCODER__DCN10_H__ */
--
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