From 8ac6c7a54ed1b98d142dce24b11c6de6a1e239a5 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Tue, 22 Oct 2024 10:36:11 +0000
Subject: [PATCH] 修改4g拨号为QMI,需要在系统里后台执行quectel-CM
---
kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | 7 +++++--
1 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
index 1b4213e..4d530d8 100644
--- a/kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
+++ b/kernel/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -1,10 +1,13 @@
Microsemi Ocelot reset controller
The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
-SoC MIPS core.
+SoC core.
+
+The reset registers are both present in the MSCC vcoreiii MIPS and
+microchip Sparx5 armv8 SoC's.
Required Properties:
- - compatible: "mscc,ocelot-chip-reset"
+ - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
Example:
reset@1070008 {
--
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