From 748e4f3d702def1a4bff191e0cf93b6a05340f01 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:41:34 +0000
Subject: [PATCH] add gpio led uart

---
 kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.h |   20 ++++----------------
 1 files changed, 4 insertions(+), 16 deletions(-)

diff --git a/kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.h b/kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
index 061b6fb..54d1f96 100644
--- a/kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
+++ b/kernel/drivers/clk/sunxi-ng/ccu-sun50i-a64.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
 /*
  * Copyright 2016 Maxime Ripard
  *
  * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
  */
 
 #ifndef _CCU_SUN50I_A64_H_
@@ -27,7 +18,9 @@
 #define CLK_PLL_AUDIO_2X		4
 #define CLK_PLL_AUDIO_4X		5
 #define CLK_PLL_AUDIO_8X		6
-#define CLK_PLL_VIDEO0			7
+
+/* PLL_VIDEO0 exported for HDMI PHY */
+
 #define CLK_PLL_VIDEO0_2X		8
 #define CLK_PLL_VE			9
 #define CLK_PLL_DDR0			10
@@ -43,7 +36,6 @@
 #define CLK_PLL_HSIC			18
 #define CLK_PLL_DE			19
 #define CLK_PLL_DDR1			20
-#define CLK_CPUX			21
 #define CLK_AXI				22
 #define CLK_APB				23
 #define CLK_AHB1			24
@@ -62,10 +54,6 @@
 #define CLK_DRAM			94
 
 /* All the DRAM gates are exported */
-
-/* Some more module clocks are exported */
-
-#define CLK_MBUS			112
 
 /* And the DSI and GPU module clock is exported */
 

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