From 748e4f3d702def1a4bff191e0cf93b6a05340f01 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:41:34 +0000
Subject: [PATCH] add gpio led uart
---
kernel/arch/arm/boot/dts/omap34xx.dtsi | 97 +++++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 86 insertions(+), 11 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/omap34xx.dtsi b/kernel/arch/arm/boot/dts/omap34xx.dtsi
index f572a47..feaa43b 100644
--- a/kernel/arch/arm/boot/dts/omap34xx.dtsi
+++ b/kernel/arch/arm/boot/dts/omap34xx.dtsi
@@ -1,7 +1,7 @@
/*
* Device Tree Source for OMAP34xx/OMAP35xx SoC
*
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
+ * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
@@ -16,16 +16,65 @@
/ {
cpus {
cpu: cpu@0 {
- /* OMAP343x/OMAP35xx variants OPP1-5 */
- operating-points = <
- /* kHz uV */
- 125000 975000
- 250000 1075000
- 500000 1200000
- 550000 1270000
- 600000 1350000
- >;
+ /* OMAP343x/OMAP35xx variants OPP1-6 */
+ operating-points-v2 = <&cpu0_opp_table>;
+
clock-latency = <300000>; /* From legacy driver */
+ #cooling-cells = <2>;
+ };
+ };
+
+ /* see Documentation/devicetree/bindings/opp/opp.txt */
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2-ti-cpu";
+ syscon = <&scm_conf>;
+
+ opp1-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ /*
+ * we currently only select the max voltage from table
+ * Table 3-3 of the omap3530 Data sheet (SPRS507F).
+ * Format is: <target min max>
+ */
+ opp-microvolt = <975000 975000 975000>;
+ /*
+ * first value is silicon revision bit mask
+ * second one 720MHz Device Identification bit mask
+ */
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp2-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1075000 1075000 1075000>;
+ opp-supported-hw = <0xffffffff 3>;
+ opp-suspend;
+ };
+
+ opp3-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1200000 1200000 1200000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp4-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ opp-microvolt = <1275000 1275000 1275000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp5-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ opp-supported-hw = <0xffffffff 3>;
+ };
+
+ opp6-720000000 {
+ opp-hz = /bits/ 64 <720000000>;
+ opp-microvolt = <1350000 1350000 1350000>;
+ /* only high-speed grade omap3530 devices */
+ opp-supported-hw = <0xffffffff 2>;
+ turbo-mode;
};
};
@@ -100,6 +149,32 @@
interrupts = <18>;
};
};
+
+ /*
+ * On omap34xx the OCP registers do not seem to be accessible
+ * at all unlike on 36xx. Maybe SGX is permanently set to
+ * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
+ * write-only at 0x50000e10. We detect SGX based on the SGX
+ * revision register instead of the unreadable OCP revision
+ * register. Also note that on early 34xx es1 revision there
+ * are also different clocks, but we do not have any dts users
+ * for it.
+ */
+ sgx_module: target-module@50000000 {
+ compatible = "ti,sysc-omap2", "ti,sysc";
+ reg = <0x50000014 0x4>;
+ reg-names = "rev";
+ clocks = <&sgx_fck>, <&sgx_ick>;
+ clock-names = "fck", "ick";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x50000000 0x4000>;
+
+ /*
+ * Closed source PowerVR driver, no child device
+ * binding or driver in mainline
+ */
+ };
};
thermal_zones: thermal-zones {
@@ -108,7 +183,7 @@
};
&ssi {
- status = "ok";
+ status = "okay";
clocks = <&ssi_ssr_fck>,
<&ssi_sst_fck>,
--
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