From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/drivers/net/ethernet/chelsio/cxgb/subr.c | 64 +++++++++----------------------
1 files changed, 19 insertions(+), 45 deletions(-)
diff --git a/kernel/drivers/net/ethernet/chelsio/cxgb/subr.c b/kernel/drivers/net/ethernet/chelsio/cxgb/subr.c
index 310add2..ea0f874 100644
--- a/kernel/drivers/net/ethernet/chelsio/cxgb/subr.c
+++ b/kernel/drivers/net/ethernet/chelsio/cxgb/subr.c
@@ -170,7 +170,7 @@
t1_link_negotiated(adapter, port_id, link_ok, speed, duplex, fc);
}
-static bool t1_pci_intr_handler(adapter_t *adapter)
+static int t1_pci_intr_handler(adapter_t *adapter)
{
u32 pcix_cause;
@@ -179,13 +179,9 @@
if (pcix_cause) {
pci_write_config_dword(adapter->pdev, A_PCICFG_INTR_CAUSE,
pcix_cause);
- /* PCI errors are fatal */
- t1_interrupts_disable(adapter);
- adapter->pending_thread_intr |= F_PL_INTR_SGE_ERR;
- pr_alert("%s: PCI error encountered.\n", adapter->name);
- return true;
+ t1_fatal_err(adapter); /* PCI errors are fatal */
}
- return false;
+ return 0;
}
#ifdef CONFIG_CHELSIO_T1_1G
@@ -214,16 +210,13 @@
/*
* Slow path interrupt handler for FPGAs.
*/
-static irqreturn_t fpga_slow_intr(adapter_t *adapter)
+static int fpga_slow_intr(adapter_t *adapter)
{
u32 cause = readl(adapter->regs + A_PL_CAUSE);
- irqreturn_t ret = IRQ_NONE;
cause &= ~F_PL_INTR_SGE_DATA;
- if (cause & F_PL_INTR_SGE_ERR) {
- if (t1_sge_intr_error_handler(adapter->sge))
- ret = IRQ_WAKE_THREAD;
- }
+ if (cause & F_PL_INTR_SGE_ERR)
+ t1_sge_intr_error_handler(adapter->sge);
if (cause & FPGA_PCIX_INTERRUPT_GMAC)
fpga_phy_intr_handler(adapter);
@@ -238,19 +231,14 @@
/* Clear TP interrupt */
writel(tp_cause, adapter->regs + FPGA_TP_ADDR_INTERRUPT_CAUSE);
}
- if (cause & FPGA_PCIX_INTERRUPT_PCIX) {
- if (t1_pci_intr_handler(adapter))
- ret = IRQ_WAKE_THREAD;
- }
+ if (cause & FPGA_PCIX_INTERRUPT_PCIX)
+ t1_pci_intr_handler(adapter);
/* Clear the interrupts just processed. */
if (cause)
writel(cause, adapter->regs + A_PL_CAUSE);
- if (ret != IRQ_NONE)
- return ret;
-
- return cause == 0 ? IRQ_NONE : IRQ_HANDLED;
+ return cause != 0;
}
#endif
@@ -854,45 +842,31 @@
/*
* Slow path interrupt handler for ASICs.
*/
-static irqreturn_t asic_slow_intr(adapter_t *adapter)
+static int asic_slow_intr(adapter_t *adapter)
{
u32 cause = readl(adapter->regs + A_PL_CAUSE);
- irqreturn_t ret = IRQ_HANDLED;
cause &= adapter->slow_intr_mask;
if (!cause)
- return IRQ_NONE;
- if (cause & F_PL_INTR_SGE_ERR) {
- if (t1_sge_intr_error_handler(adapter->sge))
- ret = IRQ_WAKE_THREAD;
- }
+ return 0;
+ if (cause & F_PL_INTR_SGE_ERR)
+ t1_sge_intr_error_handler(adapter->sge);
if (cause & F_PL_INTR_TP)
t1_tp_intr_handler(adapter->tp);
if (cause & F_PL_INTR_ESPI)
t1_espi_intr_handler(adapter->espi);
- if (cause & F_PL_INTR_PCIX) {
- if (t1_pci_intr_handler(adapter))
- ret = IRQ_WAKE_THREAD;
- }
- if (cause & F_PL_INTR_EXT) {
- /* Wake the threaded interrupt to handle external interrupts as
- * we require a process context. We disable EXT interrupts in
- * the interim and let the thread reenable them when it's done.
- */
- adapter->pending_thread_intr |= F_PL_INTR_EXT;
- adapter->slow_intr_mask &= ~F_PL_INTR_EXT;
- writel(adapter->slow_intr_mask | F_PL_INTR_SGE_DATA,
- adapter->regs + A_PL_ENABLE);
- ret = IRQ_WAKE_THREAD;
- }
+ if (cause & F_PL_INTR_PCIX)
+ t1_pci_intr_handler(adapter);
+ if (cause & F_PL_INTR_EXT)
+ t1_elmer0_ext_intr(adapter);
/* Clear the interrupts just processed. */
writel(cause, adapter->regs + A_PL_CAUSE);
readl(adapter->regs + A_PL_CAUSE); /* flush writes */
- return ret;
+ return 1;
}
-irqreturn_t t1_slow_intr_handler(adapter_t *adapter)
+int t1_slow_intr_handler(adapter_t *adapter)
{
#ifdef CONFIG_CHELSIO_T1_1G
if (!t1_is_asic(adapter))
--
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