From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/drivers/gpu/drm/nouveau/dispnv50/atom.h | 49 +++++++++++++++++++++++++++++++++++++++++++++++--
1 files changed, 47 insertions(+), 2 deletions(-)
diff --git a/kernel/drivers/gpu/drm/nouveau/dispnv50/atom.h b/kernel/drivers/gpu/drm/nouveau/dispnv50/atom.h
index 908feb1..93f8f4f 100644
--- a/kernel/drivers/gpu/drm/nouveau/dispnv50/atom.h
+++ b/kernel/drivers/gpu/drm/nouveau/dispnv50/atom.h
@@ -2,6 +2,9 @@
#define __NV50_KMS_ATOM_H__
#define nv50_atom(p) container_of((p), struct nv50_atom, state)
#include <drm/drm_atomic.h>
+#include "crc.h"
+
+struct nouveau_encoder;
struct nv50_atom {
struct drm_atomic_state state;
@@ -18,6 +21,7 @@
struct {
u32 mask;
+ u32 owned;
u32 olut;
} wndw;
@@ -54,9 +58,10 @@
u64 offset:40;
u8 buffer:1;
u8 mode:4;
- u8 size:2;
+ u16 size:11;
u8 range:2;
u8 output_mode:2;
+ void (*load)(struct drm_color_lut *, int size, void __iomem *);
} olut;
struct {
@@ -113,7 +118,17 @@
u8 nhsync:1;
u8 nvsync:1;
u8 depth:4;
+ u8 crc_raster:2;
+ u8 bpc;
} or;
+
+ struct nv50_crc_atom crc;
+
+ /* Currently only used for MST */
+ struct {
+ int pbn;
+ u8 tu:6;
+ } dp;
union nv50_head_atom_mask {
struct {
@@ -126,6 +141,7 @@
bool ovly:1;
bool dither:1;
bool procamp:1;
+ bool crc:1;
bool or:1;
};
u16 mask;
@@ -139,6 +155,19 @@
if (IS_ERR(statec))
return (void *)statec;
return nv50_head_atom(statec);
+}
+
+static inline struct drm_encoder *
+nv50_head_atom_get_encoder(struct nv50_head_atom *atom)
+{
+ struct drm_encoder *encoder;
+
+ /* We only ever have a single encoder */
+ drm_for_each_encoder_mask(encoder, atom->state.crtc->dev,
+ atom->state.encoder_mask)
+ return encoder;
+
+ return NULL;
}
#define nv50_wndw_atom(p) container_of((p), struct nv50_wndw_atom, state)
@@ -169,11 +198,18 @@
u8 buffer:1;
u8 enable:2;
u8 mode:4;
- u8 size:2;
+ u16 size:11;
u8 range:2;
u8 output_mode:2;
+ void (*load)(struct drm_color_lut *, int size,
+ void __iomem *);
} i;
} xlut;
+
+ struct {
+ u32 matrix[12];
+ bool valid;
+ } csc;
struct {
u8 mode:2;
@@ -207,14 +243,23 @@
u16 y;
} point;
+ struct {
+ u8 depth;
+ u8 k1;
+ u8 src_color:4;
+ u8 dst_color:4;
+ } blend;
+
union nv50_wndw_atom_mask {
struct {
bool ntfy:1;
bool sema:1;
bool xlut:1;
+ bool csc:1;
bool image:1;
bool scale:1;
bool point:1;
+ bool blend:1;
};
u8 mask;
} set, clr;
--
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