From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/powerpc/include/asm/book3s/64/tlbflush.h | 19 ++++++-------------
1 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/kernel/arch/powerpc/include/asm/book3s/64/tlbflush.h b/kernel/arch/powerpc/include/asm/book3s/64/tlbflush.h
index ebf572e..dcb5c38 100644
--- a/kernel/arch/powerpc/include/asm/book3s/64/tlbflush.h
+++ b/kernel/arch/powerpc/include/asm/book3s/64/tlbflush.h
@@ -147,19 +147,12 @@
flush_tlb_page(vma, address);
}
-/*
- * flush the page walk cache for the address
- */
-static inline void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address)
-{
- /*
- * Flush the page table walk cache on freeing a page table. We already
- * have marked the upper/higher level page table entry none by now.
- * So it is safe to flush PWC here.
- */
- if (!radix_enabled())
- return;
+extern bool tlbie_capable;
+extern bool tlbie_enabled;
- radix__flush_tlb_pwc(tlb, address);
+static inline bool cputlb_use_tlbie(void)
+{
+ return tlbie_enabled;
}
+
#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H */
--
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