From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/rk3xxx.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/rk3xxx.dtsi b/kernel/arch/arm/boot/dts/rk3xxx.dtsi
index 701667b..637ce78 100644
--- a/kernel/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/kernel/arch/arm/boot/dts/rk3xxx.dtsi
@@ -32,7 +32,7 @@
spi1 = &spi1;
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -70,6 +70,7 @@
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
arm,pl330-broken-no-flushp;
+ arm,pl330-periph-burst;
clocks = <&cru ACLK_DMA2>;
clock-names = "apb_pclk";
};
@@ -93,7 +94,7 @@
status = "disabled";
};
- L2: l2-cache-controller@10138000 {
+ L2: cache-controller@10138000 {
compatible = "arm,pl310-cache";
reg = <0x10138000 0x1000>;
cache-unified;
@@ -110,6 +111,13 @@
reg = <0x1013c200 0x20>;
interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cru CORE_PERI>;
+ status = "disabled";
+ /* The clock source and the sched_clock provided by the arm_global_timer
+ * on Rockchip rk3066a/rk3188 are quite unstable because their rates
+ * depend on the CPU frequency.
+ * Keep the arm_global_timer disabled in order to have the
+ * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
+ */
};
local_timer: local-timer@1013c600 {
@@ -147,6 +155,46 @@
clock-names = "baudclk", "apb_pclk";
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
status = "disabled";
+ };
+
+ qos_gpu: qos@1012d000 {
+ compatible = "syscon";
+ reg = <0x1012d000 0x20>;
+ };
+
+ qos_vpu: qos@1012e000 {
+ compatible = "syscon";
+ reg = <0x1012e000 0x20>;
+ };
+
+ qos_lcdc0: qos@1012f000 {
+ compatible = "syscon";
+ reg = <0x1012f000 0x20>;
+ };
+
+ qos_cif0: qos@1012f080 {
+ compatible = "syscon";
+ reg = <0x1012f080 0x20>;
+ };
+
+ qos_ipp: qos@1012f100 {
+ compatible = "syscon";
+ reg = <0x1012f100 0x20>;
+ };
+
+ qos_lcdc1: qos@1012f180 {
+ compatible = "syscon";
+ reg = <0x1012f180 0x20>;
+ };
+
+ qos_cif1: qos@1012f200 {
+ compatible = "syscon";
+ reg = <0x1012f200 0x20>;
+ };
+
+ qos_rga: qos@1012f280 {
+ compatible = "syscon";
+ reg = <0x1012f280 0x20>;
};
usb_otg: usb@10180000 {
@@ -193,7 +241,7 @@
status = "disabled";
};
- mmc0: dwmmc@10214000 {
+ mmc0: mmc@10214000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10214000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
@@ -207,7 +255,7 @@
status = "disabled";
};
- mmc1: dwmmc@10218000 {
+ mmc1: mmc@10218000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x10218000 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
@@ -221,7 +269,7 @@
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk2928-dw-mshc";
reg = <0x1021c000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -249,7 +297,7 @@
compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
reg = <0x20004000 0x100>;
- reboot_mode: reboot-mode {
+ reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x40>;
mode-normal = <BOOT_NORMAL>;
--
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