From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/rk312x.dtsi | 87 ++++++++++++++++++++++---------------------
1 files changed, 44 insertions(+), 43 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/rk312x.dtsi b/kernel/arch/arm/boot/dts/rk312x.dtsi
index 8f879eb..d3f61b1 100644
--- a/kernel/arch/arm/boot/dts/rk312x.dtsi
+++ b/kernel/arch/arm/boot/dts/rk312x.dtsi
@@ -57,9 +57,6 @@
aliases {
ethernet0 = &gmac;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -67,6 +64,10 @@
mmc0 = &sdmmc;
mmc1 = &sdio;
mmc2 = &emmc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ spi0 = &spi0;
};
cpus {
@@ -113,8 +114,8 @@
clocks = <&cru PLL_APLL>;
rockchip,leakage-voltage-sel = <
1 13 0
- 14 18 1
- 18 254 2
+ 14 49 1
+ 50 254 2
>;
nvmem-cells = <&cpu_leakage>;
nvmem-cell-names = "cpu_leakage";
@@ -233,7 +234,7 @@
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 456000
- SYS_STATUS_SUSPEND 456000
+ SYS_STATUS_SUSPEND 300000
SYS_STATUS_REBOOT 456000
>;
auto-min-freq = <456000>;
@@ -247,6 +248,7 @@
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1025000>;
+ status = "disabled";
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
@@ -615,7 +617,6 @@
clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
clock-names = "aclk_rga", "hclk_rga", "sclk_rga";
power-domains = <&power RK3128_PD_VIO>;
- dma-coherent;
status = "disabled";
};
@@ -670,12 +671,12 @@
compatible = "rockchip,rk3128-mipi-dsi";
reg = <0x10110000 0x4000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>, <&video_phy>;
- clock-names = "pclk", "h2p", "hs_clk";
+ clocks = <&cru PCLK_MIPI>, <&cru HCLK_VIO_H2P>;
+ clock-names = "pclk", "hclk";
resets = <&cru SRST_VIO_MIPI_DSI>;
reset-names = "apb";
phys = <&video_phy>;
- phy-names = "mipi_dphy";
+ phy-names = "dphy";
power-domains = <&power RK3128_PD_VIO>;
rockchip,grf = <&grf>;
#address-cells = <1>;
@@ -831,12 +832,11 @@
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
- clock-freq-min-max = <400000 50000000>;
- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
- clock-names = "biu", "ciu";
+ max-frequency = <50000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
dmas = <&pdma 10>;
dma-names = "rx-tx";
- num-slots = <1>;
fifo-depth = <0x100>;
bus-width = <4>;
status = "disabled";
@@ -996,14 +996,15 @@
};
video_phy: video-phy@20038000 {
- compatible = "rockchip,rk3128-video-phy";
+ compatible = "rockchip,rk3128-dsi-dphy", "rockchip,rk3128-video-phy";
reg = <0x20038000 0x4000>, <0x10110000 0x4000>;
+ reg-names = "phy", "host";
clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>,
<&cru PCLK_MIPI>;
- clock-names = "ref", "pclk_phy", "pclk_host";
+ clock-names = "ref", "pclk", "pclk_host";
#clock-cells = <0>;
resets = <&cru SRST_MIPIPHY_P>;
- reset-names = "rst";
+ reset-names = "apb";
power-domains = <&power RK3128_PD_VIO>;
#phy-cells = <0>;
status = "disabled";
@@ -1180,7 +1181,7 @@
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>;
+ pinctrl-0 = <&spi0m0_tx &spi0m0_rx &spi0m0_clk &spi0m0_cs0 &spi0m0_cs1>;
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
@@ -1290,10 +1291,6 @@
pcfg_pull_default: pcfg_pull_default {
bias-pull-pin-default;
- };
-
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
};
pcfg_output_high: pcfg-output-high {
@@ -1420,8 +1417,8 @@
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <2 RK_PD2 2 &pcfg_pull_up>,
- <2 RK_PD3 2 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>,
+ <2 RK_PD3 2 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
@@ -1435,8 +1432,8 @@
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <1 RK_PB1 2 &pcfg_pull_up>,
- <1 RK_PB2 2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>,
+ <1 RK_PB2 2 &pcfg_pull_default>;
};
uart1_cts: uart1-cts {
@@ -1450,8 +1447,8 @@
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
- <1 RK_PC3 2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+ <1 RK_PC3 2 &pcfg_pull_none>;
};
uart2_cts: uart2-cts {
@@ -1466,6 +1463,10 @@
sdmmc {
sdmmc_clk: sdmmc-clk {
rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+
+ sdmmc_det: sdmmc-det {
+ rockchip,pins = <1 RK_PC1 1 &pcfg_pull_none>;
};
sdmmc_cmd: sdmmc-cmd {
@@ -1607,60 +1608,60 @@
};
};
- spi {
- spi0_clk: spi0-clk {
+ spi0 {
+ spi0m0_clk: spi0m0-clk {
rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>;
};
- spi0_cs0: spi0-cs0 {
+ spi0m0_cs0: spi0m0-cs0 {
rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>;
};
- spi0_tx: spi0-tx {
+ spi0m0_tx: spi0m0-tx {
rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>;
};
- spi0_rx: spi0-rx {
+ spi0m0_rx: spi0m0-rx {
rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>;
};
- spi0_cs1: spi0-cs1 {
+ spi0m0_cs1: spi0m0-cs1 {
rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>;
};
- spi1_clk: spi1-clk {
+ spi0m1_clk: spi0m1-clk {
rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>;
};
- spi1_cs0: spi1-cs0 {
+ spi0m1_cs0: spi0m1-cs0 {
rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>;
};
- spi1_tx: spi1-tx {
+ spi0m1_tx: spi0m1-tx {
rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>;
};
- spi1_rx: spi1-rx {
+ spi0m1_rx: spi0m1-rx {
rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>;
};
- spi1_cs1: spi1-cs1 {
+ spi0m1_cs1: spi0m1-cs1 {
rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>;
};
- spi2_clk: spi2-clk {
+ spi0m2_clk: spi0m2-clk {
rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>;
};
- spi2_cs0: spi2-cs0 {
+ spi0m2_cs0: spi0m2-cs0 {
rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>;
};
- spi2_tx: spi2-tx {
+ spi0m2_tx: spi0m2-tx {
rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>;
};
- spi2_rx: spi2-rx {
+ spi0m2_rx: spi0m2-rx {
rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>;
};
};
--
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