From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/rk3036.dtsi | 325 +++++++++++++++++++++++++++++++++++-------------------
1 files changed, 211 insertions(+), 114 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/rk3036.dtsi b/kernel/arch/arm/boot/dts/rk3036.dtsi
index ff5710b..b290a77 100644
--- a/kernel/arch/arm/boot/dts/rk3036.dtsi
+++ b/kernel/arch/arm/boot/dts/rk3036.dtsi
@@ -18,6 +18,9 @@
aliases {
ethernet0 = &emac;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
@@ -85,7 +88,7 @@
};
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -138,7 +141,7 @@
#clock-cells = <0>;
};
- bus_intmem@10080000 {
+ bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
@@ -152,24 +155,40 @@
};
gpu: gpu@10090000 {
- compatible = "rockchip,rk3036-mali", "arm,mali-400";
+ compatible = "arm,mali400";
reg = <0x10090000 0x10000>;
+ upthreshold = <40>;
+ downdifferential = <10>;
+
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gp",
- "gpmmu",
- "pp0",
- "ppmmu0";
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+
+ interrupt-names = "Mali_GP_IRQ",
+ "Mali_GP_MMU_IRQ",
+ "Mali_PP0_IRQ",
+ "Mali_PP0_MMU_IRQ";
+
+ clocks = <&cru SCLK_GPU>;
+ clock-names = "clk_mali";
assigned-clocks = <&cru SCLK_GPU>;
assigned-clock-rates = <400000000>;
assigned-clock-parents = <&cru PLL_DPLL>;
+ power-domains = <&power RK3036_PD_GPU>;
operating-points-v2 = <&gpu_opp_table>;
- clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
- clock-names = "bus", "core";
- resets = <&cru SRST_GPU>;
+
status = "disabled";
+
+ gpu_power_model: power_model {
+ compatible = "arm,mali-simple-power-model";
+ voltage = <900>;
+ frequency = <500>;
+ static-power = <300>;
+ dynamic-power = <396>;
+ ts = <32000 4700 (-80) 2>;
+ thermal-zone = "soc-thermal";
+ };
};
gpu_opp_table: opp-table1 {
@@ -185,34 +204,36 @@
};
};
- vpu: video-codec@10108000 {
- compatible = "rockchip,rk3036-vpu", "rockchip,rk3288-vpu";
- reg = <0x10108000 0x800>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "vepu", "vdpu";
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
- clock-names = "aclk", "hclk";
- iommus = <&vpu_mmu>;
- /*
- * 3036's vpu could not run higher than 300M
- */
- assigned-clocks = <&cru ACLK_VCODEC>;
- assigned-clock-rates = <297000000>;
- assigned-clock-parents = <&cru PLL_GPLL>;
- power-domains = <&power RK3036_PD_VPU>;
+ mpp_srv: mpp-srv {
+ compatible = "rockchip,mpp-service";
+ rockchip,taskqueue-count = <1>;
+ rockchip,resetgroup-count = <1>;
+ rockchip,grf = <&grf>;
+ rockchip,grf-offset = <0x0144>;
+ rockchip,grf-values = <0x0008000a>, <0x00080002>;
+ rockchip,grf-names = "grf_rkvdec", "grf_vdpu1";
status = "disabled";
};
- vpu_service: vpu-service@10108400 {
- compatible = "rockchip,sub";
+ vdpu: vdpu@10108400 {
+ compatible = "rockchip,vpu-decoder-rk3036";
reg = <0x10108400 0x400>;
- dev_mode = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec";
+ rockchip,normal-rates = <297000000>, <0>;
+ assigned-clocks = <&cru ACLK_VCODEC>;
+ assigned-clock-rates = <297000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>;
+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>;
+ reset-names = "shared_video_a", "shared_video_h";
iommus = <&vpu_mmu>;
- allocator = <1>;
power-domains = <&power RK3036_PD_VPU>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
+ status = "disabled";
};
vpu_mmu: iommu@10108800 {
@@ -220,20 +241,32 @@
reg = <0x10108800 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
- hevc_service: hevc-service@1010c000 {
- compatible = "rockchip,sub";
+ hevc: hevc_service@1010c000 {
+ compatible = "rockchip,hevc-decoder-rk3036";
reg = <0x1010c000 0x400>;
- dev_mode = <1>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq_dec";
- allocator = <1>;
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>, <&cru ACLK_HEVC>;
+ clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
+ rockchip,normal-rates = <297000000>, <0>, <200000000>;
+ assigned-clocks = <&cru ACLK_VCODEC>;
+ assigned-clock-rates = <297000000>;
+ assigned-clock-parents = <&cru PLL_GPLL>;
+ resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>, <&cru SRST_HEVC>;
+ reset-names = "shared_video_a", "shared_video_h", "video_core";
iommus = <&hevc_mmu>;
+ rockchip,srv = <&mpp_srv>;
+ rockchip,taskqueue-node = <0>;
+ rockchip,resetgroup-node = <0>;
power-domains = <&power RK3036_PD_VPU>;
+ status = "disabled";
};
hevc_mmu: iommu@1010c440 {
@@ -241,28 +274,9 @@
reg = <0x1010c440 0x40>, <0x1010c480 0x40>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hevc_mmu";
+ clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
+ clock-names = "aclk", "iface";
#iommu-cells = <0>;
- power-domains = <&power RK3036_PD_VPU>;
- status = "disabled";
- };
-
- vpu_combo: vpu-combo {
- compatible = "rockchip,vpu_combo";
- rockchip,grf = <&grf>;
- subcnt = <2>;
- rockchip,sub = <&hevc_service>, <&vpu_service>;
- mode_bit = <3>;
- mode_ctrl = <0x144>;
- clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>,
- <&cru ACLK_HEVC>;
- clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core";
- /* RK3036's vpu could not run higher than 300M */
- assigned-clocks = <&cru ACLK_VCODEC>;
- assigned-clock-rates = <297000000>;
- assigned-clock-parents = <&cru PLL_GPLL>;
- resets = <&cru SRST_VCODEC_A>, <&cru SRST_VCODEC_H>,
- <&cru SRST_HEVC>;
- reset-names = "video_a", "video_h", "video";
power-domains = <&power RK3036_PD_VPU>;
status = "disabled";
};
@@ -284,6 +298,37 @@
vop_out_hdmi: endpoint@0 {
reg = <0>;
remote-endpoint = <&hdmi_in_vop>;
+ };
+ vop_out_tve: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&tve_in_vop>;
+ };
+ };
+ };
+
+ tve: tve@10118200 {
+ compatible = "rockchip,rk3036-tve";
+ reg = <0x10118200 0x100>;
+ clocks = <&cru ACLK_VIO>;
+ clock-names = "aclk";
+ rockchip,saturation = <0x00386346>;
+ rockchip,brightcontrast = <0x00008b00>;
+ rockchip,adjtiming = <0xa6c00880>;
+ rockchip,lumafilter0 = <0x02ff0000>;
+ rockchip,lumafilter1 = <0xf40202fd>;
+ rockchip,lumafilter2 = <0xf332d919>;
+ rockchip,daclevel = <0x3e>;
+ rockchip,grf = <&grf>;
+ status = "disabled";
+
+ ports {
+ tve_in: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ tve_in_vop: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vop_out_tve>;
+ };
};
};
};
@@ -363,6 +408,20 @@
status = "disabled";
};
+ spdif_tx: spdif-tx@10204000 {
+ compatible = "rockchip,rk3066-spdif";
+ reg = <0x10204000 0x1000>;
+ clocks = <&cru SCLK_SPDIF>, <&cru SCLK_SPDIF>;
+ clock-names = "mclk", "hclk";
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&pdma 13>;
+ dma-names = "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spdif_out>;
+ #sound-dai-cells = <0>;
+ status = "disabled";
+ };
+
sfc: sfc@10208000 {
compatible = "rockchip,sfc";
reg = <0x10208000 0x200>;
@@ -383,10 +442,12 @@
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_MMC0>;
reset-names = "reset";
+ no-mmc;
+ no-sdio;
status = "disabled";
};
- sdio: dwmmc@10218000 {
+ sdio: mmc@10218000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x10218000 0x4000>;
max-frequency = <37500000>;
@@ -397,10 +458,12 @@
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
resets = <&cru SRST_SDIO>;
reset-names = "reset";
+ no-mmc;
+ no-sd;
status = "disabled";
};
- emmc: dwmmc@1021c000 {
+ emmc: mmc@1021c000 {
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x1021c000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -411,13 +474,14 @@
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
- default-sample-phase = <158>;
+ rockchip,default-sample-phase = <158>;
disable-wp;
dmas = <&pdma 12>;
dma-names = "rx-tx";
fifo-depth = <0x100>;
non-removable;
- supports-emmc;
+ no-sdio;
+ no-sd;
pinctrl-names = "default";
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
resets = <&cru SRST_EMMC>;
@@ -429,8 +493,6 @@
compatible = "rockchip,rk3036-i2s", "rockchip,rk3066-i2s";
reg = <0x10220000 0x4000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
clock-names = "i2s_clk", "i2s_hclk";
clocks = <&cru SCLK_I2S>, <&cru HCLK_I2S>;
assigned-clocks = <&cru SCLK_I2S_PRE>;
@@ -440,7 +502,13 @@
resets = <&cru SRST_I2S>;
reset-names = "reset-m";
pinctrl-names = "default";
- pinctrl-0 = <&i2s_bus>;
+ pinctrl-0 = <&i2s_mclk
+ &i2s_sclk
+ &i2s_lrclkrx
+ &i2s_lrclktx
+ &i2s_sdo
+ &i2s_sdi>;
+ #sound-dai-cells = <0>;
status = "disabled";
};
@@ -457,6 +525,8 @@
grf: syscon@20008000 {
compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
reg = <0x20008000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
reboot-mode {
compatible = "syscon-reboot-mode";
@@ -481,12 +551,42 @@
<&cru ACLK_HEVC>;
pm_qos = <&qos_vpu>;
};
+ pd_gpu@RK3036_PD_GPU {
+ reg = <RK3036_PD_GPU>;
+ clocks = <&cru SCLK_GPU>;
+ };
+ };
+ usb2phy: usb2-phy@17c {
+ compatible = "rockchip,rk3036-usb2phy";
+ reg = <0x017c 0x0c>;
+ clocks = <&cru SCLK_OTGPHY0>;
+ clock-names = "phyclk";
+ #clock-cells = <0>;
+ clock-output-names = "usb480m_phy";
+ status = "disabled";
+
+ u2phy_otg: otg-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "otg-bvalid", "otg-id",
+ "linestate";
+ status = "disabled";
+ };
+
+ u2phy_host: host-port {
+ #phy-cells = <0>;
+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "linestate";
+ status = "disabled";
+ };
};
};
acodec: acodec-ana@20030000 {
- compatible = "rk3036-codec";
+ compatible = "rockchip,rk3036-codec";
reg = <0x20030000 0x4000>;
rockchip,grf = <&grf>;
clock-names = "acodec_pclk";
@@ -518,25 +618,6 @@
};
};
- hdmi_sound: hdmi-sound {
- compatible = "simple-audio-card";
- simple-audio-card,name = "rockchip,hdmi";
- simple-audio-card,widgets = "Headphone", "Out Jack",
- "Line", "In Jack";
- status = "disabled";
-
- simple-audio-card,dai-link {
- format = "i2s";
- mclk-fs = <256>;
- cpu {
- sound-dai = <&i2s>;
- };
- codec {
- sound-dai = <&hdmi>;
- };
- };
- };
-
timer: timer@20044000 {
compatible = "rockchip,rk3036-timer", "rockchip,rk3288-timer";
reg = <0x20044000 0x20>;
@@ -553,7 +634,7 @@
};
pwm0: pwm@20050000 {
- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050000 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -564,7 +645,7 @@
};
pwm1: pwm@20050010 {
- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050010 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -575,7 +656,7 @@
};
pwm2: pwm@20050020 {
- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050020 0x10>;
#pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
@@ -586,9 +667,10 @@
};
pwm3: pwm@20050030 {
- compatible = "rockchip,rk3036-pwm", "rockchip,rk2928-pwm";
+ compatible = "rockchip,rk3036-pwm", "rockchip,rk3288-pwm";
reg = <0x20050030 0x10>;
- #pwm-cells = <2>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ #pwm-cells = <3>;
clocks = <&cru PCLK_PWM>;
clock-names = "pwm";
pinctrl-names = "active";
@@ -681,7 +763,7 @@
compatible = "rockchip,rockchip-spi";
reg = <0x20074000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- clocks =<&cru PCLK_SPI>, <&cru SCLK_SPI>;
+ clocks = <&cru PCLK_SPI>, <&cru SCLK_SPI>;
clock-names = "apb-pclk","spi_pclk";
dmas = <&pdma 8>, <&pdma 9>;
dma-names = "tx", "rx";
@@ -703,6 +785,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x2007c000 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus";
clocks = <&cru PCLK_GPIO0>;
gpio-controller;
@@ -716,6 +799,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x20080000 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus";
clocks = <&cru PCLK_GPIO1>;
gpio-controller;
@@ -729,6 +813,7 @@
compatible = "rockchip,gpio-bank";
reg = <0x20084000 0x100>;
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "bus";
clocks = <&cru PCLK_GPIO2>;
gpio-controller;
@@ -742,35 +827,31 @@
bias-pull-pin-default;
};
- pcfg_pull_up: pcfg-pull-up {
- bias-pull-up;
- };
-
pcfg_pull_none: pcfg-pull-none {
bias-disable;
};
pwm0 {
pwm0_pin: pwm0-pin {
- rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA0 2 &pcfg_pull_default>;
};
};
pwm1 {
pwm1_pin: pwm1-pin {
- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
};
};
pwm2 {
pwm2_pin: pwm2-pin {
- rockchip,pins = <0 RK_PA1 2 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PA1 2 &pcfg_pull_default>;
};
};
pwm3 {
pwm3_pin: pwm3-pin {
- rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
+ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_default>;
};
};
@@ -845,6 +926,12 @@
};
};
+ spdif_tx {
+ spdif_out: spdif-out {
+ rockchip,pins = <0 RK_PD4 1 &pcfg_pull_default>;
+ };
+ };
+
emac {
emac_xfer: emac-xfer {
rockchip,pins = <2 RK_PB2 1 &pcfg_pull_default>, /* crs_dvalid */
@@ -885,20 +972,30 @@
};
i2s {
- i2s_bus: i2s-bus {
- rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>,
- <1 RK_PA1 1 &pcfg_pull_default>,
- <1 RK_PA2 1 &pcfg_pull_default>,
- <1 RK_PA3 1 &pcfg_pull_default>,
- <1 RK_PA4 1 &pcfg_pull_default>,
- <1 RK_PA5 1 &pcfg_pull_default>;
+ i2s_mclk: i2s-mclk {
+ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>;
+ };
+ i2s_sclk: i2s-sclk {
+ rockchip,pins = <1 RK_PA1 1 &pcfg_pull_default>;
+ };
+ i2s_lrclkrx: i2s-lrclkrx {
+ rockchip,pins = <1 RK_PA2 1 &pcfg_pull_default>;
+ };
+ i2s_lrclktx: i2s-lrclktx {
+ rockchip,pins = <1 RK_PA3 1 &pcfg_pull_default>;
+ };
+ i2s_sdo: i2s-sdo {
+ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>;
+ };
+ i2s_sdi: i2s-sdi {
+ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_default>;
};
};
hdmi {
hdmi_ctl: hdmi-ctl {
- rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
- <1 RK_PB1 1 &pcfg_pull_none>,
+ rockchip,pins = <1 RK_PB0 1 &pcfg_pull_none>,
+ <1 RK_PB1 1 &pcfg_pull_none>,
<1 RK_PB2 1 &pcfg_pull_none>,
<1 RK_PB3 1 &pcfg_pull_none>;
};
@@ -906,8 +1003,8 @@
uart0 {
uart0_xfer: uart0-xfer {
- rockchip,pins = <0 RK_PC0 1 &pcfg_pull_up>,
- <0 RK_PC1 1 &pcfg_pull_up>;
+ rockchip,pins = <0 RK_PC0 1 &pcfg_pull_default>,
+ <0 RK_PC1 1 &pcfg_pull_default>;
};
uart0_cts: uart0-cts {
@@ -921,16 +1018,16 @@
uart1 {
uart1_xfer: uart1-xfer {
- rockchip,pins = <2 RK_PC6 1 &pcfg_pull_up>,
- <2 RK_PC7 1 &pcfg_pull_up>;
+ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_default>,
+ <2 RK_PC7 1 &pcfg_pull_default>;
};
/* no rts / cts for uart1 */
};
uart2 {
uart2_xfer: uart2-xfer {
- rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>,
- <1 RK_PC3 2 &pcfg_pull_up>;
+ rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>,
+ <1 RK_PC3 2 &pcfg_pull_default>;
};
/* no rts / cts for uart2 */
};
--
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