From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 67 ++++++++++++++++-----------------
1 files changed, 32 insertions(+), 35 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi b/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
index b90cea8..b5ec4f4 100644
--- a/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
+++ b/kernel/arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi
@@ -24,46 +24,18 @@
"Headphone Jack", "MICBIAS",
"IN12", "Headphone Jack",
"Speakers", "SPKL",
- "Speakers", "SPKR";
-
- assigned-clocks = <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MOUT_USER_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>,
- <&clock_audss EXYNOS_MOUT_I2S>,
- <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock_audss EXYNOS_DOUT_AUD_BUS>,
- <&clock_audss EXYNOS_DOUT_I2S>;
-
- assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
- <&clock CLK_MOUT_EPLL>,
- <&clock CLK_MOUT_MAU_EPLL>,
- <&clock CLK_MAU_EPLL>,
- <&clock_audss EXYNOS_MOUT_AUDSS>;
-
- assigned-clock-rates = <0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <196608001>,
- <(196608002 / 2)>,
- <196608000>;
+ "Speakers", "SPKR",
+ "I2S Playback", "Mixer DAI TX",
+ "HiFi Playback", "Mixer DAI TX",
+ "Mixer DAI RX", "HiFi Capture";
cpu {
- sound-dai = <&i2s0 0>;
+ sound-dai = <&i2s0 0>, <&i2s0 1>;
};
codec {
sound-dai = <&hdmi>, <&max98090>;
};
};
-};
-
-&clock_audss {
- assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
- <&clock CLK_FOUT_EPLL>;
- assigned-clock-rates = <(196608000 / 256)>,
- <196608000>;
};
&hsi2c_5 {
@@ -81,6 +53,31 @@
&i2s0 {
status = "okay";
- assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
- assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
+ assigned-clocks = <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MOUT_USER_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_MOUT_I2S>,
+ <&i2s0 CLK_I2S_RCLK_SRC>,
+ <&clock_audss EXYNOS_DOUT_SRP>,
+ <&clock_audss EXYNOS_DOUT_AUD_BUS>,
+ <&clock_audss EXYNOS_DOUT_I2S>;
+
+ assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
+ <&clock CLK_MOUT_EPLL>,
+ <&clock CLK_MOUT_MAU_EPLL>,
+ <&clock CLK_MAU_EPLL>,
+ <&clock_audss EXYNOS_MOUT_AUDSS>,
+ <&clock_audss EXYNOS_SCLK_I2S>;
+
+ assigned-clock-rates = <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <0>,
+ <196608001>,
+ <(196608002 / 2)>,
+ <196608000>;
+
};
--
Gitblit v1.6.2