From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/exynos4210.dtsi | 118 ++++++++++++++++++++++++++++++++++++++--------------------
1 files changed, 77 insertions(+), 41 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/exynos4210.dtsi b/kernel/arch/arm/boot/dts/exynos4210.dtsi
index b6091c2..fddc661 100644
--- a/kernel/arch/arm/boot/dts/exynos4210.dtsi
+++ b/kernel/arch/arm/boot/dts/exynos4210.dtsi
@@ -8,7 +8,7 @@
* www.linaro.org
*
* Samsung's Exynos4210 SoC device nodes are listed in this file. Exynos4210
- * based board files can include this file and provide values for board specfic
+ * based board files can include this file and provide values for board specific
* bindings.
*
* Note: This file does not include device nodes for all the controllers in
@@ -51,7 +51,7 @@
#cooling-cells = <2>; /* min followed by max */
};
- cpu@901 {
+ cpu1: cpu@901 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0x901>;
@@ -72,60 +72,53 @@
};
soc: soc {
- sysram: sysram@2020000 {
+ sysram: sram@2020000 {
compatible = "mmio-sram";
reg = <0x02020000 0x20000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x02020000 0x20000>;
- smp-sysram@0 {
+ smp-sram@0 {
compatible = "samsung,exynos4210-sysram";
reg = <0x0 0x1000>;
};
- smp-sysram@1f000 {
+ smp-sram@1f000 {
compatible = "samsung,exynos4210-sysram-ns";
reg = <0x1f000 0x1000>;
};
};
- pd_lcd1: lcd1-power-domain@10023ca0 {
+ pd_lcd1: power-domain@10023ca0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CA0 0x20>;
#power-domain-cells = <0>;
label = "LCD1";
};
- l2c: l2-cache-controller@10502000 {
+ l2c: cache-controller@10502000 {
compatible = "arm,pl310-cache";
reg = <0x10502000 0x1000>;
cache-unified;
cache-level = <2>;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
arm,tag-latency = <2 2 1>;
arm,data-latency = <2 2 1>;
};
- mct: mct@10050000 {
+ mct: timer@10050000 {
compatible = "samsung,exynos4210-mct";
reg = <0x10050000 0x800>;
- interrupt-parent = <&mct_map>;
- interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <1>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map =
- <0 &gic 0 57 IRQ_TYPE_LEVEL_HIGH>,
- <1 &gic 0 69 IRQ_TYPE_LEVEL_HIGH>,
- <2 &combiner 12 6>,
- <3 &combiner 12 7>,
- <4 &gic 0 42 IRQ_TYPE_LEVEL_HIGH>,
- <5 &gic 0 48 IRQ_TYPE_LEVEL_HIGH>;
- };
+ interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <&combiner 12 6>,
+ <&combiner 12 7>,
+ <&gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
};
watchdog: watchdog@10060000 {
@@ -298,6 +291,7 @@
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>;
+ opp-suspend;
};
};
@@ -367,29 +361,28 @@
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
+ opp-suspend;
};
};
};
+};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
- thermal-sensors = <&tmu 0>;
+&cpu_alert0 {
+ temperature = <85000>; /* millicelsius */
+};
- trips {
- cpu_alert0: cpu-alert-0 {
- temperature = <85000>; /* millicelsius */
- };
- cpu_alert1: cpu-alert-1 {
- temperature = <100000>; /* millicelsius */
- };
- cpu_alert2: cpu-alert-2 {
- temperature = <110000>; /* millicelsius */
- };
- };
- };
- };
+&cpu_alert1 {
+ temperature = <100000>; /* millicelsius */
+};
+
+&cpu_alert2 {
+ temperature = <110000>; /* millicelsius */
+};
+
+&cpu_thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+ thermal-sensors = <&tmu 0>;
};
&gic {
@@ -447,6 +440,43 @@
samsung,lcd-wb;
};
+&gpu {
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pp2",
+ "ppmmu2",
+ "pp3",
+ "ppmmu3";
+ operating-points-v2 = <&gpu_opp_table>;
+
+ gpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ opp-microvolt = <950000>;
+ };
+ opp-267000000 {
+ opp-hz = /bits/ 64 <267000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
+};
+
&mdma1 {
power-domains = <&pd_lcd0>;
};
@@ -459,6 +489,12 @@
<&clock CLK_MOUT_MIXER>, <&clock CLK_SCLK_MIXER>;
};
+&pmu {
+ interrupts = <2 2>, <3 2>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
+ status = "okay";
+};
+
&pmu_system_controller {
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
"clkout4", "clkout8", "clkout9";
--
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