From 6778948f9de86c3cfaf36725a7c87dcff9ba247f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 11 Dec 2023 08:20:59 +0000
Subject: [PATCH] kernel_5.10 no rt
---
kernel/arch/arm/boot/dts/bcm-nsp.dtsi | 64 +++++++++++++++++++++++++-------
1 files changed, 50 insertions(+), 14 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/bcm-nsp.dtsi b/kernel/arch/arm/boot/dts/bcm-nsp.dtsi
index 71918d2..1dae02b 100644
--- a/kernel/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/kernel/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -34,12 +34,20 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/bcm-nsp.h>
-#include "skeleton.dtsi"
-
/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "brcm,nsp";
model = "Broadcom Northstar Plus SoC";
interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ ethernet0 = &amac0;
+ ethernet1 = &amac1;
+ ethernet2 = &amac2;
+ };
cpus {
#address-cells = <1>;
@@ -69,7 +77,7 @@
interrupt-affinity = <&cpu0>, <&cpu1>;
};
- mpcore {
+ mpcore-bus@19000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
@@ -114,7 +122,7 @@
<0x20100 0x100>;
};
- L2: l2-cache {
+ L2: cache-controller@22000 {
compatible = "arm,pl310-cache";
reg = <0x22000 0x1000>;
cache-unified;
@@ -158,7 +166,7 @@
};
};
- axi {
+ axi@18000000 {
compatible = "simple-bus";
ranges = <0x00000000 0x18000000 0x0011c40c>;
#address-cells = <1>;
@@ -192,7 +200,7 @@
status = "disabled";
};
- dma@20000 {
+ dma: dma@20000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x20000 0x1000>;
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
@@ -207,9 +215,11 @@
clocks = <&iprocslow>;
clock-names = "apb_pclk";
#dma-cells = <1>;
+ dma-coherent;
+ status = "disabled";
};
- sdio: sdhci@21000 {
+ sdio: mmc@21000 {
compatible = "brcm,sdhci-iproc-cygnus";
reg = <0x21000 0x100>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
@@ -358,7 +368,7 @@
};
ccbtimer0: timer@34000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x34000 0x1000>;
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
@@ -367,7 +377,7 @@
};
ccbtimer1: timer@35000 {
- compatible = "arm,sp804";
+ compatible = "arm,sp804", "arm,primecell";
reg = <0x35000 0x1000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
@@ -377,10 +387,36 @@
srab: srab@36000 {
compatible = "brcm,nsp-srab";
- reg = <0x36000 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
+ reg = <0x36000 0x1000>,
+ <0x3f308 0x8>,
+ <0x3f410 0xc>;
+ reg-names = "srab", "mux_config", "sgmii";
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "link_state_p0",
+ "link_state_p1",
+ "link_state_p2",
+ "link_state_p3",
+ "link_state_p4",
+ "link_state_p5",
+ "link_state_p7",
+ "link_state_p8",
+ "phy",
+ "ts",
+ "imp_sleep_timer_p5",
+ "imp_sleep_timer_p7",
+ "imp_sleep_timer_p8";
status = "disabled";
/* ports are defined in board DTS */
@@ -402,7 +438,7 @@
reg = <0x39000 0x1000>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&iprocslow>, <&iprocslow>;
- clock-names = "wdogclk", "apb_pclk";
+ clock-names = "wdog_clk", "apb_pclk";
};
lcpll0: lcpll0@3f100 {
--
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