From 61598093bbdd283a7edc367d900f223070ead8d2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:43:03 +0000
Subject: [PATCH] add ax88772C AX88772C_eeprom_tools
---
kernel/drivers/clk/samsung/clk-exynos5433.c | 88 ++++++++++++++++++++++++++++++++++++++-----
1 files changed, 77 insertions(+), 11 deletions(-)
diff --git a/kernel/drivers/clk/samsung/clk-exynos5433.c b/kernel/drivers/clk/samsung/clk-exynos5433.c
index 0f2a9d7..f203074 100644
--- a/kernel/drivers/clk/samsung/clk-exynos5433.c
+++ b/kernel/drivers/clk/samsung/clk-exynos5433.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Chanwoo Choi <cw00.choi@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*
* Common Clock Framework support for Exynos5433 SoC.
*/
@@ -176,6 +173,17 @@
ENABLE_IP_TOP,
ENABLE_CMU_TOP,
ENABLE_CMU_TOP_DIV_STAT,
+};
+
+static const struct samsung_clk_reg_dump top_suspend_regs[] = {
+ /* force all aclk clocks enabled */
+ { ENABLE_ACLK_TOP, 0x67ecffed },
+ /* force all sclk_uart clocks enabled */
+ { ENABLE_SCLK_TOP_PERIC, 0x38 },
+ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
+ { ISP_PLL_CON0, 0x85cc0502 },
+ /* ISP PLL has to be enabled for suspend: reset value + ENABLE bit */
+ { AUD_PLL_CON0, 0x84830202 },
};
/* list of all parent clock list */
@@ -549,7 +557,7 @@
/* ENABLE_ACLK_TOP */
GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
- GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
+ GATE(CLK_ACLK_IMEM_SSSX_266, "aclk_imem_sssx_266",
"div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
29, CLK_IGNORE_UNUSED, 0),
GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
@@ -558,10 +566,10 @@
GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
ENABLE_ACLK_TOP, 25,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
- GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
+ GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_200",
ENABLE_ACLK_TOP, 24,
CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
- GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
+ GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_266",
ENABLE_ACLK_TOP, 23,
CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
@@ -793,6 +801,8 @@
.nr_clk_ids = TOP_NR_CLK,
.clk_regs = top_clk_regs,
.nr_clk_regs = ARRAY_SIZE(top_clk_regs),
+ .suspend_regs = top_suspend_regs,
+ .nr_suspend_regs = ARRAY_SIZE(top_suspend_regs),
};
static void __init exynos5433_cmu_top_init(struct device_node *np)
@@ -821,6 +831,13 @@
MUX_SEL_CPIF0,
DIV_CPIF,
ENABLE_SCLK_CPIF,
+};
+
+static const struct samsung_clk_reg_dump cpif_suspend_regs[] = {
+ /* force all sclk clocks enabled */
+ { ENABLE_SCLK_CPIF, 0x3ff },
+ /* MPHY PLL has to be enabled for suspend: reset value + ENABLE bit */
+ { MPHY_PLL_CON0, 0x81c70601 },
};
/* list of all parent clock list */
@@ -863,6 +880,8 @@
.nr_clk_ids = CPIF_NR_CLK,
.clk_regs = cpif_clk_regs,
.nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
+ .suspend_regs = cpif_suspend_regs,
+ .nr_suspend_regs = ARRAY_SIZE(cpif_suspend_regs),
};
static void __init exynos5433_cmu_cpif_init(struct device_node *np)
@@ -1548,6 +1567,13 @@
ENABLE_IP_PERIC2,
};
+static const struct samsung_clk_reg_dump peric_suspend_regs[] = {
+ /* pclk: sci, pmu, sysreg, gpio_{finger, ese, touch, nfc}, uart2-0 */
+ { ENABLE_PCLK_PERIC0, 0xe00ff000 },
+ /* sclk: uart2-0 */
+ { ENABLE_SCLK_PERIC, 0x7 },
+};
+
static const struct samsung_div_clock peric_div_clks[] __initconst = {
/* DIV_PERIC */
DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
@@ -1707,6 +1733,8 @@
.nr_clk_ids = PERIC_NR_CLK,
.clk_regs = peric_clk_regs,
.nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
+ .suspend_regs = peric_suspend_regs,
+ .nr_suspend_regs = ARRAY_SIZE(peric_suspend_regs),
};
static void __init exynos5433_cmu_peric_init(struct device_node *np)
@@ -3651,6 +3679,7 @@
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
+ struct clk_hw **hws;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -3673,8 +3702,10 @@
samsung_clk_register_gate(ctx, apollo_gate_clks,
ARRAY_SIZE(apollo_gate_clks));
+ hws = ctx->clk_data.hws;
+
exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
- mout_apollo_p[0], mout_apollo_p[1], 0x200,
+ hws[CLK_MOUT_APOLLO_PLL], hws[CLK_MOUT_BUS_PLL_APOLLO_USER], 0x200,
exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
CLK_CPU_HAS_E5433_REGS_LAYOUT);
@@ -3905,6 +3936,7 @@
{
void __iomem *reg_base;
struct samsung_clk_provider *ctx;
+ struct clk_hw **hws;
reg_base = of_iomap(np, 0);
if (!reg_base) {
@@ -3927,8 +3959,10 @@
samsung_clk_register_gate(ctx, atlas_gate_clks,
ARRAY_SIZE(atlas_gate_clks));
+ hws = ctx->clk_data.hws;
+
exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
- mout_atlas_p[0], mout_atlas_p[1], 0x200,
+ hws[CLK_MOUT_ATLAS_PLL], hws[CLK_MOUT_BUS_PLL_ATLAS_USER], 0x200,
exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
CLK_CPU_HAS_E5433_REGS_LAYOUT);
@@ -5438,6 +5472,35 @@
.clk_name = "aclk_cam1_400",
};
+/*
+ * Register offset definitions for CMU_IMEM
+ */
+#define ENABLE_ACLK_IMEM_SLIMSSS 0x080c
+#define ENABLE_PCLK_IMEM_SLIMSSS 0x0908
+
+static const unsigned long imem_clk_regs[] __initconst = {
+ ENABLE_ACLK_IMEM_SLIMSSS,
+ ENABLE_PCLK_IMEM_SLIMSSS,
+};
+
+static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
+ /* ENABLE_ACLK_IMEM_SLIMSSS */
+ GATE(CLK_ACLK_SLIMSSS, "aclk_slimsss", "aclk_imem_sssx_266",
+ ENABLE_ACLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
+
+ /* ENABLE_PCLK_IMEM_SLIMSSS */
+ GATE(CLK_PCLK_SLIMSSS, "pclk_slimsss", "aclk_imem_200",
+ ENABLE_PCLK_IMEM_SLIMSSS, 0, CLK_IGNORE_UNUSED, 0),
+};
+
+static const struct samsung_cmu_info imem_cmu_info __initconst = {
+ .gate_clks = imem_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(imem_gate_clks),
+ .nr_clk_ids = IMEM_NR_CLK,
+ .clk_regs = imem_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(imem_clk_regs),
+ .clk_name = "aclk_imem_200",
+};
struct exynos5433_cmu_data {
struct samsung_clk_reg_dump *clk_save;
@@ -5534,8 +5597,8 @@
data->nr_clk_save = info->nr_clk_regs;
data->clk_suspend = info->suspend_regs;
data->nr_clk_suspend = info->nr_suspend_regs;
- data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
- "#clock-cells");
+ data->nr_pclks = of_clk_get_parent_count(dev->of_node);
+
if (data->nr_pclks > 0) {
data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
data->nr_pclks, GFP_KERNEL);
@@ -5635,6 +5698,9 @@
.compatible = "samsung,exynos5433-cmu-mscl",
.data = &mscl_cmu_info,
}, {
+ .compatible = "samsung,exynos5433-cmu-imem",
+ .data = &imem_cmu_info,
+ }, {
},
};
--
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