From 61598093bbdd283a7edc367d900f223070ead8d2 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:43:03 +0000
Subject: [PATCH] add ax88772C AX88772C_eeprom_tools
---
kernel/drivers/clk/meson/clk-mpll.c | 50 +++++++++++++++++++++++++++++++++++++++-----------
1 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/kernel/drivers/clk/meson/clk-mpll.c b/kernel/drivers/clk/meson/clk-mpll.c
index 650f75c..fc9df48 100644
--- a/kernel/drivers/clk/meson/clk-mpll.c
+++ b/kernel/drivers/clk/meson/clk-mpll.c
@@ -12,7 +12,11 @@
*/
#include <linux/clk-provider.h>
-#include "clkc.h"
+#include <linux/module.h>
+#include <linux/spinlock.h>
+
+#include "clk-regmap.h"
+#include "clk-mpll.h"
#define SDM_DEN 16384
#define N2_MIN 4
@@ -111,20 +115,11 @@
else
__acquire(mpll->lock);
- /* Enable and set the fractional part */
+ /* Set the fractional part */
meson_parm_write(clk->map, &mpll->sdm, sdm);
- meson_parm_write(clk->map, &mpll->sdm_en, 1);
-
- /* Set additional fractional part enable if required */
- if (MESON_PARM_APPLICABLE(&mpll->ssen))
- meson_parm_write(clk->map, &mpll->ssen, 1);
/* Set the integer divider part */
meson_parm_write(clk->map, &mpll->n2, n2);
-
- /* Set the magic misc bit if required */
- if (MESON_PARM_APPLICABLE(&mpll->misc))
- meson_parm_write(clk->map, &mpll->misc, 1);
if (mpll->lock)
spin_unlock_irqrestore(mpll->lock, flags);
@@ -134,13 +129,46 @@
return 0;
}
+static int mpll_init(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_mpll_data *mpll = meson_clk_mpll_data(clk);
+
+ if (mpll->init_count)
+ regmap_multi_reg_write(clk->map, mpll->init_regs,
+ mpll->init_count);
+
+ /* Enable the fractional part */
+ meson_parm_write(clk->map, &mpll->sdm_en, 1);
+
+ /* Set spread spectrum if possible */
+ if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
+ unsigned int ss =
+ mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
+ meson_parm_write(clk->map, &mpll->ssen, ss);
+ }
+
+ /* Set the magic misc bit if required */
+ if (MESON_PARM_APPLICABLE(&mpll->misc))
+ meson_parm_write(clk->map, &mpll->misc, 1);
+
+ return 0;
+}
+
const struct clk_ops meson_clk_mpll_ro_ops = {
.recalc_rate = mpll_recalc_rate,
.round_rate = mpll_round_rate,
};
+EXPORT_SYMBOL_GPL(meson_clk_mpll_ro_ops);
const struct clk_ops meson_clk_mpll_ops = {
.recalc_rate = mpll_recalc_rate,
.round_rate = mpll_round_rate,
.set_rate = mpll_set_rate,
+ .init = mpll_init,
};
+EXPORT_SYMBOL_GPL(meson_clk_mpll_ops);
+
+MODULE_DESCRIPTION("Amlogic MPLL driver");
+MODULE_AUTHOR("Michael Turquette <mturquette@baylibre.com>");
+MODULE_LICENSE("GPL v2");
--
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