From 50a212ec906f7524620675f0c57357691c26c81f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 16 Oct 2024 01:20:19 +0000
Subject: [PATCH] 修改GPIO导出默认初始值
---
kernel/arch/arm/boot/dts/rv1108.dtsi | 168 +++++++++++++++++++++++++++++++++++++++++++------------
1 files changed, 130 insertions(+), 38 deletions(-)
diff --git a/kernel/arch/arm/boot/dts/rv1108.dtsi b/kernel/arch/arm/boot/dts/rv1108.dtsi
index f5c2560..b079c00 100644
--- a/kernel/arch/arm/boot/dts/rv1108.dtsi
+++ b/kernel/arch/arm/boot/dts/rv1108.dtsi
@@ -32,6 +32,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0xf00>;
+ clock-latency = <40000>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>; /* min followed by max */
dynamic-power-coefficient = <75>;
@@ -73,6 +74,7 @@
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ arm,cpu-registers-not-fw-configured;
clock-frequency = <24000000>;
};
@@ -83,7 +85,7 @@
#clock-cells = <0>;
};
- amba {
+ amba: bus {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@@ -101,7 +103,7 @@
};
};
- bus_intmem@10080000 {
+ bus_intmem: sram@10080000 {
compatible = "mmio-sram";
reg = <0x10080000 0x2000>;
#address-cells = <1>;
@@ -118,6 +120,7 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 6>, <&pdma 7>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m0_xfer>;
status = "disabled";
@@ -132,6 +135,7 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 4>, <&pdma 5>;
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "disabled";
@@ -146,6 +150,7 @@
clock-frequency = <24000000>;
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
clock-names = "baudclk", "apb_pclk";
+ dmas = <&pdma 2>, <&pdma 3>;
pinctrl-names = "default";
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
status = "disabled";
@@ -161,6 +166,7 @@
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_xfer>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -188,6 +194,7 @@
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_xfer>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -198,7 +205,7 @@
clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
clock-names = "spiclk", "apb_pclk";
dmas = <&pdma 8>, <&pdma 9>;
- #dma-cells = <2>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -210,7 +217,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
- pinctrl-names = "default";
+ pinctrl-names = "active";
pinctrl-0 = <&pwm4_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -222,7 +229,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
- pinctrl-names = "default";
+ pinctrl-names = "active";
pinctrl-0 = <&pwm5_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -234,7 +241,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
- pinctrl-names = "default";
+ pinctrl-names = "active";
pinctrl-0 = <&pwm6_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -246,7 +253,7 @@
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
clock-names = "pwm", "pclk";
- pinctrl-names = "default";
+ pinctrl-names = "active";
pinctrl-0 = <&pwm7_pin>;
#pwm-cells = <3>;
status = "disabled";
@@ -282,6 +289,14 @@
status = "disabled";
};
};
+ };
+
+ timer: timer@10350000 {
+ compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
+ reg = <0x10350000 0x20>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>, <&cru PCLK_TIMER>;
+ clock-names = "timer", "pclk";
};
watchdog: wdt@10360000 {
@@ -337,9 +352,9 @@
clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
clock-names = "tsadc", "apb_pclk";
pinctrl-names = "init", "default", "sleep";
- pinctrl-0 = <&otp_gpio>;
+ pinctrl-0 = <&otp_pin>;
pinctrl-1 = <&otp_out>;
- pinctrl-2 = <&otp_gpio>;
+ pinctrl-2 = <&otp_pin>;
resets = <&cru SRST_TSADC>;
reset-names = "tsadc-apb";
rockchip,hw-tshut-temp = <120000>;
@@ -352,7 +367,6 @@
reg = <0x1038c000 0x100>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#io-channel-cells = <1>;
- clock-frequency = <1000000>;
clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
clock-names = "saradc", "apb_pclk";
status = "disabled";
@@ -368,6 +382,7 @@
clock-names = "i2c", "pclk";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_xfer>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -437,17 +452,7 @@
#reset-cells = <1>;
};
- nandc: nandc@30100000 {
- compatible = "rockchip,rk-nandc";
- reg = <0x30100000 0x1000>;
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- nandc_id = <0>;
- clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
- clock-names = "clk_nandc", "hclk_nandc";
- status = "disabled";
- };
-
- emmc: dwmmc@30110000 {
+ emmc: mmc@30110000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30110000 0x4000>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
@@ -459,7 +464,7 @@
status = "disabled";
};
- sdio: dwmmc@30120000 {
+ sdio: mmc@30120000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30120000 0x4000>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
@@ -471,7 +476,7 @@
status = "disabled";
};
- sdmmc: dwmmc@30130000 {
+ sdmmc: mmc@30130000 {
compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0x30130000 0x4000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
@@ -490,7 +495,6 @@
reg = <0x30140000 0x20000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -501,7 +505,6 @@
reg = <0x30160000 0x20000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_HOST0>, <&u2phy>;
- clock-names = "usbhost", "utmi";
phys = <&u2phy_host>;
phy-names = "usb";
status = "disabled";
@@ -518,9 +521,30 @@
g-np-tx-fifo-size = <16>;
g-rx-fifo-size = <280>;
g-tx-fifo-size = <256 128 128 64 32 16>;
- g-use-dma;
phys = <&u2phy_otg>;
phy-names = "usb2-phy";
+ status = "disabled";
+ };
+
+ gmac: eth@30200000 {
+ compatible = "rockchip,rv1108-gmac";
+ reg = <0x30200000 0x10000>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ clocks = <&cru SCLK_MAC>,
+ <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
+ <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
+ clock-names = "stmmaceth",
+ "mac_clk_rx", "mac_clk_tx",
+ "clk_mac_ref", "clk_mac_refout",
+ "aclk_mac", "pclk_mac";
+ /* rv1108 only supports an rmii interface */
+ phy-mode = "rmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&rmii_pins>;
+ rockchip,grf = <&grf>;
status = "disabled";
};
@@ -535,10 +559,6 @@
<0x32014000 0x2000>,
<0x32016000 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- rockchip_system_monitor: rockchip-system-monitor {
- compatible = "rockchip,system-monitor";
};
pinctrl: pinctrl {
@@ -653,6 +673,42 @@
input-enable;
};
+ emmc {
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
+ <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
+ };
+
+ emmc_clk: emmc-clk {
+ rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
+ };
+
+ emmc_cmd: emmc-cmd {
+ rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
+ };
+ };
+
+ gmac {
+ rmii_pins: rmii-pins {
+ rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
+ <1 RK_PC3 2 &pcfg_pull_none>,
+ <1 RK_PC4 2 &pcfg_pull_none>,
+ <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
+ <1 RK_PB5 3 &pcfg_pull_none>,
+ <1 RK_PB6 3 &pcfg_pull_none>,
+ <1 RK_PB7 3 &pcfg_pull_none>,
+ <1 RK_PC2 3 &pcfg_pull_none>;
+ };
+ };
+
i2c0 {
i2c0_xfer: i2c0-xfer {
rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
@@ -673,7 +729,7 @@
<0 RK_PC6 3 &pcfg_pull_none>;
};
- i2c2m1_gpio: i2c2m1-gpio {
+ i2c2m1_pins: i2c2m1-pins {
rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -685,7 +741,7 @@
<1 RK_PD4 2 &pcfg_pull_none>;
};
- i2c2m05v_gpio: i2c2m05v-gpio {
+ i2c2m05v_pins: i2c2m05v-pins {
rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
<1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
};
@@ -771,12 +827,48 @@
};
};
+ spim0 {
+ spim0_clk: spim0-clk {
+ rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
+ };
+
+ spim0_cs0: spim0-cs0 {
+ rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
+ };
+
+ spim0_tx: spim0-tx {
+ rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
+ };
+
+ spim0_rx: spim0-rx {
+ rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
+ };
+ };
+
+ spim1 {
+ spim1_clk: spim1-clk {
+ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
+ };
+
+ spim1_cs0: spim1-cs0 {
+ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
+ };
+
+ spim1_rx: spim1-rx {
+ rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
+ };
+
+ spim1_tx: spim1-tx {
+ rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
+ };
+ };
+
tsadc {
otp_out: otp-out {
rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
};
- otp_gpio: otp-gpio {
+ otp_pin: otp-pin {
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -784,7 +876,7 @@
uart0 {
uart0_xfer: uart0-xfer {
rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
- <3 RK_PA5 1 &pcfg_pull_up>;
+ <3 RK_PA5 1 &pcfg_pull_none>;
};
uart0_cts: uart0-cts {
@@ -795,7 +887,7 @@
rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
};
- uart0_rts_gpio: uart0-rts-gpio {
+ uart0_rts_pin: uart0-rts-pin {
rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
@@ -803,7 +895,7 @@
uart1 {
uart1_xfer: uart1-xfer {
rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
- <1 RK_PD2 1 &pcfg_pull_up>;
+ <1 RK_PD2 1 &pcfg_pull_none>;
};
uart1_cts: uart1-cts {
@@ -818,14 +910,14 @@
uart2m0 {
uart2m0_xfer: uart2m0-xfer {
rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
- <2 RK_PD1 1 &pcfg_pull_up>;
+ <2 RK_PD1 1 &pcfg_pull_none>;
};
};
uart2m1 {
uart2m1_xfer: uart2m1-xfer {
rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
- <3 RK_PC2 2 &pcfg_pull_up>;
+ <3 RK_PC2 2 &pcfg_pull_none>;
};
};
--
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