From 50a212ec906f7524620675f0c57357691c26c81f Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Wed, 16 Oct 2024 01:20:19 +0000
Subject: [PATCH] 修改GPIO导出默认初始值

---
 kernel/Documentation/vm/mmu_notifier.rst |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/kernel/Documentation/vm/mmu_notifier.rst b/kernel/Documentation/vm/mmu_notifier.rst
index 47baa1c..df5d777 100644
--- a/kernel/Documentation/vm/mmu_notifier.rst
+++ b/kernel/Documentation/vm/mmu_notifier.rst
@@ -89,7 +89,7 @@
 
 So here because at time N+2 the clear page table entry was not pair with a
 notification to invalidate the secondary TLB, the device see the new value for
-addrB before seing the new value for addrA. This break total memory ordering
+addrB before seeing the new value for addrA. This break total memory ordering
 for the device.
 
 When changing a pte to write protect or to point to a new write protected page

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