From 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:44:59 +0000
Subject: [PATCH] gmac get mac form eeprom
---
kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c | 108 +++++++++++++++++++++++++++++++++--------------------
1 files changed, 67 insertions(+), 41 deletions(-)
diff --git a/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c b/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
index d1cbb0f..cee207d 100644
--- a/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/kernel/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- *
*/
#include <linux/kernel.h>
@@ -33,18 +21,15 @@
#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
-static void __iomem *apbmisc_base;
-static void __iomem *strapping_base;
static bool long_ram_code;
+static u32 strapping;
+static u32 chipid;
u32 tegra_read_chipid(void)
{
- if (!apbmisc_base) {
- WARN(1, "Tegra Chip ID not yet available\n");
- return 0;
- }
+ WARN(!chipid, "Tegra APB MISC not yet available\n");
- return readl_relaxed(apbmisc_base + 4);
+ return chipid;
}
u8 tegra_get_chip_id(void)
@@ -52,12 +37,46 @@
return (tegra_read_chipid() >> 8) & 0xff;
}
+u8 tegra_get_major_rev(void)
+{
+ return (tegra_read_chipid() >> 4) & 0xf;
+}
+
+u8 tegra_get_minor_rev(void)
+{
+ return (tegra_read_chipid() >> 16) & 0xf;
+}
+
+u8 tegra_get_platform(void)
+{
+ return (tegra_read_chipid() >> 20) & 0xf;
+}
+
+bool tegra_is_silicon(void)
+{
+ switch (tegra_get_chip_id()) {
+ case TEGRA194:
+ case TEGRA234:
+ if (tegra_get_platform() == 0)
+ return true;
+
+ return false;
+ }
+
+ /*
+ * Chips prior to Tegra194 have a different way of determining whether
+ * they are silicon or not. Since we never supported simulation on the
+ * older Tegra chips, don't bother extracting the information and just
+ * report that we're running on silicon.
+ */
+ return true;
+}
+
u32 tegra_read_straps(void)
{
- if (strapping_base)
- return readl_relaxed(strapping_base);
- else
- return 0;
+ WARN(!chipid, "Tegra ABP MISC not yet available\n");
+
+ return strapping;
}
u32 tegra_read_ram_code(void)
@@ -75,46 +94,45 @@
static const struct of_device_id apbmisc_match[] __initconst = {
{ .compatible = "nvidia,tegra20-apbmisc", },
{ .compatible = "nvidia,tegra186-misc", },
+ { .compatible = "nvidia,tegra194-misc", },
+ { .compatible = "nvidia,tegra234-misc", },
{},
};
void __init tegra_init_revision(void)
{
- u32 id, chip_id, minor_rev;
- int rev;
+ u8 chip_id, minor_rev;
- id = tegra_read_chipid();
- chip_id = (id >> 8) & 0xff;
- minor_rev = (id >> 16) & 0xf;
+ chip_id = tegra_get_chip_id();
+ minor_rev = tegra_get_minor_rev();
switch (minor_rev) {
case 1:
- rev = TEGRA_REVISION_A01;
+ tegra_sku_info.revision = TEGRA_REVISION_A01;
break;
case 2:
- rev = TEGRA_REVISION_A02;
+ tegra_sku_info.revision = TEGRA_REVISION_A02;
break;
case 3:
if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
tegra_fuse_read_spare(19)))
- rev = TEGRA_REVISION_A03p;
+ tegra_sku_info.revision = TEGRA_REVISION_A03p;
else
- rev = TEGRA_REVISION_A03;
+ tegra_sku_info.revision = TEGRA_REVISION_A03;
break;
case 4:
- rev = TEGRA_REVISION_A04;
+ tegra_sku_info.revision = TEGRA_REVISION_A04;
break;
default:
- rev = TEGRA_REVISION_UNKNOWN;
+ tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
}
-
- tegra_sku_info.revision = rev;
tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
}
void __init tegra_init_apbmisc(void)
{
+ void __iomem *apbmisc_base, *strapping_base;
struct resource apbmisc, straps;
struct device_node *np;
@@ -171,13 +189,21 @@
}
}
- apbmisc_base = ioremap_nocache(apbmisc.start, resource_size(&apbmisc));
- if (!apbmisc_base)
+ apbmisc_base = ioremap(apbmisc.start, resource_size(&apbmisc));
+ if (!apbmisc_base) {
pr_err("failed to map APBMISC registers\n");
+ } else {
+ chipid = readl_relaxed(apbmisc_base + 4);
+ iounmap(apbmisc_base);
+ }
- strapping_base = ioremap_nocache(straps.start, resource_size(&straps));
- if (!strapping_base)
+ strapping_base = ioremap(straps.start, resource_size(&straps));
+ if (!strapping_base) {
pr_err("failed to map strapping options registers\n");
+ } else {
+ strapping = readl_relaxed(strapping_base);
+ iounmap(strapping_base);
+ }
long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
}
--
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