From 37f49e37ab4cb5d0bc4c60eb5c6d4dd57db767bb Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Fri, 10 May 2024 07:44:59 +0000
Subject: [PATCH] gmac get mac form eeprom
---
kernel/drivers/clk/rockchip/clk-cpu.c | 239 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 217 insertions(+), 22 deletions(-)
diff --git a/kernel/drivers/clk/rockchip/clk-cpu.c b/kernel/drivers/clk/rockchip/clk-cpu.c
index 81f35c0..365d4ec 100644
--- a/kernel/drivers/clk/rockchip/clk-cpu.c
+++ b/kernel/drivers/clk/rockchip/clk-cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -5,10 +6,6 @@
* based on clk/samsung/clk-cpu.c
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*
* A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
* The CPU clock is typically derived from a hierarchy of clock
@@ -196,6 +193,13 @@
alt_div = reg_data->div_core_mask[0];
}
+ /*
+ * Change parents and add dividers in a single transaction.
+ *
+ * NOTE: we do this in a single transaction so we're never
+ * dividing the primary parent by the extra dividers that were
+ * needed for the alt.
+ */
pr_debug("%s: setting div %lu as alt-rate %lu > old-rate %lu\n",
__func__, alt_div, alt_prate, ndata->old_rate);
@@ -209,13 +213,19 @@
if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST))
rockchip_boost_add_core_div(cpuclk->pll_hw, alt_prate);
- /* select alternate parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_alt,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
-
rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
+
+ /* select alternate parent */
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
spin_unlock_irqrestore(cpuclk->lock, flags);
return 0;
@@ -241,11 +251,23 @@
if (ndata->old_rate < ndata->new_rate)
rockchip_cpuclk_set_dividers(cpuclk, rate);
- /* re-mux to primary parent */
- writel(HIWORD_UPDATE(reg_data->mux_core_main,
- reg_data->mux_core_mask,
- reg_data->mux_core_shift),
- cpuclk->reg_base + reg_data->core_reg[0]);
+ /*
+ * post-rate change event, re-mux to primary parent and remove dividers.
+ *
+ * NOTE: we do this in a single transaction so we're never dividing the
+ * primary parent by the extra dividers that were needed for the alt.
+ */
+
+ if (reg_data->mux_core_reg)
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->mux_core_reg);
+ else
+ writel(HIWORD_UPDATE(reg_data->mux_core_main,
+ reg_data->mux_core_mask,
+ reg_data->mux_core_shift),
+ cpuclk->reg_base + reg_data->core_reg[0]);
rockchip_cpuclk_set_post_muxs(cpuclk, rate);
@@ -290,14 +312,16 @@
}
struct clk *rockchip_clk_register_cpuclk(const char *name,
- const char *const *parent_names, u8 num_parents,
+ u8 num_parents,
+ struct clk *parent, struct clk *alt_parent,
const struct rockchip_cpuclk_reg_data *reg_data,
const struct rockchip_cpuclk_rate_table *rates,
int nrates, void __iomem *reg_base, spinlock_t *lock)
{
struct rockchip_cpuclk *cpuclk;
- struct clk_init_data init = {};
+ struct clk_init_data init;
struct clk *clk, *cclk, *pll_clk;
+ const char *parent_name;
int ret;
if (num_parents < 2) {
@@ -305,12 +329,18 @@
return ERR_PTR(-EINVAL);
}
+ if (IS_ERR(parent) || IS_ERR(alt_parent)) {
+ pr_err("%s: invalid parent clock(s)\n", __func__);
+ return ERR_PTR(-EINVAL);
+ }
+
cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
if (!cpuclk)
return ERR_PTR(-ENOMEM);
+ parent_name = clk_hw_get_name(__clk_get_hw(parent));
init.name = name;
- init.parent_names = &parent_names[reg_data->mux_core_main];
+ init.parent_names = &parent_name;
init.num_parents = 1;
init.ops = &rockchip_cpuclk_ops;
@@ -328,7 +358,7 @@
cpuclk->clk_nb.notifier_call = rockchip_cpuclk_notifier_cb;
cpuclk->hw.init = &init;
if (IS_ENABLED(CONFIG_ROCKCHIP_CLK_BOOST) && reg_data->pll_name) {
- pll_clk = __clk_lookup(reg_data->pll_name);
+ pll_clk = clk_get_parent(parent);
if (!pll_clk) {
pr_err("%s: could not lookup pll clock: (%s)\n",
__func__, reg_data->pll_name);
@@ -339,7 +369,7 @@
rockchip_boost_init(cpuclk->pll_hw);
}
- cpuclk->alt_parent = __clk_lookup(parent_names[reg_data->mux_core_alt]);
+ cpuclk->alt_parent = alt_parent;
if (!cpuclk->alt_parent) {
pr_err("%s: could not lookup alternate parent: (%d)\n",
__func__, reg_data->mux_core_alt);
@@ -354,11 +384,11 @@
goto free_cpuclk;
}
- clk = __clk_lookup(parent_names[reg_data->mux_core_main]);
+ clk = parent;
if (!clk) {
pr_err("%s: could not lookup parent clock: (%d) %s\n",
__func__, reg_data->mux_core_main,
- parent_names[reg_data->mux_core_main]);
+ parent_name);
ret = -EINVAL;
goto free_alt_parent;
}
@@ -400,3 +430,168 @@
kfree(cpuclk);
return ERR_PTR(ret);
}
+
+static int rockchip_cpuclk_v2_pre_rate_change(struct rockchip_cpuclk *cpuclk,
+ struct clk_notifier_data *ndata)
+{
+ unsigned long new_rate = roundup(ndata->new_rate, 1000);
+ const struct rockchip_cpuclk_rate_table *rate;
+ unsigned long flags;
+
+ rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for cpuclk\n",
+ __func__, new_rate);
+ return -EINVAL;
+ }
+
+ if (new_rate > ndata->old_rate) {
+ spin_lock_irqsave(cpuclk->lock, flags);
+ rockchip_cpuclk_set_dividers(cpuclk, rate);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ }
+
+ return 0;
+}
+
+static int rockchip_cpuclk_v2_post_rate_change(struct rockchip_cpuclk *cpuclk,
+ struct clk_notifier_data *ndata)
+{
+ unsigned long new_rate = roundup(ndata->new_rate, 1000);
+ const struct rockchip_cpuclk_rate_table *rate;
+ unsigned long flags;
+
+ rate = rockchip_get_cpuclk_settings(cpuclk, new_rate);
+ if (!rate) {
+ pr_err("%s: Invalid rate : %lu for cpuclk\n",
+ __func__, new_rate);
+ return -EINVAL;
+ }
+
+ if (new_rate < ndata->old_rate) {
+ spin_lock_irqsave(cpuclk->lock, flags);
+ rockchip_cpuclk_set_dividers(cpuclk, rate);
+ spin_unlock_irqrestore(cpuclk->lock, flags);
+ }
+
+ return 0;
+}
+
+static int rockchip_cpuclk_v2_notifier_cb(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct clk_notifier_data *ndata = data;
+ struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_nb(nb);
+ int ret = 0;
+
+ pr_debug("%s: event %lu, old_rate %lu, new_rate: %lu\n",
+ __func__, event, ndata->old_rate, ndata->new_rate);
+ if (event == PRE_RATE_CHANGE)
+ ret = rockchip_cpuclk_v2_pre_rate_change(cpuclk, ndata);
+ else if (event == POST_RATE_CHANGE)
+ ret = rockchip_cpuclk_v2_post_rate_change(cpuclk, ndata);
+
+ return notifier_from_errno(ret);
+}
+
+struct clk *rockchip_clk_register_cpuclk_v2(const char *name,
+ const char *const *parent_names,
+ u8 num_parents, void __iomem *base,
+ int muxdiv_offset, u8 mux_shift,
+ u8 mux_width, u8 mux_flags,
+ int div_offset, u8 div_shift,
+ u8 div_width, u8 div_flags,
+ unsigned long flags, spinlock_t *lock,
+ const struct rockchip_cpuclk_rate_table *rates,
+ int nrates)
+{
+ struct rockchip_cpuclk *cpuclk;
+ struct clk_hw *hw;
+ struct clk_mux *mux = NULL;
+ struct clk_divider *div = NULL;
+ const struct clk_ops *mux_ops = NULL, *div_ops = NULL;
+ int ret;
+
+ if (num_parents > 1) {
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ mux->reg = base + muxdiv_offset;
+ mux->shift = mux_shift;
+ mux->mask = BIT(mux_width) - 1;
+ mux->flags = mux_flags;
+ mux->lock = lock;
+ mux_ops = (mux_flags & CLK_MUX_READ_ONLY) ? &clk_mux_ro_ops
+ : &clk_mux_ops;
+ }
+
+ if (div_width > 0) {
+ div = kzalloc(sizeof(*div), GFP_KERNEL);
+ if (!div) {
+ ret = -ENOMEM;
+ goto free_mux;
+ }
+
+ div->flags = div_flags;
+ if (div_offset)
+ div->reg = base + div_offset;
+ else
+ div->reg = base + muxdiv_offset;
+ div->shift = div_shift;
+ div->width = div_width;
+ div->lock = lock;
+ div_ops = (div_flags & CLK_DIVIDER_READ_ONLY)
+ ? &clk_divider_ro_ops
+ : &clk_divider_ops;
+ }
+
+ hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
+ mux ? &mux->hw : NULL, mux_ops,
+ div ? &div->hw : NULL, div_ops,
+ NULL, NULL, flags);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto free_div;
+ }
+
+ cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
+ if (!cpuclk) {
+ ret = -ENOMEM;
+ goto unregister_clk;
+ }
+
+ cpuclk->reg_base = base;
+ cpuclk->lock = lock;
+ cpuclk->clk_nb.notifier_call = rockchip_cpuclk_v2_notifier_cb;
+ ret = clk_notifier_register(hw->clk, &cpuclk->clk_nb);
+ if (ret) {
+ pr_err("%s: failed to register clock notifier for %s\n",
+ __func__, name);
+ goto free_cpuclk;
+ }
+
+ if (nrates > 0) {
+ cpuclk->rate_count = nrates;
+ cpuclk->rate_table = kmemdup(rates,
+ sizeof(*rates) * nrates,
+ GFP_KERNEL);
+ if (!cpuclk->rate_table) {
+ ret = -ENOMEM;
+ goto free_cpuclk;
+ }
+ }
+
+ return hw->clk;
+
+free_cpuclk:
+ kfree(cpuclk);
+unregister_clk:
+ clk_hw_unregister_composite(hw);
+free_div:
+ kfree(div);
+free_mux:
+ kfree(mux);
+
+ return ERR_PTR(ret);
+}
--
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