From 36f0949ef9854b82a9a3154d970da4e3b8d12a61 Mon Sep 17 00:00:00 2001
From: hc <hc@nodka.com>
Date: Mon, 06 Nov 2023 07:23:29 +0000
Subject: [PATCH] rk3568 rkbin init
---
kernel/drivers/thermal/rockchip_thermal.c | 174 +++++++++++++++++++++++++++++++++++++++++++++++++++-------
1 files changed, 153 insertions(+), 21 deletions(-)
diff --git a/kernel/drivers/thermal/rockchip_thermal.c b/kernel/drivers/thermal/rockchip_thermal.c
index 7d2ad2e..01ad033 100644
--- a/kernel/drivers/thermal/rockchip_thermal.c
+++ b/kernel/drivers/thermal/rockchip_thermal.c
@@ -230,6 +230,7 @@
#define TSADCV2_AUTO_PERIOD_HT 0x6c
#define TSADCV3_AUTO_PERIOD 0x154
#define TSADCV3_AUTO_PERIOD_HT 0x158
+#define TSADCV3_Q_MAX 0x210
#define TSADCV2_AUTO_EN BIT(0)
#define TSADCV2_AUTO_EN_MASK BIT(16)
@@ -240,6 +241,7 @@
#define TSADCV2_AUTO_TSHUT_POLARITY_MASK BIT(24)
#define TSADCV3_AUTO_Q_SEL_EN BIT(1)
+#define TSADCV3_AUTO_Q_SEL_EN_MASK BIT(17)
#define TSADCV2_INT_SRC_EN(chn) BIT(chn)
#define TSADCV2_INT_SRC_EN_MASK(chn) BIT(16 + (chn))
@@ -253,6 +255,7 @@
#define TSADCV2_DATA_MASK 0xfff
#define TSADCV3_DATA_MASK 0x3ff
#define TSADCV4_DATA_MASK 0x1ff
+#define TSADCV5_DATA_MASK 0x7ff
#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
@@ -264,6 +267,9 @@
#define TSADCV5_AUTO_PERIOD_HT_TIME 1622 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_TIME 5000 /* 2.5ms */
#define TSADCV6_AUTO_PERIOD_HT_TIME 5000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_TIME 3000 /* 2.5ms */
+#define TSADCV7_AUTO_PERIOD_HT_TIME 3000 /* 2.5ms */
+#define TSADCV3_Q_MAX_VAL 0x7ff /* 11bit 2047 */
#define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
#define TSADCV5_USER_INTER_PD_SOC 0xfc0 /* 97us, at least 90us */
@@ -278,6 +284,7 @@
#define RK1808_BUS_GRF_SOC_CON0 0x0400
#define RK3568_GRF_TSADC_CON 0x0600
+#define RK3528_GRF_TSADC_CON 0x40030
#define RK3568_GRF_TSADC_ANA_REG0 (0x10001 << 0)
#define RK3568_GRF_TSADC_ANA_REG1 (0x10001 << 1)
#define RK3568_GRF_TSADC_ANA_REG2 (0x10001 << 2)
@@ -299,9 +306,11 @@
#define PX30S_TSADC_TDC_MODE (0x10001 << 4)
#define PX30S_TSADC_TRIM (0xf0007 << 0)
-#define MIN_TEMP (-40000)
+
+/* -40 to 125 is reliable, outside the range existed unreliability */
+#define MIN_TEMP (-60000)
#define LOWEST_TEMP (-273000)
-#define MAX_TEMP (125000)
+#define MAX_TEMP (180000)
#define MAX_ENV_TEMP (85000)
#define BASE (1024)
@@ -325,9 +334,9 @@
int temp;
};
-
static const struct tsadc_table rv1108_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {342, MIN_TEMP},
{374, -40000},
{382, -35000},
{389, -30000},
@@ -362,11 +371,13 @@
{618, 115000},
{626, 120000},
{634, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {722, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk1808_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {3423, MIN_TEMP},
{3455, -40000},
{3463, -35000},
{3471, -30000},
@@ -401,11 +412,13 @@
{3709, 115000},
{3718, 120000},
{3726, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3820, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3228_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {568, MIN_TEMP},
{588, -40000},
{593, -35000},
{598, -30000},
@@ -440,11 +453,13 @@
{749, 115000},
{754, 120000},
{760, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {821, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3288_code_table[] = {
- {TSADCV2_DATA_MASK, -40000},
+ {TSADCV2_DATA_MASK, MIN_TEMP},
+ {3833, MIN_TEMP},
{3800, -40000},
{3792, -35000},
{3783, -30000},
@@ -479,11 +494,15 @@
{3452, 115000},
{3437, 120000},
{3421, 125000},
- {0, 125000},
+ {3350, 145000},
+ {3270, 165000},
+ {3195, MAX_TEMP},
+ {0, MAX_TEMP},
};
static const struct tsadc_table rk3328_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {261, MIN_TEMP},
{296, -40000},
{304, -35000},
{313, -30000},
@@ -517,11 +536,15 @@
{644, 115000},
{659, 120000},
{675, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {745, 145000},
+ {825, 165000},
+ {900, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3368_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {98, MIN_TEMP},
{106, -40000},
{108, -35000},
{110, -30000},
@@ -556,11 +579,13 @@
{167, 115000},
{169, 120000},
{171, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {193, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3399_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {368, MIN_TEMP},
{402, -40000},
{410, -35000},
{419, -30000},
@@ -595,11 +620,54 @@
{668, 115000},
{677, 120000},
{685, 125000},
- {TSADCV3_DATA_MASK, 125000},
+ {782, MAX_TEMP},
+ {TSADCV3_DATA_MASK, MAX_TEMP},
+};
+
+static const struct tsadc_table rk3528_code_table[] = {
+ {0, MIN_TEMP},
+ {1386, MIN_TEMP},
+ {1419, -40000},
+ {1427, -35000},
+ {1435, -30000},
+ {1443, -25000},
+ {1452, -20000},
+ {1460, -15000},
+ {1468, -10000},
+ {1477, -5000},
+ {1486, 0},
+ {1494, 5000},
+ {1502, 10000},
+ {1510, 15000},
+ {1519, 20000},
+ {1527, 25000},
+ {1535, 30000},
+ {1544, 35000},
+ {1552, 40000},
+ {1561, 45000},
+ {1569, 50000},
+ {1578, 55000},
+ {1586, 60000},
+ {1594, 65000},
+ {1603, 70000},
+ {1612, 75000},
+ {1620, 80000},
+ {1628, 85000},
+ {1637, 90000},
+ {1646, 95000},
+ {1654, 100000},
+ {1662, 105000},
+ {1671, 110000},
+ {1679, 115000},
+ {1688, 120000},
+ {1696, 125000},
+ {1790, MAX_TEMP},
+ {TSADCV5_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3568_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {1448, MIN_TEMP},
{1584, -40000},
{1620, -35000},
{1652, -30000},
@@ -634,16 +702,19 @@
{2636, 115000},
{2672, 120000},
{2704, 125000},
- {TSADCV2_DATA_MASK, 125000},
+ {3076, MAX_TEMP},
+ {TSADCV2_DATA_MASK, MAX_TEMP},
};
static const struct tsadc_table rk3588_code_table[] = {
- {0, -40000},
+ {0, MIN_TEMP},
+ {194, MIN_TEMP},
{215, -40000},
{285, 25000},
{350, 85000},
{395, 125000},
- {TSADCV4_DATA_MASK, 125000},
+ {455, MAX_TEMP},
+ {TSADCV4_DATA_MASK, MAX_TEMP},
};
static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
@@ -968,6 +1039,37 @@
if (!IS_ERR(grf)) {
regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TDC_MODE);
regmap_write(grf, PX30_GRF_SOC_CON0, PX30S_TSADC_TRIM);
+ }
+}
+
+static void rk_tsadcv11_initialize(struct regmap *grf, void __iomem *regs,
+ enum tshut_polarity tshut_polarity)
+{
+ writel_relaxed(TSADCV7_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
+ writel_relaxed(TSADCV7_AUTO_PERIOD_HT_TIME,
+ regs + TSADCV3_AUTO_PERIOD_HT);
+ writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_INT_DEBOUNCE);
+ writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
+ regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
+ writel_relaxed(TSADCV3_Q_MAX_VAL, regs + TSADCV3_Q_MAX);
+ writel_relaxed(TSADCV3_AUTO_Q_SEL_EN | TSADCV3_AUTO_Q_SEL_EN_MASK,
+ regs + TSADCV2_AUTO_CON);
+ if (tshut_polarity == TSHUT_HIGH_ACTIVE)
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
+ TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+ else
+ writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
+ regs + TSADCV2_AUTO_CON);
+
+ if (!IS_ERR(grf)) {
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
+ udelay(15);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
+ regmap_write(grf, RK3528_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
+ usleep_range(100, 200);
}
}
@@ -1639,6 +1741,30 @@
},
};
+static const struct rockchip_tsadc_chip rk3528_tsadc_data = {
+ .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+ .chn_num = 1, /* one channels for tsadc */
+
+ .tshut_mode = TSHUT_MODE_OTP, /* default TSHUT via GPIO give PMIC */
+ .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
+ .tshut_temp = 95000,
+
+ .initialize = rk_tsadcv11_initialize,
+ .irq_ack = rk_tsadcv4_irq_ack,
+ .control = rk_tsadcv4_control,
+ .get_temp = rk_tsadcv4_get_temp,
+ .set_alarm_temp = rk_tsadcv3_alarm_temp,
+ .set_tshut_temp = rk_tsadcv3_tshut_temp,
+ .set_tshut_mode = rk_tsadcv4_tshut_mode,
+
+ .table = {
+ .id = rk3528_code_table,
+ .length = ARRAY_SIZE(rk3528_code_table),
+ .data_mask = TSADCV2_DATA_MASK,
+ .mode = ADC_INCREMENT,
+ },
+};
+
static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
@@ -1757,6 +1883,12 @@
.data = (void *)&rk3399_tsadc_data,
},
#endif
+#ifdef CONFIG_CPU_RK3528
+ {
+ .compatible = "rockchip,rk3528-tsadc",
+ .data = (void *)&rk3528_tsadc_data,
+ },
+#endif
#ifdef CONFIG_CPU_RK3568
{
.compatible = "rockchip,rk3568-tsadc",
--
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